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68 lines
2.0 KiB
VHDL
68 lines
2.0 KiB
VHDL
-- $Id: iob_reg_i_gen.vhd 984 2018-01-02 20:56:27Z mueller $
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--
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: iob_reg_i_gen - syn
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-- Description: Registered IOB, input only, vector
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic Spartan, Virtex
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-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
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-- Revision History:
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-- Date Rev Version Comment
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-- 2007-12-16 101 1.0.1 add INIT generic port
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-- 2007-12-08 100 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.xlib.all;
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entity iob_reg_i_gen is -- registered IOB, input, vector
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generic (
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DWIDTH : positive := 16; -- data port width
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INIT : slbit := '0'); -- initial state
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port (
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CLK : in slbit; -- clock
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CE : in slbit := '1'; -- clock enable
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DI : out slv(DWIDTH-1 downto 0); -- input data
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PAD : in slv(DWIDTH-1 downto 0) -- i/o pad
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);
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end iob_reg_i_gen;
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architecture syn of iob_reg_i_gen is
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signal R_DI : slv(DWIDTH-1 downto 0) := (others=>INIT);
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attribute iob : string;
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attribute iob of R_DI : signal is "true";
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if CE = '1' then
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R_DI <= PAD;
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end if;
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end if;
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end process proc_regs;
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DI <= R_DI;
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end syn;
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