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123 lines
4.0 KiB
VHDL
123 lines
4.0 KiB
VHDL
-- $Id: iob_reg_io_gen.vhd 984 2018-01-02 20:56:27Z mueller $
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--
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-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: iob_reg_io_gen - syn
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-- Description: Registered IOB, in/output, vector
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--
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-- Dependencies: iob_keeper_gen [sim only]
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-- Test bench: -
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-- Target Devices: generic Spartan, Virtex
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
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-- Revision History:
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-- Date Rev Version Comment
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-- 2008-05-22 149 1.0.4 use internally TE to match OBUFT T polarity
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-- 2008-05-22 148 1.0.3 remove UNISIM prim's; PULL implemented only for sim
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-- 2008-05-18 147 1.0.2 add PULL generic, to enable PULL-UP,-DOWN or KEEPER
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-- 2007-12-16 101 1.0.1 add INIT generic ports
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-- 2007-12-08 100 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.xlib.all;
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entity iob_reg_io_gen is -- registered IOB, in/output, vector
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generic (
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DWIDTH : positive := 16; -- data port width
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INITI : slbit := '0'; -- initial state ( in flop)
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INITO : slbit := '0'; -- initial state (out flop)
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INITE : slbit := '0'; -- initial state ( oe flop)
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PULL : string := "NONE"); -- pull-up,-down or keeper
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port (
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CLK : in slbit; -- clock
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CEI : in slbit := '1'; -- clock enable ( in flops)
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CEO : in slbit := '1'; -- clock enable (out flops)
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OE : in slbit; -- output enable
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DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
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DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
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PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
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);
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end iob_reg_io_gen;
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architecture syn of iob_reg_io_gen is
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signal R_TE : slbit := not INITE;
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signal R_DI : slv(DWIDTH-1 downto 0) := (others=>INITI);
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signal R_DO : slv(DWIDTH-1 downto 0) := (others=>INITO);
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constant all_z : slv(DWIDTH-1 downto 0) := (others=>'Z');
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constant all_l : slv(DWIDTH-1 downto 0) := (others=>'L');
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constant all_h : slv(DWIDTH-1 downto 0) := (others=>'H');
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attribute iob : string;
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attribute iob of R_TE : signal is "true";
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attribute iob of R_DI : signal is "true";
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attribute iob of R_DO : signal is "true";
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begin
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assert PULL="NONE" or PULL="UP" or PULL="DOWN" or PULL="KEEP"
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report "assert(PULL): only NONE, UP, DOWN, OR KEEP supported"
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severity failure;
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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R_TE <= not OE;
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if CEI = '1' then
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R_DI <= to_x01(PAD);
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end if;
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if CEO = '1' then
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R_DO <= DO;
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end if;
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end if;
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end process proc_regs;
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proc_comb: process (R_TE, R_DO)
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begin
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if R_TE = '1' then
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PAD <= all_z;
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else
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PAD <= R_DO;
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end if;
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end process proc_comb;
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DI <= R_DI;
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-- Note: PULL (UP, DOWN or KEEP) is only implemented for simulation, not
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-- for inference in synthesis. Use pin attributes in UCF's or XDC's
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--
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-- synthesis translate_off
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PULL_UP: if PULL = "UP" generate
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PAD <= all_h;
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end generate PULL_UP;
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PULL_DOWN: if PULL = "DOWN" generate
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PAD <= all_l;
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end generate PULL_DOWN;
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PULL_KEEP: if PULL = "KEEP" generate
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KEEPER : iob_keeper_gen
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generic map (DWIDTH => DWIDTH)
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port map (PAD => PAD);
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end generate PULL_KEEP;
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-- synthesis translate_on
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end syn;
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