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53 lines
1.4 KiB
VHDL
53 lines
1.4 KiB
VHDL
-- $Id: iob_reg_i.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: iob_reg_i - syn
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-- Description: Registered IOB, input only
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic Spartan, Virtex
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-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
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-- Revision History:
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-- Date Rev Version Comment
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-- 2007-12-16 101 1.0.1 add INIT generic port
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-- 2007-12-08 100 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.xlib.all;
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entity iob_reg_i is -- registered IOB, input
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generic (
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INIT : slbit := '0'); -- initial state
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port (
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CLK : in slbit; -- clock
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CE : in slbit := '1'; -- clock enable
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DI : out slbit; -- input data
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PAD : in slbit -- i/o pad
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);
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end iob_reg_i;
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architecture syn of iob_reg_i is
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begin
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IOB : iob_reg_i_gen
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generic map (
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DWIDTH => 1,
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INIT => INIT)
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port map (
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CLK => CLK,
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CE => CE,
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DI(0) => DI,
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PAD(0) => PAD
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);
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end syn;
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