mirror of
https://github.com/wfjm/w11.git
synced 2026-01-20 10:24:25 +00:00
d87ac86f53
- Goals for rlink v4
- 16 bit addresses (instead of 8 bit)
- more robust encoding, support for error recovery at transport level
- add features to reduce round trips
- improved attention handling
- new 'list abort' command
- For further details see README_Rlink_V4.txt
- use own C++ based tcl shell tclshcpp instead of tclsh
121 lines
3.9 KiB
Makefile
121 lines
3.9 KiB
Makefile
# $Id: Makefile 613 2014-12-20 08:47:50Z mueller $
|
|
#
|
|
# 'Meta Makefile' for whole retro project
|
|
# allows to make all synthesis targets
|
|
# allows to make all test bench targets
|
|
#
|
|
# Revision History:
|
|
# Date Rev Version Comment
|
|
# 2014-06-14 562 1.0.8 suspend nexys4 syn targets
|
|
# 2013-09-28 535 1.0.7 add nexys4 port for sys_gen/tst_sram,w11a
|
|
# 2013-05-01 513 1.0.6 add clean_sim_tmp and clean_syn_tmp targets
|
|
# 2012-12-29 466 1.0.5 add tst_rlink_cuff
|
|
# 2011-12-26 445 1.0.4 add tst_fx2loop
|
|
# 2011-12-23 444 1.0.3 enforce -j 1 in sub-makes
|
|
# 2011-11-27 433 1.0.2 add new nexys3 ports
|
|
# 2011-11-18 426 1.0.1 add tst_serport and tst_snhumanio
|
|
# 2011-07-09 391 1.0 Initial version
|
|
#
|
|
SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic
|
|
SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic3
|
|
SYN_all += rtl/sys_gen/tst_fx2loop/nexys3/ic
|
|
SYN_all += rtl/sys_gen/tst_fx2loop/nexys3/ic3
|
|
SYN_all += rtl/sys_gen/tst_rlink/nexys2
|
|
SYN_all += rtl/sys_gen/tst_rlink/nexys3
|
|
SYN_all += rtl/sys_gen/tst_rlink/s3board
|
|
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
|
|
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
|
|
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys3/ic
|
|
SYN_all += rtl/sys_gen/tst_rlink_cuff/atlys/ic
|
|
SYN_all += rtl/sys_gen/tst_serloop/nexys2
|
|
SYN_all += rtl/sys_gen/tst_serloop/nexys3
|
|
SYN_all += rtl/sys_gen/tst_serloop/s3board
|
|
SYN_all += rtl/sys_gen/tst_snhumanio/atlys
|
|
SYN_all += rtl/sys_gen/tst_snhumanio/nexys2
|
|
SYN_all += rtl/sys_gen/tst_snhumanio/nexys3
|
|
SYN_all += rtl/sys_gen/tst_snhumanio/s3board
|
|
SYN_all += rtl/sys_gen/w11a/nexys2
|
|
SYN_all += rtl/sys_gen/w11a/nexys3
|
|
SYN_all += rtl/sys_gen/w11a/s3board
|
|
|
|
SIM_all += rtl/bplib/nxcramlib/tb
|
|
SIM_all += rtl/sys_gen/tst_rlink/nexys2/tb
|
|
SIM_all += rtl/sys_gen/tst_rlink/nexys3/tb
|
|
SIM_all += rtl/sys_gen/tst_rlink/s3board/tb
|
|
SIM_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
|
|
SIM_all += rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
|
|
SIM_all += rtl/sys_gen/tst_serloop/nexys2/tb
|
|
SIM_all += rtl/sys_gen/tst_serloop/nexys3/tb
|
|
SIM_all += rtl/sys_gen/tst_serloop/s3board/tb
|
|
SIM_all += rtl/sys_gen/w11a/nexys2/tb
|
|
SIM_all += rtl/sys_gen/w11a/nexys3/tb
|
|
SIM_all += rtl/sys_gen/w11a/s3board/tb
|
|
SIM_all += rtl/vlib/comlib/tb
|
|
SIM_all += rtl/vlib/rlink/tb
|
|
SIM_all += rtl/vlib/serport/tb
|
|
SIM_all += rtl/w11a/tb
|
|
#
|
|
.PHONY : all all_sim all_syn
|
|
.PHONY : clean clean_sim clean_sim_tmp clean_sym clean_sym_tmp
|
|
.PHONY : $(SYN_all) $(SIM_all)
|
|
#
|
|
all :
|
|
@echo "No default action defined:"
|
|
@echo " for VHDL simulation/synthesis use:"
|
|
@echo " make -j `nproc` all_sim"
|
|
@echo " make -j `nproc` all_syn"
|
|
@echo " make clean"
|
|
@echo " make clean_sim"
|
|
@echo " make clean_syn"
|
|
@echo " make clean_sim_tmp"
|
|
@echo " make clean_syn_tmp"
|
|
@echo " for tool/documentation generation use:"
|
|
@echo " make -j `nproc` all_lib"
|
|
@echo " make clean_lib"
|
|
@echo " make all_tcl"
|
|
@echo " make all_dox"
|
|
#
|
|
#
|
|
clean : clean_sim clean_syn
|
|
#
|
|
clean_sim :
|
|
for dir in $(SIM_all); do $(MAKE) -C $$dir clean; done
|
|
clean_syn :
|
|
for dir in $(SYN_all); do $(MAKE) -C $$dir clean; done
|
|
#
|
|
clean_sim_tmp :
|
|
for dir in $(SIM_all); do $(MAKE) -C $$dir ghdl_tmp_clean; done
|
|
clean_syn_tmp :
|
|
for dir in $(SYN_all); do $(MAKE) -C $$dir ise_tmp_clean; done
|
|
#
|
|
all_sim : $(SIM_all)
|
|
#
|
|
all_syn : $(SYN_all)
|
|
@if [ -n "`find -name "*_par.log" | xargs grep -L 'All constraints were met'`" ] ; then \
|
|
echo "++++++++++ some designs have no timing closure: ++++++++++"; \
|
|
find -name "*_par.log" | xargs grep -L 'All constraints were met'; \
|
|
echo "++++++++++ ++++++++++++++++++++++++++++++++++++ ++++++++++"; \
|
|
fi
|
|
#
|
|
# Neither ghdl nor xst allow multiple parallel compiles in one directory.
|
|
# The following ensures that the sub-makes are called with -j 1 and will
|
|
# not try to run multiple compiles on one directory.
|
|
#
|
|
$(SIM_all):
|
|
$(MAKE) -j 1 -C $@
|
|
$(SYN_all):
|
|
$(MAKE) -j 1 -C $@
|
|
#
|
|
all_lib :
|
|
$(MAKE) -C tools/src
|
|
clean_lib :
|
|
$(MAKE) -C tools/src distclean
|
|
#
|
|
all_tcl :
|
|
(cd tools/tcl; setup_packages)
|
|
#
|
|
all_dox :
|
|
(cd tools/dox; make_doxy)
|
|
#
|
|
all_all : all_sim all_syn all_lib all_tcl
|