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Code Issues Releases Wiki Activity

PSurge working without Sound

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This commit is contained in:
Marcel
2019-09-22 18:46:10 +02:00
parent 8ce667b3c8
commit 06077042d9
51 changed files with 733 additions and 2693 deletions
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96
Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.qsf
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@@ -18,14 +18,14 @@
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 17:50:10 March 09, 2019
# Date created = 18:23:45 September 22, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# time_pilot_mist_assignment_defaults.qdf
# Power_Surge_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@@ -45,6 +45,28 @@ set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Power_Surge_MiST.sv
set_global_assignment -name VHDL_FILE rtl/power_surge.vhd
set_global_assignment -name VHDL_FILE rtl/gen_video.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/time_pilot_sound_board.vhd
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
set_global_assignment -name VHDL_FILE rtl/rom/power_surge_sprite_grphx.vhd
set_global_assignment -name VHDL_FILE rtl/rom/power_surge_sprite_color_lut.vhd
set_global_assignment -name VHDL_FILE rtl/rom/power_surge_sound_prog.vhd
set_global_assignment -name VHDL_FILE rtl/rom/power_surge_palette_green_red.vhd
set_global_assignment -name VHDL_FILE rtl/rom/power_surge_palette_blue_green.vhd
set_global_assignment -name VHDL_FILE rtl/rom/power_surge_char_grphx.vhd
set_global_assignment -name VHDL_FILE rtl/rom/power_surge_char_color_lut.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80se.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name SYSTEMVERILOG_FILE ../../../common/mist/sdram.sv
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
# Pin & Location Assignments
# ==========================
@@ -78,6 +100,45 @@ set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
# Classic Timing Assignments
# ==========================
@@ -87,8 +148,11 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name TOP_LEVEL_ENTITY SNES_top
set_global_assignment -name TOP_LEVEL_ENTITY Power_Surge_MiST
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
# Fitter Assignments
# ==================
@@ -132,33 +196,21 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
# ----------------------------
# start ENTITY(TimePilot_MiST)
# ------------------------------
# start ENTITY(Power_Surge_MiST)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(TimePilot_MiST)
# --------------------------
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name VERILOG_FILE "../Neuer Ordner (2)/rtl/DE0-CV/SNES_top.v"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SOURCE_FILE "../Neuer Ordner (2)/rtl/snes_core.sflp"
set_global_assignment -name SOURCE_FILE "../Neuer Ordner (2)/rtl/dma_core.sflp"
set_global_assignment -name SOURCE_FILE "../Neuer Ordner (2)/rtl/display.sflp"
set_global_assignment -name SOURCE_FILE "../Neuer Ordner (2)/rtl/DE0-CV/VGA_ctrl.sflp"
set_global_assignment -name SOURCE_FILE "../Neuer Ordner (2)/rtl/DE0-CV/dsdac16.sflp"
set_global_assignment -name SOURCE_FILE "../Neuer Ordner (2)/rtl/DE0-CV/DDS_50to10738635.sflp"
set_global_assignment -name SOURCE_FILE "../Neuer Ordner (2)/rtl/DE0-CV/DDS_50to1024000.sflp"
set_global_assignment -name SOURCE_FILE "../Neuer Ordner (2)/rtl/DE0-CV/core.sflp"
# end ENTITY(Power_Surge_MiST)
# ----------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

4
Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.srf
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@@ -1,5 +1 @@
{ "" "" "" "*" { } { } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 13310 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}

8
Arcade_MiST/Konami Classic/Power_Surge_MiST/README.txt
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@@ -1,3 +1,11 @@
Arcade: Power Surge port to MiST by Gehstock
PSURGE.ROM is required at the root of the SD-Card.
Todo: Sound
---------------------------------------------------------------------------------
-- Time pilot by Dar (darfpga@aol.fr) (29/10/2017)
-- http://darfpga.blogspot.fr

BIN
Arcade_MiST/Konami Classic/Power_Surge_MiST/Release/Power_Surge.rbf Normal file
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0
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/time_pilot_prog.bin → Arcade_MiST/Konami Classic/Power_Surge_MiST/Release/power_surge_prog.bin
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BIN
Arcade_MiST/Konami Classic/Power_Surge_MiST/Snapshot/Power_Surge.rbf
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Binary file not shown.

256
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/Power_Surge_MiST.sv Normal file
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@@ -0,0 +1,256 @@
//============================================================================
// Arcade: Power Surge
//
// Port to MiST
// Copyright (C) 2017 Gehstock
//
// Time pilot by Dar (darfpga@aol.fr) (29/10/2017)
// http://darfpga.blogspot.fr
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module Power_Surge_MiST(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"PSURGE;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"T6,Reset;",
"V,v1.10.",`BUILD_DATE
};
assign LED = 1;
assign AUDIO_R = AUDIO_L;
assign SDRAM_CLK = clock_48;
wire clock_48, clock_12, clock_14, pll_locked;
pll pll(
.inclk0(CLOCK_27),
.c0(clock_48),//24,57600000
.c1(clock_12),//12.28800000
.c2(clock_14),//14.31800000
.locked(pll_locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
reg [10:0] audio;
wire hb, vb;
wire blankn = ~(hb | vb);
wire ce_vid;
wire hs, vs;
wire [4:0] r,g,b;
wire [14:0] rom_addr;
wire [15:0] rom_do;
wire rom_rd;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
data_io data_io(
.clk_sys ( clock_48 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
sdram rom(
.*,
.init ( ~pll_locked ),
.clk ( clock_48 ),
.wtbt ( 2'b00 ),
.dout ( rom_do ),
.din ( {ioctl_dout, ioctl_dout} ),
.addr ( ioctl_downl ? ioctl_addr : rom_addr ),
.we ( ioctl_downl & ioctl_wr ),
.rd ( !ioctl_downl & rom_rd),
.ready()
);
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clock_48) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | status[6] | ~rom_loaded;
end
power_surge power_surge(
.clock_12(clock_12),
.clock_14(clock_14),
.reset(reset),
.video_r(r),
.video_g(g),
.video_b(b),
.video_hblank(hb),
.video_vblank(vb),
.video_hs(hs),
.video_vs(vs),
.audio_out(audio),
.roms_addr(rom_addr),
.roms_do(rom_do[7:0]),
.roms_rd(rom_rd),
.dip_switch_1("01111000"), // Cabinet Unknown Lives Lives Initial_Energy Unknown Unknown Unknown
.dip_switch_2("11100000"), // Stop_at_Junctions, Unknown, Unknown, Cheat, Coin_B Coin_B Coin_A Coin_A
.start2(btn_two_players),
.start1(btn_one_player),
.coin1(btn_coin),
.fire1(m_fire),
.right1(m_right),
.left1(m_left),
.down1(m_down),
.up1(m_up),
.fire2(m_fire),
.right2(m_right),
.left2(m_left),
.down2(m_down),
.up2(m_up)
);
mist_video #(.COLOR_DEPTH(5), .SD_HCNT_WIDTH(10)) mist_video(//Wrong Colors have no Idea
.clk_sys ( clock_48 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? r : 0 ),
.G ( blankn ? g : 0 ),
.B ( blankn ? b : 0 ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
// .ce_divider(0),
.rotate ( {1'b0,status[2]} ),
.scandoubler_disable( scandoublerD ),
.scanlines ( status[4:3] ),
.ypbpr ( ypbpr )
);
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
.clk_sys (clock_48 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(.C_bits(16))dac(
.clk_i(clock_48),
.res_n_i(1),
.dac_i({audio, 5'b00000}),
.dac_o(AUDIO_L)
);
wire m_up = ~status[2] ? btn_right | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
wire m_down = ~status[2] ? btn_left | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_up | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = ~status[2] ? btn_down | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
//wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
//reg btn_fire2 = 0;
//reg btn_fire3 = 0;
reg btn_coin = 0;
always @(posedge clock_48) begin
reg old_state;
old_state <= key_strobe;
if(old_state != key_strobe) begin
case(key_code)
'h75: btn_up <= key_pressed; // up
'h72: btn_down <= key_pressed; // down
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
// 'h14: btn_fire3 <= key_pressed; // ctrl
// 'h11: btn_fire2 <= key_pressed; // alt
'h29: btn_fire1 <= key_pressed; // Space
endcase
end
end
endmodule

210
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/TimePilot_MiST.sv
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@@ -1,210 +0,0 @@
//============================================================================
// Arcade: Time Pilot
//
// Port to MiST
// Copyright (C) 2017 Gehstock
//
// Time pilot by Dar (darfpga@aol.fr) (29/10/2017)
// http://darfpga.blogspot.fr
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module TimePilot_MiST(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"PSurge;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"T6,Reset;",
"V,v1.10.",`BUILD_DATE
};
assign LED = 1;
assign AUDIO_R = AUDIO_L;
wire clock_24, clock_14, clock_12, pix_ce;
wire pll_locked;
pll pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clock_24),//24,57600000
.c1(clock_14),//14.31800000
.c2(clock_12),//12.28800000
.locked(pll_locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [10:0] ps2_key;
reg [10:0] audio;
wire hb, vb;
wire blankn = ~(hb | vb);
wire ce_vid;
wire hs, vs;
wire [4:0] r,g,b;
time_pilot time_pilot(
.clock_12(clock_12),
.clock_14(clock_14),
.reset(status[0] | status[6] | buttons[1]),
.video_r(r),
.video_g(g),
.video_b(b),
.video_hblank(hb),
.video_vblank(vb),
.video_clk(pix_ce),
.video_hs(hs),
.video_vs(vs),
.audio_out(audio),
.dip_switch_1("11111111"), // Cabinet Unknown Lives Lives Initial_Energy Unknown Unknown Unknown
.dip_switch_2("11111010"), // Stop_at_Junctions Unknown Unknown Cheat Coin_B Coin_B Coin_A Coin_A
.start2(btn_two_players),
.start1(btn_one_player),
.coin1(btn_coin),
.fire1(m_fire),
.right1(m_right),
.left1(m_left),
.down1(m_down),
.up1(m_up),
.fire2(m_fire),
.right2(m_right),
.left2(m_left),
.down2(m_down),
.up2(m_up),
.dbg_cpu_addr()
);
video_mixer video_mixer(
.clk_sys(clock_24),
.ce_pix(pix_ce),
.ce_pix_actual(pix_ce),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? r[2:0] : "000"),
.G(blankn ? g[2:0] : "000"),
.B(blankn ? b[2:0] : "000"),
.HSync(hs),
.VSync(vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.rotate({1'b0,status[2]}),
.scandoublerD(scandoublerD),
.scanlines(scandoublerD ? 2'b00 : status[4:3]),
.ypbpr(ypbpr),
.ypbpr_full(1),
.line_start(0),
.mono(0)
);
mist_io #(
.STRLEN(($size(CONF_STR)>>3)))
mist_io(
.clk_sys (clock_24 ),
.conf_str (CONF_STR ),
.SPI_SCK (SPI_SCK ),
.CONF_DATA0 (CONF_DATA0 ),
.SPI_SS2 (SPI_SS2 ),
.SPI_DO (SPI_DO ),
.SPI_DI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoublerD (scandoublerD ),
.ypbpr (ypbpr ),
.ps2_key (ps2_key ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac dac(
.clk_i(clock_24),
.res_n_i(1),
.dac_i({"0000", audio}),
.dac_o(AUDIO_L)
);
// NORMAL ROTATED
wire m_up = btn_right | joystick_0[0] | joystick_1[0];// : btn_up | joystick_0[3] | joystick_1[3];
wire m_down = btn_left | joystick_0[1] | joystick_1[1];// : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = btn_up | joystick_0[3] | joystick_1[3];// : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = btn_down | joystick_0[2] | joystick_1[2];// : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
/*
wire m_up = status[2] ? btn_up & joystick_0[3] & joystick_1[3] : btn_right & joystick_0[0] & joystick_1[0];
wire m_down = status[2] ? btn_down & joystick_0[2] & joystick_1[2] : btn_left & joystick_0[1] & joystick_1[1];
wire m_left = status[2] ? btn_left & joystick_0[1] & joystick_1[1] : btn_up & joystick_0[3] & joystick_1[3];
wire m_right = status[2] ? btn_right & joystick_0[0] & joystick_1[0] : btn_down & joystick_0[2] & joystick_1[2];
*/
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
reg btn_fire3 = 0;
reg btn_coin = 0;
wire pressed = ps2_key[9];
wire [7:0] code = ps2_key[7:0];
always @(posedge clock_24) begin
reg old_state;
old_state <= ps2_key[10];
if(old_state != ps2_key[10]) begin
case(code)
'h75: btn_up <= pressed; // up
'h72: btn_down <= pressed; // down
'h6B: btn_left <= pressed; // left
'h74: btn_right <= pressed; // right
'h76: btn_coin <= pressed; // ESC
'h05: btn_one_player <= pressed; // F1
'h06: btn_two_players <= pressed; // F2
'h14: btn_fire3 <= pressed; // ctrl
'h11: btn_fire2 <= pressed; // alt
'h29: btn_fire1 <= pressed; // Space
endcase
end
end
endmodule

48
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/dac.vhd
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@@ -1,48 +0,0 @@
-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dac is
generic (
C_bits : integer := 15
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(C_bits-1 downto 0);
dac_o : out std_logic
);
end dac;
architecture rtl of dac is
signal sig_in: unsigned(C_bits downto 0);
begin
seq: process(clk_i, res_n_i)
begin
if res_n_i = '0' then
sig_in <= to_unsigned(2**C_bits, sig_in'length);
dac_o <= '0';
elsif rising_edge(clk_i) then
-- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
dac_o <= sig_in(C_bits);
end if;
end process seq;
end rtl;

454
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/hq2x.sv
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@@ -1,454 +0,0 @@
//
//
// Copyright (c) 2012-2013 Ludvig Strigeus
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <=1024 ? 9 : 10 )
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
wire [DWIDTH:0] out[2];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule
module hq2x_out #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input [1:0] rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input [1:0] wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
wire [DWIDTH:0] out[4];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
endmodule
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
input clock,
input [DWIDTH:0] data,
input [AWIDTH:0] rdaddress,
input [AWIDTH:0] wraddress,
input wren,
output [DWIDTH:0] q
);
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b(q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({(DWIDTH+1){1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = NUMWORDS,
altsyncram_component.numwords_b = NUMWORDS,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = AWIDTH+1,
altsyncram_component.widthad_b = AWIDTH+1,
altsyncram_component.width_a = DWIDTH+1,
altsyncram_component.width_b = DWIDTH+1,
altsyncram_component.width_byteena_a = 1;
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////////
module DiffCheck
(
input [17:0] rgb1,
input [17:0] rgb2,
output result
);
wire [5:0] r = rgb1[5:1] - rgb2[5:1];
wire [5:0] g = rgb1[11:7] - rgb2[11:7];
wire [5:0] b = rgb1[17:13] - rgb2[17:13];
wire [6:0] t = $signed(r) + $signed(b);
wire [6:0] gx = {g[5], g};
wire [7:0] y = $signed(t) + $signed(gx);
wire [6:0] u = $signed(r) - $signed(b);
wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
// if y is inside (-24..24)
wire y_inside = (y < 8'h18 || y >= 8'he8);
// if u is inside (-4, 4)
wire u_inside = (u < 7'h4 || u >= 7'h7c);
// if v is inside (-6, 6)
wire v_inside = (v < 8'h6 || v >= 8'hfA);
assign result = !(y_inside && u_inside && v_inside);
endmodule
module InnerBlend
(
input [8:0] Op,
input [5:0] A,
input [5:0] B,
input [5:0] C,
output [5:0] O
);
function [8:0] mul6x3;
input [5:0] op1;
input [2:0] op2;
begin
mul6x3 = 9'd0;
if(op2[0]) mul6x3 = mul6x3 + op1;
if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
end
endfunction
wire OpOnes = Op[4];
wire [8:0] Amul = mul6x3(A, Op[7:5]);
wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
wire [8:0] At = Amul;
wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
wire [9:0] Res = {At, 1'b0} + Bt + Ct;
assign O = Op[8] ? A : Res[9:4];
endmodule
module Blend
(
input [5:0] rule,
input disable_hq2x,
input [17:0] E,
input [17:0] A,
input [17:0] B,
input [17:0] D,
input [17:0] F,
input [17:0] H,
output [17:0] Result
);
reg [1:0] input_ctrl;
reg [8:0] op;
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
localparam AB = 2'b00;
localparam AD = 2'b01;
localparam DB = 2'b10;
localparam BD = 2'b11;
wire is_diff;
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
always @* begin
case({!is_diff, rule[5:2]})
1,17: {op, input_ctrl} = {BLEND1, AB};
2,18: {op, input_ctrl} = {BLEND1, DB};
3,19: {op, input_ctrl} = {BLEND1, BD};
4,20: {op, input_ctrl} = {BLEND2, DB};
5,21: {op, input_ctrl} = {BLEND2, AB};
6,22: {op, input_ctrl} = {BLEND2, AD};
8: {op, input_ctrl} = {BLEND0, 2'bxx};
9: {op, input_ctrl} = {BLEND0, 2'bxx};
10: {op, input_ctrl} = {BLEND0, 2'bxx};
11: {op, input_ctrl} = {BLEND1, AB};
12: {op, input_ctrl} = {BLEND1, AB};
13: {op, input_ctrl} = {BLEND1, AB};
14: {op, input_ctrl} = {BLEND1, DB};
15: {op, input_ctrl} = {BLEND1, BD};
24: {op, input_ctrl} = {BLEND2, DB};
25: {op, input_ctrl} = {BLEND5, DB};
26: {op, input_ctrl} = {BLEND6, DB};
27: {op, input_ctrl} = {BLEND2, DB};
28: {op, input_ctrl} = {BLEND4, DB};
29: {op, input_ctrl} = {BLEND5, DB};
30: {op, input_ctrl} = {BLEND3, BD};
31: {op, input_ctrl} = {BLEND3, DB};
default: {op, input_ctrl} = 11'bxx;
endcase
// Setting op[8] effectively disables HQ2X because blend will always return E.
if (disable_hq2x) op[8] = 1;
end
// Generate inputs to the inner blender. Valid combinations.
// 00: E A B
// 01: E A D
// 10: E D B
// 11: E B D
wire [17:0] Input1 = E;
wire [17:0] Input2 = !input_ctrl[1] ? A :
!input_ctrl[0] ? D : B;
wire [17:0] Input3 = !input_ctrl[0] ? B : D;
InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]);
InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]);
InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
(
input clk,
input ce_x4,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input [1:0] read_y,
input [AWIDTH+1:0] read_x,
output [DWIDTH:0] outpixel
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
localparam DWIDTH = HALF_DEPTH ? 8 : 17;
wire [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
reg [17:0] A, B, D, F, G, H;
reg [7:0] pattern, nextpatt;
reg [1:0] i;
reg [7:0] y;
wire curbuf = y[0];
reg prevbuf = 0;
wire iobuf = !curbuf;
wire diff0, diff1;
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
wire [17:0] blend_result;
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
reg Curr2_addr1;
reg [AWIDTH:0] Curr2_addr2;
wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
wire [DWIDTH:0] Curr2tmp;
reg [AWIDTH:0] wrin_addr2;
reg [DWIDTH:0] wrpix;
reg wrin_en;
function [17:0] h2rgb;
input [8:0] v;
begin
h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
end
endfunction
function [8:0] rgb2h;
input [17:0] v;
begin
rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
end
endfunction
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
(
.clk(clk),
.rdaddr(Curr2_addr2),
.rdbuf(Curr2_addr1),
.q(Curr2tmp),
.wraddr(wrin_addr2),
.wrbuf(iobuf),
.data(wrpix),
.wren(wrin_en)
);
reg [1:0] wrout_addr1;
reg [AWIDTH+1:0] wrout_addr2;
reg wrout_en;
reg [DWIDTH:0] wrdata;
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
(
.clk(clk),
.rdaddr(read_x),
.rdbuf(read_y),
.q(outpixel),
.wraddr(wrout_addr2),
.wrbuf(wrout_addr1),
.data(wrdata),
.wren(wrout_en)
);
always @(posedge clk) begin
reg [AWIDTH:0] offs;
reg old_reset_line;
reg old_reset_frame;
wrout_en <= 0;
wrin_en <= 0;
if(ce_x4) begin
pattern <= new_pattern;
if(~&offs) begin
if (i == 0) begin
Curr2_addr1 <= prevbuf;
Curr2_addr2 <= offs;
end
if (i == 1) begin
Prev2 <= Curr2;
Curr2_addr1 <= curbuf;
Curr2_addr2 <= offs;
end
if (i == 2) begin
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
wrpix <= inputpixel;
wrin_addr2 <= offs;
wrin_en <= 1;
end
if (i == 3) begin
offs <= offs + 1'd1;
end
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
else wrdata <= blend_result;
wrout_addr1 <= {curbuf, i[1]};
wrout_addr2 <= {offs, i[1]^i[0]};
wrout_en <= 1;
end
if(i==3) begin
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
{A, G} <= {Prev0, Next0};
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
{Prev0, Prev1} <= {Prev1, Prev2};
{Curr0, Curr1} <= {Curr1, Curr2};
{Next0, Next1} <= {Next1, Next2};
end else begin
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
{B, F, H, D} <= {F, H, D, B};
end
i <= i + 1'b1;
if(old_reset_line && ~reset_line) begin
old_reset_frame <= reset_frame;
offs <= 0;
i <= 0;
y <= y + 1'd1;
prevbuf <= curbuf;
if(old_reset_frame & ~reset_frame) begin
y <= 0;
prevbuf <= 0;
end
end
old_reset_line <= reset_line;
end
end
endmodule // Hq2x

530
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/mist_io.v
View File

@@ -1,530 +0,0 @@
//
// mist_io.v
//
// mist_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
// Copyright (c) 2015-2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
//
// Use buffer to access SD card. It's time-critical part.
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
// (Sorgelig)
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = clk_sys/(PS2DIV*2)
//
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
(
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
// Global clock. It should be around 100MHz (higher is better).
input clk_sys,
// Global SPI clock from ARM. 24MHz
input SPI_SCK,
input CONF_DATA0,
input SPI_SS2,
output SPI_DO,
input SPI_DI,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
// output reg [31:0] joystick_2,
// output reg [31:0] joystick_3,
// output reg [31:0] joystick_4,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoublerD,
output ypbpr,
output reg [31:0] status,
// SD config
input sd_conf,
input sd_sdhc,
output [1:0] img_mounted, // signaling that new image has been mounted
output reg [31:0] img_size, // size of image in bytes
// SD block level access
input [31:0] sd_lba,
input [1:0] sd_rd,
input [1:0] sd_wr,
output reg sd_ack,
output reg sd_ack_conf,
// SD byte level access. Signals for 2-PORT altsyncram.
output reg [8:0] sd_buff_addr,
output reg [7:0] sd_buff_dout,
input [7:0] sd_buff_din,
output reg sd_buff_wr,
// ps2 keyboard emulation
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
// ps2 alternative interface.
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
output reg [10:0] ps2_key = 0,
// [24] - toggles with every event
output reg [24:0] ps2_mouse = 0,
// ARM -> FPGA download
input ioctl_ce,
output reg ioctl_download = 0, // signal indicating an active download
output reg [7:0] ioctl_index, // menu index used to upload the file
output reg ioctl_wr = 0,
output reg [24:0] ioctl_addr,
output reg [7:0] ioctl_dout
);
reg [7:0] but_sw;
reg [2:0] stick_idx;
reg [1:0] mount_strobe = 0;
assign img_mounted = mount_strobe;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoublerD = but_sw[4];
assign ypbpr = but_sw[5];
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire drive_sel = sd_rd[1] | sd_wr[1];
wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [9:0] byte_cnt; // counts bytes
reg spi_do;
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
reg [7:0] spi_data_out;
// SPI transmitter
always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
reg [7:0] spi_data_in;
reg spi_data_ready = 0;
// SPI receiver
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
reg [6:0] sbuf;
reg [31:0] sd_lba_r;
reg drive_sel_r;
if(CONF_DATA0) begin
bit_cnt <= 0;
byte_cnt <= 0;
spi_data_out <= core_type;
end
else
begin
bit_cnt <= bit_cnt + 1'd1;
sbuf <= {sbuf[5:0], SPI_DI};
// finished reading command byte
if(bit_cnt == 7) begin
if(!byte_cnt) cmd <= {sbuf, SPI_DI};
spi_data_in <= {sbuf, SPI_DI};
spi_data_ready <= ~spi_data_ready;
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
spi_data_out <= 0;
case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
// reading config string
8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
// reading sd card status
8'h16: if(byte_cnt == 0) begin
spi_data_out <= sd_cmd;
sd_lba_r <= sd_lba;
drive_sel_r <= drive_sel;
end else if (byte_cnt == 1) begin
spi_data_out <= drive_sel_r;
end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
// reading sd card write data
8'h18: spi_data_out <= sd_buff_din;
endcase
end
end
end
reg [31:0] ps2_key_raw = 0;
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
// transfer to clk_sys domain
always@(posedge clk_sys) begin
reg old_ss1, old_ss2;
reg old_ready1, old_ready2;
reg [2:0] b_wr;
reg got_ps2 = 0;
old_ss1 <= CONF_DATA0;
old_ss2 <= old_ss1;
old_ready1 <= spi_data_ready;
old_ready2 <= old_ready1;
sd_buff_wr <= b_wr[0];
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
b_wr <= (b_wr<<1);
if(old_ss2) begin
got_ps2 <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
sd_buff_addr <= 0;
if(got_ps2) begin
if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24];
if(cmd == 5) begin
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
end
end
end
else
if(old_ready2 ^ old_ready1) begin
if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
if(byte_cnt < 2) begin
if (cmd == 8'h19) sd_ack_conf <= 1;
if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
mount_strobe <= 0;
if(cmd == 5) ps2_key_raw <= 0;
end else begin
case(cmd)
// buttons and switches
8'h01: but_sw <= spi_data_in;
8'h02: joystick_0 <= spi_data_in;
8'h03: joystick_1 <= spi_data_in;
// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
// store incoming ps2 mouse bytes
8'h04: begin
got_ps2 <= 1;
case(byte_cnt)
2: ps2_mouse[7:0] <= spi_data_in;
3: ps2_mouse[15:8] <= spi_data_in;
4: ps2_mouse[23:16] <= spi_data_in;
endcase
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in;
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
end
// store incoming ps2 keyboard bytes
8'h05: begin
got_ps2 <= 1;
ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in};
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in;
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
end
8'h15: status[7:0] <= spi_data_in;
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
8'h19,
// send sector IO -> FPGA
// flag that download begins
8'h17: begin
sd_buff_dout <= spi_data_in;
b_wr <= 1;
end
// joystick analog
8'h1a: begin
// first byte is joystick index
if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
else if(byte_cnt == 3) begin
// second byte is x axis
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
end else if(byte_cnt == 4) begin
// third byte is y axis
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
end
end
// notify image selection
8'h1c: mount_strobe[spi_data_in[0]] <= 1;
// send image info
8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
// status, 32bit version
8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
default: ;
endcase
end
end
end
/////////////////////////////// PS2 ///////////////////////////////
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
reg clk_ps2;
always @(negedge clk_sys) begin
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
clk_ps2 <= ~clk_ps2;
cnt <= 0;
end
end
// keyboard
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_kbd_tx_state;
reg [7:0] ps2_kbd_tx_byte;
reg ps2_kbd_parity;
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_kbd_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_kbd_r_inc <= 0;
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
// transmitter is idle?
if(ps2_kbd_tx_state == 0) begin
// data in fifo present?
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
// load tx register from fifo
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
ps2_kbd_r_inc <= 1;
// reset parity
ps2_kbd_parity <= 1;
// start transmitter
ps2_kbd_tx_state <= 1;
// put start bit on data line
ps2_kbd_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
if(ps2_kbd_tx_byte[0])
ps2_kbd_parity <= !ps2_kbd_parity;
end
// transmission of parity
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
// transmission of stop bit
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
// advance state machine
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
else ps2_kbd_tx_state <= 0;
end
end
end
// mouse
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_mouse_tx_state;
reg [7:0] ps2_mouse_tx_byte;
reg ps2_mouse_parity;
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_mouse_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_mouse_r_inc <= 0;
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
// transmitter is idle?
if(ps2_mouse_tx_state == 0) begin
// data in fifo present?
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
// load tx register from fifo
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
ps2_mouse_r_inc <= 1;
// reset parity
ps2_mouse_parity <= 1;
// start transmitter
ps2_mouse_tx_state <= 1;
// put start bit on data line
ps2_mouse_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
if(ps2_mouse_tx_byte[0])
ps2_mouse_parity <= !ps2_mouse_parity;
end
// transmission of parity
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
// transmission of stop bit
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
// advance state machine
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
else ps2_mouse_tx_state <= 0;
end
end
end
/////////////////////////////// DOWNLOADING ///////////////////////////////
reg [7:0] data_w;
reg [24:0] addr_w;
reg rclk = 0;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
reg rdownload = 0;
// data_io has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS2) begin
reg [6:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [24:0] addr;
if(SPI_SS2) cnt <= 0;
else begin
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
// finished command byte
if(cnt == 7) cmd <= {sbuf, SPI_DI};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
case(ioctl_index[4:0])
1: addr <= 25'h200000; // TRD buffer at 2MB
2: addr <= 25'h400000; // tape buffer at 4MB
default: addr <= 25'h150000; // boot rom
endcase
rdownload <= 1;
end else begin
addr_w <= addr;
rdownload <= 0;
end
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
addr_w <= addr;
data_w <= {sbuf, SPI_DI};
addr <= addr + 1'd1;
rclk <= ~rclk;
end
// expose file (menu) index
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
end
end
// transfer to ioctl_clk domain.
// ioctl_index is set before ioctl_download, so it's stable already
always@(posedge clk_sys) begin
reg rclkD, rclkD2;
if(ioctl_ce) begin
ioctl_download <= rdownload;
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wr <= 0;
if(rclkD != rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wr <= 1;
end
end
end
endmodule

194
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/osd.v
View File

@@ -1,194 +0,0 @@
// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input clk_sys,
// SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
input [1:0] rotate, //[0] - rotate [1] - left or right
// VGA signals coming from core
input [5:0] R_in,
input [5:0] G_in,
input [5:0] B_in,
input HSync,
input VSync,
// VGA signals going to video connector
output [5:0] R_out,
output [5:0] G_out,
output [5:0] B_out
);
parameter OSD_X_OFFSET = 10'd0;
parameter OSD_Y_OFFSET = 10'd0;
parameter OSD_COLOR = 3'd0;
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS3) begin
reg [4:0] cnt;
reg [10:0] bcnt;
reg [7:0] sbuf;
reg [7:0] cmd;
if(SPI_SS3) begin
cnt <= 0;
bcnt <= 0;
end else begin
sbuf <= {sbuf[6:0], SPI_DI};
// 0:7 is command, rest payload
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], SPI_DI};
// lower three command bits are line address
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
bcnt <= bcnt + 1'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [9:0] h_cnt;
reg [9:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
// vertical counter
reg [9:0] v_cnt;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
wire doublescan = (dsp_height>350);
reg ce_pix;
always @(negedge clk_sys) begin
integer cnt = 0;
integer pixsz, pixcnt;
reg hs;
cnt <= cnt + 1;
hs <= HSync;
pixcnt <= pixcnt + 1;
if(pixcnt == pixsz) pixcnt <= 0;
ce_pix <= !pixcnt;
if(hs && ~HSync) begin
cnt <= 0;
pixsz <= (cnt >> 9) - 1;
pixcnt <= 0;
ce_pix <= 1;
end
end
always @(posedge clk_sys) begin
reg hsD, hsD2;
reg vsD, vsD2;
if(ce_pix) begin
// bring hsync into local clock domain
hsD <= HSync;
hsD2 <= hsD;
// falling edge of HSync
if(!hsD && hsD2) begin
h_cnt <= 0;
hs_high <= h_cnt;
end
// rising edge of HSync
else if(hsD && !hsD2) begin
h_cnt <= 0;
hs_low <= h_cnt;
v_cnt <= v_cnt + 1'd1;
end else begin
h_cnt <= h_cnt + 1'd1;
end
vsD <= VSync;
vsD2 <= vsD;
// falling edge of VSync
if(!vsD && vsD2) begin
v_cnt <= 0;
vs_high <= v_cnt;
end
// rising edge of VSync
else if(vsD && !vsD2) begin
v_cnt <= 0;
vs_low <= v_cnt;
end
end
end
// area in which OSD is being displayed
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
wire [9:0] osd_hcnt = h_cnt - h_osd_start;
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
wire [9:0] osd_hcnt_next = osd_hcnt + 2'd1; // one pixel offset for osd pixel
wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2; // two pixel offset for osd byte address register
wire osd_de = osd_enable &&
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
reg [10:0] osd_buffer_addr;
wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
reg osd_pixel;
always @(posedge clk_sys) begin
if(ce_pix) begin
osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
(doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} :
{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
end
end
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
endmodule

4
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/pll.qip
View File

@@ -1,4 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

69
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/pll.v
View File

@@ -37,26 +37,17 @@
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
c1,
c2,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
@@ -72,11 +63,11 @@ module pll (
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire6),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
@@ -111,17 +102,17 @@ module pll (
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 78,
altpll_component.clk0_divide_by = 26,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 71,
altpll_component.clk0_multiply_by = 47,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 134,
altpll_component.clk1_divide_by = 104,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 71,
altpll_component.clk1_multiply_by = 47,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 156,
altpll_component.clk2_divide_by = 395,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 71,
altpll_component.clk2_multiply_by = 208,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
@@ -131,7 +122,7 @@ module pll (
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
@@ -196,15 +187,15 @@ endmodule
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "134"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "156"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "26"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "104"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "395"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.305970"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.288462"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.807693"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.201923"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "14.217722"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -231,13 +222,13 @@ endmodule
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "71"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "71"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "47"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "47"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "208"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57627100"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.31800000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.28800000"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.78400000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.19600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "14.22800000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
@@ -252,9 +243,9 @@ endmodule
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
@@ -290,17 +281,17 @@ endmodule
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "26"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "47"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "134"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "104"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "71"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "47"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "156"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "395"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "71"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "208"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
@@ -309,7 +300,7 @@ endmodule
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
@@ -352,13 +343,11 @@ endmodule
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0

103
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot.vhd → Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/power_surge.vhd
View File

@@ -79,7 +79,7 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity time_pilot is
entity power_surge is
port(
clock_12 : in std_logic;
clock_14 : in std_logic;
@@ -93,7 +93,9 @@ port(
video_hs : out std_logic;
video_vs : out std_logic;
audio_out : out std_logic_vector(10 downto 0);
roms_addr : out std_logic_vector(14 downto 0);
roms_do : in std_logic_vector(7 downto 0);
roms_rd : out std_logic;
dip_switch_1 : in std_logic_vector(7 downto 0); -- Coinage_B / Coinage_A
dip_switch_2 : in std_logic_vector(7 downto 0); -- Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1)
@@ -111,13 +113,11 @@ port(
right2 : in std_logic;
left2 : in std_logic;
down2 : in std_logic;
up2 : in std_logic;
dbg_cpu_addr : out std_logic_vector(15 downto 0)
up2 : in std_logic
);
end time_pilot;
end power_surge;
architecture struct of time_pilot is
architecture struct of power_surge is
signal reset_n: std_logic;
signal clock_12n : std_logic;
@@ -160,7 +160,7 @@ architecture struct of time_pilot is
signal ch_pixel_bit2 : std_logic;
signal ch_color_set : std_logic_vector(4 downto 0);
signal ch_palette_addr : std_logic_vector(7 downto 0);
signal ch_palette_do : std_logic_vector(3 downto 0);
signal ch_palette_do : std_logic_vector(7 downto 0);
signal spram_addr : std_logic_vector(7 downto 0);
signal spram1_we : std_logic;
@@ -178,7 +178,7 @@ architecture struct of time_pilot is
signal sp_pixels : std_logic_vector(7 downto 0);
signal sp_color_set : std_logic_vector(5 downto 0);
signal sp_palette_addr : std_logic_vector(7 downto 0);
signal sp_palette_do : std_logic_vector(3 downto 0);
signal sp_palette_do : std_logic_vector(7 downto 0);
signal sp_read_out : std_logic_vector(3 downto 0);
signal sp_blank : std_logic;
@@ -220,14 +220,6 @@ clock_12n <= not clock_12;
clock_6n <= not clock_6;
reset_n <= not reset;
-- debug
process (reset, clock_12)
begin
if rising_edge(clock_12) and cpu_ena ='1' and cpu_mreq_n ='0' then
dbg_cpu_addr <= cpu_addr;
end if;
end process;
-- make 6MHz clock from 12MHz
process (clock_12)
begin
@@ -299,12 +291,11 @@ input_1 <= "111" & not fire1 & not down1 & not up1 & not right1 & not le
input_2 <= "111" & not fire2 & not down2 & not up2 & not right2 & not left2; -- ?/2FL/2SR/2SL/2DW/2UP/2RI/2LE
-- cpu input address decoding (mirror mostly from Mame)
cpu_di <= cpu_rom_do when cpu_addr(15 downto 0) < X"6" else -- 0000-5FFF 011000 00000 00000
cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) < X"6" else -- 0000-5FFF
X"80" when cpu_addr(14 downto 0) = X"6" and
cpu_addr(2 downto 0) = "100" else -- 6004 Protection 110000000000100
X"80" when cpu_addr(15 downto 0) = "0110000000000100" else -- 6004 Protection
wram_do when cpu_addr(15 downto 12) = X"A" else -- A000-AFFF
spram1_do when cpu_addr(15 downto 12) = X"B" and
@@ -352,15 +343,9 @@ spram_addr <= cpu_addr(7 downto 0) when cpu_ena = '1' else "00" & spcnt & pxcnt(
wram_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"A" else '0';
spram1_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"B" and cpu_addr(10) = '0' else '0';
spram2_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"B" and cpu_addr(10) = '1' else '0';
C0xx_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"C" and cpu_addr(9 downto 8) = "00" else '0';
C0xx_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 8) = "11000000" else '0';
C3xx_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"C" and cpu_addr(9 downto 8) = "11" else '0';
-- Misc registers : interrupt enable/clear, cocktail flip, sound trigger
-- m_mainlatch->q_out_cb<0>().set_nop();
-- m_mainlatch->q_out_cb<4>().set_nop();
-- m_mainlatch->q_out_cb<5>().set_nop();
-- m_mainlatch->q_out_cb<6>().set_nop();
process (clock_6)
begin
if rising_edge(clock_6) then
@@ -369,12 +354,12 @@ begin
end if;
if C3xx_we = '1' then
-- if cpu_addr(3 downto 1) = "000" then itt_n <= cpu_do; end if;
if cpu_addr(3 downto 1) = "000" then itt_n <= cpu_do; end if;
if cpu_addr(3 downto 1) = "001" then flip <= not cpu_do(0); end if;
if cpu_addr(3 downto 1) = "010" then sound_trig <= cpu_do(0); end if;
end if;
cpu_nmi_n <= vblank;
--cpu_int_n
cpu_int_n <= '1';
-- if itt_n(0) = '0' then
-- cpu_nmi_n <= '1';
-- else -- lauch nmi and end of frame
@@ -476,7 +461,7 @@ begin
end process;
-- write colors to buffer when not transparent
sp_buffer_write_we <= '0' when sp_palette_do = "0000" else '1';
sp_buffer_write_we <= '0' when sp_palette_do(3 downto 0) = "0000" else '1';
-- read sprite line buffer and erase after read
process (clock_12)
@@ -511,8 +496,8 @@ end process;
sp_buffer_ram1_addr <= sp_buffer_read_addr when sp_buffer_sel = '0' else sp_buffer_write_addr;
sp_buffer_ram2_addr <= sp_buffer_read_addr when sp_buffer_sel = '1' else sp_buffer_write_addr;
sp_buffer_ram1_di <= "0000" when sp_buffer_sel = '0' else sp_palette_do;
sp_buffer_ram2_di <= "0000" when sp_buffer_sel = '1' else sp_palette_do;
sp_buffer_ram1_di <= "0000" when sp_buffer_sel = '0' else sp_palette_do(3 downto 0);
sp_buffer_ram2_di <= "0000" when sp_buffer_sel = '1' else sp_palette_do(3 downto 0);
sp_buffer_ram1_we <= not clock_6 when sp_buffer_sel = '0' else sp_buffer_write_we;
sp_buffer_ram2_we <= not clock_6 when sp_buffer_sel = '1' else sp_buffer_write_we;
@@ -583,7 +568,7 @@ end process;
-- select rbg color and bank with respect to char/sprite selection
rgb_palette_addr <=
'1' & ch_palette_do when (sp_read_out = "0000" or sp_blank = '1') else
'1' & ch_palette_do(3 downto 0) when (sp_read_out = "0000" or sp_blank = '1') else
'0' & sp_read_out;
-- register and assign rbg palette output
@@ -629,7 +614,7 @@ begin
if hcnt = hcnt_base-4 then
hblank <= '1';
if vcnt = 490 then
if vcnt = 496 then
vblank <= '1'; -- 492 ok
elsif vcnt = 262 then
vblank <= '0'; -- 262 ok
@@ -675,13 +660,19 @@ port map(
DO => cpu_do
);
roms_addr <= cpu_addr(14 downto 0);
cpu_rom_do <= roms_do;
roms_rd <= '1';
-- cpu1 program ROM
rom_cpu1 : entity work.time_pilot_prog
port map(
clk => clock_6n,
addr => cpu_addr(14 downto 0),
data => cpu_rom_do
);
--rom_cpu1 : entity work.power_surge_prog
--port map(
-- clk => clock_6n,
-- addr => cpu_addr(14 downto 0),
-- data => cpu_rom_do
--);
-- working/char RAM 0xA000-0xAFFF
wram : entity work.gen_ram
@@ -739,7 +730,7 @@ port map(
);
-- char graphics ROM
char_graphics : entity work.time_pilot_char_grphx
char_graphics : entity work.power_surge_char_grphx
port map(
clk => clock_6,
addr => ch_graphx_addr,
@@ -747,7 +738,7 @@ port map(
);
-- char palette ROM
ch_palette : entity work.time_pilot_char_color_lut
ch_palette : entity work.power_surge_char_color_lut
port map(
clk => clock_6,
addr => ch_palette_addr,
@@ -755,7 +746,7 @@ port map(
);
-- sprite graphics ROM
sp_graphics : entity work.time_pilot_sprite_grphx
sp_graphics : entity work.power_surge_sprite_grphx
port map(
clk => clock_6,
addr => sp_graphx_addr,
@@ -763,7 +754,7 @@ port map(
);
-- sprite palette ROM
sp_palette : entity work.time_pilot_sprite_color_lut
sp_palette : entity work.power_surge_sprite_color_lut
port map(
clk => clock_6,
addr => sp_palette_addr,
@@ -771,7 +762,7 @@ port map(
);
-- rgb palette ROM 1
rgb_palette_gb : entity work.time_pilot_palette_blue_green
rgb_palette_gb : entity work.power_surge_palette_blue_green
port map(
clk => clock_6,
addr => rgb_palette_addr,
@@ -779,7 +770,7 @@ port map(
);
-- rgb palette ROM 2
rgb_palette_br : entity work.time_pilot_palette_green_red
rgb_palette_br : entity work.power_surge_palette_green_red
port map(
clk => clock_6,
addr => rgb_palette_addr,
@@ -787,17 +778,15 @@ port map(
);
-- sound board
--time_pilot_sound_board : entity work.time_pilot_sound_board
--port map(
--clock_14 => clock_14,
--reset => reset,
time_pilot_sound_board : entity work.time_pilot_sound_board
port map(
clock_14 => clock_14,
reset => reset,
--sound_trig => sound_trig,
--sound_cmd => sound_cmd,
sound_trig => sound_trig,
sound_cmd => sound_cmd,
--audio_out => audio_out,
--dbg_cpu_addr => open
--);
audio_out => audio_out
);
end struct;

19
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/gen/make_power_surge_proms.bat Normal file
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@@ -0,0 +1,19 @@
copy /B p1 + p2 + p3 power_surge_prog.bin
make_vhdl_prom power_surge_prog.bin power_surge_prog.vhd
copy /B p6 + p7 power_surge_sound.bin
make_vhdl_prom power_surge_sound.bin power_surge_sound_prog.vhd
make_vhdl_prom p4 power_surge_char_grphx.vhd
copy /B p5 + tm5 power_surge_sprite_grphx.bin
make_vhdl_prom power_surge_sprite_grphx.bin power_surge_sprite_grphx.vhd
make_vhdl_prom timeplt.b4 power_surge_palette_blue_green.vhd
make_vhdl_prom timeplt.b5 power_surge_palette_green_red.vhd
make_vhdl_prom timeplt.e9 power_surge_sprite_color_lut.vhd
make_vhdl_prom timeplt.e12 power_surge_char_color_lut.vhd
pause

0
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/make_vhdl_prom.exe → Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/gen/make_vhdl_prom.exe
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BIN
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/psurge.zip → Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/gen/psurge.zip
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18
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/make_time_pilot_proms.bat
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@@ -1,18 +0,0 @@
copy /B p1 + p2 + p3 time_pilot_prog.bin
make_vhdl_prom time_pilot_prog.bin time_pilot_prog.vhd
copy /B p6 + p7 time_pilot_sound.bin
make_vhdl_prom time_pilot_sound.bin time_pilot_sound_prog.vhd
make_vhdl_prom p4 time_pilot_char_grphx.vhd
copy /B p5 + tm5 time_pilot_sprite_grphx.bin
make_vhdl_prom time_pilot_sprite_grphx.bin time_pilot_sprite_grphx.vhd
make_vhdl_prom timeplt.b4 time_pilot_palette_blue_green.vhd
make_vhdl_prom timeplt.b5 time_pilot_palette_green_red.vhd
make_vhdl_prom timeplt.e9 time_pilot_sprite_color_lut.vhd
make_vhdl_prom timeplt.e12 time_pilot_char_color_lut.vhd

BIN
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/p1
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BIN
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/p2
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BIN
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/p3
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BIN
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/p4
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BIN
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/p5
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BIN
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/p6
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Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/p7
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38
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_char_color_lut.vhd Normal file
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@@ -0,0 +1,38 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity power_surge_char_color_lut is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of power_surge_char_color_lut is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"0D",X"0F",X"0C",X"0A",X"04",X"01",X"0F",X"0B",X"04",X"01",X"0F",X"0C",X"04",X"01",X"0F",
X"0E",X"04",X"01",X"0F",X"00",X"04",X"01",X"0F",X"0A",X"04",X"05",X"01",X"0B",X"04",X"05",X"01",
X"0C",X"04",X"05",X"01",X"0E",X"04",X"05",X"01",X"00",X"04",X"05",X"01",X"0A",X"06",X"08",X"02",
X"0B",X"06",X"08",X"02",X"0C",X"06",X"08",X"02",X"0E",X"06",X"08",X"02",X"00",X"06",X"08",X"02",
X"00",X"01",X"04",X"0F",X"00",X"04",X"02",X"06",X"00",X"01",X"08",X"04",X"00",X"0D",X"01",X"05",
X"00",X"02",X"03",X"01",X"00",X"0C",X"0F",X"03",X"00",X"05",X"02",X"08",X"0A",X"01",X"04",X"03",
X"00",X"06",X"0F",X"02",X"00",X"0F",X"03",X"05",X"00",X"03",X"01",X"0F",X"0A",X"02",X"0D",X"05",
X"00",X"01",X"0F",X"08",X"0A",X"02",X"0D",X"05",X"0A",X"0B",X"09",X"0F",X"09",X"09",X"09",X"09",
X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

4
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_char_grphx.vhd → Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_char_grphx.vhd
View File

@@ -1,7 +1,7 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity time_pilot_char_grphx is
entity power_surge_char_grphx is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
@@ -9,7 +9,7 @@ port (
);
end entity;
architecture prom of time_pilot_char_grphx is
architecture prom of power_surge_char_grphx is
type rom is array(0 to 8191) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",

4
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_palette_blue_green.vhd → Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_palette_blue_green.vhd
View File

@@ -1,7 +1,7 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity time_pilot_palette_blue_green is
entity power_surge_palette_blue_green is
port (
clk : in std_logic;
addr : in std_logic_vector(4 downto 0);
@@ -9,7 +9,7 @@ port (
);
end entity;
architecture prom of time_pilot_palette_blue_green is
architecture prom of power_surge_palette_blue_green is
type rom is array(0 to 31) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"05",X"06",X"07",X"FC",X"05",X"BD",X"B5",X"FD",X"05",X"B0",X"A5",X"E0",X"00",X"F7",

4
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_palette_green_red.vhd → Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_palette_green_red.vhd
View File

@@ -1,7 +1,7 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity time_pilot_palette_green_red is
entity power_surge_palette_green_red is
port (
clk : in std_logic;
addr : in std_logic_vector(4 downto 0);
@@ -9,7 +9,7 @@ port (
);
end entity;
architecture prom of time_pilot_palette_green_red is
architecture prom of power_surge_palette_green_red is
type rom is array(0 to 31) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"3E",X"3E",X"80",X"FE",X"00",X"AC",X"EE",X"AC",X"C0",X"14",X"00",X"28",X"38",X"16",X"BC",

4
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_prog.vhd → Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_prog.vhd
View File

@@ -1,7 +1,7 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity time_pilot_prog is
entity power_surge_prog is
port (
clk : in std_logic;
addr : in std_logic_vector(14 downto 0);
@@ -9,7 +9,7 @@ port (
);
end entity;
architecture prom of time_pilot_prog is
architecture prom of power_surge_prog is
type rom is array(0 to 24575) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"F3",X"C3",X"00",X"30",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",

215
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_sound_prog.vhd → Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_sound_prog.vhd
View File

@@ -1,7 +1,7 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity time_pilot_sound_prog2 is
entity power_surge_sound_prog is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
@@ -9,8 +9,8 @@ port (
);
end entity;
architecture prom of time_pilot_sound_prog2 is
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
architecture prom of power_surge_sound_prog is
type rom is array(0 to 8191) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"21",X"00",X"30",X"06",X"00",X"C3",X"7C",X"01",X"32",X"00",X"50",X"3A",X"00",X"40",X"C9",X"FF",
X"32",X"00",X"70",X"3A",X"00",X"60",X"C9",X"FF",X"78",X"CF",X"79",X"32",X"00",X"40",X"C9",X"FF",
@@ -316,7 +316,214 @@ architecture prom of time_pilot_sound_prog2 is
X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"B7",X"60",
X"75",X"73",X"72",X"70",X"2F",X"2F",X"2F",X"2F",X"2F",X"2F",X"2F",X"2F",X"30",X"30",X"30",X"30",
X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"B0",X"FF",X"FF",X"1F",
X"0E",X"3F",X"07",X"5F",X"09",X"7F",X"00",X"22",X"23",X"24",X"25",X"26",X"27",X"28",X"29",X"2A");
X"0E",X"3F",X"07",X"5F",X"09",X"7F",X"00",X"22",X"23",X"24",X"25",X"26",X"27",X"28",X"29",X"2A",
X"2B",X"2C",X"2D",X"AE",X"FF",X"1F",X"0E",X"3F",X"07",X"5F",X"09",X"26",X"27",X"28",X"29",X"2A",
X"2B",X"2C",X"2D",X"2E",X"2F",X"30",X"31",X"B2",X"FF",X"1F",X"08",X"3F",X"07",X"5F",X"08",X"A2",
X"FF",X"1F",X"0D",X"3F",X"0C",X"5F",X"07",X"7F",X"00",X"4D",X"40",X"60",X"55",X"40",X"60",X"FF",
X"1F",X"01",X"5F",X"05",X"4D",X"40",X"60",X"80",X"FF",X"FF",X"1F",X"0E",X"3F",X"0C",X"5F",X"07",
X"7F",X"00",X"4D",X"40",X"60",X"55",X"40",X"60",X"FF",X"1F",X"02",X"5F",X"05",X"4D",X"40",X"60",
X"80",X"FF",X"FF",X"1F",X"02",X"3F",X"07",X"5F",X"05",X"7F",X"00",X"AA",X"A9",X"20",X"28",X"28",
X"28",X"28",X"20",X"29",X"29",X"29",X"29",X"20",X"28",X"28",X"28",X"28",X"20",X"A3",X"FF",X"FF",
X"FF",X"1F",X"02",X"3F",X"09",X"5F",X"05",X"7F",X"00",X"AA",X"A9",X"20",X"28",X"28",X"28",X"28",
X"20",X"29",X"29",X"29",X"29",X"20",X"28",X"28",X"28",X"28",X"20",X"A3",X"FF",X"FF",X"FF",X"1F",
X"02",X"3F",X"0A",X"5F",X"05",X"7F",X"00",X"AA",X"A9",X"20",X"28",X"28",X"28",X"28",X"20",X"29",
X"29",X"29",X"29",X"20",X"28",X"28",X"28",X"28",X"20",X"A3",X"FF",X"FF",X"FF",X"1F",X"0E",X"3F",
X"0A",X"5F",X"09",X"7F",X"02",X"2E",X"2E",X"2E",X"2E",X"2E",X"2E",X"2E",X"2E",X"2F",X"2F",X"2F",
X"2F",X"2F",X"2F",X"2F",X"2F",X"32",X"32",X"32",X"32",X"32",X"32",X"32",X"32",X"33",X"33",X"33",
X"33",X"33",X"33",X"33",X"33",X"32",X"32",X"32",X"32",X"32",X"32",X"32",X"32",X"2F",X"2F",X"2F",
X"2F",X"2F",X"2F",X"2F",X"2F",X"2E",X"2E",X"2E",X"2E",X"2E",X"2E",X"2E",X"2E",X"2C",X"2C",X"2C",
X"2C",X"2C",X"2C",X"2C",X"2C",X"6E",X"6F",X"6E",X"6F",X"6E",X"6F",X"6E",X"6F",X"AE",X"FF",X"1F",
X"02",X"3F",X"0A",X"5F",X"09",X"2E",X"2E",X"2E",X"2E",X"2E",X"2E",X"2E",X"2E",X"2F",X"2F",X"2F",
X"2F",X"2F",X"2F",X"2F",X"2F",X"32",X"32",X"32",X"32",X"32",X"32",X"32",X"32",X"33",X"33",X"33",
X"33",X"33",X"33",X"33",X"33",X"32",X"32",X"32",X"32",X"32",X"32",X"32",X"32",X"2F",X"2F",X"2F",
X"2F",X"2F",X"2F",X"2F",X"2F",X"2E",X"2E",X"2E",X"2E",X"2E",X"2E",X"2E",X"2E",X"2C",X"2C",X"2C",
X"2C",X"2C",X"2C",X"2C",X"2C",X"6E",X"6F",X"6E",X"6F",X"6E",X"6F",X"6E",X"6F",X"AE",X"FF",X"FF",
X"1F",X"0E",X"3F",X"0A",X"5F",X"09",X"7F",X"02",X"72",X"6F",X"6A",X"66",X"72",X"6F",X"6A",X"66",
X"70",X"6D",X"68",X"64",X"70",X"6D",X"68",X"64",X"72",X"6F",X"6A",X"66",X"72",X"6F",X"6A",X"66",
X"70",X"6D",X"68",X"64",X"70",X"6D",X"68",X"64",X"6F",X"70",X"6F",X"70",X"3F",X"05",X"B2",X"FF",
X"1F",X"0E",X"5F",X"00",X"60",X"5F",X"09",X"72",X"6F",X"6A",X"60",X"72",X"6F",X"6A",X"60",X"70",
X"6D",X"68",X"60",X"70",X"6D",X"68",X"60",X"72",X"6F",X"6A",X"60",X"72",X"6F",X"6A",X"60",X"70",
X"6D",X"68",X"60",X"70",X"6D",X"68",X"1F",X"08",X"6B",X"6D",X"6B",X"6D",X"AF",X"FF",X"FF",X"1F",
X"0E",X"3F",X"0B",X"5F",X"09",X"7F",X"00",X"77",X"75",X"73",X"72",X"70",X"6E",X"6D",X"6B",X"A9",
X"FF",X"1F",X"08",X"3F",X"0B",X"5F",X"08",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",
X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",
X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",
X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"B0",X"AD",X"FF",X"1F",X"08",X"3F",X"0B",X"5F",X"08",
X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",
X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",
X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",X"2B",
X"AB",X"A9",X"FF",X"3A",X"82",X"30",X"3C",X"32",X"82",X"30",X"47",X"3A",X"83",X"30",X"A0",X"20",
X"23",X"3A",X"85",X"30",X"3D",X"32",X"85",X"30",X"20",X"1A",X"3A",X"84",X"30",X"47",X"3A",X"86",
X"30",X"80",X"32",X"84",X"30",X"32",X"85",X"30",X"3A",X"87",X"30",X"3D",X"32",X"87",X"30",X"28",
X"05",X"CD",X"79",X"15",X"AF",X"C9",X"3E",X"FF",X"C9",X"06",X"00",X"3A",X"88",X"30",X"4F",X"3A",
X"89",X"30",X"57",X"1E",X"08",X"21",X"8C",X"30",X"3E",X"08",X"32",X"00",X"50",X"7E",X"E6",X"0F",
X"32",X"00",X"40",X"23",X"1D",X"28",X"0E",X"04",X"78",X"A1",X"20",X"FB",X"15",X"20",X"F8",X"3A",
X"89",X"30",X"57",X"18",X"E3",X"3A",X"8B",X"30",X"3D",X"C8",X"32",X"8B",X"30",X"3A",X"89",X"30",
X"47",X"3A",X"8A",X"30",X"80",X"32",X"89",X"30",X"C9",X"3A",X"82",X"30",X"3C",X"32",X"82",X"30",
X"47",X"3A",X"83",X"30",X"A0",X"20",X"23",X"3A",X"85",X"30",X"3D",X"32",X"85",X"30",X"20",X"1A",
X"3A",X"84",X"30",X"47",X"3A",X"86",X"30",X"80",X"32",X"84",X"30",X"32",X"85",X"30",X"3A",X"87",
X"30",X"3D",X"32",X"87",X"30",X"28",X"05",X"CD",X"EF",X"15",X"AF",X"C9",X"3E",X"FF",X"C9",X"06",
X"00",X"3A",X"88",X"30",X"4F",X"3A",X"89",X"30",X"57",X"1E",X"04",X"21",X"8C",X"30",X"3E",X"08",
X"32",X"00",X"50",X"7E",X"E6",X"0F",X"32",X"00",X"40",X"23",X"1D",X"28",X"0E",X"04",X"78",X"A1",
X"20",X"FB",X"15",X"20",X"F8",X"3A",X"89",X"30",X"57",X"18",X"E3",X"3A",X"8B",X"30",X"3D",X"C8",
X"32",X"8B",X"30",X"3A",X"89",X"30",X"47",X"3A",X"8A",X"30",X"80",X"32",X"89",X"30",X"C9",X"3E",
X"0B",X"32",X"94",X"30",X"01",X"12",X"00",X"11",X"82",X"30",X"21",X"8B",X"16",X"ED",X"B0",X"3A",
X"89",X"30",X"32",X"95",X"30",X"3E",X"01",X"21",X"00",X"00",X"CD",X"08",X"04",X"3E",X"01",X"CD",
X"7B",X"03",X"3E",X"01",X"0E",X"01",X"CD",X"ED",X"03",X"3E",X"01",X"2E",X"00",X"CD",X"34",X"04",
X"AF",X"C9",X"CD",X"B9",X"15",X"B7",X"C8",X"3A",X"94",X"30",X"3D",X"32",X"94",X"30",X"28",X"18",
X"01",X"12",X"00",X"11",X"82",X"30",X"21",X"8B",X"16",X"ED",X"B0",X"3A",X"95",X"30",X"C6",X"08",
X"32",X"95",X"30",X"32",X"89",X"30",X"AF",X"C9",X"3E",X"FF",X"C9",X"00",X"00",X"10",X"10",X"FF",
X"10",X"00",X"10",X"FF",X"FF",X"0A",X"0F",X"0A",X"00",X"3E",X"50",X"32",X"98",X"30",X"3E",X"50",
X"32",X"99",X"30",X"21",X"00",X"00",X"22",X"9A",X"30",X"3E",X"10",X"32",X"9C",X"30",X"3E",X"01",
X"21",X"00",X"00",X"CD",X"08",X"04",X"3E",X"01",X"CD",X"7B",X"03",X"3E",X"01",X"0E",X"00",X"CD",
X"ED",X"03",X"3E",X"01",X"2E",X"01",X"CD",X"34",X"04",X"AF",X"C9",X"2A",X"9A",X"30",X"23",X"22",
X"9A",X"30",X"3E",X"08",X"32",X"00",X"50",X"7E",X"E6",X"0F",X"32",X"00",X"40",X"3A",X"99",X"30",
X"3D",X"20",X"FD",X"3A",X"9C",X"30",X"3D",X"28",X"05",X"32",X"9C",X"30",X"AF",X"C9",X"3E",X"10",
X"32",X"9C",X"30",X"3A",X"99",X"30",X"3D",X"32",X"99",X"30",X"3A",X"98",X"30",X"3D",X"28",X"05",
X"32",X"98",X"30",X"AF",X"C9",X"3E",X"FF",X"C9",X"3E",X"20",X"32",X"94",X"30",X"01",X"12",X"00",
X"11",X"82",X"30",X"21",X"64",X"17",X"ED",X"B0",X"3A",X"89",X"30",X"32",X"95",X"30",X"3E",X"01",
X"21",X"00",X"00",X"CD",X"08",X"04",X"3E",X"01",X"CD",X"7B",X"03",X"3E",X"01",X"0E",X"01",X"CD",
X"ED",X"03",X"3E",X"01",X"2E",X"00",X"CD",X"34",X"04",X"AF",X"C9",X"CD",X"43",X"15",X"B7",X"C8",
X"3A",X"94",X"30",X"3D",X"32",X"94",X"30",X"28",X"18",X"01",X"12",X"00",X"11",X"82",X"30",X"21",
X"64",X"17",X"ED",X"B0",X"3A",X"95",X"30",X"C6",X"01",X"32",X"95",X"30",X"32",X"89",X"30",X"AF",
X"C9",X"3E",X"FF",X"C9",X"00",X"00",X"10",X"10",X"FF",X"10",X"00",X"10",X"FF",X"FF",X"0A",X"0C",
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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
begin
process(clk)
begin

38
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_sprite_color_lut.vhd Normal file
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@@ -0,0 +1,38 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity power_surge_sprite_color_lut is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of power_surge_sprite_color_lut is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"0D",X"0F",X"05",X"00",X"0E",X"06",X"0A",X"00",X"04",X"09",X"01",X"00",X"04",X"09",X"01",
X"00",X"04",X"09",X"01",X"00",X"0C",X"05",X"01",X"00",X"0E",X"05",X"01",X"00",X"0D",X"05",X"01",
X"00",X"0B",X"05",X"01",X"00",X"01",X"0F",X"04",X"00",X"01",X"0F",X"04",X"00",X"01",X"0F",X"04",
X"00",X"08",X"07",X"0C",X"00",X"01",X"0F",X"04",X"00",X"01",X"0F",X"04",X"00",X"0A",X"05",X"01",
X"00",X"05",X"09",X"01",X"00",X"0B",X"0D",X"05",X"00",X"06",X"05",X"01",X"00",X"0A",X"03",X"01",
X"00",X"0C",X"03",X"01",X"00",X"0E",X"03",X"01",X"00",X"0D",X"03",X"01",X"00",X"0B",X"03",X"01",
X"00",X"0E",X"0C",X"0F",X"00",X"05",X"03",X"01",X"00",X"0E",X"06",X"09",X"00",X"04",X"09",X"05",
X"00",X"09",X"0E",X"06",X"00",X"04",X"0E",X"05",X"00",X"09",X"0E",X"05",X"00",X"0B",X"05",X"01",
X"00",X"0C",X"07",X"01",X"00",X"05",X"0F",X"09",X"00",X"05",X"04",X"09",X"00",X"0A",X"03",X"01",
X"00",X"0C",X"02",X"03",X"00",X"0C",X"06",X"03",X"00",X"0C",X"06",X"09",X"00",X"0C",X"06",X"01",
X"00",X"0E",X"06",X"0C",X"00",X"0C",X"02",X"0F",X"00",X"0C",X"02",X"09",X"00",X"0C",X"02",X"01",
X"00",X"01",X"08",X"0F",X"00",X"0E",X"06",X"0F",X"00",X"09",X"0A",X"0F",X"00",X"05",X"06",X"0F",
X"00",X"0B",X"09",X"05",X"00",X"0A",X"06",X"0C",X"00",X"0A",X"06",X"09",X"00",X"0A",X"02",X"09",
X"00",X"06",X"01",X"0F",X"00",X"04",X"01",X"0F",X"00",X"0A",X"03",X"01",X"00",X"0A",X"02",X"0C",
X"00",X"05",X"09",X"01",X"00",X"0A",X"02",X"01",X"00",X"0E",X"02",X"09",X"00",X"0E",X"02",X"0C",
X"00",X"01",X"04",X"0F",X"00",X"01",X"04",X"0F",X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

4
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_sprite_grphx.vhd → Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_sprite_grphx.vhd
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@@ -1,7 +1,7 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity time_pilot_sprite_grphx is
entity power_surge_sprite_grphx is
port (
clk : in std_logic;
addr : in std_logic_vector(13 downto 0);
@@ -9,7 +9,7 @@ port (
);
end entity;
architecture prom of time_pilot_sprite_grphx is
architecture prom of power_surge_sprite_grphx is
type rom is array(0 to 16383) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"91",X"23",

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Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/psurge (1).zip
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194
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/scandoubler.v
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@@ -1,194 +0,0 @@
//
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
// TODO: Delay vsync one line
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
(
// system interface
input clk_sys,
input ce_pix,
input ce_pix_actual,
input hq2x,
// shifter video interface
input hs_in,
input vs_in,
input line_start,
input [DWIDTH:0] r_in,
input [DWIDTH:0] g_in,
input [DWIDTH:0] b_in,
input mono,
// output interface
output reg hs_out,
output vs_out,
output [DWIDTH:0] r_out,
output [DWIDTH:0] g_out,
output [DWIDTH:0] b_out
);
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <=1024 ? 9 : 10 )
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
assign vs_out = vs_in;
reg [2:0] phase;
reg [2:0] ce_div;
reg [7:0] pix_len = 0;
wire [7:0] pl = pix_len + 1'b1;
reg ce_x1, ce_x4;
reg req_line_reset;
wire ls_in = hs_in | line_start;
always @(negedge clk_sys) begin
reg old_ce;
reg [2:0] ce_cnt;
reg [7:0] pixsz2, pixsz4 = 0;
old_ce <= ce_pix;
if(~&pix_len) pix_len <= pix_len + 1'd1;
ce_x4 <= 0;
ce_x1 <= 0;
// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
phase <= phase + 1'd1;
ce_x4 <= 1;
end
if(~old_ce & ce_pix) begin
pixsz2 <= {1'b0, pl[7:1]};
pixsz4 <= {2'b00, pl[7:2]};
ce_x1 <= 1;
ce_x4 <= 1;
pix_len <= 0;
phase <= phase + 1'd1;
ce_cnt <= ce_cnt + 1'd1;
if(ce_pix_actual) begin
phase <= 0;
ce_div <= ce_cnt + 1'd1;
ce_cnt <= 0;
req_line_reset <= 0;
end
if(ls_in) req_line_reset <= 1;
end
end
reg ce_sd;
always @(*) begin
case(ce_div)
2: ce_sd = !phase[0];
4: ce_sd = !phase[1:0];
default: ce_sd <= 1;
endcase
end
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
.ce_x4(ce_x4 & ce_sd),
.inputpixel({b_in,g_in,r_in}),
.mono(mono),
.disable_hq2x(~hq2x),
.reset_frame(vs_in),
.reset_line(req_line_reset),
.read_y(sd_line),
.read_x(sd_h_actual),
.outpixel({b_out,g_out,r_out})
);
reg [10:0] sd_h_actual;
always @(*) begin
case(ce_div)
2: sd_h_actual = sd_h[10:1];
4: sd_h_actual = sd_h[10:2];
default: sd_h_actual = sd_h;
endcase
end
reg [10:0] sd_h;
reg [1:0] sd_line;
always @(posedge clk_sys) begin
reg [11:0] hs_max,hs_rise,hs_ls;
reg [10:0] hcnt;
reg [11:0] sd_hcnt;
reg hs, hs2, vs, ls;
if(ce_x1) begin
hs <= hs_in;
ls <= ls_in;
if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
// falling edge of hsync indicates start of line
if(hs && !hs_in) begin
hs_max <= {hcnt,1'b1};
hcnt <= 0;
if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
end else begin
hcnt <= hcnt + 1'd1;
end
// save position of rising edge
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
vs <= vs_in;
if(vs && ~vs_in) sd_line <= 0;
end
if(ce_x4) begin
hs2 <= hs_in;
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1'd1;
sd_h <= sd_h + 1'd1;
if(hs2 && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 0;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_out <= 0;
if(sd_hcnt == hs_rise) hs_out <= 1;
if(sd_hcnt == hs_ls) sd_h <= 0;
if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1;
end
end
endmodule

38
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_char_color_lut.vhd
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@@ -1,38 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity time_pilot_char_color_lut is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(3 downto 0)
);
end entity;
architecture prom of time_pilot_char_color_lut is
type rom is array(0 to 255) of std_logic_vector(3 downto 0);
signal rom_data: rom := (
"0000","1101","1111","1100","1010","0100","0001","1111","1011","0100","0001","1111","1100","0100","0001","1111",
"1110","0100","0001","1111","0000","0100","0001","1111","1010","0100","0101","0001","1011","0100","0101","0001",
"1100","0100","0101","0001","1110","0100","0101","0001","0000","0100","0101","0001","1010","0110","1000","0010",
"1011","0110","1000","0010","1100","0110","1000","0010","1110","0110","1000","0010","0000","0110","1000","0010",
"0000","0001","0100","1111","0000","0100","0010","0110","0000","0001","1000","0100","0000","1101","0001","0101",
"0000","0010","0011","0001","0000","1100","1111","0011","0000","0101","0010","1000","1010","0001","0100","0011",
"0000","0110","1111","0010","0000","1111","0011","0101","0000","0011","0001","1111","1010","0010","1101","0101",
"0000","0001","1111","1000","1010","0010","1101","0101","1010","1011","1001","1111","1001","1001","1001","1001",
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

290
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_mist.vhd
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@@ -1,290 +0,0 @@
---------------------------------------------------------------------------------
-- Mist Top level for Time pilot by Dar (darfpga@aol.fr) (29/10/2017)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- Educational use only
-- Do not redistribute synthetized file with roms
-- Do not redistribute roms whatever the form
-- Use at your own risk
---------------------------------------------------------------------------------
-- Use time_pilot_lite.sdc to compile (Timequest constraints)
-- /!\
-- Don't forget to set device configuration mode with memory initialization
-- (Assignments/Device/Pin options/Configuration mode)
---------------------------------------------------------------------------------
-- Uses 1 pll for 12MHz and 14MHz generation from 27MHz
--
-- Mist key :
-- Right Button : reset game
--
-- Keyboard players inputs :
--
-- ESC : Add coin
-- 2 : Start 2 players
-- 1 : Start 1 player
-- SPACE : Fire
-- RIGHT arrow : rotate right
-- LEFT arrow : rotate left
-- UP arrow : rotate up
-- DOWN arrow : rotate down
--
-- Other details : see time_pilot.vhd
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
entity time_pilot_mist is
port(
CLOCK_27 : in std_logic;
AUDIO_L : out std_logic;
AUDIO_R : out std_logic;
VGA_R : out std_logic_vector(5 downto 0);
VGA_G : out std_logic_vector(5 downto 0);
VGA_B : out std_logic_vector(5 downto 0);
VGA_VS : out std_logic;
VGA_HS : out std_logic;
LED : out std_logic;
SPI_SCK : in std_logic;
SPI_DI : in std_logic;
SPI_DO : out std_logic;
SPI_SS3 : in std_logic;
CONF_DATA0 : in std_logic
);
end time_pilot_mist;
architecture struct of time_pilot_mist is
signal clock_48 : std_logic;
signal clock_12 : std_logic;
signal clock_14 : std_logic;
signal reset : std_logic;
signal pll_locked: std_logic;
signal r : std_logic_vector(4 downto 0);
signal g : std_logic_vector(4 downto 0);
signal b : std_logic_vector(4 downto 0);
signal hsync : std_logic;
signal vsync : std_logic;
signal hblank : std_logic;
signal vblank : std_logic;
signal audio : std_logic_vector(10 downto 0);
signal audio_pwm : std_logic;
signal reset_n : std_logic;
signal ps2_clk : std_logic;
signal ps2_dat : std_logic;
signal joy_u : std_logic;
signal joy_l : std_logic;
signal joy_r : std_logic;
signal joy_d : std_logic;
signal scanlines : std_logic_vector(1 downto 0);
signal hq2x : std_logic;
signal buttons : std_logic_vector(1 downto 0);
signal joy0 : std_logic_vector(7 downto 0);
signal joy1 : std_logic_vector(7 downto 0);
signal status : std_logic_vector(31 downto 0);
signal scandoubler_disable : std_logic;
signal ypbpr : std_logic;
signal pix_ce : std_logic;
signal kbd_joy0 : std_logic_vector(7 downto 0);
signal ps2Clk : std_logic;
signal ps2Data : std_logic;
signal VGA_R_O : std_logic_vector(2 downto 0);
signal VGA_G_O : std_logic_vector(2 downto 0);
signal VGA_B_O : std_logic_vector(2 downto 0);
constant CONF_STR : string :=
"Time Pilot;;O4,Joystick Control,Upright,Normal;O89,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;T5,Reset;V,v1.00";
function to_slv(s: string) return std_logic_vector is
constant ss: string(1 to s'length) := s;
variable rval: std_logic_vector(1 to 8 * s'length);
variable p: integer;
variable c: integer;
begin
for i in ss'range loop
p := 8 * i;
c := character'pos(ss(i));
rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8));
end loop;
return rval;
end function;
component mist_io
generic ( STRLEN : integer := 0 );
port (
clk_sys :in std_logic;
SPI_SCK, CONF_DATA0, SPI_DI :in std_logic;
SPI_DO : out std_logic;
conf_str : in std_logic_vector(8*STRLEN-1 downto 0);
buttons : out std_logic_vector(1 downto 0);
joystick_0 : out std_logic_vector(7 downto 0);
joystick_1 : out std_logic_vector(7 downto 0);
status : out std_logic_vector(31 downto 0);
scandoubler_disable, ypbpr : out std_logic;
ps2_kbd_clk : out std_logic;
ps2_kbd_data : out std_logic
);
end component mist_io;
component video_mixer
generic ( LINE_LENGTH : integer := 384; HALF_DEPTH : integer := 1 );
port (
clk_sys, ce_pix, ce_pix_actual : in std_logic;
SPI_SCK, SPI_SS3, SPI_DI : in std_logic;
scanlines : in std_logic_vector(1 downto 0);
scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic;
R, G, B : in std_logic_vector(2 downto 0);
HSync, VSync, line_start, mono : in std_logic;
VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0);
VGA_VS, VGA_HS : out std_logic
);
end component video_mixer;
component keyboard
PORT(
clk : in std_logic;
reset : in std_logic;
ps2_kbd_clk : in std_logic;
ps2_kbd_data : in std_logic;
joystick : out std_logic_vector (7 downto 0)
);
end component;
begin
reset <= status(0) or status(5) or buttons(1) or not pll_locked;
clocks : entity work.mist_pll_12M_14M
port map(
inclk0 => CLOCK_27,
c0 => clock_12,--12.28800000
c1 => clock_14,--14.31800000
c2 => clock_48,
locked => pll_locked
);
scanlines(1) <= '1' when status(9 downto 8) = "11" and scandoubler_disable = '0' else '0';
scanlines(0) <= '1' when status(9 downto 8) = "10" and scandoubler_disable = '0' else '0';
hq2x <= '1' when status(9 downto 8) = "01" else '0';
vmixer : video_mixer
port map (
clk_sys => clock_48,
ce_pix => pix_ce,
ce_pix_actual => pix_ce,
SPI_SCK => SPI_SCK,
SPI_SS3 => SPI_SS3,
SPI_DI => SPI_DI,
scanlines => scanlines,
scandoubler_disable => scandoubler_disable,
hq2x => hq2x,
ypbpr => ypbpr,
ypbpr_full => '1',
R => VGA_R_O,
G => VGA_G_O,
B => VGA_B_O,
HSync => hsync,
VSync => vsync,
line_start => '0',
mono => '0',
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_VS => VGA_VS,
VGA_HS => VGA_HS
);
mist_io_inst : mist_io
generic map (STRLEN => CONF_STR'length)
port map (
clk_sys => clock_48,
SPI_SCK => SPI_SCK,
CONF_DATA0 => CONF_DATA0,
SPI_DI => SPI_DI,
SPI_DO => SPI_DO,
conf_str => to_slv(CONF_STR),
buttons => buttons,
scandoubler_disable => scandoubler_disable,
ypbpr => ypbpr,
joystick_1 => joy1,
joystick_0 => joy0,
status => status,
ps2_kbd_clk => ps2Clk,
ps2_kbd_data => ps2Data
);
Joy_r <= joy0(0) or joy1(0) or kbd_joy0(7) when status(4) = '0'
else joy0(3) or joy1(3) or kbd_joy0(4);
Joy_l <= joy0(1) or joy1(1) or kbd_joy0(6) when status(4) = '0'
else joy0(2) or joy1(2) or kbd_joy0(5);
Joy_u <= joy0(3) or joy1(3) or kbd_joy0(4) when status(4) = '0'
else joy0(1) or joy1(1) or kbd_joy0(6);
Joy_d <= joy0(2) or joy1(2) or kbd_joy0(5) when status(4) = '0'
else joy0(0) or joy1(0) or kbd_joy0(7);
time_pilot : entity work.time_pilot
port map(
clock_12 => clock_12,
clock_14 => clock_14,
reset => reset,
video_r => r,
video_g => g,
video_b => b,
video_hblank => open,
video_vblank => open,
video_clk => pix_ce,
video_hs => hsync,
video_vs => vsync,
audio_out => audio,
dip_switch_1 => X"FF", -- Coinage_B / Coinage_A
dip_switch_2 => X"4B", -- Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1)
start2 => kbd_joy0(2) or status(3),
start1 => kbd_joy0(1) or status(2),
coin1 => kbd_joy0(3) or status(1),
fire1 => joy0(4) or joy1(4) or kbd_joy0(0),
right1 => Joy_r,
left1 => Joy_l,
down1 => Joy_d,
up1 => Joy_u,
fire2 => joy0(4) or joy1(4) or kbd_joy0(0),
right2 => Joy_r,
left2 => Joy_l,
down2 => Joy_d,
up2 => Joy_u,
dbg_cpu_addr => open
);
VGA_R_O <= r(4 downto 2);
VGA_G_O <= g(4 downto 2);
VGA_B_O <= b(4 downto 2);
u_keyboard : keyboard
port map(
clk => clock_48,
reset => reset,
ps2_kbd_clk => ps2Clk,
ps2_kbd_data => ps2Data,
joystick => kbd_joy0
);
u_dac : entity work.dac
port map(
clk_i => clock_48,
res_n_i => not reset,
dac_i => audio,
dac_o => audio_pwm
);
AUDIO_L <= audio_pwm;
AUDIO_R <= audio_pwm;
LED <= '1';
end struct;

16
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_sound_board.vhd
View File

@@ -34,9 +34,7 @@ port(
sound_cmd : in std_logic_vector(7 downto 0);
sound_trig : in std_logic;
audio_out : out std_logic_vector(10 downto 0);
dbg_cpu_addr : out std_logic_vector(15 downto 0)
audio_out : out std_logic_vector(10 downto 0)
);
end time_pilot_sound_board;
@@ -117,14 +115,6 @@ begin
clock_14n <= not clock_14;
reset_n <= not reset;
-- debug
process (reset, clock_14)
begin
if rising_edge(clock_14) and cpu_mreq_n ='0' then
dbg_cpu_addr <= cpu_addr;
end if;
end process;
--------------------------------------------------------
-- RC filters equation
--
@@ -340,10 +330,10 @@ port map(
);
-- cpu1 program ROM
rom_cpu1 : entity work.time_pilot_sound_prog2
rom_cpu1 : entity work.power_surge_sound_prog
port map(
clk => clock_14n,
addr => cpu_addr(11 downto 0),
addr => cpu_addr(12 downto 0),
data => cpu_rom_do
);

278
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_sound_prog2.vhd
View File

@@ -1,278 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity time_pilot_sound_prog2 is
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of time_pilot_sound_prog2 is
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"21",X"00",X"30",X"06",X"00",X"C3",X"7C",X"01",X"32",X"00",X"50",X"3A",X"00",X"40",X"C9",X"FF",
X"32",X"00",X"70",X"3A",X"00",X"60",X"C9",X"FF",X"78",X"CF",X"79",X"32",X"00",X"40",X"C9",X"FF",
X"78",X"D7",X"79",X"32",X"00",X"60",X"C9",X"FF",X"87",X"85",X"6F",X"7C",X"CE",X"00",X"67",X"7E",
X"23",X"66",X"6F",X"E9",X"FF",X"FF",X"FF",X"FF",X"D9",X"08",X"CD",X"40",X"00",X"08",X"D9",X"C9",
X"3E",X"0E",X"CF",X"B7",X"28",X"26",X"32",X"0B",X"30",X"CD",X"2D",X"01",X"3A",X"0B",X"30",X"CB",
X"77",X"20",X"3F",X"3A",X"06",X"30",X"B7",X"3A",X"0B",X"30",X"C2",X"E6",X"00",X"21",X"06",X"30",
X"36",X"00",X"B7",X"F2",X"FE",X"00",X"CB",X"BF",X"CD",X"89",X"00",X"C9",X"21",X"00",X"30",X"06",
X"04",X"AF",X"77",X"23",X"10",X"FC",X"C9",X"21",X"00",X"30",X"06",X"02",X"0E",X"03",X"BE",X"28",
X"05",X"23",X"23",X"10",X"F9",X"41",X"79",X"90",X"C9",X"CD",X"77",X"00",X"C8",X"AF",X"77",X"23",
X"77",X"C9",X"3A",X"06",X"30",X"B7",X"20",X"27",X"3A",X"09",X"30",X"2A",X"07",X"30",X"BD",X"D8",
X"BC",X"D8",X"3E",X"FF",X"32",X"06",X"30",X"06",X"00",X"21",X"00",X"30",X"3A",X"0B",X"30",X"77",
X"23",X"70",X"23",X"70",X"23",X"70",X"3E",X"01",X"32",X"04",X"30",X"CD",X"BE",X"02",X"C9",X"3A",
X"0B",X"30",X"CB",X"B7",X"CD",X"77",X"00",X"28",X"04",X"23",X"36",X"00",X"C9",X"3A",X"09",X"30",
X"47",X"3A",X"07",X"30",X"B8",X"D0",X"21",X"00",X"30",X"3A",X"0B",X"30",X"77",X"23",X"36",X"00",
X"3E",X"FF",X"32",X"06",X"30",X"C9",X"3A",X"09",X"30",X"47",X"3A",X"07",X"30",X"B8",X"D0",X"AF",
X"32",X"06",X"30",X"3A",X"0B",X"30",X"21",X"00",X"30",X"77",X"23",X"36",X"00",X"C9",X"32",X"0B",
X"30",X"CD",X"77",X"00",X"28",X"04",X"23",X"36",X"00",X"C9",X"AF",X"CD",X"77",X"00",X"28",X"08",
X"3A",X"0B",X"30",X"77",X"23",X"36",X"00",X"C9",X"CD",X"2D",X"01",X"21",X"00",X"30",X"B7",X"C8",
X"3D",X"87",X"4F",X"06",X"00",X"09",X"3A",X"0B",X"30",X"77",X"23",X"70",X"C9",X"3A",X"00",X"30",
X"CD",X"4F",X"01",X"32",X"07",X"30",X"3A",X"02",X"30",X"CD",X"4F",X"01",X"32",X"08",X"30",X"3A",
X"0B",X"30",X"CD",X"4F",X"01",X"32",X"09",X"30",X"CD",X"61",X"01",X"32",X"0A",X"30",X"C9",X"21",
X"AD",X"05",X"CB",X"77",X"28",X"05",X"CB",X"B7",X"21",X"AD",X"05",X"06",X"00",X"4F",X"09",X"7E",
X"C9",X"2A",X"07",X"30",X"7C",X"BD",X"38",X"09",X"3A",X"09",X"30",X"BD",X"38",X"0C",X"3E",X"01",
X"C9",X"3A",X"09",X"30",X"BC",X"38",X"03",X"3E",X"02",X"C9",X"AF",X"C9",X"70",X"23",X"7C",X"FE",
X"34",X"20",X"F9",X"F9",X"ED",X"56",X"21",X"00",X"80",X"22",X"0C",X"30",X"77",X"01",X"3F",X"07",
X"DF",X"E7",X"32",X"0E",X"30",X"32",X"0F",X"30",X"CD",X"A2",X"02",X"CD",X"A6",X"02",X"CD",X"AA",
X"02",X"CD",X"B0",X"02",X"CD",X"B4",X"02",X"CD",X"B8",X"02",X"3A",X"06",X"30",X"B7",X"28",X"06",
X"FB",X"00",X"00",X"F3",X"18",X"0F",X"FB",X"3E",X"0F",X"CF",X"E6",X"40",X"20",X"F9",X"3E",X"0F",
X"CF",X"E6",X"40",X"28",X"F9",X"F3",X"3A",X"06",X"30",X"B7",X"20",X"2E",X"3E",X"00",X"32",X"04",
X"30",X"3A",X"01",X"30",X"B7",X"3A",X"00",X"30",X"28",X"05",X"CD",X"85",X"02",X"18",X"03",X"CD",
X"68",X"02",X"3E",X"01",X"32",X"04",X"30",X"3A",X"03",X"30",X"B7",X"3A",X"02",X"30",X"28",X"05",
X"CD",X"85",X"02",X"18",X"B5",X"CD",X"68",X"02",X"18",X"B0",X"3E",X"00",X"32",X"04",X"30",X"3A",
X"01",X"30",X"B7",X"3A",X"00",X"30",X"28",X"05",X"CD",X"3C",X"02",X"18",X"9D",X"CD",X"12",X"02",
X"18",X"98",X"CB",X"B7",X"32",X"00",X"30",X"CD",X"BE",X"02",X"3A",X"00",X"30",X"21",X"F9",X"04",
X"EF",X"B7",X"20",X"6B",X"21",X"01",X"30",X"36",X"01",X"11",X"53",X"05",X"3A",X"00",X"30",X"6F",
X"26",X"00",X"29",X"19",X"5E",X"23",X"56",X"ED",X"53",X"10",X"30",X"C9",X"B7",X"C8",X"2A",X"10",
X"30",X"CD",X"33",X"00",X"B7",X"C8",X"21",X"00",X"30",X"3D",X"28",X"06",X"36",X"00",X"AF",X"32",
X"06",X"30",X"23",X"36",X"00",X"C9",X"B7",X"C8",X"E6",X"03",X"C5",X"47",X"3A",X"04",X"30",X"4F",
X"87",X"81",X"80",X"32",X"05",X"30",X"C1",X"C9",X"F5",X"CD",X"BE",X"02",X"F1",X"E6",X"3F",X"21",
X"F9",X"04",X"EF",X"B7",X"C2",X"8F",X"02",X"21",X"01",X"30",X"3A",X"04",X"30",X"87",X"5F",X"16",
X"00",X"19",X"36",X"01",X"C9",X"B7",X"C8",X"E6",X"3F",X"21",X"53",X"05",X"EF",X"B7",X"C8",X"57",
X"21",X"00",X"30",X"3A",X"04",X"30",X"4F",X"06",X"00",X"09",X"09",X"15",X"28",X"01",X"70",X"23",
X"70",X"C9",X"06",X"08",X"18",X"06",X"06",X"09",X"18",X"02",X"06",X"0A",X"0E",X"00",X"DF",X"C9",
X"06",X"08",X"18",X"06",X"06",X"09",X"18",X"02",X"06",X"0A",X"0E",X"00",X"E7",X"C9",X"01",X"00",
X"08",X"3A",X"04",X"30",X"B7",X"20",X"0C",X"DF",X"04",X"DF",X"04",X"DF",X"0E",X"3F",X"CD",X"2D",
X"03",X"AF",X"C9",X"E7",X"04",X"E7",X"04",X"E7",X"0E",X"3F",X"CD",X"39",X"03",X"AF",X"C9",X"CD",
X"56",X"02",X"3A",X"05",X"30",X"3D",X"21",X"EB",X"02",X"EF",X"C9",X"F7",X"02",X"00",X"03",X"09",
X"03",X"12",X"03",X"1B",X"03",X"24",X"03",X"CD",X"A2",X"02",X"0E",X"09",X"CD",X"2D",X"03",X"C9",
X"CD",X"A6",X"02",X"0E",X"12",X"CD",X"2D",X"03",X"C9",X"CD",X"AA",X"02",X"0E",X"24",X"CD",X"2D",
X"03",X"C9",X"CD",X"B0",X"02",X"0E",X"09",X"CD",X"39",X"03",X"C9",X"CD",X"B4",X"02",X"0E",X"12",
X"CD",X"39",X"03",X"C9",X"CD",X"B8",X"02",X"0E",X"24",X"CD",X"39",X"03",X"C9",X"3A",X"0E",X"30",
X"B1",X"32",X"0E",X"30",X"06",X"07",X"4F",X"DF",X"C9",X"3A",X"0F",X"30",X"B1",X"32",X"0F",X"30",
X"06",X"07",X"4F",X"E7",X"C9",X"06",X"06",X"3A",X"04",X"30",X"B7",X"20",X"02",X"DF",X"C9",X"E7",
X"C9",X"06",X"06",X"3A",X"04",X"30",X"B7",X"20",X"04",X"78",X"CF",X"4F",X"C9",X"78",X"D7",X"4F",
X"C9",X"3A",X"0E",X"30",X"A0",X"B1",X"32",X"0E",X"30",X"4F",X"06",X"07",X"DF",X"C9",X"3A",X"0F",
X"30",X"A0",X"B1",X"32",X"0F",X"30",X"4F",X"06",X"07",X"E7",X"C9",X"21",X"91",X"03",X"3D",X"87",
X"5F",X"16",X"00",X"19",X"5E",X"23",X"56",X"4B",X"42",X"3A",X"04",X"30",X"B7",X"28",X"D2",X"18",
X"DD",X"08",X"FE",X"10",X"FD",X"20",X"FB",X"21",X"AD",X"03",X"3D",X"87",X"5F",X"16",X"00",X"19",
X"5E",X"23",X"56",X"4B",X"42",X"3A",X"04",X"30",X"B7",X"28",X"B6",X"18",X"C1",X"01",X"F7",X"02",
X"EF",X"04",X"DF",X"21",X"C9",X"03",X"3D",X"87",X"5F",X"16",X"00",X"19",X"5E",X"23",X"56",X"4B",
X"42",X"3A",X"04",X"30",X"B7",X"28",X"9A",X"18",X"A5",X"00",X"F6",X"00",X"ED",X"00",X"DB",X"21",
X"E7",X"03",X"3D",X"87",X"5F",X"16",X"00",X"19",X"5E",X"23",X"56",X"4B",X"42",X"3A",X"04",X"30",
X"B7",X"CA",X"61",X"03",X"C3",X"6E",X"03",X"09",X"FF",X"12",X"FF",X"24",X"FF",X"C6",X"07",X"47",
X"3A",X"04",X"30",X"B7",X"20",X"02",X"DF",X"C9",X"E7",X"C9",X"C6",X"07",X"47",X"3A",X"04",X"30",
X"B7",X"78",X"20",X"02",X"CF",X"C9",X"D7",X"C9",X"3D",X"87",X"47",X"4D",X"3A",X"04",X"30",X"B7",
X"20",X"05",X"DF",X"4C",X"04",X"DF",X"C9",X"E7",X"4C",X"04",X"E7",X"C9",X"3D",X"87",X"67",X"3A",
X"04",X"30",X"B7",X"7C",X"20",X"07",X"CF",X"6F",X"7C",X"3C",X"CF",X"67",X"C9",X"D7",X"6F",X"7C",
X"3C",X"D7",X"67",X"C9",X"CD",X"56",X"02",X"7D",X"FE",X"04",X"D0",X"F5",X"21",X"83",X"04",X"3A",
X"05",X"30",X"3D",X"87",X"5F",X"16",X"00",X"19",X"5E",X"23",X"56",X"2A",X"0C",X"30",X"7B",X"A5",
X"6F",X"7A",X"A4",X"67",X"22",X"0C",X"30",X"F1",X"B7",X"20",X"02",X"77",X"C9",X"21",X"83",X"04",
X"87",X"87",X"4F",X"87",X"81",X"4F",X"06",X"00",X"09",X"3A",X"05",X"30",X"3D",X"87",X"5F",X"16",
X"00",X"19",X"5E",X"23",X"56",X"2A",X"0C",X"30",X"7B",X"B5",X"6F",X"7A",X"B4",X"67",X"22",X"0C",
X"30",X"77",X"C9",X"3F",X"FF",X"FF",X"FC",X"FF",X"F3",X"FC",X"FF",X"F3",X"FF",X"CF",X"FF",X"80",
X"00",X"00",X"02",X"00",X"08",X"02",X"00",X"08",X"00",X"20",X"00",X"40",X"00",X"00",X"01",X"00",
X"04",X"01",X"00",X"04",X"00",X"10",X"00",X"C0",X"00",X"00",X"03",X"00",X"0C",X"03",X"00",X"0C",
X"00",X"30",X"00",X"0E",X"10",X"C6",X"07",X"47",X"3A",X"04",X"30",X"B7",X"20",X"02",X"DF",X"C9",
X"E7",X"C9",X"06",X"0B",X"4D",X"3A",X"04",X"30",X"B7",X"20",X"05",X"DF",X"04",X"4C",X"DF",X"C9",
X"E7",X"04",X"4C",X"E7",X"C9",X"3A",X"04",X"30",X"B7",X"3E",X"0B",X"47",X"20",X"07",X"CF",X"6F",
X"78",X"3C",X"CF",X"67",X"C9",X"D7",X"6F",X"78",X"3C",X"D7",X"67",X"C9",X"4F",X"06",X"0D",X"3A",
X"04",X"30",X"B7",X"20",X"02",X"DF",X"C9",X"E7",X"C9",X"BE",X"02",X"B0",X"0F",X"7D",X"0F",X"8E",
X"0F",X"5A",X"10",X"F4",X"0F",X"DA",X"05",X"08",X"17",X"DA",X"05",X"82",X"1B",X"99",X"16",X"D2",
X"0F",X"2F",X"16",X"76",X"17",X"DA",X"05",X"27",X"1B",X"B6",X"1D",X"DA",X"05",X"9D",X"1C",X"DA",
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X"0C",X"2A",X"07",X"2A",X"07",X"2A",X"07",X"2A",X"07",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"4E",
X"CB",X"21",X"06",X"00",X"21",X"34",X"09",X"09",X"5E",X"23",X"56",X"ED",X"53",X"7A",X"30",X"DD",
X"73",X"04",X"DD",X"72",X"05",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"4E",X"CB",X"21",X"06",X"00",
X"21",X"60",X"09",X"09",X"5E",X"23",X"56",X"DD",X"73",X"0B",X"DD",X"72",X"0C",X"18",X"35",X"DD",
X"6E",X"02",X"DD",X"66",X"03",X"4E",X"06",X"00",X"21",X"7C",X"0A",X"09",X"7E",X"32",X"7E",X"30",
X"DD",X"77",X"01",X"18",X"1F",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"7E",X"DD",X"77",X"08",X"18",
X"13",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"7E",X"DD",X"77",X"06",X"DD",X"77",X"07",X"DD",X"77",
X"0D",X"DD",X"77",X"0E",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"23",X"DD",X"75",X"02",X"DD",X"74",
X"03",X"C3",X"2D",X"0C",X"DD",X"35",X"0F",X"C0",X"3A",X"7E",X"30",X"DD",X"77",X"0F",X"DD",X"CB",
X"0A",X"46",X"C2",X"17",X"0D",X"DD",X"7E",X"0E",X"D6",X"01",X"FA",X"17",X"0D",X"DD",X"77",X"0E",
X"DD",X"7E",X"09",X"FE",X"04",X"28",X"08",X"DD",X"4E",X"0E",X"3E",X"02",X"CD",X"ED",X"03",X"DD",
X"4E",X"0E",X"3E",X"03",X"CD",X"ED",X"03",X"DD",X"35",X"0A",X"C0",X"DD",X"6E",X"02",X"DD",X"66",
X"03",X"2B",X"7E",X"47",X"E6",X"1F",X"CA",X"D4",X"07",X"FE",X"1F",X"C2",X"ED",X"07",X"DD",X"7E",
X"09",X"FE",X"04",X"28",X"07",X"3E",X"02",X"0E",X"00",X"CD",X"ED",X"03",X"3E",X"03",X"0E",X"00",
X"CD",X"ED",X"03",X"DD",X"36",X"0A",X"FF",X"C9",X"DD",X"35",X"01",X"C0",X"3A",X"7E",X"30",X"DD",
X"77",X"01",X"DD",X"CB",X"00",X"46",X"C2",X"64",X"0D",X"DD",X"7E",X"07",X"D6",X"01",X"FA",X"64",
X"0D",X"DD",X"77",X"07",X"DD",X"35",X"00",X"C0",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"7E",X"47",
X"E6",X"1F",X"CA",X"F0",X"08",X"FE",X"1F",X"C2",X"F6",X"08",X"23",X"DD",X"75",X"02",X"DD",X"74",
X"03",X"78",X"E6",X"E0",X"0F",X"0F",X"0F",X"0F",X"4F",X"06",X"00",X"21",X"94",X"0D",X"09",X"5E",
X"23",X"56",X"EB",X"E9",X"A4",X"0D",X"C2",X"0D",X"D8",X"0D",X"EB",X"08",X"EB",X"08",X"EB",X"08",
X"EB",X"08",X"EB",X"08",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"4E",X"CB",X"21",X"06",X"00",X"21",
X"34",X"09",X"09",X"5E",X"23",X"56",X"ED",X"53",X"7A",X"30",X"DD",X"73",X"04",X"DD",X"72",X"05",
X"18",X"23",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"4E",X"06",X"00",X"21",X"7C",X"0A",X"09",X"7E",
X"32",X"7E",X"30",X"DD",X"77",X"01",X"18",X"0D",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"7E",X"DD",
X"77",X"06",X"DD",X"77",X"07",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"23",X"DD",X"75",X"02",X"DD",
X"74",X"03",X"C3",X"68",X"0D",X"3E",X"01",X"2E",X"00",X"CD",X"34",X"04",X"3E",X"02",X"2E",X"00",
X"CD",X"34",X"04",X"3E",X"03",X"2E",X"00",X"CD",X"34",X"04",X"3E",X"01",X"CD",X"7B",X"03",X"3E",
X"02",X"CD",X"7B",X"03",X"3E",X"03",X"CD",X"7B",X"03",X"21",X"4B",X"0E",X"11",X"4A",X"30",X"01",
X"30",X"00",X"ED",X"B0",X"3A",X"80",X"30",X"07",X"4F",X"07",X"81",X"4F",X"06",X"00",X"21",X"F3",
X"0E",X"09",X"11",X"4C",X"30",X"CD",X"41",X"0E",X"11",X"5C",X"30",X"CD",X"41",X"0E",X"11",X"6C",
X"30",X"7E",X"12",X"CD",X"48",X"0E",X"7E",X"12",X"23",X"13",X"C9",X"01",X"01",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"DD",X"21",X"4A",X"30",X"CD",
X"9A",X"0B",X"DD",X"7E",X"08",X"FE",X"01",X"28",X"28",X"FE",X"02",X"28",X"3B",X"DD",X"21",X"5A",
X"30",X"CD",X"A9",X"0B",X"DD",X"21",X"6A",X"30",X"CD",X"C3",X"0B",X"3C",X"28",X"02",X"AF",X"C9",
X"DD",X"21",X"4A",X"30",X"3E",X"FF",X"DD",X"BE",X"00",X"20",X"04",X"DD",X"BE",X"10",X"C8",X"AF",
X"C9",X"DD",X"21",X"4A",X"30",X"CD",X"EC",X"0B",X"DD",X"21",X"6A",X"30",X"CD",X"FB",X"0B",X"DD",
X"21",X"5A",X"30",X"CD",X"FB",X"0B",X"18",X"15",X"DD",X"21",X"4A",X"30",X"CD",X"DD",X"0B",X"DD",
X"21",X"5A",X"30",X"CD",X"A9",X"0B",X"DD",X"21",X"6A",X"30",X"CD",X"FB",X"0B",X"DD",X"21",X"4A",
X"30",X"3E",X"FF",X"DD",X"BE",X"00",X"20",X"09",X"DD",X"BE",X"0A",X"20",X"04",X"DD",X"BE",X"10",
X"C8",X"AF",X"C9",X"6B",X"10",X"81",X"10",X"95",X"10",X"9D",X"10",X"CD",X"10",X"FB",X"10",X"BD",
X"13",X"0F",X"14",X"5F",X"14",X"23",X"11",X"34",X"11",X"43",X"11",X"6B",X"10",X"81",X"10",X"95",
X"10",X"52",X"11",X"EC",X"11",X"24",X"12",X"5C",X"12",X"AE",X"12",X"FE",X"12",X"6B",X"10",X"81",
X"10",X"95",X"10",X"BF",X"14",X"D1",X"14",X"0A",X"15",X"6B",X"10",X"81",X"10",X"95",X"10",X"FC",
X"10",X"11",X"11",X"22",X"11",X"6B",X"10",X"81",X"10",X"95",X"10",X"60",X"14",X"90",X"14",X"BE",
X"14",X"FF",X"12",X"15",X"13",X"29",X"13",X"31",X"13",X"40",X"13",X"49",X"13",X"4A",X"13",X"59",
X"13",X"62",X"13",X"6B",X"10",X"81",X"10",X"95",X"10",X"6B",X"10",X"81",X"10",X"95",X"10",X"63",
X"13",X"7F",X"13",X"80",X"13",X"81",X"13",X"9D",X"13",X"9E",X"13",X"9F",X"13",X"BB",X"13",X"BC",
X"13",X"6B",X"10",X"81",X"10",X"95",X"10",X"6B",X"10",X"81",X"10",X"95",X"10",X"3E",X"00",X"32",
X"12",X"30",X"32",X"80",X"30",X"CD",X"8C",X"0A",X"AF",X"C9",X"CD",X"1A",X"0B",X"C9",X"3E",X"01",
X"32",X"12",X"30",X"32",X"80",X"30",X"CD",X"8C",X"0A",X"AF",X"C9",X"CD",X"1A",X"0B",X"C9",X"3E",
X"08",X"32",X"12",X"30",X"32",X"80",X"30",X"CD",X"8C",X"0A",X"AF",X"C9",X"CD",X"1A",X"0B",X"C9",
X"3E",X"03",X"32",X"12",X"30",X"32",X"80",X"30",X"CD",X"8C",X"0A",X"AF",X"C9",X"CD",X"1A",X"0B",
X"C9",X"3E",X"0C",X"32",X"12",X"30",X"32",X"80",X"30",X"CD",X"8C",X"0A",X"AF",X"C9",X"CD",X"1A",
X"0B",X"C9",X"3E",X"05",X"32",X"12",X"30",X"32",X"80",X"30",X"CD",X"8C",X"0A",X"AF",X"C9",X"CD",
X"1A",X"0B",X"C9",X"3E",X"06",X"32",X"12",X"30",X"32",X"80",X"30",X"CD",X"8C",X"0A",X"AF",X"C9",
X"CD",X"1A",X"0B",X"C9",X"3E",X"0A",X"32",X"12",X"30",X"32",X"80",X"30",X"CD",X"8C",X"0A",X"AF");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

38
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_sprite_color_lut.vhd
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@@ -1,38 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity time_pilot_sprite_color_lut is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(3 downto 0)
);
end entity;
architecture prom of time_pilot_sprite_color_lut is
type rom is array(0 to 255) of std_logic_vector(3 downto 0);
signal rom_data: rom := (
"0000","1101","1111","0101","0000","1110","0110","1010","0000","0100","1001","0001","0000","0100","1001","0001",
"0000","0100","1001","0001","0000","1100","0101","0001","0000","1110","0101","0001","0000","1101","0101","0001",
"0000","1011","0101","0001","0000","0001","1111","0100","0000","0001","1111","0100","0000","0001","1111","0100",
"0000","1000","0111","1100","0000","0001","1111","0100","0000","0001","1111","0100","0000","1010","0101","0001",
"0000","0101","1001","0001","0000","1011","1101","0101","0000","0110","0101","0001","0000","1010","0011","0001",
"0000","1100","0011","0001","0000","1110","0011","0001","0000","1101","0011","0001","0000","1011","0011","0001",
"0000","1110","1100","1111","0000","0101","0011","0001","0000","1110","0110","1001","0000","0100","1001","0101",
"0000","1001","1110","0110","0000","0100","1110","0101","0000","1001","1110","0101","0000","1011","0101","0001",
"0000","1100","0111","0001","0000","0101","1111","1001","0000","0101","0100","1001","0000","1010","0011","0001",
"0000","1100","0010","0011","0000","1100","0110","0011","0000","1100","0110","1001","0000","1100","0110","0001",
"0000","1110","0110","1100","0000","1100","0010","1111","0000","1100","0010","1001","0000","1100","0010","0001",
"0000","0001","1000","1111","0000","1110","0110","1111","0000","1001","1010","1111","0000","0101","0110","1111",
"0000","1011","1001","0101","0000","1010","0110","1100","0000","1010","0110","1001","0000","1010","0010","1001",
"0000","0110","0001","1111","0000","0100","0001","1111","0000","1010","0011","0001","0000","1010","0010","1100",
"0000","0101","1001","0001","0000","1010","0010","0001","0000","1110","0010","1001","0000","1110","0010","1100",
"0000","0001","0100","1111","0000","0001","0100","1111","0000","1111","1111","1111","0000","0000","0000","0000");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

243
Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/video_mixer.sv
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@@ -1,243 +0,0 @@
//
//
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//
// LINE_LENGTH: Length of display line in pixels
// Usually it's length from HSync to HSync.
// May be less if line_start is used.
//
// HALF_DEPTH: If =1 then color dept is 3 bits per component
// For half depth 6 bits monochrome is available with
// mono signal enabled and color = {G, R}
module video_mixer
#(
parameter LINE_LENGTH = 480,
parameter HALF_DEPTH = 1,
parameter OSD_COLOR = 3'd4,
parameter OSD_X_OFFSET = 10'd0,
parameter OSD_Y_OFFSET = 10'd0
)
(
// master clock
// it should be multiple by (ce_pix*4).
input clk_sys,
// Pixel clock or clock_enable (both are accepted).
input ce_pix,
// Some systems have multiple resolutions.
// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
input ce_pix_actual,
// OSD SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// 0 = HVSync 31KHz, 1 = CSync 15KHz
input scandoublerD,
// High quality 2x scaling
input hq2x,
// YPbPr always uses composite sync
input ypbpr,
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
input ypbpr_full,
input [1:0] rotate, //[0] - rotate [1] - left or right
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
input [DWIDTH:0] B,
// Monochrome mode (for HALF_DEPTH only)
input mono,
// interlace sync. Positive pulses.
input HSync,
input VSync,
// Falling of this signal means start of informative part of line.
// It can be horizontal blank signal.
// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel
// before first informative pixel.
input line_start,
// MiST video output signals
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_VS,
output VGA_HS
);
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
wire [DWIDTH:0] R_sd;
wire [DWIDTH:0] G_sd;
wire [DWIDTH:0] B_sd;
wire hs_sd, vs_sd;
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
(
.*,
.hs_in(HSync),
.vs_in(VSync),
.r_in(R),
.g_in(G),
.b_in(B),
.hs_out(hs_sd),
.vs_out(vs_sd),
.r_out(R_sd),
.g_out(G_sd),
.b_out(B_sd)
);
wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd);
wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd);
wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd);
generate
if(HALF_DEPTH) begin
wire [5:0] r = mono ? {gt,rt} : {rt,rt};
wire [5:0] g = mono ? {gt,rt} : {gt,gt};
wire [5:0] b = mono ? {gt,rt} : {bt,bt};
end else begin
wire [5:0] r = rt;
wire [5:0] g = gt;
wire [5:0] b = bt;
end
endgenerate
wire hs = (scandoublerD ? HSync : hs_sd);
wire vs = (scandoublerD ? VSync : vs_sd);
reg scanline = 0;
always @(posedge clk_sys) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) scanline <= ~scanline;
if(old_vs && ~vs) scanline <= 0;
end
wire [5:0] r_out, g_out, b_out;
always @(*) begin
case(scanlines & {scanline, scanline})
1: begin // reduce 25% = 1/2 + 1/4
r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
end
2: begin // reduce 50% = 1/2
r_out = {1'b0, r[5:1]};
g_out = {1'b0, g[5:1]};
b_out = {1'b0, b[5:1]};
end
3: begin // reduce 75% = 1/4
r_out = {2'b00, r[5:2]};
g_out = {2'b00, g[5:2]};
b_out = {2'b00, b[5:2]};
end
default: begin
r_out = r;
g_out = g;
b_out = b;
end
endcase
end
wire [5:0] red, green, blue;
osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
(
.*,
.R_in(r_out),
.G_in(g_out),
.B_in(b_out),
.HSync(hs),
.VSync(vs),
.rotate(rotate),
.R_out(red),
.G_out(green),
.B_out(blue)
);
wire [5:0] yuv_full[225] = '{
6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
6'd63
};
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
endmodule

5
Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/TimePilot_MiST.sv
View File

@@ -83,7 +83,6 @@ wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [10:0] ps2_key;
reg [10:0] audio;
wire hb, vb;
wire blankn = ~(hb | vb);
@@ -166,9 +165,7 @@ time_pilot time_pilot(
.right2(m_right),
.left2(m_left),
.down2(m_down),
.up2(m_up),
.dbg_cpu_addr()
);
.up2(m_up) );
mist_video #(.COLOR_DEPTH(5), .SD_HCNT_WIDTH(10)) mist_video(//Wrong Colors have no Idea
.clk_sys ( clock_48 ),