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IremM62: dedicated clock routing to SDRAM, sync SDRAM to vid_clk

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This commit is contained in:
Gyorgy Szombathelyi 2020-03-03 21:01:52 +01:00
parent a6b61b8b60
commit 0819e6964d
5 changed files with 43 additions and 36 deletions
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2
Arcade_MiST/IremM62 Hardware/IremM62.qsf
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@ -191,7 +191,7 @@ set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULA
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
# Assembler Assignments
# =====================

19
Arcade_MiST/IremM62 Hardware/IremM62.sdc
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@ -53,9 +53,9 @@ set_time_format -unit ns -decimal_places 3
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[2]"
set vid_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set game_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set vid_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
set game_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
set aud_clk "pll|altpll_component|auto_generated|pll1|clk[3]"
#**************************************************************
@ -91,11 +91,11 @@ set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $aud_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $aud_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sdram_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $vid_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock [get_clocks $aud_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock [get_clocks $aud_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock [get_clocks $game_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock [get_clocks $vid_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
@ -106,6 +106,7 @@ set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
set_clock_groups -asynchronous -group [get_clocks $sdram_clk] -group [get_clocks $aud_clk]
set_clock_groups -asynchronous -group [get_clocks $game_clk] -group [get_clocks $aud_clk]
#**************************************************************
# Set False Path
@ -117,8 +118,6 @@ set_clock_groups -asynchronous -group [get_clocks $sdram_clk] -group [get_clocks
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_clocks $game_clk] -to [get_clocks $sdram_clk] -setup 2
set_multicycle_path -from [get_clocks $game_clk] -to [get_clocks $sdram_clk] -hold 1
set_multicycle_path -to {VGA_*[*]} -setup 3
set_multicycle_path -to {VGA_*[*]} -hold 2

11
Arcade_MiST/IremM62 Hardware/rtl/IremM62_MiST.sv
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@ -57,9 +57,9 @@ wire pll_locked;
pll_mist pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_sys),
.c1(clk_vid),
.c2(clk_sd),
.c0(clk_sd),
.c1(clk_sys),
.c2(clk_vid),
.c3(clk_aud),
.locked(pll_locked)
);
@ -144,12 +144,15 @@ data_io data_io(
);
wire [24:0] sp_ioctl_addr = ioctl_addr - 20'h30000;
reg clkref;
always @(posedge clk_vid) clkref <= ~clkref;
reg port1_req, port2_req;
sdram sdram(
.*,
.init_n ( pll_locked ),
.clk ( clk_sd ),
.clk ( clk_sd ),
.clkref ( clkref ),
// port1 used for main + sound CPU
.port1_req ( port1_req ),

42
Arcade_MiST/IremM62 Hardware/rtl/pll_mist.vhd
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@ -166,19 +166,19 @@ BEGIN
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_duty_cycle => 50,
clk0_multiply_by => 44,
clk0_multiply_by => 88,
clk0_phase_shift => "0",
clk1_divide_by => 27,
clk1_duty_cycle => 50,
clk1_multiply_by => 11,
clk1_multiply_by => 44,
clk1_phase_shift => "0",
clk2_divide_by => 27,
clk2_duty_cycle => 50,
clk2_multiply_by => 88,
clk2_multiply_by => 11,
clk2_phase_shift => "0",
clk3_divide_by => 9000,
clk3_divide_by => 5400,
clk3_duty_cycle => 50,
clk3_multiply_by => 299,
clk3_multiply_by => 179,
clk3_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
@ -269,10 +269,10 @@ END SYN;
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "44.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "11.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "88.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.897000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "88.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "44.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "11.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.895000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@ -306,13 +306,13 @@ END SYN;
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "88"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "44.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "11.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "88.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89700000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "88.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "44.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "11.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89500000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
@ -371,19 +371,19 @@ END SYN;
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "44"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "88"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "44"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "88"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9000"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5400"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "299"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "179"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"

5
Arcade_MiST/IremM62 Hardware/rtl/sdram.sv
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@ -37,6 +37,7 @@ module sdram (
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
input clkref, // sync the state machine to clkref rising edge
input port1_req,
output reg port1_ack,
@ -108,8 +109,12 @@ localparam STATE_LAST = 3'd7;
reg [2:0] t;
always @(posedge clk) begin
reg clkref_d;
clkref_d <= clkref;
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
if (~clkref_d & clkref) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------