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GNU GENERAL PUBLIC LICENSE
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the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<http://www.gnu.org/philosophy/why-not-lgpl.html>.

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---------------------------------------------------------------------------------
--
-- Arcade: Atari Tetris for MiSTer by MiSTer-X
-- 02 December 2019
--
---------------------------------------------------------------------------------
-- 65xx compatible microprocessor core
----------------------------------------------
-- FPGAARCADE SVN: $Id: T65.vhd 1347 2015-05-27 20:07:34Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
---------------------------------------------------------------------------------
-- Pokey
----------------------------------------------
-- (c) 2013 mark watson
---------------------------------------------------------------------------------
--
--
-- Keyboard inputs :
--
-- F2 : Coin + Start 2 players
-- F1 : Coin + Start 1 player
-- DOWN,LEFT,RIGHT arrows : Movements
-- SPACE : Rotate
--
-- MAME/IPAC/JPAC Style Keyboard inputs:
-- 5 : Coin 1
-- 6 : Coin 2
-- 1 : Start 1 Player
-- 2 : Start 2 Players
-- F,D,G : Player 2 Movements
-- A : Player 2 Rotate
--
-- Joystick support.
--
--
---------------------------------------------------------------------------------
*** Attention ***
ROM is not included. In order to use this arcade, you need to provide a correct ROM file.
Find this zip file somewhere. You need to find the file exactly as required.
Do not rename other zip files even if they also represent the same game - they are not compatible!
The name of zip is taken from M.A.M.E. project, so you can get more info about
hashes and contained files there.
To generate the ROM using Windows:
1) Copy the zip into "releases" directory
2) Execute bat file - it will show the name of zip file containing required files.
3) Put required zip into the same directory and execute the bat again.
4) If everything will go without errors or warnings, then you will get the a.*.rom file.
5) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
To generate the ROM using Linux/MacOS:
1) Copy the zip into "releases" directory
2) Execute build_rom.sh
3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
To generate the ROM using MiSTer:
1) scp "releases" directory along with the zip file onto MiSTer:/media/fat/
2) Using OSD execute build_rom.sh
3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 00:21:03 December 03, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "00:21:03 December 03, 2019"
# Revisions
PROJECT_REVISION = "Tetris"
PROJECT_REVISION = "Timber"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 13:14:18 November 17, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Timber_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY Tetris_MiST
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# -------------------------
# start ENTITY(DoTron_MiST)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(DoTron_MiST)
# -----------------------
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/tet.stp
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Tetris_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/FPGA_ATetris.v
set_global_assignment -name VERILOG_FILE rtl/ATARI_SLAPSTIK1.v
set_global_assignment -name VHDL_FILE rtl/Pokey/syncreset_enable_divider.vhd
set_global_assignment -name VHDL_FILE rtl/Pokey/synchronizer.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_poly_17_9.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_poly_5.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_poly_4.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_noise_filter.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_keyboard_scanner.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_countdown_timer.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/latch_delay_line.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/delay_line.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/complete_address_decoder.vhdl
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VERILOG_FILE rtl/hvgen.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name QIP_FILE ../../common/CPU/T65/T65.qip
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name SIGNALTAP_FILE output_files/tet.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

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// Copyright (c) 2019 MiSTer-X
`define INIT_BS 2'd3
`define BS_BANK0 (AD==13'h0080)
`define BS_BANK1 (AD==13'h0090)
`define BS_BANK2 (AD==13'h00A0)
`define BS_BANK3 (AD==13'h00B0)
`define AT_1 ((AD & 13'h007F)==13'hFFFF)
`define AT_2 ((AD & 13'h1FFF)==13'h1DFF)
`define AT_3 ((AD & 13'h1FFC)==13'h1B5C)
`define AT_4 ((AD & 13'h1FCF)==13'h0080)
`define BW_1 ((AD & 13'h1FF0)==13'h1540)
`define BW_2C0 ((AX & 13'h1FF3)==13'h1540)
`define BW_2S0 ((AX & 13'h1FF3)==13'h1541)
`define BW_2C1 ((AX & 13'h1FF3)==13'h1542)
`define BW_2S1 ((AX & 13'h1FF3)==13'h1543)
`define BW_3 ((AD & 13'h1FF8)==13'h1550)
module ATARI_SLAPSTIK1
(
input RST,
input CLK,
input CLKEN,
input CS,
input [12:0] AD,
output reg [1:0] BS = `INIT_BS
);
`define SS_RESET (AD==13'h0000)
`define BS_BANKx (`BS_BANK0|`BS_BANK1|`BS_BANK2|`BS_BANK3)
`define S_DI 0
`define S_EN 1
`define S_AT1 2
`define S_AT2 3
`define S_AT3 4
`define S_BW1 5
`define S_BW2 6
`define S_BW3 7
reg bwa;
reg [1:0] ta,tb;
wire [12:0] AX = AD^{11'h0,bwa,bwa};
reg [2:0] state = `S_DI;
always @(posedge CLK) begin
if (RST) begin
state <= `S_DI;
BS <= `INIT_BS;
end
else if (CLKEN & CS) begin
if (`SS_RESET) state <= `S_EN;
else case (state)
`S_DI:;
`S_EN: if `BS_BANKx begin BS <= AD[5:4]; state <= `S_DI; end else
if `AT_1 begin state <= `S_AT1; end else
if `AT_2 begin state <= `S_AT2; end else
if `BW_1 begin state <= `S_BW1; end
`S_AT1: if `AT_2 begin state <= `S_AT2; end else state <= `S_EN;
`S_AT2: if `AT_3 begin ta <= AD[1:0]; state <= `S_AT3; end else state <= `S_EN;
`S_AT3: if `AT_4 begin BS <= ta; state <= `S_DI; end
`S_BW1: if `BS_BANKx begin bwa <= 0; tb <= BS; state <= `S_BW2; end
`S_BW2: if `BW_2C0 begin bwa <= ~bwa; tb[0] <= 1'b0; end else
if `BW_2S0 begin bwa <= ~bwa; tb[0] <= 1'b1; end else
if `BW_2C1 begin bwa <= ~bwa; tb[1] <= 1'b0; end else
if `BW_2S1 begin bwa <= ~bwa; tb[1] <= 1'b1; end else
if `BW_3 begin state <= `S_BW3; end
`S_BW3: if `BS_BANKx begin BS <= tb; state <= `S_DI; end
default:;
endcase
end
end
endmodule

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/***********************************************
FPGA Atari-Tetris
Copyright (c) 2019 MiSTer-X
Converted to clock-enable & SDRAM by Slingshot
************************************************/
module FPGA_ATetris
(
input MCLK, // 14.318MHz
input RESET,
input [10:0] INP, // Negative Logic
input [8:0] HPOS,
input [8:0] VPOS,
output PCLK,
output PCLK_EN,
output [7:0] POUT,
output [15:0] AOUT,
output [15:0] PRAD,
input [7:0] PRDT,
output [15:0] CRAD,
input [15:0] CRDT
);
// INP = {`SELFT,`COIN2,`COIN1,`P2LF,`P2RG,`P2DW,`P2RO,`P1LF,`P1RG,`P1DW,`P1RO};
// Reset Line
wire WDRST;
wire RST = WDRST|RESET;
// CPU-Bus
wire [15:0] CPUAD;
wire [7:0] CPUDO,CPUDI;
wire CPUWR,CPUIRQ;
// Clock Generator
wire PCLKx2,CPUCE;
ATETRIS_CLKGEN cgen(MCLK,PCLKx2,PCLK,PCLK_EN,CPUCE);
// ROMs
//wire [15:0] PRAD;
//wire [7:0] PRDT;
wire CRCL;
//wire [15:0] CRAD;
//wire [7:0] CRDT;
//DLROM #(16,8) prom(DEVCL,PRAD,PRDT, ROMCL,ROMAD,ROMDT,ROMEN & ~ROMAD[16]);
//DLROM #(16,8) crom( CRCL,CRAD,CRDT, ROMCL,ROMAD,ROMDT,ROMEN & ROMAD[16]);
// ROM Bank Control
wire PRDV;
ATETRIS_ROMAXS romaxs(RST,MCLK,CPUCE,CPUAD,PRAD,PRDV);
// RAMs
wire [7:0] RMDT;
wire RMDV;
ATETRIS_RAMS rams(MCLK,CPUAD,CPUWR,CPUDO,RMDT,RMDV);
// Video
wire [7:0] VDDT;
wire VDDV;
wire VBLK;
ATETRIS_VIDEO video(
MCLK,PCLK_EN,HPOS,VPOS,
POUT,VBLK,
CRCL,CRAD,CRDT,
CPUAD,CPUDO,CPUWR,VDDT,VDDV
);
// Sound & Input port
wire [7:0] P0 = {INP[10],VBLK,4'b1111,INP[8],INP[9]};
wire [7:0] P1 = INP[7:0];
wire [7:0] SNDT;
wire SNDV;
ATETRIS_SOUND sound(
RST,P0,P1,
AOUT,
MCLK,CPUCE,CPUAD,CPUDO,CPUWR,SNDT,SNDV
);
// IRQ Generator & Watch-Dog Timer
ATETRIS_IRQWDT irqwdt(RST,VPOS, MCLK,CPUCE,CPUAD,CPUWR, CPUIRQ,WDRST);
// CPU data selector
wire dum;
DSEL4x8 dsel(dum,CPUDI,
SNDV,SNDT,
VDDV,VDDT,
RMDV,RMDT,
PRDV,PRDT
);
// CPU
CPU6502W cpu(RST,MCLK,CPUCE,CPUAD,CPUWR,CPUDO,CPUDI,CPUIRQ);
endmodule
module ATETRIS_CLKGEN
(
input MCLK, // 14.318MHz
output PCLKx2, // 14.318MHz
output PCLK, // 7.1590MHz
output PCLK_EN,// 7.1590MHz
output CPUCE // 1.1789MHz
);
reg [2:0] clkdiv;
always @(posedge MCLK) clkdiv <= clkdiv+1'd1;
assign PCLKx2 = MCLK;
assign PCLK = clkdiv[0];
assign PCLK_EN= ~clkdiv[0];
assign CPUCE = clkdiv == 3'b011;
endmodule
module ATETRIS_ROMAXS
(
input RESET,
input MCLK,
input CE,
input [15:0] CPUAD,
output [15:0] PRAD,
output PRDV
);
wire [1:0] BS;
ATARI_SLAPSTIK1 bnkctr(RESET,MCLK,CE,(CPUAD[15:13]==3'b011),CPUAD[12:0],BS);
assign PRAD = {CPUAD[15],(CPUAD[15] ? CPUAD[14] : BS[0]),CPUAD[13:0]};
assign PRDV = (CPUAD[15]|(CPUAD[15:14]==2'b01));
endmodule
module ATETRIS_RAMS
(
input MCLK,
input [15:0] CPUAD,
input CPUWR,
input [7:0] CPUDO,
output [7:0] RMDT,
output RMDV
);
// WorkRAM
wire WRDV = (CPUAD[15:12]==4'b0000); // $0000-$0FFF
wire [7:0] WRDT;
//RAM_B #(12) wram(DEVCL,CPUAD,WRDV,CPUWR,CPUDO,WRDT);
spram#(
.widthad_a(12),
.width_a(8))
wram(
.address(CPUAD),
.clock(MCLK),
.data(CPUDO),
.wren(CPUWR & WRDV),
.q(WRDT)
);
// NVRAM
wire NVDV = (CPUAD[15:10]==6'b0010_01); // $24xx-$27xx
wire [7:0] NVDT;
//RAM_B #(9,255) nvram(DEVCL,CPUAD,NVDV,CPUWR,CPUDO,NVDT);
spram#(
.init_file("nvinit.hex"),
.widthad_a(9),
.width_a(8))
nvram(
.address(CPUAD),
.clock(MCLK),
.data(CPUDO),
.wren(CPUWR & NVDV),
.q(NVDT)
);
DSEL4x8 dsel(RMDV,RMDT,
WRDV,WRDT,
NVDV,NVDT
);
endmodule
module ATETRIS_IRQWDT
(
input RESET,
input [8:0] VP,
input MCLK,
input CE,
input [15:0] CPUAD,
input CPUWR,
output reg IRQ = 0,
output WDRST
);
wire tWDTR = (CPUAD[15:10]==6'b0011_00) & CPUWR; // $3000-$33FF
wire tIRQA = (CPUAD[15:10]==6'b0011_10) & CPUWR; // $3800-$3BFF
// IRQ Generator
reg [8:0] pVP;
always @(posedge MCLK) begin
if (RESET) begin
IRQ <= 0;
pVP <= 0;
end
else if (CE) begin
if (tIRQA) IRQ <= 0;
else if (pVP!=VP) begin
case (VP)
48,112,176,240: IRQ <= 1;
80,144,208, 16: IRQ <= 0;
default:;
endcase
pVP <= VP;
end
end
end
// Watch-Dog Timer
reg [3:0] WDT = 0;
assign WDRST = WDT[3];
reg [8:0] pVPT;
always @(posedge MCLK) begin
if (tWDTR) WDT <= 0;
else if (pVPT!=VP) begin
if (VP==0) WDT <= (WDT==8) ? 14 : (WDT+1);
pVPT <= VP;
end
end
endmodule
module ATETRIS_VIDEO
(
input MCLK,
input PCLK_EN,
input [8:0] HPOS,
input [8:0] VPOS,
output [7:0] POUT,
output VBLK,
output CRCL,
output reg [15:0] CRAD,
input [15:0] CRDT,
input [15:0] CPUAD,
input [7:0] CPUDO,
input CPUWR,
output [7:0] VDDT,
output VDDV
);
wire [8:0] HP = HPOS+1'd1;
wire [8:0] VP = VPOS;
// PlayField scanline generator
wire [10:0] VRAD = {VP[7:3],HP[8:3]};
wire [15:0] VRDT;
reg [15:0] VRDT_LATCH, VRDT_LATCHD;
reg [7:0] CRDT_REG;
//(* preserve *) reg [5:0] CH;
wire [5:0] CH = {VP[2:0],HP[2:0]};
always @(posedge MCLK) begin
if (PCLK_EN) begin
CRAD <= {VRDT[10:0],CH[5:1]};
end
end
assign CRCL = ~MCLK;
reg [3:0] OPIX;
always @(*) begin
case (HPOS[1:0])
2'b01: OPIX = CRDT[ 7: 4];
2'b10: OPIX = CRDT[ 3: 0];
2'b11: OPIX = CRDT[15:12];
2'b00: OPIX = CRDT[11: 8];
endcase
end
reg [7:0] PALT;
always @(posedge MCLK) begin
if (PCLK_EN) begin
VRDT_LATCH <= VRDT;
VRDT_LATCHD <= VRDT_LATCH;
PALT <= {VRDT_LATCHD[15:12],OPIX};
end
end
assign VBLK = (VPOS>=240);
// CPU interface
wire csP = (CPUAD[15:10]==6'b0010_00); // $2000-$23FF
wire csV = (CPUAD[15:12]==4'b0001); // $1000-$1FFF
wire csH = csV & CPUAD[0];
wire csL = csV & ~CPUAD[0];
wire wrH = csH & CPUWR;
wire wrL = csL & CPUWR;
wire wrP = csP & CPUWR;
wire [7:0] vdtH,vdtL,palD;
DSEL4x8 dsel(VDDV,VDDT,
csP,palD,
csH,vdtH,
csL,vdtL
);
// VideoRAMs
//DPRAMrw #(11,8) vrmH(PCLK,VRAD,VRDT[15:8], CPUCL,CPUAD[11:1],CPUDO,wrH,vdtH);
dpram #(11,8) vrmH (
.clk_a_i(MCLK),
.en_a_i(1),
.we_i(wrH),
.addr_a_i(CPUAD[11:1]),
.data_a_i(CPUDO),
.data_a_o(vdtH),
.clk_b_i(MCLK),
.addr_b_i(VRAD),
.data_b_o(VRDT[15:8])
);
//DPRAMrw #(11,8) vrmL(PCLK,VRAD,VRDT[ 7:0], CPUCL,CPUAD[11:1],CPUDO,wrL,vdtL);
dpram #(11,8) vrmL (
.clk_a_i(MCLK),
.en_a_i(1),
.we_i(wrL),
.addr_a_i(CPUAD[11:1]),
.data_a_i(CPUDO),
.data_a_o(vdtL),
.clk_b_i(MCLK),
.addr_b_i(VRAD),
.data_b_o(VRDT[7:0])
);
//DPRAMrw #(8,8) palt(MCLK,PALT,POUT, MCLK,CPUAD[ 7:0],CPUDO,wrP,palD);
dpram #(8,8) palt (
.clk_a_i(MCLK),
.en_a_i(1),
.we_i(wrP),
.addr_a_i(CPUAD[ 7:0]),
.data_a_i(CPUDO),
.data_a_o(palD),
.clk_b_i(MCLK),
.addr_b_i(PALT),
.data_b_o(POUT)
);
endmodule
module ATETRIS_SOUND
(
input RESET,
input [7:0] INP0,
input [7:0] INP1,
output [15:0] AOUT,
input MCLK,
input CE,
input [15:0] CPUAD,
input [7:0] CPUDO,
input CPUWR,
output [7:0] SNDT,
output SNDV
);
wire csPx = (CPUAD[15:10]==6'b0010_10);
wire csP0 = (CPUAD[5:4]==2'b00) & csPx; // $280x
wire csP1 = (CPUAD[5:4]==2'b01) & csPx; // $281x
wire [7:0] rdt0,rdt1;
wire [7:0] snd0,snd1;
PokeyW p0(MCLK,CE,RESET, CPUAD,csP0,CPUWR,CPUDO,rdt0, INP0,snd0);
PokeyW p1(MCLK,CE,RESET, CPUAD,csP1,CPUWR,CPUDO,rdt1, INP1,snd1);
DSEL4x8 dsel(SNDV,SNDT,
csP0,rdt0,
csP1,rdt1
);
wire [8:0] snd = snd0+snd1;
assign AOUT = {snd,7'h0};
endmodule
// CPU-IP wrapper
module CPU6502W
(
input RST,
input CLK,
input CE,
output [15:0] AD,
output WR,
output [7:0] DO,
input [7:0] DI,
input IRQ
);
wire rw;
assign WR = ~rw;
T65 cpu
(
.mode(2'b01),
// .BCD_en(1'b1),
.res_n(~RST),
.enable(CE),
.clk(CLK),
.rdy(1'b1),
.abort_n(1'b1),
.irq_n(~IRQ),
.nmi_n(1'b1),
.so_n(1'b1),
.r_w_n(rw),
.a(AD),
.di(DI),
.do(DO)
);
endmodule
// Pokey-IP wrapper
module PokeyW
(
input CLK,
input CE,
input RST,
input [3:0] AD,
input CS,
input WE,
input [7:0] WD,
output [7:0] RD,
input [7:0] P,
output [7:0] SND
);
wire [3:0] ch0,ch1,ch2,ch3;
pokey core (
.RESET_N(~RST),
.CLK(CLK),
.ADDR(AD),
.DATA_IN(WD),
.DATA_OUT(RD),
.WR_EN(WE & CS),
.ENABLE_179(CE),
.POT_IN(P),
.CHANNEL_0_OUT(ch0),
.CHANNEL_1_OUT(ch1),
.CHANNEL_2_OUT(ch2),
.CHANNEL_3_OUT(ch3)
);
assign SND = ch0+ch1+ch2+ch3;
endmodule
// Data selector
module DSEL4x8
(
output odv,
output [7:0] odt,
input en0, input [7:0] dt0,
input en1, input [7:0] dt1,
input en2, input [7:0] dt2,
input en3, input [7:0] dt3
);
assign odv = en0|en1|en2|en3;
assign odt = en0 ? dt0 :
en1 ? dt1 :
en2 ? dt2 :
en3 ? dt3 :
8'h00;
endmodule

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---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END complete_address_decoder;
--ARCHITECTURE vhdl OF complete_address_decoder IS
--BEGIN
-- comp_gen:
-- for i in 0 to ((2**width)-1) generate
-- addr_decoded(i) <= '1' when i=to_integer(unsigned(addr_in)) else '0';
-- end generate;
--end vhdl;
architecture tree of complete_address_decoder is
constant STAGE : natural:=width;
type std_logic_2d is array (natural range <>,natural range <>) of std_logic;
signal p: std_logic_2d(stage downto 0,2**stage-1 downto 0);
signal a: std_logic_vector(width-1 downto 0) ;
begin
a<=addr_in;
process(a,p)
begin
p(stage,0) <= '1';
for s in stage downto 1 loop
for r in 0 to (2**(stage-s)-1) loop
p(s-1,2*r) <= (not a(s-1)) and p(s,r);
p(s-1,2*r+1) <= a(s-1) and p(s,r);
end loop;
end loop;
for i in 0 to (2**stage-1) loop
addr_decoded(i) <= p(0,i);
end loop;
end process;
end tree;

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---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END delay_line;
ARCHITECTURE vhdl OF delay_line IS
signal shift_reg : std_logic_vector(COUNT-1 downto 0);
signal shift_next : std_logic_vector(COUNT-1 downto 0);
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_N = '0') then
shift_reg <= (others=>'0');
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- shift on enable
process(shift_reg,enable,data_in,sync_reset)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= data_in&shift_reg(COUNT-1 downto 1);
end if;
if (sync_reset = '1') then
shift_next <= (others=>'0');
end if;
end process;
-- output
data_out <= shift_reg(0) and enable;
END vhdl;

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---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY latch_delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END latch_delay_line;
ARCHITECTURE vhdl OF latch_delay_line IS
signal shift_reg : std_logic_vector(COUNT-1 downto 0);
signal shift_next : std_logic_vector(COUNT-1 downto 0);
signal data_in_reg : std_logic;
signal data_in_next : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_N = '0') then
shift_reg <= (others=>'0');
data_in_reg <= '0';
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
data_in_reg <= data_in_next;
end if;
end process;
-- shift on enable
process(shift_reg,enable,data_in,data_in_reg,sync_reset)
begin
shift_next <= shift_reg;
data_in_next <= data_in or data_in_reg;
if (enable = '1') then
shift_next <= (data_in or data_in_reg)&shift_reg(COUNT-1 downto 1);
data_in_next <= '0';
end if;
if (sync_reset = '1') then
shift_next <= (others=>'0');
data_in_next <= '0';
end if;
end process;
-- output
data_out <= shift_reg(0) and enable;
END vhdl;

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---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_countdown_timer IS
generic(UNDERFLOW_DELAY : natural := 3);
PORT
(
CLK : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
ENABLE_UNDERFLOW : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
DATA_OUT : OUT STD_LOGIC
);
END pokey_countdown_timer;
ARCHITECTURE vhdl OF pokey_countdown_timer IS
component delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END component;
function To_Std_Logic(L: BOOLEAN) return std_ulogic is
begin
if L then
return('1');
else
return('0');
end if;
end function To_Std_Logic;
signal count_reg : std_logic_vector(7 downto 0);
signal count_next: std_logic_vector(7 downto 0);
signal underflow : std_logic;
signal count_command : std_logic_vector(1 downto 0);
signal underflow_command: std_logic_vector(1 downto 0);
BEGIN
-- Instantiate delay (provides output)
underflow0_delay : delay_line
generic map (COUNT=>UNDERFLOW_DELAY)
port map(clk=>clk,sync_reset=>wr_en,data_in=>underflow,enable=>ENABLE_UNDERFLOW,reset_n=>reset_n,data_out=>data_out);
-- register
process(clk,reset_n)
begin
if (reset_N = '0') then
count_reg <= (others=>'0');
elsif (clk'event and clk='1') then
count_reg <= count_next;
end if;
end process;
-- count down on enable
process(count_reg,enable,wr_en,count_command,data_in)
begin
count_command <= enable&wr_en;
case count_command is
when "10" =>
count_next <= std_logic_vector(unsigned(count_reg) -1);
when "01"|"11" =>
count_next <= data_in;
when others =>
count_next <= count_reg;
end case;
end process;
-- underflow
process(count_reg,enable,underflow_command)
begin
underflow_command <= enable & To_Std_Logic(count_reg = X"00");
case underflow_command is
when "11" =>
underflow <= '1';
when others =>
underflow <= '0';
end case;
end process;
END vhdl;

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---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pokey_keyboard_scanner is
port
(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic; -- typically hsync or equiv timing
keyboard_response : in std_logic_vector(1 downto 0);
debounce_disable : in std_logic;
scan_enable : in std_logic;
keyboard_scan : out std_logic_vector(5 downto 0);
key_held : out std_logic;
shift_held : out std_logic;
keycode : out std_logic_vector(7 downto 0);
other_key_irq : out std_logic;
break_irq : out std_logic
);
end pokey_keyboard_scanner;
architecture vhdl of pokey_keyboard_scanner is
signal bincnt_next : std_logic_vector(5 downto 0);
signal bincnt_reg : std_logic_vector(5 downto 0);
signal break_pressed_next : std_logic;
signal break_pressed_reg : std_logic;
signal shift_pressed_next : std_logic;
signal shift_pressed_reg : std_logic;
signal control_pressed_next : std_logic;
signal control_pressed_reg : std_logic;
signal compare_latch_next : std_logic_vector(5 downto 0);
signal compare_latch_reg : std_logic_vector(5 downto 0);
signal keycode_latch_next : std_logic_vector(7 downto 0);
signal keycode_latch_reg : std_logic_vector(7 downto 0);
signal irq_next : std_logic;
signal irq_reg : std_logic;
signal break_irq_next : std_logic;
signal break_irq_reg : std_logic;
signal key_held_next : std_logic;
signal key_held_reg : std_logic;
signal my_key : std_logic;
signal state_next : std_logic_vector(1 downto 0);
signal state_reg : std_logic_vector(1 downto 0);
constant state_wait_key : std_logic_vector(1 downto 0) := "00";
constant state_key_bounce : std_logic_vector(1 downto 0) := "01";
constant state_valid_key : std_logic_vector(1 downto 0) := "10";
constant state_key_debounce : std_logic_vector(1 downto 0) := "11";
begin
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
bincnt_reg <= (others=>'0');
break_pressed_reg <= '0';
shift_pressed_reg <= '0';
control_pressed_reg <= '0';
compare_latch_reg <= (others=>'0');
keycode_latch_reg <= (others=>'1');
key_held_reg <= '0';
state_reg <= state_wait_key;
irq_reg <= '0';
break_irq_reg <= '0';
elsif (clk'event and clk = '1') then
bincnt_reg <= bincnt_next;
state_reg <= state_next;
break_pressed_reg <= break_pressed_next;
shift_pressed_reg <= shift_pressed_next;
control_pressed_reg <= control_pressed_next;
compare_latch_reg <= compare_latch_next;
keycode_latch_reg <= keycode_latch_next;
key_held_reg <= key_held_next;
state_reg <= state_next;
irq_reg <= irq_next;
break_irq_reg <= break_irq_next;
end if;
end process;
process (enable, keyboard_response, scan_enable, key_held_reg, my_key, state_reg,bincnt_reg, compare_latch_reg, break_pressed_next, break_pressed_reg, shift_pressed_reg, break_irq_reg, control_pressed_reg, keycode_latch_reg, debounce_disable)
begin
bincnt_next <= bincnt_reg;
state_next <= state_reg;
compare_latch_next <= compare_latch_reg;
irq_next <= '0';
break_irq_next <= '0';
break_pressed_next <= break_pressed_reg;
shift_pressed_next <= shift_pressed_reg;
control_pressed_next <= control_pressed_reg;
keycode_latch_next <= keycode_latch_reg;
key_held_next <= key_held_reg;
my_key <= '0';
if (bincnt_reg = compare_latch_reg or debounce_disable='1') then
my_key <= '1';
end if;
if (enable = '1' and scan_enable='1') then
bincnt_next <= std_logic_vector(unsigned(bincnt_reg) + 1); -- check another key
key_held_next<= '0';
case state_reg is
when state_wait_key =>
if (keyboard_response(0) = '0') then -- detected key press
if (debounce_disable = '1') then
keycode_latch_next <= control_pressed_reg&shift_pressed_reg&bincnt_reg;
irq_next <= '1';
key_held_next<= '1';
else
state_next <= state_key_bounce;
compare_latch_next <= bincnt_reg;
end if;
end if;
when state_key_bounce =>
if (keyboard_response(0) = '0') then -- detected key press
if (my_key = '1') then -- same key
keycode_latch_next <= control_pressed_reg&shift_pressed_reg&compare_latch_reg;
irq_next <= '1';
key_held_next<= '1';
state_next <= state_valid_key;
else -- different key (multiple keys pressed)
state_next <= state_wait_key;
end if;
else -- key not pressed
if (my_key = '1') then -- same key, no longer pressed
state_next <= state_wait_key;
end if;
end if;
when state_valid_key =>
key_held_next<= '1';
if (my_key = '1') then -- only response to my key
if (keyboard_response(0) = '1') then -- no longer pressed
state_next <= state_key_debounce;
end if;
end if;
when state_key_debounce =>
key_held_next<= '1';
if (my_key = '1') then
if (keyboard_response(0) = '1') then -- no longer pressed
key_held_next<= '0';
state_next <= state_wait_key;
else
state_next <= state_valid_key;
end if;
end if;
when others=>
state_next <= state_wait_key;
end case;
if (bincnt_reg(3 downto 0) = "0000") then
case bincnt_reg(5 downto 4) is
when "11" =>
break_pressed_next <= not(keyboard_response(1)); --0x30
when "01" =>
shift_pressed_next <= not(keyboard_response(1)); --0x10
when "00" =>
control_pressed_next <= not(keyboard_response(1)); -- 0x00
when others =>
--
end case;
end if;
end if;
if (break_pressed_next='1' and break_pressed_reg='0') then
break_irq_next <= '1';
end if;
end process;
-- outputs
keyboard_scan <= not(bincnt_reg);
key_held <= key_held_reg;
shift_held <= shift_pressed_reg;
keycode <= keycode_latch_reg;
other_key_irq <= irq_reg;
break_irq <= break_irq_reg;
end vhdl;

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---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_noise_filter IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
PULSE_IN : IN STD_LOGIC;
NOISE_4 : IN STD_LOGIC;
NOISE_5 : IN STD_LOGIC;
NOISE_LARGE : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
PULSE_OUT : OUT STD_LOGIC
);
END pokey_noise_filter;
ARCHITECTURE vhdl OF pokey_noise_filter IS
-- signal pulse_noise_a : std_logic;
-- signal pulse_noise_b : std_logic;
signal audclk : std_logic;
signal out_next : std_logic;
signal out_reg : std_logic;
BEGIN
process(clk,reset_n)
begin
if (reset_n='0') then
out_reg <= '0';
elsif (clk'event and clk='1') then
out_reg <= out_next;
end if;
end process;
pulse_out <= out_reg;
process(pulse_in, noise_4, noise_5, noise_large, noise_select, audclk, out_reg, sync_reset)
begin
audclk <= pulse_in;
out_next <= out_reg;
if (NOISE_SELECT(2) = '0') then
audclk <= pulse_in and noise_5;
end if;
if (audclk = '1') then
if (NOISE_SELECT(0) = '1') then
-- toggle
out_next <= not(out_reg);
else
-- sample
if (NOISE_SELECT(1) = '1') then
out_next <= noise_4;
else
out_next <= noise_large;
end if;
end if;
end if;
if (sync_reset = '1') then
out_next <= '0';
end if;
end process;
end vhdl;

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---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_poly_17_9 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC;
RAND_OUT : OUT std_logic_vector(7 downto 0)
);
END pokey_poly_17_9;
ARCHITECTURE vhdl OF pokey_poly_17_9 IS
signal shift_reg: std_logic_vector(16 downto 0);
signal shift_next: std_logic_vector(16 downto 0);
signal cycle_delay_reg : std_logic;
signal cycle_delay_next : std_logic;
signal select_9_17_del_reg : std_logic;
signal select_9_17_del_next : std_logic;
signal feedback : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
shift_reg <= "01010101010101010";
cycle_delay_reg <= '0';
select_9_17_del_reg <= '0';
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
cycle_delay_reg <= cycle_delay_next;
select_9_17_del_reg <= select_9_17_del_next;
end if;
end process;
-- next state (as pokey decap)
feedback <= shift_reg(13) xnor shift_reg(8);
process(enable,shift_reg,feedback,select_9_17,select_9_17_del_reg,init,cycle_delay_reg)
begin
shift_next <= shift_reg;
cycle_delay_next <= cycle_delay_reg;
select_9_17_del_next <= select_9_17_del_reg;
if (enable = '1') then
select_9_17_del_next <= select_9_17;
shift_next(15 downto 8) <= shift_reg(16 downto 9);
shift_next(7) <= feedback;
shift_next(6 downto 0) <= shift_reg(7 downto 1);
shift_next(16) <= ((feedback and select_9_17_del_reg) or (shift_reg(0) and not(select_9_17))) and not(init);
cycle_delay_next <= shift_reg(9);
end if;
end process;
-- output
bit_out <= cycle_delay_reg; -- from pokey schematics
RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8));
END vhdl;

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---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_poly_4 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END pokey_poly_4;
ARCHITECTURE vhdl OF pokey_poly_4 IS
signal shift_reg: std_logic_vector(3 downto 0);
signal shift_next: std_logic_vector(3 downto 0);
BEGIN
-- register
process(clk, reset_n)
begin
if (reset_n = '0') then
shift_reg <= "1010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state
process(shift_reg,enable,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= ((shift_reg(1) xnor shift_reg(0)) and not(init))&shift_reg(3 downto 1);
end if;
end process;
-- output
bit_out <= shift_reg(0);
END vhdl;

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---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_poly_5 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END pokey_poly_5;
ARCHITECTURE vhdl OF pokey_poly_5 IS
signal shift_reg: std_logic_vector(4 downto 0);
signal shift_next: std_logic_vector(4 downto 0);
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
shift_reg <= "01010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state
process(shift_reg,enable,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= ((shift_reg(2) xnor shift_reg(0)) and not(init))&shift_reg(4 downto 1);
end if;
end process;
-- output
bit_out <= shift_reg(0);
END vhdl;

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---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY synchronizer IS
PORT
(
CLK : IN STD_LOGIC;
RAW : IN STD_LOGIC;
SYNC : OUT STD_LOGIC
);
END synchronizer;
ARCHITECTURE vhdl OF synchronizer IS
signal ff_next : std_logic_vector(2 downto 0);
signal ff_reg : std_logic_vector(2 downto 0);
begin
-- register
process(clk)
begin
if (clk'event and clk='1') then
ff_reg <= ff_next;
end if;
end process;
ff_next <= RAW&ff_reg(2 downto 1);
SYNC <= ff_reg(0);
end vhdl;

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---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY syncreset_enable_divider IS
generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
PORT
(
CLK : IN STD_LOGIC;
SYNCRESET : in std_logic;
RESET_N : IN STD_LOGIC;
ENABLE_IN : IN STD_LOGIC;
ENABLE_OUT : OUT STD_LOGIC
);
END syncreset_enable_divider;
ARCHITECTURE vhdl OF syncreset_enable_divider IS
function log2c(n : integer) return integer is
variable m,p : integer;
begin
m := 0;
p := 1;
while p<n loop
m:=m+1;
p:=p*2;
end loop;
return m;
end log2c;
constant WIDTH : natural := log2c(COUNT);
signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
signal count_next : std_logic_vector(WIDTH-1 downto 0);
signal enabled_out_next : std_logic;
signal enabled_out_reg : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
count_reg <= (others=>'0');
enabled_out_reg <= '0';
elsif (clk'event and clk='1') then
count_reg <= count_next;
enabled_out_reg <= enabled_out_next;
end if;
end process;
-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
process(count_reg,enable_in,enabled_out_reg,syncreset)
begin
count_next <= count_reg;
enabled_out_next <= enabled_out_reg;
if (enable_in = '1') then
count_next <= std_logic_vector(unsigned(count_reg) + 1);
enabled_out_next <= '0';
if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
count_next <= std_logic_vector(to_unsigned(0,WIDTH));
enabled_out_next <= '1';
end if;
end if;
if (syncreset='1') then
count_next <= std_logic_vector(to_unsigned(resetcount,width));
end if;
end process;
-- output
enable_out <= enabled_out_reg and enable_in;
END vhdl;

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module Tetris_MiST(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl/build_id.v"
localparam CONF_STR = {
"TETRIS;ROM;",
"O2,Service,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blend,Off,On;",
"T0,Reset;",
"V,v1.0.",`BUILD_DATE
};
assign LED = ~ioctl_downl;
assign SDRAM_CLK = clk_sd;
assign SDRAM_CKE = 1;
assign AUDIO_R = AUDIO_L;
wire clk_sys, clk_sd;
wire pll_locked;
pll_mist pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_sd),//3xclk_sys
.c1(clk_sys),//14.318
.locked(pll_locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [15:0] audio;
wire hs, vs, hb, vb;
wire blankn = ~(hb | vb);
wire [2:0] g, r;
wire [1:0] b;
wire [15:0] rom_addr;
wire [15:0] rom_do;
wire [15:0] gfx_addr;
wire [15:0] gfx_do;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
data_io data_io(
.clk_sys ( clk_sd ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
reg port1_req, port2_req;
sdram sdram(
.*,
.init_n ( pll_locked ),
.clk ( clk_sd ),
.clkref ( PCLK ),
// port1 used for main CPU
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( ioctl_downl ? 16'hffff : {2'b00, rom_addr[15:1]}),
.cpu1_q ( rom_do ),
// port2 for gfx
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( ioctl_addr[23:1] - 16'h8000 ),
.port2_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port2_we ( ioctl_downl ),
.port2_d ( {ioctl_dout, ioctl_dout} ),
.port2_q ( ),
.gfx_addr ( gfx_addr[15:1] ),
.gfx_q ( gfx_do )
);
always @(posedge clk_sd) begin
reg ioctl_wr_last = 0;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
port1_req <= ~port1_req;
port2_req <= ~port2_req;
end
end
end
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clk_sd) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ~rom_loaded;
end
wire [10:0] INP = ~{status[2],1'b1, btn_coin, m_left2, m_right2, m_down2, m_fire2, m_left1, m_right1, m_down1, m_fire1};
FPGA_ATetris FPGA_ATetris(
.MCLK(clk_sys), // 14.318MHz
.RESET(reset),
.INP(INP), // Negative Logic
.HPOS(HPOS),
.VPOS(VPOS),
.PCLK(PCLK),
.PCLK_EN(PCLK_EN),
.POUT(POUT),
.AOUT(audio),
.PRAD(rom_addr),
.PRDT(rom_addr[0] ? rom_do[15:8] : rom_do[7:0]),
.CRAD(gfx_addr),
.CRDT(gfx_do)
);
wire PCLK;
wire PCLK_EN;
wire [8:0] HPOS,VPOS;
wire [7:0] POUT;
hvgen hvgen(
.MCLK(clk_sys),
.PCLK_EN(PCLK_EN),
.HPOS(HPOS),
.VPOS(VPOS),
.iRGB(POUT),
.oRGB({r,g,b}),
.HBLK(hb),
.VBLK(vb),
.HSYN(hs),
.VSYN(vs)
);
mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? r : 0 ),
.G ( blankn ? g : 0 ),
.B ( blankn ? {b,b[0]} : 0 ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.ce_divider ( 1'b1 ),
.blend ( status[5] ),
.scandoubler_disable(scandoublerD ),
.scanlines ( status[4:3] ),
.ypbpr ( ypbpr )
);
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.C_bits(16))
dac_l(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(audio),
.dac_o(AUDIO_L)
);
wire m_down1 = btn_down | joystick_0[2];
wire m_left1 = btn_left | joystick_0[1];
wire m_right1 = btn_right | joystick_0[0];
wire m_fire1 = btn_fire1 | joystick_0[4];
wire m_down2 = joystick_1[2];
wire m_left2 = joystick_1[1];
wire m_right2 = joystick_1[0];
wire m_fire2 = joystick_1[4];
//reg btn_one_player = 0;
//reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
//reg btn_up = 0;
reg btn_fire1 = 0;
//reg btn_fire2 = 0;
//reg btn_fire3 = 0;
reg btn_coin = 0;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
always @(posedge clk_sys) begin
if(key_strobe) begin
case(key_code)
// 'h75: btn_up <= key_pressed; // up
'h72: btn_down <= key_pressed; // down
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
// 'h05: btn_one_player <= key_pressed; // F1
// 'h06: btn_two_players <= key_pressed; // F2
// 'h14: btn_fire3 <= key_pressed; // ctrl
// 'h11: btn_fire2 <= key_pressed; // alt
'h29: btn_fire1 <= key_pressed; // Space
endcase
end
end
endmodule

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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-------------------------------------------------------------------------------
-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dpram is
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
port (
clk_a_i : in std_logic;
en_a_i : in std_logic;
we_i : in std_logic;
addr_a_i : in std_logic_vector(addr_width_g-1 downto 0);
data_a_i : in std_logic_vector(data_width_g-1 downto 0);
data_a_o : out std_logic_vector(data_width_g-1 downto 0);
clk_b_i : in std_logic;
addr_b_i : in std_logic_vector(addr_width_g-1 downto 0);
data_b_o : out std_logic_vector(data_width_g-1 downto 0)
);
end dpram;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dpram is
type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0);
signal ram_q : ram_t;
begin
mem_a: process (clk_a_i)
begin
if rising_edge(clk_a_i) then
if we_i = '1' and en_a_i = '1' then
ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i;
data_a_o <= data_a_i;
else
data_a_o <= ram_q(to_integer(unsigned(addr_a_i)));
end if;
end if;
end process mem_a;
mem_b: process (clk_b_i)
begin
if rising_edge(clk_b_i) then
data_b_o <= ram_q(to_integer(unsigned(addr_b_i)));
end if;
end process mem_b;
end rtl;

45
Arcade_MiST/Atari Tetris/rtl/hvgen.v Normal file
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@ -0,0 +1,45 @@
module hvgen
(
input MCLK,
input PCLK_EN,
output [8:0] HPOS,
output [8:0] VPOS,
input PCLK,
input [7:0] iRGB,
output reg [7:0] oRGB,
output reg HBLK = 1,
output reg VBLK = 1,
output reg HSYN = 1,
output reg VSYN = 1
);
reg [8:0] hcnt = 0;
reg [8:0] vcnt = 0;
assign HPOS = hcnt-1'd1;
assign VPOS = vcnt;
always @(posedge MCLK) begin
if (PCLK_EN) begin
case (hcnt)
0: begin HBLK <= 0; hcnt <= hcnt+1'd1; end
337: begin HBLK <= 1; hcnt <= hcnt+1'd1; end
352: begin HSYN <= 0; hcnt <= hcnt+1'd1; end
416: begin HSYN <= 1; hcnt <= 481; end
511: begin hcnt <= 0;
case (vcnt)
239: begin VBLK <= 1; vcnt <= vcnt+1'd1; end
248: begin VSYN <= 0; vcnt <= vcnt+1'd1; end
259: begin VSYN <= 1; vcnt <= vcnt+1'd1; end
262: begin VBLK <= 0; vcnt <= 0; end
default: vcnt <= vcnt+1'd1;
endcase
end
default: hcnt <= hcnt+1'd1;
endcase
oRGB <= (HBLK|VBLK) ? 8'h0 : iRGB;
end
end
endmodule

18
Arcade_MiST/Atari Tetris/rtl/nvinit.hex Normal file
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:020000040000FA
:20000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00
:20002000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0
:20004000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0
:20006000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA0
:20008000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80
:2000A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF60
:2000C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF40
:2000E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF20
:20010000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
:20012000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF
:20014000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBF
:20016000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9F
:20018000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7F
:2001A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5F
:2001C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3F
:2001E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1F
:00000001FF

429
Arcade_MiST/Atari Tetris/rtl/pll_mist.vhd Normal file
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@ -0,0 +1,429 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll_mist.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll_mist IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll_mist;
ARCHITECTURE SYN OF pll_mist IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 22,
clk0_duty_cycle => 50,
clk0_multiply_by => 35,
clk0_phase_shift => "0",
clk1_divide_by => 66,
clk1_duty_cycle => 50,
clk1_multiply_by => 35,
clk1_phase_shift => "0",
clk2_divide_by => 180,
clk2_duty_cycle => 50,
clk2_multiply_by => 191,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll_mist",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "22"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "66"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "180"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "42.954544"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.318182"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "28.650000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "35"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "35"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "191"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "57.27200000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.31800000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "28.63600000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "22"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "35"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "66"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "35"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "180"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "191"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

328
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//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
input clkref, // sync state machine to this signal's rising edge
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output [15:0] port1_q,
input [15:1] cpu1_addr,
output reg [15:0] cpu1_q,
input port2_req,
output reg port2_ack,
input port2_we,
input [23:1] port2_a,
input [1:0] port2_ds,
input [15:0] port2_d,
output [15:0] port2_q,
input [15:1] gfx_addr,
output reg [15:0] gfx_q
);
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
localparam RFRSH_CYCLES = 10'd842;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
/*
SDRAM state machine for 2 bank interleaved access
1 word burst, CL2
cmd issued registered
0 RAS0 cas1
1 ras0
2 CAS0 data1 returned
3 RAS1 cas0
4 ras1
5 CAS1 data0 returned
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5
localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7
localparam STATE_READ1 = 3'd2;
localparam STATE_LAST = 3'd5;
reg [2:0] t;
always @(posedge clk) begin
reg clkref_d;
clkref_d <= clkref;
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
if (~clkref_d & clkref) t <= 3'd4;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[2];
reg [24:1] addr_latch_next[2];
reg [15:1] addr_last[2];
reg [15:1] addr_last2[2];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
reg [1:0] we_latch;
reg [1:0] ds[2];
localparam PORT_NONE = 2'd0;
localparam PORT_CPU1 = 2'd1;
localparam PORT_REQ = 2'd2;
localparam PORT_SND = 2'd1;
reg [2:0] next_port[2];
reg [2:0] port[2];
reg refresh;
reg [10:0] refresh_cnt;
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
// PORT1: bank 0,1
always @(*) begin
if (refresh) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end else if (port1_req ^ port1_ack) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
next_port[0] = PORT_CPU1;
addr_latch_next[0] = { 9'd0, cpu1_addr };
end else begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end
end
// PORT2: bank 2,3
always @(*) begin
if (port2_req ^ port2_ack) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (gfx_addr != addr_last2[PORT_SND]) begin
next_port[1] = PORT_SND;
addr_latch_next[1] = { 1'b1, 8'd0, gfx_addr };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
end
end
always @(posedge clk) begin
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
if(init) begin
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
end
end else begin
// RAS phase
// bank 0,1
if(t == STATE_RAS0) begin
addr_latch[0] <= addr_latch_next[0];
port[0] <= next_port[0];
{ oe_latch[0], we_latch[0] } <= 2'b00;
if (next_port[0] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
addr_last[next_port[0]] <= addr_latch_next[0][15:1];
if (next_port[0] == PORT_REQ) begin
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
ds[0] <= port1_ds;
din_latch[0] <= port1_d;
end else begin
{ oe_latch[0], we_latch[0] } <= 2'b10;
ds[0] <= 2'b11;
end
end
end
// bank 2,3
if(t == STATE_RAS1) begin
refresh <= 1'b0;
addr_latch[1] <= addr_latch_next[1];
{ oe_latch[1], we_latch[1] } <= 2'b00;
port[1] <= next_port[1];
if (next_port[1] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[1][22:10];
SDRAM_BA <= addr_latch_next[1][24:23];
addr_last2[next_port[1]] <= addr_latch_next[1][15:1];
if (next_port[1] == PORT_REQ) begin
{ oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
end
end
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
refresh <= 1'b1;
refresh_cnt <= 0;
sd_cmd <= CMD_AUTO_REFRESH;
end
end
// CAS phase
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
if (we_latch[0]) begin
SDRAM_DQ <= din_latch[0];
port1_ack <= port1_req;
end
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[0][24:23];
end
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if (we_latch[1]) begin
SDRAM_DQ <= din_latch[1];
port2_ack <= port2_req;
end
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[1][24:23];
end
// Data returned
if(t == STATE_READ0 && oe_latch[0]) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; end
default: ;
endcase;
end
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ: begin port2_q <= SDRAM_DQ/*sd_din*/; port2_ack <= port2_req; end
PORT_SND: begin gfx_q <= SDRAM_DQ/*sd_din*/; end
default: ;
endcase;
end
end
end
endmodule

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY spram IS
GENERIC
(
init_file : string := "";
--numwords_a : natural;
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END spram;
ARCHITECTURE SYN OF spram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;