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2048_Mist/README.md
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# 2048-DE1
VHDL implementation of 2048 Game on Altera DE1 FPGA Board developed in the "Digital Systems M" course of the University of Bologna
# 2048-MIST
VHDL implementation of 2048 Game on MiST FPGA Board developed in the "Digital Systems M" course of the University of Bologna
Controls

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Soundboards_MiST/AS-2518-51_snd-master/AS-2518-51_snd.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 21:32:18 December 01, 2015
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "21:32:18 December 01, 2015"
# Revisions
PROJECT_REVISION = "AS-2518-51_snd"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 21:32:18 December 01, 2015
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# AS-2518-51_snd_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name TOP_LEVEL_ENTITY minibd_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:32:18 DECEMBER 01, 2015"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity robotron_sound_top -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity robotron_sound_top -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity robotron_sound_top -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity robotron_sound_top -section_id Top
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name VHDL_FILE rtl/minibd_top.vhd
set_global_assignment -name VHDL_FILE "rtl/AS-2518-51_core.vhd"
set_global_assignment -name QIP_FILE rtl/williams_snd_pll.qip
set_global_assignment -name QIP_FILE rtl/U4_ROM.qip
set_global_assignment -name VHDL_FILE rtl/PS2Controller.vhd
set_global_assignment -name VHDL_FILE rtl/pia6821.vhd
set_global_assignment -name VHDL_FILE rtl/MPU_RAM.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv
set_global_assignment -name VHDL_FILE rtl/m6810.vhd
set_global_assignment -name VHDL_FILE rtl/KeyboardMapper.vhd
set_global_assignment -name VHDL_FILE rtl/Keyboard.vhd
set_global_assignment -name VHDL_FILE rtl/Debouncer.vhd
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name VHDL_FILE rtl/cpu68.vhd
set_global_assignment -name VHDL_FILE "rtl/ay-3-8910-core.Vhd"
set_global_assignment -name VHDL_FILE "rtl/ay-3-8910_vectors.vhd"
set_global_assignment -name VHDL_FILE "rtl/ay-3-8910.Vhd"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Soundboards_MiST/AS-2518-51_snd-master/README.txt Normal file
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Bally AS-2518-51 sound board, the predecessor of the Squawk & Talk used in late 70's Bally pinballs
https://github.com/FPGA-Code/AS-2518-51_snd
No Video Output!!!
Keyboard Controls

BIN
Soundboards_MiST/AS-2518-51_snd-master/Release/AS-2518-51_snd.rbf Normal file
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Binary file not shown.

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Soundboards_MiST/AS-2518-51_snd-master/clean.bat Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

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Soundboards_MiST/AS-2518-51_snd-master/rtl/AS-2518-51_core.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity AS_2518_51 is
port(
cpu_clk : in std_logic;
reset_l : in std_logic;
test_sw_l : in std_logic;
addr_i : in std_logic_vector(5 downto 0);
snd_int_i : in std_logic;
audio : out std_logic_vector(10 downto 0)
);
end;
architecture rtl of AS_2518_51 is
signal E : std_logic;
signal reset_h : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_din : std_logic_vector(7 downto 0) := x"FF";
signal cpu_dout : std_logic_vector(7 downto 0);
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal pia_pa_i : std_logic_vector(7 downto 0) := x"FF";
signal pia_pa_o : std_logic_vector(7 downto 0);
signal pia_pb_i : std_logic_vector(7 downto 0) := x"FF";
signal pia_pb_o : std_logic_vector(7 downto 0);
signal pia_dout : std_logic_vector(7 downto 0);
signal pia_irq_a : std_logic;
signal pia_irq_b : std_logic;
signal pia_cb1 : std_logic;
signal pia_cs : std_logic;
signal ay_pa_i : std_logic_vector(7 downto 0);
signal rom_dout : std_logic_vector(7 downto 0);
signal rom_cs : std_logic;
signal ram_dout : std_logic_vector(7 downto 0);
signal ram_cs : std_logic;
signal snd_a : std_logic_vector(7 downto 0);
signal snd_b : std_logic_vector(7 downto 0);
signal snd_c : std_logic_vector(7 downto 0);
signal clk_div : std_logic_vector(2 downto 0);
begin
reset_h <= (not reset_l);
E <= clk_div(2);
divider: process(cpu_clk)
begin
if rising_edge(cpu_clk) then
clk_div <= clk_div + '1';
end if;
end process;
cpu_irq <= pia_irq_a or pia_irq_b;
cpu_nmi <= not test_sw_l;
rom_cs <= cpu_addr(12) and cpu_vma;
pia_cs <= cpu_addr(7) and (not cpu_addr(12)) and cpu_vma;
ram_cs <= (not cpu_addr(7)) and (not cpu_addr(12)) and cpu_vma;
-- Bus control
cpu_din <=
pia_dout when pia_cs = '1' else
rom_dout when rom_cs = '1' else
ram_dout when ram_cs = '1' else
x"FF";
U3: entity work.cpu68
port map(
clk => cpu_clk,
rst => reset_h,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr,
data_in => cpu_din,
data_out => cpu_dout,
hold => '0',
halt => '0',
irq => cpu_irq,
nmi => cpu_nmi
);
U4: entity work.U4_ROM
port map(
address => cpu_addr(10 downto 0),
clock => cpu_clk,
q => rom_dout
);
U2: entity work.PIA6821
port map(
clk => cpu_clk,
rst => reset_h,
cs => pia_cs,
rw => cpu_rw,
addr => cpu_addr(1 downto 0),
data_in => cpu_dout,
data_out => pia_dout,
irqa => pia_irq_a,
irqb => pia_irq_b,
pa_i => pia_pa_i,
pa_o => pia_pa_o,
ca1 => snd_int_i,
ca2_i => '1',
ca2_o => open,
pb_i => x"FF",
pb_o => pia_pb_o,
cb1 => pia_cb1,
cb2_i => '0',
cb2_o => open
);
U10: entity work.m6810
port map(
clk => cpu_clk,
rst => reset_h,
address => cpu_addr(6 downto 0),
cs => ram_cs,
rw => cpu_rw,
data_in => cpu_dout,
data_out => ram_dout
);
U1: entity work.AY_3_8910
port map(
clk => cpu_clk,
reset => reset_h,
clk_en => e,
cpu_d_in => pia_pa_o,
cpu_d_out => pia_pa_i,
cpu_bdir => pia_pb_o(1),
cpu_bc1 => pia_pb_o(0),
cpu_bc2 => '1',
io_a_in => ay_pa_i,
io_b_in => x"FF",
io_a_out => open,
io_b_out => open,
snd_A => snd_a,
snd_B => snd_b,
snd_C => snd_c
);
ay_pa_i(5 downto 0) <= not addr_i;
ay_pa_i(7 downto 6) <= "00";
audio <= snd_a & '0' + snd_b & '0'+ snd_c & '0';
end rtl;

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-- (C) Rui T. Sousa from http://sweet.ua.pt/~a16360
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Debouncer is
generic (Delay : positive);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Input : in STD_LOGIC;
Output : out STD_LOGIC
);
end Debouncer;
architecture Behavioral of Debouncer is
signal DelayCounter : natural range 0 to Delay;
signal Internal : STD_LOGIC;
begin
process(Clock, Reset)
begin
if Reset = '1' then
Output <= '0';
Internal <= '0';
DelayCounter <= 0;
elsif rising_edge(Clock) then
if Input /= Internal then
Internal <= Input;
DelayCounter <= 0;
elsif DelayCounter = Delay then
Output <= Internal;
else
DelayCounter <= DelayCounter + 1;
end if;
end if;
end process;
end Behavioral;

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-- (C) Rui T. Sousa from http://sweet.ua.pt/~a16360
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Keyboard is
GENERIC(
clk_freq : INTEGER := 32 );-- system clock frequency in MHz
port (
Reset : in std_logic;
Clock : in std_logic;
PS2Clock : inout std_logic;
PS2Data : inout std_logic;
CodeReady : out std_logic;
ScanCode : out std_logic_vector(9 downto 0)
);
end Keyboard;
architecture Behavioral of Keyboard is
signal Send : std_logic;
signal Command : std_logic_vector(7 downto 0);
signal PS2Busy : std_logic;
signal PS2Error : std_logic;
signal DataReady : std_logic;
signal DataByte : std_logic_vector(7 downto 0);
begin
PS2_Controller: entity work.PS2Controller
generic map (clk_freq => clk_freq)
port map (
Reset => Reset,
Clock => Clock,
PS2Clock => PS2Clock,
PS2Data => PS2Data,
Send => Send,
Command => Command,
PS2Busy => PS2Busy,
PS2Error => PS2Error,
DataReady => DataReady,
DataByte => DataByte
);
Keyboard_Mapper: entity work.KeyboardMapper
port map (
Clock => Clock,
Reset => Reset,
PS2Busy => PS2Busy,
PS2Error => PS2Error,
DataReady => DataReady,
DataByte => DataByte,
Send => Send,
Command => Command,
CodeReady => CodeReady,
ScanCode => ScanCode
);
end Behavioral;

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-- (C) Rui T. Sousa from http://sweet.ua.pt/~a16360
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity KeyboardMapper is
port (
Clock : in std_logic;
Reset : in std_logic;
PS2Busy : in std_logic;
PS2Error : in std_logic;
DataReady : in std_logic;
DataByte : in std_logic_vector(7 downto 0);
Send : out std_logic;
Command : out std_logic_vector(7 downto 0);
CodeReady : out std_logic;
ScanCode : out std_logic_vector(9 downto 0)
);
end KeyboardMapper;
-- ScanCode(9) = 1 -> Extended
-- = 0 -> Regular (Not Extended)
-- ScanCode(8) = 1 -> Break
-- = 0 -> Make
-- ScanCode(7 downto 0) -> Key Code
architecture Behavioral of KeyboardMapper is
type StateType is (ResetKbd, ResetAck, WaitForBAT, Start, Extended, ExtendedBreak, Break, LEDs, CheckAck);
signal State : StateType;
signal CapsLock : STD_LOGIC;
signal NumLock : STD_LOGIC;
signal ScrollLock : STD_LOGIC;
-- signal PauseON : STD_LOGIC;
-- signal i : natural range 0 to 7;
signal KbdFound : std_logic := '0';
begin
process(Reset, PS2Error, Clock)
begin
if Reset = '1' or PS2Error = '1' then
CapsLock <= '0';
NumLock <= '0';
ScrollLock <= '0';
-- PauseON <= '0';
-- i <= 0;
Send <= '0';
Command <= (others => '0');
CodeReady <= '0';
ScanCode <= (others => '0');
KbdFound <= '0';
State <= Start;
elsif rising_edge(Clock) then
case State is
when ResetKbd =>
if PS2Busy = '0' then
Send <= '1';
Command <= x"FF";
State <= ResetAck;
end if;
when ResetAck =>
Send <= '0';
if Dataready = '1' then
if DataByte = x"FA" then
State <= WaitForBAT;
else
State <= ResetKbd;
end if;
end if;
when WaitForBAT =>
if DataReady = '1' then
if DataByte = x"AA" then -- BAT(self test) completed successfully
State <= Start;
KbdFound <= '1';
else
State <= ResetKbd;
end if;
end if;
when Start =>
CodeReady <= '0';
if DataReady = '1' then
case DataByte is
when x"E0" =>
State <= Extended;
when x"F0" =>
State <= Break;
when x"FA" => --Acknowledge
null;
when x"AA" =>
State <= Start;
when x"FC" =>
State <= ResetKbd;
when x"58" =>
Send <= '1';
Command <= x"ED";
CapsLock <= not CapsLock;
ScanCode <= "00" & DataByte;
CodeReady <= '1';
State <= LEDs;
when x"77" =>
Send <= '1';
Command <= x"ED";
NumLock <= not NumLock;
ScanCode <= "00" & DataByte;
CodeReady <= '1';
State <= LEDs;
when x"7E" =>
Send <= '1';
Command <= x"ED";
ScrollLock <= not ScrollLock;
ScanCode <= "00" & DataByte;
CodeReady <= '1';
State <= LEDs;
when others =>
ScanCode <= "00" & DataByte;
CodeReady <= '1';
State <= Start;
end case;
end if;
when Extended =>
if DataReady = '1' then
if DataByte = x"F0" then
State <= ExtendedBreak;
else
ScanCode <= "10" & DataByte;
CodeReady <= '1';
State <= Start;
end if;
end if;
when ExtendedBreak =>
if DataReady = '1' then
ScanCode <= "11" & DataByte;
CodeReady <= '1';
State <= Start;
end if;
when Break =>
if DataReady = '1' then
ScanCode <= "01" & DataByte;
CodeReady <= '1';
State <= Start;
end if;
when LEDs =>
Send <= '0';
CodeReady <= '0';
if Dataready = '1' then
if DataByte = x"FA" then
Send <= '1';
Command <= "00000" & CapsLock & NumLock & ScrollLock;
State <= CheckAck;
elsif DataByte = x"FE" then
Send <= '1';
end if;
end if;
when CheckAck =>
Send <= '0';
if Dataready = '1' then
if DataByte = x"FA" then
State <= Start;
elsif DataByte = x"FE" then
Send <= '1';
end if;
end if;
when others => null;
end case;
end if;
end process;
end Behavioral;

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-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: MPU_RAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY MPU_RAM IS
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END MPU_RAM;
ARCHITECTURE SYN OF mpu_ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 128,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 7,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "7"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL MPU_RAM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MPU_RAM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MPU_RAM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MPU_RAM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MPU_RAM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

209
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-- (C) Rui T. Sousa from http://sweet.ua.pt/~a16360
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PS2Controller is
GENERIC(
clk_freq : INTEGER := 50 );-- system clock frequency in MHz
port (
Reset : in std_logic;
Clock : in std_logic;
PS2Clock : in std_logic;
PS2Data : in std_logic;
Send : in std_logic;
Command : in std_logic_vector(7 downto 0);
PS2Busy : out std_logic;
PS2Error : buffer std_logic;
DataReady : out std_logic;
DataByte : out std_logic_vector(7 downto 0)
);
end PS2Controller;
architecture Behavioral of PS2Controller is
constant ClockFreq : natural := clk_freq; -- MHz
constant Time100us : natural := 100 * ClockFreq;
constant Time20us : natural := 20 * ClockFreq;
constant DebounceDelay : natural := 16;
type StateType is (Idle, ReceiveData, InhibitComunication, RequestToSend, SendData, CheckAck, WaitRiseClock);
signal State : StateType;
signal BitsRead : natural range 0 to 10;
signal BitsSent : natural range 0 to 10;
signal Byte : std_logic_vector(7 downto 0);
signal CountOnes : std_logic; -- One bit only to know if even or odd number of ones
signal DReady : std_logic;
signal PS2ClockPrevious : std_logic;
signal PS2ClockOut : std_logic;
signal PS2Clock_Z : std_logic;
signal PS2Clock_D : std_logic;
signal PS2DataOut : std_logic;
signal PS2Data_Z : std_logic;
signal PS2Data_D : std_logic;
signal TimeCounter : natural range 0 to Time100us;
begin
DebounceClock: entity work.Debouncer
generic map (Delay => DebounceDelay)
port map (
Clock => Clock,
Reset => Reset,
Input => PS2Clock,
Output => PS2Clock_D
);
DebounceData: entity work.Debouncer
generic map (Delay => DebounceDelay)
port map (
Clock => Clock,
Reset => Reset,
Input => PS2Data,
Output => PS2Data_D
);
--PS2Clock <= PS2ClockOut when PS2Clock_Z <= '0' else 'Z';
--PS2Data <= PS2DataOut when PS2Data_Z <= '0' else 'Z';
process(Reset, Clock)
begin
if Reset = '1' then
PS2Clock_Z <= '1';
PS2ClockOut <= '1';
PS2Data_Z <= '1';
PS2DataOut <= '1';
DataReady <= '0';
DReady <= '0';
DataByte <= (others => '0');
PS2Busy <= '0';
PS2Error <= '0';
BitsRead <= 0;
BitsSent <= 0;
CountOnes <= '0';
TimeCounter <= 0;
PS2ClockPrevious <= '1';
Byte <= x"FF";
State <= InhibitComunication;
elsif rising_edge(Clock) then
PS2ClockPrevious <= PS2Clock_D;
case State is
when Idle =>
DataReady <= '0';
DReady <= '0';
BitsRead <= 0;
PS2Error <= '0';
CountOnes <= '0';
if PS2Data_D = '0' then -- Start bit
PS2Busy <= '1';
State <= ReceiveData;
elsif Send = '1' then
Byte <= Command;
PS2Busy <= '1';
TimeCounter <= 0;
State <= InhibitComunication;
else
State <= Idle;
end if;
when ReceiveData =>
if PS2ClockPrevious = '1' and PS2Clock_D = '0' then -- falling edge
case BitsRead is
when 1 to 8 => -- 8 Data bits
Byte(BitsRead - 1) <= PS2Data_D;
if PS2Data_D = '1' then
CountOnes <= not CountOnes;
end if;
when 9 => -- Parity bit
case CountOnes is
when '0' =>
if PS2Data_D = '0' then
PS2Error <= '1'; -- Error when CountOnes is even (0)
else -- and parity bit is unasserted
PS2Error <= '0';
end if;
when others =>
if PS2Data_D = '1' then
PS2Error <= '1'; -- Error when CountOnes is odd (1)
else -- and parity bit is asserted
PS2Error <= '0';
end if;
end case;
when 10 => -- Stop bit
if PS2Error = '0' then
DataByte <= Byte;
DReady <= '1';
else
DReady <= '0';
end if;
State <= WaitRiseClock;
when others => null;
end case;
BitsRead <= BitsRead + 1;
end if;
when InhibitComunication =>
PS2Clock_Z <= '0';
PS2ClockOut <= '0';
if TimeCounter = Time100us then
TimeCounter <= 0;
State <= RequestToSend;
else
TimeCounter <= TimeCounter + 1;
end if;
when RequestToSend =>
PS2Clock_Z <= '1';
PS2Data_Z <= '0';
PS2DataOut <= '0'; -- Sets the start bit, valid when PS2Clock is high
if TimeCounter = Time20us then
TimeCounter <= 0;
PS2ClockOut <= '1';
BitsSent <= 1;
State <= SendData;
else
TimeCounter <= TimeCounter + 1;
end if;
when SendData =>
PS2Clock_Z <= '1';
if PS2ClockPrevious = '1' and PS2Clock_D = '0' then -- falling edge
case BitsSent is
when 1 to 8 => -- 8 Data bits
if Byte(BitsSent - 1) = '0' then
PS2DataOut <= '0';
else
CountOnes <= not CountOnes;
PS2DataOut <= '1';
end if;
when 9 => -- Parity bit
if CountOnes = '0' then
PS2DataOut <= '1';
else
PS2DataOut <= '0';
end if;
when 10 => -- Stop bit
PS2DataOut <= '1';
State <= CheckAck;
when others => null;
end case;
BitsSent <= BitsSent + 1;
end if;
when CheckAck =>
PS2Data_Z <= '1';
if PS2ClockPrevious = '1' and PS2Clock_D = '0' then
if PS2Data_D = '1' then -- no Acknowledge received
PS2Error <= '1';
end if;
State <= WaitRiseClock;
end if;
when WaitRiseClock =>
if PS2ClockPrevious = '0' and PS2Clock_D = '1' then
PS2Busy <= '0';
DataReady <= DReady;
State <= Idle;
end if;
when others => null;
end case;
end if;
end process;
end Behavioral;

129
Soundboards_MiST/AS-2518-51_snd-master/rtl/ROM/NitroGroundshaker.hex Normal file
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:100000008E007F4F97834397828634978386079726
:10001000817F003F8632CE3D2D0926FD4A26F79688
:10002000800E3E8E007FCE0033DF31BD10C3860EC2
:10003000BD10D3BD10EB810327010E3648CE1075DD
:10004000BD10B532810422158607BD10D3863FBD91
:1000500016448608BD10D3EE00AD002007EE00DF89
:1000600021BD113B7D003F270BBD12B6CE1323DF10
:10007000217E113B3E15A2157B17141713158E1404
:10008000BD12AF14E4157A1507133E13511357131D
:100090005D12A61429157A1559157A140E157A13BE
:1000A00083157A157A14A7145313C8147E13A61354
:1000B000FB13631429DF2C9B2D24037C002C972D2C
:1000C000DE2C394F36BD10D34FBD1632324C811065
:1000D00026F239BD112A97809726C603D7825FD7AB
:1000E00082399626810E2603962E39BD111AC60135
:1000F000D78296805FD782369626840FCE110A4D1E
:100100002704084A26FC32A40039FF0FFF0FFF0F17
:100110001FFF1F1F1FFFFF0F1FFFD681C4FBD781CB
:10012000375FD78033CA04D78139D681C4FBD781E2
:10013000375F53D78033CA04D78139DE21E601A661
:1001400000840F36A60084F0CE12157F003D444493
:1001500044BD10B532EE00AD0020E03932323937FF
:10016000BD10D332BD163220164D2702D647D725F3
:100170009625270B7A0025CE007D0926FD20F1DE8D
:10018000210808DF2139DE2120F88DF3201C37BD3E
:1001900010D3BD10E28DE8334D271E200D37BD1062
:1001A000D3BD10E28DD9334D260F5D2B0DC47FDBFF
:1001B00022D722C600D921D7213950C47F9622D711
:1001C0002290229722D621C200D7213937DE21E69C
:1001D0000237BD117FBD1186DE319621A700962220
:1001E000A7010808DF3132972232972139DE310921
:1001F00009A6009721A6019722DF3139BD10D38DC2
:1002000006BD16327E11869627489B2748489B27B5
:100210008B01972739115F123812351242123F11A4
:100220008A119D118E116911FC129611ED12721234
:1002300084115B115C73003DBD1186C601200673FD
:10024000003DBD117F37BD10D3BD10E2337D003DB1
:100250002B031B20011025037E1632BD1632962675
:1002600085F9260481062605810B2701394CC60134
:1002700020D37F002FD730BD10D3DE2FA600BD16B0
:10028000327E117F7F002FD730BD10D3BD10E2DE4C
:100290002FA7007E117F4D270ABD1186EE00AD000D
:1002A0007E117F7E11CCA112AAF08606973F39A15C
:1002B00012B27F003F3ECE0040DF1DC608963F8150
:1002C000012605CE131B202781022605CE131320FD
:1002D0001E81032605CE130B201581042605CE139F
:1002E00003200C81052605CE12FB2003CE12F3BDA0
:1002F00016FF39FF0B870C0D0A0403FF09000D0DD3
:100300000A0403FF07BE0A0E0B0403FF0600080ED3
:100310000C0303FF055E050E0D0303FF04AF020F80
:100320000E030307FCC242C343C844C945CF46C1BC
:1003300041C04081472070FB212F7FF550EF00C066
:10034000023007FC080F090C80196901292878F888
:10035000F00090022450EB0073021D50E500600293
:100360001850DF07F708100C280D010F070E0716AD
:1003700080042E7EFA0E102680042E7EFA2F7FED4A
:100380000800F007F608100C280D0100100F070EEA
:1003900007101680042E7EFA0E102680042E7EFA98
:1003A0002F7FEC0800F007FE08100C080D0100205C
:1003B000A013BB3020A013BB0800F00E20202E7E1F
:1003C000FC0E20102E7EFCB007FC081009100C104B
:1003D0000D01002802280F08A013EA3028A013EA14
:1003E00040102F7FF308000900F00E082032102E75
:1003F0007EFA0E081032102E7EFAB007F70C28088D
:10040000100D090F0C96807D2F7FFA0800F007FE73
:1004100008300C000B600D0E0E028001400201003E
:1004200070F81C2E7EF40800F007FE0030080C0661
:100430000C0F000E018008181F2E7EF9080A3003E9
:100440001F8008181E2F7FF9080A30031E2676E544
:100450000800F007FE008008000F000E0F8008184B
:1004600040061F2E7EF7080000802F6F10800818AE
:1004700040061E2F7FF7080000802E7EE0F0A114BA
:100480009B07FE01000C2808300D090F100E4000DC
:1004900070202E7EFC2F7FF507FFF0963F27078107
:1004A0000127037A003F390F0307FE080F0E4000B3
:1004B000308003102E7EFA07FF2F7FEDF007FE003D
:1004C0008008000F000E0F8008181F2E7EF908000C
:1004D00040032F6F0E8008181E2F7FF9080040037D
:1004E0002E7EE4F009300C0E020107FD0D0D128086
:1004F0000A72FB800008300C18070706010D011670
:10050000800A76FB80FFF0030F07FC080F090A0E34
:1005100004010600008000207002212E7EF70830C2
:100520000C05004001000D0D0F140E0A8004102E62
:100530007EFA0E0A8001202E7EFA102F7FEC090031
:1005400008300C2807F706010D0116800A76FB809B
:10055000FFA11555F07F003F3907F502300830093B
:10056000300C2006010D0E8050162276FA0E2080E7
:1005700050122E7EFA08000900F0F0CE0001DF1DB7
:10058000C606CE174EBD16FFC60FD71C204ACE009A
:1005900000DF1DC61CCE1754BD16FFC6AFD71C7E8C
:1005A0001650860F971C973ECE0001DF1DCE1770A8
:1005B000C606BD16FF8D21CE0001DF1DCE1770C609
:1005C00006BD16FF8D12963E4A81082706971C9796
:1005D0003E20D54FBD164439961CD605D707D60206
:1005E000D70843840FD6018D5B5A26FDC6035A26D1
:1005F000FD43840FD6018D4C5A26FD7A000827173B
:100600007A000726DD43840FD6058D38D707D6013B
:100610009B062B1D01201408090143840FD6028D6F
:1006200023D708D601D003D1042706D701C005205F
:10063000B839D626C10E2603972E39C10726028463
:10064000BFBD112A379780C602D7827F0082333917
:10065000CE16F1DF1F8680D6032A09D627545454BC
:100660005C5A26FD7A0008274C7A0009274C7A004C
:100670000A274C7A000B26DFD60327DBC47FD70B73
:10068000D62758DB27CB0BD7277A001B260ED60F91
:10069000D71BDE1F098C16EA274EDF1FD6272B0635
:1006A000D407C47F2005D407C47F50361B1632DE22
:1006B0001FAD0020A2CE00002008CE00012003CEF6
:1006C00000026D1827126A18260EE60CE718E600DD
:1006D000EB10E1142712E700E600E708AB04600422
:1006E00016DE1FAD007E16573954545454545454DA
:1006F000548D073617BD1644323954545454393684
:10070000A600DF1FDE1DA7007C001EDE1F085A2684
:10071000EF32390FC611D71586FE9701CE01C009F9
:100720002722D700860FBD16440927187A00002615
:10073000F8092710D7004FBD16440927077A000093
:1007400026F820DBD001C11022D296800E39FE049B
:100750000204FF00010A00003F3F0000010A000000
:10076000050500000101000031FF00000505000043
:100770004803010CFF000000000000000000000022
:100780000000000000000000000000000000000069
:100790000000000000000000000000000000000059
:1007A0000000000000000000000000000000000049
:1007B0000000000000000000000000000000000039
:1007C0000000000000000000000000000000000029
:1007D0000000000000000000000000000000000019
:1007E0000000000000000000000000000000000009
:1007F0000000000000000000102310001000100096
:00000001FF

3
Soundboards_MiST/AS-2518-51_snd-master/rtl/U4_ROM.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "U4_ROM.vhd"]

143
Soundboards_MiST/AS-2518-51_snd-master/rtl/U4_ROM.vhd Normal file
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-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: U4_ROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY U4_ROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END U4_ROM;
ARCHITECTURE SYN OF u4_rom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "./ROM/NitroGroundshaker.hex",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2048,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 11,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "./ROM/NitroGroundshaker.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./ROM/NitroGroundshaker.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL U4_ROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL U4_ROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL U4_ROM.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL U4_ROM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL U4_ROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

375
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library IEEE;
use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
Use IEEE.std_logic_unsigned.all;
-- (async) 5 to 8-bit linear to log value convolver
entity lin5_to_log8 is
port
(
a : in std_logic_vector(4 downto 0);
o : out std_logic_vector(7 downto 0)
);
end lin5_to_log8;
architecture rtl of lin5_to_log8 is
begin
o <= X"00" when a = "00000" else
X"01" when a = "00001" else
X"01" when a = "00010" else
X"02" when a = "00011" else
X"02" when a = "00100" else
X"02" when a = "00101" else
X"03" when a = "00110" else
X"04" when a = "00111" else
X"04" when a = "01000" else
X"05" when a = "01001" else
X"06" when a = "01010" else
X"08" when a = "01011" else
X"09" when a = "01100" else
X"0B" when a = "01101" else
X"0D" when a = "01110" else
X"10" when a = "01111" else
X"13" when a = "10000" else
X"16" when a = "10001" else
X"1B" when a = "10010" else
X"20" when a = "10011" else
X"26" when a = "10100" else
X"2D" when a = "10101" else
X"36" when a = "10110" else
X"40" when a = "10111" else
X"4C" when a = "11000" else
X"5A" when a = "11001" else
X"6B" when a = "11010" else
X"80" when a = "11011" else
X"98" when a = "11100" else
X"B5" when a = "11101" else
X"D7" when a = "11110" else
X"FF" when a = "11111";
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
Use IEEE.std_logic_unsigned.all;
-- AY-3-8910 sound generator
-- Internals
entity ay_3_8910_core is
port
(
clk : in std_logic;
reset : in std_logic;
clk_en : in std_logic; -- Clock enable pulse - this should occur between 1 and 2.5MHz
-- Registers
TPA : in std_logic_vector(11 downto 0); -- Tone generator period channel A
TPB : in std_logic_vector(11 downto 0); -- Tone generator period channel B
TPC : in std_logic_vector(11 downto 0); -- Tone generator period channel C
NGP : in std_logic_vector(4 downto 0); -- Noise generator period
MCIOEN : in std_logic_vector(7 downto 0); -- Mixer, control and I/O enable
ACA : in std_logic_vector(4 downto 0); -- Amplitude control channel A
ACB : in std_logic_vector(4 downto 0); -- Amplitude control channel B
ACC : in std_logic_vector(4 downto 0); -- Amplitude control channel C
EPC : in std_logic_vector(15 downto 0); -- Envelope period control
ESR : in std_logic_vector(3 downto 0); -- Envelope shape/cycle control
ESR_updated : in std_logic; -- ESR was written, reset envelope
-- Sound output
snd_A : out std_logic_vector(7 downto 0);
snd_B : out std_logic_vector(7 downto 0);
snd_C : out std_logic_vector(7 downto 0);
-- Test outputs
deb_clk16_en : out std_logic;
deb_clk1256_en : out std_logic;
deb_wave_A : out std_logic;
deb_wave_B : out std_logic;
deb_wave_C : out std_logic;
deb_noise_out : out std_logic;
deb_mixed_A : out std_logic;
deb_mixed_B : out std_logic;
deb_mixed_C : out std_logic;
deb_env_out : out std_logic_vector(3 downto 0);
deb_ampl_A : out std_logic_vector(3 downto 0);
deb_ampl_B : out std_logic_vector(3 downto 0);
deb_ampl_C : out std_logic_vector(3 downto 0);
deb_psnd_A : out std_logic_vector(4 downto 0);
deb_psnd_B : out std_logic_vector(4 downto 0);
deb_psnd_C : out std_logic_vector(4 downto 0);
deb_ef_cont : out std_logic;
deb_ef_attack : out std_logic;
deb_ef_alt : out std_logic;
deb_ef_hold : out std_logic;
deb_div_cnt : out std_logic_vector(7 downto 0);
deb_tcnt_A : out std_logic_vector(11 downto 0);
deb_tcnt_B : out std_logic_vector(11 downto 0);
deb_tcnt_C : out std_logic_vector(11 downto 0);
deb_nse : out std_logic_vector(4 downto 0);
deb_ecnt : out std_logic_vector(15 downto 0);
deb_ephase : out std_logic_vector(3 downto 0);
deb_nse_lfsr : out std_logic_vector(17 downto 0);
deb_noise_in : out std_logic;
deb_env_holding : out std_logic;
deb_env_inv : out std_logic
) ;
end ay_3_8910_core;
architecture rtl of ay_3_8910_core is
signal clk16_en : std_logic; -- High 1/16 of input clock
signal clk256_en : std_logic; -- High 1/256 of input clock
signal wave_A : std_logic; -- Square wave A
signal wave_B : std_logic; -- Square wave B
signal wave_C : std_logic; -- Square wave C
signal noise_out : std_logic; -- Noise wave
signal mixed_A : std_logic; -- Mixed wave A
signal mixed_B : std_logic; -- Mixed wave B
signal mixed_C : std_logic; -- Mixed wave C
signal env_out : std_logic_vector(3 downto 0); -- Envelope wave
signal ampl_A : std_logic_vector(3 downto 0); -- Current amplitude, channel A
signal ampl_B : std_logic_vector(3 downto 0); -- Current amplitude, channel B
signal ampl_C : std_logic_vector(3 downto 0); -- Current amplitude, channel C
signal psnd_A : std_logic_vector(4 downto 0); -- Sound out, channel A, pre lin-log
signal psnd_B : std_logic_vector(4 downto 0); -- Sound out, channel A, pre lin-log
signal psnd_C : std_logic_vector(4 downto 0); -- Sound out, channel A, pre lin-log
signal ef_cont : std_logic; -- Envelope continue
signal ef_attack : std_logic; -- Envelope attack
signal ef_alt : std_logic; -- Envelope alternate
signal ef_hold : std_logic; -- Envelope hold
use work.all;
begin
-- Magic helper signals
ef_cont <= ESR(3);
ef_attack <= ESR(2);
ef_alt <= ESR(1);
ef_hold <= ESR(0);
-- Debug signals
deb_clk16_en <= clk16_en;
deb_clk1256_en <= clk256_en;
deb_wave_A <= wave_A;
deb_wave_B <= wave_B;
deb_wave_C <= wave_C;
deb_noise_out <= noise_out;
deb_mixed_A <= mixed_A;
deb_mixed_B <= mixed_B;
deb_mixed_C <= mixed_C;
deb_env_out <= env_out;
deb_ampl_A <= ampl_A;
deb_ampl_B <= ampl_B;
deb_ampl_C <= ampl_C;
deb_psnd_A <= psnd_A;
deb_psnd_B <= psnd_B;
deb_psnd_C <= psnd_C;
deb_ef_cont <= ef_cont;
deb_ef_attack <= ef_attack;
deb_ef_alt <= ef_alt;
deb_ef_hold <= ef_hold;
-- Waveform mixer scale selection
ampl_A <= env_out when ACA(4) = '1' else ACA(3 downto 0);
ampl_B <= env_out when ACB(4) = '1' else ACB(3 downto 0);
ampl_C <= env_out when ACC(4) = '1' else ACC(3 downto 0);
-- Waveform output
psnd_A(4 downto 1) <= ampl_A when mixed_A = '1' else X"0"; psnd_A(0) <= '1';
psnd_B(4 downto 1) <= ampl_B when mixed_B = '1' else X"0"; psnd_B(0) <= '1';
psnd_C(4 downto 1) <= ampl_C when mixed_C = '1' else X"0"; psnd_C(0) <= '1';
-- Instantiate linear to logarithmic output convolvers
sA_log: entity lin5_to_log8 port map(a => psnd_A, o => snd_A);
sB_log: entity lin5_to_log8 port map(a => psnd_B, o => snd_B);
sC_log: entity lin5_to_log8 port map(a => psnd_C, o => snd_C);
-- Waveform mixers
mixed_A <= (wave_A or MCIOEN(0)) and (noise_out or MCIOEN(3));
mixed_B <= (wave_B or MCIOEN(1)) and (noise_out or MCIOEN(4));
mixed_C <= (wave_C or MCIOEN(2)) and (noise_out or MCIOEN(5));
-- Main process
process (clk, clk_en, reset)
variable div_cnt : std_logic_vector(7 downto 0); -- Clock divider counter
variable wave_A_v : std_logic; -- Square wave A
variable wave_B_v : std_logic; -- Square wave B
variable wave_C_v : std_logic; -- Square wave C
variable tcnt_A : std_logic_vector(11 downto 0); -- Square wave A period counter
variable tcnt_B : std_logic_vector(11 downto 0); -- Square wave B period counter
variable tcnt_C : std_logic_vector(11 downto 0); -- Square wave C period counter
variable nse : std_logic_vector(4 downto 0); -- Noise period counter
variable ecnt : std_logic_vector(15 downto 0); -- Envelope period counter
variable ephase : std_logic_vector(3 downto 0); -- Envelope waveform counter
variable nse_lfsr : std_logic_vector(17 downto 0); -- Noise generator LFSR
variable noise_in : std_logic;
variable env_holding: std_logic; -- Envelope in hold state
variable env_inv : std_logic; -- Envelope inverted
begin
-- Debug signals
deb_div_cnt <= div_cnt; -- 7 downto 0
deb_tcnt_A <= tcnt_A; -- 11 downto 0
deb_tcnt_B <= tcnt_B; -- 11 downto 0
deb_tcnt_C <= tcnt_C; -- 11 downto 0
deb_nse <= nse; -- 4 downto 0
deb_ecnt <= ecnt; -- 15 downto 0
deb_ephase <= ephase; -- 3 downto 0
deb_nse_lfsr <= nse_lfsr; -- 17 downto 0
deb_noise_in <= noise_in;
deb_env_holding <= env_holding;
deb_env_inv <= env_inv;
wave_A <= wave_A_v;
wave_B <= wave_B_v;
wave_C <= wave_C_v;
if div_cnt(3 downto 0) = "1111" then
clk16_en <= '1';
else
clk16_en <= '0';
end if;
-- clk256_en <= (div_cnt = "11111111");
noise_out <= nse_lfsr(0);
if reset = '1' then
wave_A_v := '0';
wave_B_v := '0';
wave_C_v := '0';
div_cnt := X"00";
tcnt_A := X"000";
tcnt_B := X"000";
tcnt_C := X"000";
nse_lfsr := "000000000000000000";
ecnt := X"0000";
ephase := X"0";
env_holding := '0';
env_inv := '0';
elsif rising_edge(clk) then
if clk_en = '1' then
-- Clock divider
div_cnt := div_cnt + 1;
-- Envelope shape/cycle control updated, reset envelope state
if ESR_updated = '1' then
ecnt := X"0000";
ephase := X"0";
env_holding := '0';
env_inv := '0';
end if;
-- Envelope waveform generation
-- Envelope holding
if env_holding = '1' then
if ef_cont = '1' then
env_out(3) <= (ef_attack xor ef_alt);
env_out(2) <= (ef_attack xor ef_alt);
env_out(1) <= (ef_attack xor ef_alt);
env_out(0) <= (ef_attack xor ef_alt);
else
env_out <= X"0";
end if;
-- Otherwise envelope is a function of ephase
else
env_out(3) <= ((not ef_attack) xor env_inv) xor ephase(3);
env_out(2) <= ((not ef_attack) xor env_inv) xor ephase(2);
env_out(1) <= ((not ef_attack) xor env_inv) xor ephase(1);
env_out(0) <= ((not ef_attack) xor env_inv) xor ephase(0);
end if;
-- Events with period clk/16
if clk16_en = '1' then
-- Tone generator counters
-- Channel A
if unsigned(tcnt_A) >= unsigned(TPA) then
wave_A_v := not wave_A_v;
tcnt_A := X"000";
else
tcnt_A := tcnt_A + 1;
end if;
-- Channel B
if unsigned(tcnt_B) >= unsigned(TPB) then
wave_B_v := not wave_B_v;
tcnt_B := X"000";
else
tcnt_B := tcnt_B + 1;
end if;
-- Channel C
if unsigned(tcnt_C) >= unsigned(TPC) then
wave_C_v := not wave_C_v;
tcnt_C := X"000";
else
tcnt_C := tcnt_C + 1;
end if;
-- Noise period counter and LFSR
if nse >= NGP then
nse := "00000";
noise_in := nse_lfsr(0) xnor nse_lfsr(3); -- Input = bit 0 xor bit 3
nse_lfsr(16 downto 0) := nse_lfsr(17 downto 1); -- Shift right - bit 0 is output bit
nse_lfsr(17) := noise_in; -- Bit 16 is input bit
else
nse := nse + 1;
end if;
-- Envelope counters
if ecnt >= EPC then
if ephase = "1111" then
-- If hold flag is set, latch hold value after one envelope cycle
if ef_hold = '1' or ef_cont = '0' then
env_holding := '1';
end if;
-- If alternate flag is set, toggle inverted flag
if ef_alt = '1' then
env_inv := not env_inv;
end if;
ephase := X"0";
else
ephase := ephase + 1;
end if;
ecnt := X"0000";
else
ecnt := ecnt + 1;
end if;
end if;
-- Events with period clk/256
-- if clk256_en = '1' then
-- end if;
end if;
end if;
end process;
end rtl;

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library IEEE;
use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
-- AY-3-8910 sound generator
-- Chip-level module, registers and decoding
entity ay_3_8910 is
port
(
-- AY-3-8910 sound controller
clk : in std_logic;
reset : in std_logic;
clk_en : in std_logic; -- Clock enable pulse - this should occur between 1 and 2.5MHz
-- CPU I/F
cpu_d_in : in std_logic_vector(7 downto 0);
cpu_d_out : out std_logic_vector(7 downto 0);
cpu_bdir : in std_logic;
cpu_bc1 : in std_logic;
cpu_bc2 : in std_logic;
-- I/O I/F
io_a_in : in std_logic_vector(7 downto 0);
io_b_in : in std_logic_vector(7 downto 0);
io_a_out : out std_logic_vector(7 downto 0);
io_b_out : out std_logic_vector(7 downto 0);
-- Sound output
snd_A : out std_logic_vector(7 downto 0);
snd_B : out std_logic_vector(7 downto 0);
snd_C : out std_logic_vector(7 downto 0)
-- Debug
--deb_addr : out std_logic_vector(3 downto 0);
--deb_TPA : out std_logic_vector(11 downto 0); -- Tone generator period channel A
--deb_TPB : out std_logic_vector(11 downto 0); -- Tone generator period channel B
--deb_TPC : out std_logic_vector(11 downto 0); -- Tone generator period channel C
--deb_NGP : out std_logic_vector(4 downto 0); -- Noise generator period
--deb_MCIOEN : out std_logic_vector(7 downto 0); -- Mixer, control and I/O enable
--deb_ACA : out std_logic_vector(4 downto 0); -- Amplitude control channel A
--deb_ACB : out std_logic_vector(4 downto 0); -- Amplitude control channel B
--deb_ACC : out std_logic_vector(4 downto 0); -- Amplitude control channel C
--deb_EPC : out std_logic_vector(15 downto 0); -- Envelope period control
--deb_ESR : out std_logic_vector(3 downto 0); -- Envelope shape/cycle control
--deb_ESR_updated : out std_logic; -- ESR was written, reset envelope
-- Test outputs
--deb_clk16_en : out std_logic;
--deb_clk1256_en : out std_logic;
--deb_wave_A : out std_logic;
--deb_wave_B : out std_logic;
--deb_wave_C : out std_logic;
--deb_noise_out : out std_logic;
--deb_mixed_A : out std_logic;
--deb_mixed_B : out std_logic;
--deb_mixed_C : out std_logic;
--deb_env_out : out std_logic_vector(3 downto 0);
--deb_ampl_A : out std_logic_vector(3 downto 0);
--deb_ampl_B : out std_logic_vector(3 downto 0);
--deb_ampl_C : out std_logic_vector(3 downto 0);
--deb_psnd_A : out std_logic_vector(4 downto 0);
--deb_psnd_B : out std_logic_vector(4 downto 0);
--deb_psnd_C : out std_logic_vector(4 downto 0);
--deb_ef_cont : out std_logic;
--deb_ef_attack : out std_logic;
--deb_ef_alt : out std_logic;
--deb_ef_hold : out std_logic;
--deb_div_cnt : out std_logic_vector(7 downto 0);
--deb_tcnt_A : out std_logic_vector(11 downto 0);
--deb_tcnt_B : out std_logic_vector(11 downto 0);
--deb_tcnt_C : out std_logic_vector(11 downto 0);
--deb_nse : out std_logic_vector(4 downto 0);
--deb_ecnt : out std_logic_vector(15 downto 0);
--deb_ephase : out std_logic_vector(3 downto 0);
--deb_nse_lfsr : out std_logic_vector(17 downto 0);
--deb_noise_in : out std_logic;
--deb_env_holding : out std_logic;
--deb_env_inv : out std_logic
) ;
end ay_3_8910;
architecture rtl of ay_3_8910 is
signal TPA : std_logic_vector(11 downto 0); -- Tone generator period channel A
signal TPB : std_logic_vector(11 downto 0); -- Tone generator period channel B
signal TPC : std_logic_vector(11 downto 0); -- Tone generator period channel C
signal NGP : std_logic_vector(4 downto 0); -- Noise generator period
signal MCIOEN : std_logic_vector(7 downto 0); -- Mixer, control and I/O enable
signal ACA : std_logic_vector(4 downto 0); -- Amplitude control channel A
signal ACB : std_logic_vector(4 downto 0); -- Amplitude control channel B
signal ACC : std_logic_vector(4 downto 0); -- Amplitude control channel C
signal EPC : std_logic_vector(15 downto 0); -- Envelope period control
signal ESR : std_logic_vector(3 downto 0); -- Envelope shape/cycle control
signal PAO : std_logic_vector(7 downto 0); -- Port A out
signal PBO : std_logic_vector(7 downto 0); -- Port B out
signal ESR_updated : std_logic; -- ESR was written, reset envelope
use work.all;
begin
-- Connect core sound processing module to input registers
ay_core: entity ay_3_8910_core port map(clk => clk, reset => reset, clk_en => clk_en,
TPA => TPA, TPB => TPB, TPC => TPC, NGP => NGP, MCIOEN => MCIOEN, ACA => ACA, ACB => ACB,
ACC => ACC, EPC => EPC, ESR => ESR, ESR_updated => ESR_updated,
snd_A => snd_A, snd_B => snd_B, snd_C => snd_C
--deb_clk16_en => deb_clk16_en,
--deb_clk1256_en => deb_clk1256_en,
--deb_wave_A => deb_wave_A,
--deb_wave_B => deb_wave_B,
--deb_wave_C => deb_wave_C,
--deb_noise_out => deb_noise_out,
--deb_mixed_A => deb_mixed_A,
--deb_mixed_B => deb_mixed_B,
--deb_mixed_C => deb_mixed_C,
--deb_env_out => deb_env_out,
--deb_ampl_A => deb_ampl_A,
--deb_ampl_B => deb_ampl_B,
--deb_ampl_C => deb_ampl_C,
--deb_psnd_A => deb_psnd_A,
--deb_psnd_B => deb_psnd_B,
--deb_psnd_C => deb_psnd_C,
--deb_ef_cont => deb_ef_cont,
--deb_ef_attack => deb_ef_attack,
--deb_ef_alt => deb_ef_alt,
--deb_ef_hold => deb_ef_hold,
--deb_div_cnt => deb_div_cnt,
--deb_tcnt_A => deb_tcnt_A,
--deb_tcnt_B => deb_tcnt_B,
--deb_tcnt_C => deb_tcnt_C,
--deb_nse => deb_nse,
--deb_ecnt => deb_ecnt,
--deb_ephase => deb_ephase,
--deb_nse_lfsr => deb_nse_lfsr,
--deb_noise_in => deb_noise_in,
--deb_env_holding => deb_env_holding,
--deb_env_inv => deb_env_inv
);
-- I/O outputs
io_a_out <= PAO when MCIOEN(6) = '0' else X"FF";
io_b_out <= PBO when MCIOEN(7) = '0' else X"FF";
-- Main process
process (clk, clk_en, reset)
variable addr : std_logic_vector(3 downto 0); -- Addressed register
variable rTPA : std_logic_vector(11 downto 0); -- Tone generator period channel A
variable rTPB : std_logic_vector(11 downto 0); -- Tone generator period channel B
variable rTPC : std_logic_vector(11 downto 0); -- Tone generator period channel C
variable rNGP : std_logic_vector(4 downto 0); -- Noise generator period
variable rMCIOEN : std_logic_vector(7 downto 0); -- Mixer, control and I/O enable
variable rACA : std_logic_vector(4 downto 0); -- Amplitude control channel A
variable rACB : std_logic_vector(4 downto 0); -- Amplitude control channel B
variable rACC : std_logic_vector(4 downto 0); -- Amplitude control channel C
variable rEPC : std_logic_vector(15 downto 0); -- Envelope period control
variable rESR : std_logic_vector(3 downto 0); -- Envelope shape/cycle control
variable rPAO : std_logic_vector(7 downto 0); -- Port A out
variable rPBO : std_logic_vector(7 downto 0); -- Port B out
variable rESR_updated : std_logic; -- ESR was written, reset envelope
begin
TPA <= rTPA; TPB <= rTPB;
TPC <= rTPC; NGP <= rNGP;
MCIOEN <= rMCIOEN; ACA <= rACA;
ACB <= rACB; ACC <= rACC;
EPC <= rEPC; ESR <= rESR;
PAO <= rPAO; PBO <= rPBO;
ESR_updated <= rESR_updated;
-- Debug
--deb_addr <= addr;
--deb_TPA <= TPA;
--deb_TPB <= TPB;
--deb_TPC <= TPC;
--deb_NGP <= NGP;
--deb_MCIOEN <= MCIOEN;
--deb_ACA <= ACA;
--deb_ACB <= ACB;
--deb_ACC <= ACC;
--deb_EPC <= EPC;
--deb_ESR <= ESR;
--deb_ESR_updated <= ESR_updated;
if reset = '1' then
rTPA := X"000";
rTPB := X"000";
rTPC := X"000";
rNGP := "00000";
rMCIOEN := X"00";
rACA := "00000";
rACB := "00000";
rACC := "00000";
rEPC := X"0000";
rESR := X"0";
rESR_updated := '0';
elsif rising_edge(clk) then
-- if clk_en = '1' then
rESR_updated := '0';
-- Latch address
if (cpu_bdir = '0' and cpu_bc2 = '0' and cpu_bc1 = '1') or
(cpu_bdir = '1' and cpu_bc2 = '0' and cpu_bc1 = '0') or
(cpu_bdir = '1' and cpu_bc2 = '1' and cpu_bc1 = '1') then
addr(3 downto 0) := cpu_d_in(3 downto 0);
-- Data write
elsif (cpu_bdir = '1' and cpu_bc2 = '1' and cpu_bc1 = '0') then
case addr(3 downto 0) is
when X"0" => rTPA(7 downto 0) := cpu_d_in(7 downto 0);
when X"1" => rTPA(11 downto 8) := cpu_d_in(3 downto 0);
when X"2" => rTPB(7 downto 0) := cpu_d_in(7 downto 0);
when X"3" => rTPB(11 downto 8) := cpu_d_in(3 downto 0);
when X"4" => rTPC(7 downto 0) := cpu_d_in(7 downto 0);
when X"5" => rTPC(11 downto 8) := cpu_d_in(3 downto 0);
when X"6" => rNGP(4 downto 0) := cpu_d_in(4 downto 0);
when X"7" => rMCIOEN(7 downto 0) := cpu_d_in(7 downto 0);
when X"8" => rACA(4 downto 0) := cpu_d_in(4 downto 0);
when X"9" => rACB(4 downto 0) := cpu_d_in(4 downto 0);
when X"A" => rACC(4 downto 0) := cpu_d_in(4 downto 0);
when X"B" => rEPC(7 downto 0) := cpu_d_in(7 downto 0);
when X"C" => rEPC(15 downto 8) := cpu_d_in(7 downto 0);
when X"D" => rESR(3 downto 0) := cpu_d_in(3 downto 0); rESR_updated := '1';
when X"E" => rPAO(7 downto 0) := cpu_d_in(7 downto 0);
when X"F" => rPBO(7 downto 0) := cpu_d_in(7 downto 0);
when others =>
end case;
-- Data read
elsif (cpu_bdir = '0' and cpu_bc2 = '1' and cpu_bc1 = '1') then
cpu_d_out <= X"00";
case addr(3 downto 0) is
when X"0" => cpu_d_out <= rTPA(7 downto 0);
when X"1" => cpu_d_out(3 downto 0) <= rTPA(11 downto 8);
when X"2" => cpu_d_out <= rTPB(7 downto 0);
when X"3" => cpu_d_out(3 downto 0) <= rTPB(11 downto 8);
when X"4" => cpu_d_out <= rTPC(7 downto 0);
when X"5" => cpu_d_out(3 downto 0) <= rTPC(11 downto 8);
when X"6" => cpu_d_out(4 downto 0) <= rNGP(4 downto 0);
when X"7" => cpu_d_out <= rMCIOEN(7 downto 0);
when X"8" => cpu_d_out(4 downto 0) <= rACA(4 downto 0);
when X"9" => cpu_d_out(4 downto 0) <= rACB(4 downto 0);
when X"A" => cpu_d_out(4 downto 0) <= rACC(4 downto 0);
when X"B" => cpu_d_out <= rEPC(7 downto 0);
when X"C" => cpu_d_out <= rEPC(15 downto 8);
when X"D" => cpu_d_out(3 downto 0) <= rESR(3 downto 0);
when X"E" => cpu_d_out <= io_a_in(7 downto 0);
when X"F" => cpu_d_out <= io_b_in(7 downto 0);
when others =>
end case;
end if;
-- end if;
end if;
end process;
end rtl;

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-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- $Id: dac.vhd,v 1.1 2006/05/10 20:57:06 arnim Exp $
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dac is
generic (
msbi_g : integer := 7
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
end dac;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dac is
signal DACout_q : std_logic;
signal DeltaAdder_s,
SigmaAdder_s,
SigmaLatch_q,
DeltaB_s : unsigned(msbi_g+2 downto 0);
begin
DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
SigmaLatch_q(msbi_g+2);
DeltaB_s(msbi_g downto 0) <= (others => '0');
DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
seq: process (clk_i, res_n_i)
begin
if res_n_i = '0' then
SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
DACout_q <= '0';
elsif clk_i'event and clk_i = '1' then
SigmaLatch_q <= SigmaAdder_s;
DACout_q <= SigmaLatch_q(msbi_g+2);
end if;
end process seq;
dac_o <= DACout_q;
end rtl;

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ADDRESS_ACLR_A=NONE
CLOCK_ENABLE_INPUT_A=BYPASS
CLOCK_ENABLE_OUTPUT_A=BYPASS
INIT_FILE=./ROM/NitroGroundshaker.hex
INTENDED_DEVICE_FAMILY="Cyclone III"
NUMWORDS_A=2048
OPERATION_MODE=ROM
OUTDATA_ACLR_A=NONE
OUTDATA_REG_A=UNREGISTERED
WIDTHAD_A=11
WIDTH_A=8
WIDTH_BYTEENA_A=1
DEVICE_FAMILY="Cyclone III"
address_a
clock0
q_a

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-----------------------------------------------------------------------
--
-- Copyright 2009-2011 ShareBrained Technology, Inc.
--
-- This file is part of robotron-fpga.
--
-- robotron-fpga is free software: you can redistribute
-- it and/or modify it under the terms of the GNU General
-- Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- robotron-fpga is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the
-- implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General
-- Public License along with robotron-fpga. If not, see
-- <http://www.gnu.org/licenses/>.
--
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity m6810 is
Port ( clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector (6 downto 0);
cs : in std_logic;
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0));
end m6810;
architecture rtl of m6810 is
subtype word_t is std_logic_vector(7 downto 0);
type memory_t is array(127 downto 0) of word_t;
signal ram : memory_t;
signal address_reg : std_logic_vector(6 downto 0);
signal we : std_logic;
begin
process(clk)
begin
if( rising_edge(clk) ) then
if( we = '1' and cs = '1' ) then
ram(to_integer(unsigned(address))) <= data_in;
end if;
address_reg <= address;
end if;
end process;
we <= not rw;
data_out <= ram(to_integer(unsigned(address)));
end architecture rtl;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity minibd_top is
port(
CLOCK_27 : in std_logic;
SPI_SCK : in std_logic;
SPI_DO : out std_logic;
SPI_DI : in std_logic;
SPI_SS2 : in std_logic;
SPI_SS3 : in std_logic;
CONF_DATA0 : in std_logic;
LED : out std_logic;
AUDIO_L : out std_logic;
AUDIO_R : out std_logic
);
end minibd_top;
architecture rtl of minibd_top is
-- Sound board signals
signal reset_l : std_logic;
signal ps2_clk : std_logic;
signal ps2_dat : std_logic;
signal cpu_clk : std_logic;
signal snd_ctl : std_logic_vector(7 downto 0);
signal audio : std_logic_vector(10 downto 0);
-- PS/2 interface signals
signal scanCode : std_logic_vector(9 downto 0);
signal send : std_logic;
signal Command : std_logic_vector(7 downto 0);
signal PS2Busy : std_logic;
signal PS2Error : std_logic;
signal dataByte : std_logic_vector(7 downto 0);
signal dataReady : std_logic;
signal buttons : std_logic_vector(1 downto 0);
component mist_io generic(STRLEN : integer := 0 ); port
(
clk_sys : in std_logic;
SPI_SCK : in std_logic;
CONF_DATA0 : in std_logic;
SPI_SS2 : in std_logic;
SPI_DI : in std_logic;
SPI_DO : out std_logic;
buttons : out std_logic_vector(1 downto 0);
ps2_kbd_clk : out std_logic;
ps2_kbd_data : out std_logic
);
end component mist_io;
begin
reset_l <= not buttons(1);
LED <= '1';
io: mist_io
port map(
clk_sys => CLOCK_27,
SPI_SCK => SPI_SCK,
CONF_DATA0 => CONF_DATA0,
SPI_SS2 => SPI_SS2,
SPI_DO => SPI_DO,
SPI_DI => SPI_DI,
buttons => buttons,
ps2_kbd_clk => ps2_clk,
ps2_kbd_data => ps2_dat
);
Core: entity work.AS_2518_51
port map(
cpu_clk => cpu_clk,
reset_l => reset_l,
addr_i => snd_ctl(5 downto 0),
snd_int_i => not scancode(8),
test_sw_l => '1',
audio => audio
);
PLL: entity work.williams_snd_pll
port map(
areset => not reset_l,
inclk0 => CLOCK_27,
c0 => cpu_clk
);
keyboard: entity work.PS2Controller
port map(
Reset => not reset_l,
Clock => CLOCK_27,
PS2Clock => ps2_clk,
PS2Data => ps2_dat,
Send => send,
Command => command,
PS2Busy => ps2Busy,
PS2Error => ps2Error,
DataReady => dataReady,
DataByte => dataByte
);
decoder: entity work.KeyboardMapper
port map(
Clock => CLOCK_27,
Reset => not reset_l,
PS2Busy => ps2Busy,
PS2Error => ps2Error,
DataReady => dataReady,
DataByte => dataByte,
Send => send,
Command => command,
CodeReady => open,
ScanCode => scanCode
);
inputreg: process
begin
wait until rising_edge(CLOCK_27);
if scanCode(8) = '0' then
snd_ctl(5 downto 0) <= not scanCode(5 downto 0);
else
snd_ctl(5 downto 0) <= "111111";
end if;
end process;
snd_ctl(7 downto 6) <= "11";
Audio_DACl: entity work.dac
port map(
clk_i => CLOCK_27,
res_n_i => reset_l,
dac_i => audio(10 downto 3),
dac_o => AUDIO_L
);
Audio_DACr: entity work.dac
port map(
clk_i => CLOCK_27,
res_n_i => reset_l,
dac_i => audio(10 downto 3),
dac_o => AUDIO_R
);
end rtl;

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//
// mist_io.v
//
// mist_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
//
// Use buffer to access SD card. It's time-critical part.
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
// (Sorgelig)
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = clk_sys/(PS2DIV*2)
//
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
(
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
// Global clock. It should be around 100MHz (higher is better).
input clk_sys,
// Global SPI clock from ARM. 24MHz
input SPI_SCK,
input CONF_DATA0,
input SPI_SS2,
output SPI_DO,
input SPI_DI,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output ypbpr,
output reg [31:0] status,
// SD config
input sd_conf,
input sd_sdhc,
output img_mounted, // signaling that new image has been mounted
output reg [31:0] img_size, // size of image in bytes
// SD block level access
input [31:0] sd_lba,
input sd_rd,
input sd_wr,
output reg sd_ack,
output reg sd_ack_conf,
// SD byte level access. Signals for 2-PORT altsyncram.
output reg [8:0] sd_buff_addr,
output reg [7:0] sd_buff_dout,
input [7:0] sd_buff_din,
output reg sd_buff_wr,
// ps2 keyboard emulation
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
input ps2_caps_led,
// ARM -> FPGA download
output reg ioctl_download = 0, // signal indicating an active download
output reg [7:0] ioctl_index, // menu index used to upload the file
output ioctl_wr,
output reg [23:0] ioctl_addr,
output reg [7:0] ioctl_dout
);
reg [7:0] b_data;
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [9:0] byte_cnt; // counts bytes
reg [7:0] but_sw;
reg [2:0] stick_idx;
reg mount_strobe = 0;
assign img_mounted = mount_strobe;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
assign ypbpr = but_sw[5];
wire [7:0] spi_dout = { sbuf, SPI_DI};
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
reg spi_do;
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1};
// drive MISO only when transmitting core id
always@(negedge SPI_SCK) begin
if(!CONF_DATA0) begin
// first byte returned is always core type, further bytes are
// command dependent
if(byte_cnt == 0) begin
spi_do <= core_type[~bit_cnt];
end else begin
case(cmd)
// reading config string
8'h14: begin
// returning a byte from string
if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
else spi_do <= 0;
end
// reading sd card status
8'h16: begin
if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
else spi_do <= 0;
end
// reading sd card write data
8'h18:
spi_do <= b_data[~bit_cnt];
// reading keyboard LED status
8'h1f:
spi_do <= kbd_led[~bit_cnt];
default:
spi_do <= 0;
endcase
end
end
end
reg b_wr2,b_wr3;
always @(negedge clk_sys) begin
b_wr3 <= b_wr2;
sd_buff_wr <= b_wr3;
end
// SPI receiver
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
if(CONF_DATA0) begin
b_wr2 <= 0;
bit_cnt <= 0;
byte_cnt <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
end else begin
b_wr2 <= 0;
sbuf <= spi_dout[6:0];
bit_cnt <= bit_cnt + 1'd1;
if(bit_cnt == 5) begin
if (byte_cnt == 0) sd_buff_addr <= 0;
if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
end
// finished reading command byte
if(bit_cnt == 7) begin
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
if(byte_cnt == 0) begin
cmd <= spi_dout;
if(spi_dout == 8'h19) begin
sd_ack_conf <= 1;
sd_buff_addr <= 0;
end
if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
sd_ack <= 1;
sd_buff_addr <= 0;
end
if(spi_dout == 8'h18) b_data <= sd_buff_din;
mount_strobe <= 0;
end else begin
case(cmd)
// buttons and switches
8'h01: but_sw <= spi_dout;
8'h02: joystick_0 <= spi_dout;
8'h03: joystick_1 <= spi_dout;
// store incoming ps2 mouse bytes
8'h04: begin
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout;
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
end
// store incoming ps2 keyboard bytes
8'h05: begin
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout;
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
end
8'h15: status[7:0] <= spi_dout;
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
8'h19,
// send sector IO -> FPGA
// flag that download begins
8'h17: begin
sd_buff_dout <= spi_dout;
b_wr2 <= 1;
end
8'h18: b_data <= sd_buff_din;
// joystick analog
8'h1a: begin
// first byte is joystick index
if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
else if(byte_cnt == 2) begin
// second byte is x axis
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
end else if(byte_cnt == 3) begin
// third byte is y axis
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
end
end
// notify image selection
8'h1c: mount_strobe <= 1;
// send image info
8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
// status, 32bit version
8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
default: ;
endcase
end
end
end
end
/////////////////////////////// PS2 ///////////////////////////////
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
reg clk_ps2;
always @(negedge clk_sys) begin
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
clk_ps2 <= ~clk_ps2;
cnt <= 0;
end
end
// keyboard
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_kbd_tx_state;
reg [7:0] ps2_kbd_tx_byte;
reg ps2_kbd_parity;
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_kbd_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_kbd_r_inc <= 0;
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
// transmitter is idle?
if(ps2_kbd_tx_state == 0) begin
// data in fifo present?
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
// load tx register from fifo
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
ps2_kbd_r_inc <= 1;
// reset parity
ps2_kbd_parity <= 1;
// start transmitter
ps2_kbd_tx_state <= 1;
// put start bit on data line
ps2_kbd_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
if(ps2_kbd_tx_byte[0])
ps2_kbd_parity <= !ps2_kbd_parity;
end
// transmission of parity
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
// transmission of stop bit
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
// advance state machine
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
else ps2_kbd_tx_state <= 0;
end
end
end
// mouse
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_mouse_tx_state;
reg [7:0] ps2_mouse_tx_byte;
reg ps2_mouse_parity;
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_mouse_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_mouse_r_inc <= 0;
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
// transmitter is idle?
if(ps2_mouse_tx_state == 0) begin
// data in fifo present?
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
// load tx register from fifo
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
ps2_mouse_r_inc <= 1;
// reset parity
ps2_mouse_parity <= 1;
// start transmitter
ps2_mouse_tx_state <= 1;
// put start bit on data line
ps2_mouse_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
if(ps2_mouse_tx_byte[0])
ps2_mouse_parity <= !ps2_mouse_parity;
end
// transmission of parity
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
// transmission of stop bit
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
// advance state machine
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
else ps2_mouse_tx_state <= 0;
end
end
end
/////////////////////////////// DOWNLOADING ///////////////////////////////
reg [7:0] data_w;
reg [23:0] addr_w;
reg rclk = 0;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
// data_io has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS2) begin
reg [6:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [23:0] addr;
if(SPI_SS2) cnt <= 0;
else begin
rclk <= 0;
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
// increase target address after write
if(rclk) addr <= addr + 1'd1;
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
// finished command byte
if(cnt == 7) cmd <= {sbuf, SPI_DI};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
addr <= 0;
ioctl_download <= 1;
end else begin
addr_w <= addr;
ioctl_download <= 0;
end
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
addr_w <= addr;
data_w <= {sbuf, SPI_DI};
rclk <= 1;
end
// expose file (menu) index
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
end
end
assign ioctl_wr = |ioctl_wrd;
reg [1:0] ioctl_wrd;
always@(negedge clk_sys) begin
reg rclkD, rclkD2;
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wrd<= {ioctl_wrd[0],1'b0};
if(rclkD & ~rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wrd <= 2'b11;
end
end
endmodule

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--===========================================================================--
--
-- S Y N T H E Z I A B L E I/O Port C O R E
--
-- www.OpenCores.Org - May 2004
-- This core adheres to the GNU public license
--
-- File name : pia6821.vhd
--
-- Purpose : Implements 2 x 8 bit parallel I/O ports
-- with programmable data direction registers
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
--===========================================================================----
--
-- Revision History:
--
-- Date: Revision Author
-- 1 May 2004 0.0 John Kent
-- Initial version developed from ioport.vhd
--
--===========================================================================----
--
-- Memory Map
--
-- IO + $00 - Port A Data & Direction register
-- IO + $01 - Port A Control register
-- IO + $02 - Port B Data & Direction Direction Register
-- IO + $03 - Port B Control Register
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pia6821 is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irqa : out std_logic;
irqb : out std_logic;
pa_i : in std_logic_vector(7 downto 0);
pa_o : out std_logic_vector(7 downto 0);
ca1 : in std_logic;
ca2_i : in std_logic;
ca2_o : out std_logic;
pb_i : in std_logic_vector(7 downto 0);
pb_o : out std_logic_vector(7 downto 0);
cb1 : in std_logic;
cb2_i : in std_logic;
cb2_o : out std_logic
);
end;
architecture pia_arch of pia6821 is
signal porta_ddr : std_logic_vector(7 downto 0);
signal porta_data : std_logic_vector(7 downto 0);
signal porta_ctrl : std_logic_vector(5 downto 0);
signal porta_read : std_logic;
signal portb_ddr : std_logic_vector(7 downto 0);
signal portb_data : std_logic_vector(7 downto 0);
signal portb_ctrl : std_logic_vector(5 downto 0);
signal portb_read : std_logic;
signal portb_write : std_logic;
signal ca1_del : std_logic;
signal ca1_rise : std_logic;
signal ca1_fall : std_logic;
signal ca1_edge : std_logic;
signal irqa1 : std_logic;
signal ca2_del : std_logic;
signal ca2_rise : std_logic;
signal ca2_fall : std_logic;
signal ca2_edge : std_logic;
signal irqa2 : std_logic;
signal ca2_out : std_logic;
signal cb1_del : std_logic;
signal cb1_rise : std_logic;
signal cb1_fall : std_logic;
signal cb1_edge : std_logic;
signal irqb1 : std_logic;
signal cb2_del : std_logic;
signal cb2_rise : std_logic;
signal cb2_fall : std_logic;
signal cb2_edge : std_logic;
signal irqb2 : std_logic;
signal cb2_out : std_logic;
begin
--------------------------------
--
-- read I/O port
--
--------------------------------
pia_read : process( addr, cs,
irqa1, irqa2, irqb1, irqb2,
porta_ddr, portb_ddr,
porta_data, portb_data,
porta_ctrl, portb_ctrl,
pa_i, pb_i )
variable count : integer;
begin
case addr is
when "00" =>
for count in 0 to 7 loop
if porta_ctrl(2) = '0' then
data_out(count) <= porta_ddr(count);
porta_read <= '0';
else
if porta_ddr(count) = '1' then
data_out(count) <= porta_data(count);
else
data_out(count) <= pa_i(count);
end if;
porta_read <= cs;
end if;
end loop;
portb_read <= '0';
when "01" =>
data_out <= irqa1 & irqa2 & porta_ctrl;
porta_read <= '0';
portb_read <= '0';
when "10" =>
for count in 0 to 7 loop
if portb_ctrl(2) = '0' then
data_out(count) <= portb_ddr(count);
portb_read <= '0';
else
if portb_ddr(count) = '1' then
data_out(count) <= portb_data(count);
else
data_out(count) <= pb_i(count);
end if;
portb_read <= cs;
end if;
end loop;
porta_read <= '0';
when "11" =>
data_out <= irqb1 & irqb2 & portb_ctrl;
porta_read <= '0';
portb_read <= '0';
when others =>
data_out <= "00000000";
porta_read <= '0';
portb_read <= '0';
end case;
end process;
---------------------------------
--
-- Write I/O ports
--
---------------------------------
pia_write : process( clk, rst, addr, cs, rw, data_in,
porta_ctrl, portb_ctrl,
porta_data, portb_data,
porta_ctrl, portb_ctrl,
porta_ddr, portb_ddr )
begin
if rst = '1' then
porta_ddr <= "00000000";
porta_data <= "00000000";
porta_ctrl <= "000000";
portb_ddr <= "00000000";
portb_data <= "00000000";
portb_ctrl <= "000000";
portb_write <= '0';
elsif clk'event and clk = '1' then
if cs = '1' and rw = '0' then
case addr is
when "00" =>
if porta_ctrl(2) = '0' then
porta_ddr <= data_in;
porta_data <= porta_data;
else
porta_ddr <= porta_ddr;
porta_data <= data_in;
end if;
porta_ctrl <= porta_ctrl;
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
when "01" =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= data_in(5 downto 0);
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
when "10" =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
if portb_ctrl(2) = '0' then
portb_ddr <= data_in;
portb_data <= portb_data;
portb_write <= '0';
else
portb_ddr <= portb_ddr;
portb_data <= data_in;
portb_write <= '1';
end if;
portb_ctrl <= portb_ctrl;
when "11" =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= data_in(5 downto 0);
portb_write <= '0';
when others =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
end case;
else
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
portb_data <= portb_data;
portb_ddr <= portb_ddr;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
end if;
end if;
end process;
---------------------------------
--
-- direction control port a
--
---------------------------------
porta_direction : process ( porta_data, porta_ddr )
variable count : integer;
begin
for count in 0 to 7 loop
if porta_ddr(count) = '1' then
pa_o(count) <= porta_data(count);
else
pa_o(count) <= 'Z';
end if;
end loop;
end process;
---------------------------------
--
-- CA1 Edge detect
--
---------------------------------
ca1_input : process( clk, rst, ca1, ca1_del,
ca1_rise, ca1_fall, ca1_edge,
irqa1, porta_ctrl, porta_read )
begin
if rst = '1' then
ca1_del <= '0';
ca1_rise <= '0';
ca1_fall <= '0';
ca1_edge <= '0';
irqa1 <= '0';
elsif clk'event and clk = '0' then
ca1_del <= ca1;
ca1_rise <= (not ca1_del) and ca1;
ca1_fall <= ca1_del and (not ca1);
if ca1_edge = '1' then
irqa1 <= '1';
elsif porta_read = '1' then
irqa1 <= '0';
else
irqa1 <= irqa1;
end if;
end if;
if porta_ctrl(1) = '0' then
ca1_edge <= ca1_fall;
else
ca1_edge <= ca1_rise;
end if;
end process;
---------------------------------
--
-- CA2 Edge detect
--
---------------------------------
ca2_input : process( clk, rst, ca2_i, ca2_del,
ca2_rise, ca2_fall, ca2_edge,
irqa2, porta_ctrl, porta_read )
begin
if rst = '1' then
ca2_del <= '0';
ca2_rise <= '0';
ca2_fall <= '0';
ca2_edge <= '0';
irqa2 <= '0';
elsif clk'event and clk = '0' then
ca2_del <= ca2_i;
ca2_rise <= (not ca2_del) and ca2_i;
ca2_fall <= ca2_del and (not ca2_i);
if porta_ctrl(5) = '0' and ca2_edge = '1' then
irqa2 <= '1';
elsif porta_read = '1' then
irqa2 <= '0';
else
irqa2 <= irqa2;
end if;
end if;
if porta_ctrl(4) = '0' then
ca2_edge <= ca2_fall;
else
ca2_edge <= ca2_rise;
end if;
end process;
---------------------------------
--
-- CA2 output control
--
---------------------------------
ca2_output : process( clk, rst, porta_ctrl, porta_read, ca1_edge, ca2_out )
begin
if rst='1' then
ca2_out <= '0';
elsif clk'event and clk='0' then
case porta_ctrl(5 downto 3) is
when "100" => -- read PA clears, CA1 edge sets
if porta_read = '1' then
ca2_out <= '0';
elsif ca1_edge = '1' then
ca2_out <= '1';
else
ca2_out <= ca2_out;
end if;
when "101" => -- read PA clears, E sets
ca2_out <= not porta_read;
when "110" => -- set low
ca2_out <= '0';
when "111" => -- set high
ca2_out <= '1';
when others => -- no change
ca2_out <= ca2_out;
end case;
end if;
end process;
---------------------------------
--
-- CA2 direction control
--
---------------------------------
ca2_direction : process( porta_ctrl, ca2_out )
begin
if porta_ctrl(5) = '0' then
ca2_o <= 'Z';
else
ca2_o <= ca2_out;
end if;
end process;
---------------------------------
--
-- direction control port b
--
---------------------------------
portb_direction : process ( portb_data, portb_ddr )
variable count : integer;
begin
for count in 0 to 7 loop
if portb_ddr(count) = '1' then
pb_o(count) <= portb_data(count);
else
pb_o(count) <= 'Z';
end if;
end loop;
end process;
---------------------------------
--
-- CB1 Edge detect
--
---------------------------------
cb1_input : process( clk, rst, cb1, cb1_del,
cb1_rise, cb1_fall, cb1_edge,
irqb1, portb_ctrl, portb_read )
begin
if rst = '1' then
cb1_del <= '0';
cb1_rise <= '0';
cb1_fall <= '0';
cb1_edge <= '0';
irqb1 <= '0';
elsif clk'event and clk = '0' then
cb1_del <= cb1;
cb1_rise <= (not cb1_del) and cb1;
cb1_fall <= cb1_del and (not cb1);
if cb1_edge = '1' then
irqb1 <= '1';
elsif portb_read = '1' then
irqb1 <= '0';
else
irqb1 <= irqb1;
end if;
end if;
if portb_ctrl(1) = '0' then
cb1_edge <= cb1_fall;
else
cb1_edge <= cb1_rise;
end if;
end process;
---------------------------------
--
-- CB2 Edge detect
--
---------------------------------
cb2_input : process( clk, rst, cb2_i, cb2_del,
cb2_rise, cb2_fall, cb2_edge,
irqb2, portb_ctrl, portb_read )
begin
if rst = '1' then
cb2_del <= '0';
cb2_rise <= '0';
cb2_fall <= '0';
cb2_edge <= '0';
irqb2 <= '0';
elsif clk'event and clk = '0' then
cb2_del <= cb2_i;
cb2_rise <= (not cb2_del) and cb2_i;
cb2_fall <= cb2_del and (not cb2_i);
if portb_ctrl(5) = '0' and cb2_edge = '1' then
irqb2 <= '1';
elsif portb_read = '1' then
irqb2 <= '0';
else
irqb2 <= irqb2;
end if;
end if;
if portb_ctrl(4) = '0' then
cb2_edge <= cb2_fall;
else
cb2_edge <= cb2_rise;
end if;
end process;
---------------------------------
--
-- CB2 output control
--
---------------------------------
cb2_output : process( clk, rst, portb_ctrl, portb_write, cb1_edge, cb2_out )
begin
if rst='1' then
cb2_out <= '0';
elsif clk'event and clk='0' then
case portb_ctrl(5 downto 3) is
when "100" => -- write PB clears, CA1 edge sets
if portb_write = '1' then
cb2_out <= '0';
elsif cb1_edge = '1' then
cb2_out <= '1';
else
cb2_out <= cb2_out;
end if;
when "101" => -- write PB clears, E sets
cb2_out <= not portb_write;
when "110" => -- set low
cb2_out <= '0';
when "111" => -- set high
cb2_out <= '1';
when others => -- no change
cb2_out <= cb2_out;
end case;
end if;
end process;
---------------------------------
--
-- CB2 direction control
--
---------------------------------
cb2_direction : process( portb_ctrl, cb2_out )
begin
if portb_ctrl(5) = '0' then
cb2_o <= 'Z';
else
cb2_o <= cb2_out;
end if;
end process;
---------------------------------
--
-- IRQ control
--
---------------------------------
pia_irq : process( irqa1, irqa2, irqb1, irqb2, porta_ctrl, portb_ctrl )
begin
irqa <= (irqa1 and porta_ctrl(0)) or (irqa2 and porta_ctrl(3));
irqb <= (irqb1 and portb_ctrl(0)) or (irqb2 and portb_ctrl(3));
end process;
end pia_arch;

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Soundboards_MiST/AS-2518-51_snd-master/rtl/williams_snd_pll.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "williams_snd_pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "williams_snd_pll.ppf"]

355
Soundboards_MiST/AS-2518-51_snd-master/rtl/williams_snd_pll.vhd Normal file
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-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: williams_snd_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY williams_snd_pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END williams_snd_pll;
ARCHITECTURE SYN OF williams_snd_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1350,
clk0_duty_cycle => 50,
clk0_multiply_by => 179,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=williams_snd_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1350"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "3.580000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "179"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "3.58000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "williams_snd_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1350"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "179"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL williams_snd_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL williams_snd_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL williams_snd_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL williams_snd_pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL williams_snd_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL williams_snd_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON