Midway8080: add Laguna Racer

2026-01-21 01:57:28 +00:00 · 2022-10-14 22:34:40 +02:00 · 2022-10-14 22:34:40 +02:00 · 0f0d3f5ac7
commit 0f0d3f5ac7
parent a45deb28ba
24 changed files with 2834 additions and 0 deletions
--- a/Hardware/LagunaRacer_MiST/Lagunar.qpf
+++ b/Hardware/LagunaRacer_MiST/Lagunar.qpf
@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:27:39  November 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:27:39  November 20, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "Lagunar"
--- a/Hardware/LagunaRacer_MiST/Lagunar.qsf
+++ b/Hardware/LagunaRacer_MiST/Lagunar.qsf
@ -0,0 +1,175 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 20:51:02  August 09, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Lagunar_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY Lagunar_mist
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ----------------------------
+# start ENTITY(DLagunar_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(DLagunar_mist)
+# --------------------------
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Lagunar_mist.sv
+set_global_assignment -name VHDL_FILE rtl/spy_hunter_control.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Lagunar_memory.sv
+set_global_assignment -name VHDL_FILE rtl/Lagunar_Overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/sound/sprint1_sound.vhd
+set_global_assignment -name VHDL_FILE rtl/sound/screech.vhd
+set_global_assignment -name VHDL_FILE rtl/sound/EngineSound.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--- a/Hardware/LagunaRacer_MiST/Lagunar.sdc
+++ b/Hardware/LagunaRacer_MiST/Lagunar.sdc
@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
--- a/Hardware/LagunaRacer_MiST/Lagunar_description.txt
+++ b/Hardware/LagunaRacer_MiST/Lagunar_description.txt
--- a/Hardware/LagunaRacer_MiST/README.txt
+++ b/Hardware/LagunaRacer_MiST/README.txt
@ -0,0 +1,27 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: 280zzzap port to MiST by Gehstock 
+-- 05 June 2019
+-- 
+---------------------------------------------------------------------------------
+-- 
+-- Midway 8080 Hardware
+-- Audio based on work by Paul Walsh.
+-- Audio and scan converter by MikeJ.
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F1          : Start
+--   SPACE       : Fire
+--   RIGHT/LEFT  : Movement
+--
+-- Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+ToDo: Color Prom
+      Controls + DIP
+	
+
--- a/Hardware/LagunaRacer_MiST/clean.bat
+++ b/Hardware/LagunaRacer_MiST/clean.bat
@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
--- a/Hardware/LagunaRacer_MiST/rtl/Lagunar_Overlay.vhd
+++ b/Hardware/LagunaRacer_MiST/rtl/Lagunar_Overlay.vhd
@ -0,0 +1,99 @@
+--Datsun 280 ZZZAP Color Overlay Gehstock 2019
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity Lagunar_Overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end Lagunar_Overlay;
+
+architecture rtl of Lagunar_Overlay is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_B1      : boolean;
+	signal Overlay_B1_VCnt : boolean;
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+	signal col_data        : std_logic_vector(3 downto 0);
+	signal col_addr        : std_logic_vector(9 downto 0);
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  Overlay_B1_VCnt <= false;
+	  Overlay_B1 <= false;
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  Overlay_B1 <= false;
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_B1)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_B1 then
+		VideoRGB  <= "001";
+	  else
+		VideoRGB  <= "111";
+	  end if;
+	end if;
+  end process;
+  
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;
--- a/Hardware/LagunaRacer_MiST/rtl/Lagunar_memory.sv
+++ b/Hardware/LagunaRacer_MiST/rtl/Lagunar_memory.sv
@ -0,0 +1,79 @@
+module Lagunar_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+
+
+sprom #(
+	.init_file("./roms/lagunar_h.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_0)
+	);
+	
+sprom #(
+	.init_file("./roms/lagunar_g.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_1)
+	);
+
+sprom #(
+	.init_file("./roms/lagunar_f.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_2)
+	);
+	
+sprom #(
+	.init_file("./roms/lagunar_e.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_3)
+	);
+
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3) begin
+	Rom_out = 8'b00000000;
+	case (Addr[15:11])
+		6'b00000 : Rom_out = rom_data_0; //0
+		6'b00001 : Rom_out = rom_data_1; //0800
+		6'b00010 : Rom_out = rom_data_2; //1000
+		6'b00011 : Rom_out = rom_data_3; //1800
+		default : Rom_out = 8'b00000000;
+	endcase
+end
+
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8))
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule
--- a/Hardware/LagunaRacer_MiST/rtl/Lagunar_mist.sv
+++ b/Hardware/LagunaRacer_MiST/rtl/Lagunar_mist.sv
@ -0,0 +1,259 @@
+module Lagunar_mist(
+	output        LED,
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"LAGUNAR;;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+    "O2,Rotate Controls,Off,On;",
+    "P1,Switches;",
+    "P1O89,Coinage,1C_1C,1C_2C,2C_1C,2C_3C;",
+    "P1OAB,Game Time,45+22s,60+30s,75+37s,90+45s;",
+    "P1OCD,Extended Time At,350,400,450,500;",
+    "P1OEF,Mode,Normal,RAM/ROM Test,Input Test,No Extended Time;",
+	"T0,Reset;",
+	"V,v0.00.",`BUILD_DATE
+};
+
+wire  [1:0] scanlines = status[4:3];
+wire        rotate    = status[2];
+wire        overlay   = 0;
+wire  [7:0] dip       = status[15:8];
+
+assign LED = 1;
+
+wire clk_core, clk_vid, clk_aud;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_vid),
+	.c2(clk_aud)
+);
+wire        reset = status[0] | buttons[1];
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        no_csync;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_core       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+wire signed [7:0] steering;
+wire signed [7:0] steering_adj = -(steering + 8'h10); // range adjust and negate: 30-b0 -> 40-c0
+wire [7:0] pedal;
+
+spy_hunter_control controls (
+	.clock_40(clk_core),
+	.reset(reset),
+	.vsync(vs),
+	.gas_plus(m_up),
+	.gas_minus(m_down),
+	.steering_plus(m_right),
+	.steering_minus(m_left),
+	.steering(steering),
+	.gas(pedal)
+);
+
+wire       gear;
+input_toggle gear_sw(
+	.clk(clk_core),
+	.reset(reset),
+	.btn(m_fireA),
+	.state(gear)
+);
+
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+wire  [7:0] audio;
+
+invaderst invaderst(
+	.Rst_n(~reset),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(m_coin1 | m_coin2),
+	.Sel1Player(m_one_player),
+	.Sel2Player(m_two_players),
+	.Fire(gear),
+	.Pedal(pedal[7:4]),
+	.Steering(steering_adj),
+	.DIP(dip),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+
+Lagunar_memory Lagunar_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+
+Lagunar_Overlay Lagunar_Overlay (
+	.Video(Video),
+	.Overlay(~overlay),
+	.CLK(clk_core),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+
+mist_video #(.COLOR_DEPTH(1)) mist_video(
+	.clk_sys(clk_vid),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R(r),
+	.G(g),
+	.B(b),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(scanlines),
+	.ce_divider(0),
+    .rotate({1'b1, rotate}),
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
+	);
+/*
+ --* Port 3:
+ --* bit 0= sound freq
+ --* bit 1= sound freq
+ --* bit 2= sound freq
+ --* bit 3= sound freq
+ --* bit 4= HI SHIFT MODIFIER
+ --* bit 5= LO SHIFT MODIFIER
+ --* bit 6= NC
+ --* bit 7= NC
+ --*
+ --* Port 5:
+ --* bit 0= BOOM sound
+ --* bit 1= ENGINE sound
+ --* bit 2= Screeching Sound
+ --* bit 3= after car blows up, before it appears again
+ --* bit 4= NC
+ --* bit 5= coin counter
+ --* bit 6= NC
+ --* bit 7= NC
+*/
+audio audio_inst (
+	.Clk_5(clk_aud),
+	.Motor1_n(SoundCtrl5[1]),
+	.Skid1(SoundCtrl5[2]),
+	.Crash_n(~SoundCtrl5[0]),
+	.NoiseReset_n(1'b1),
+	.motorspeed(SoundCtrl3[3:0]),
+	.Audio1(audio)
+);
+
+assign AUDIO_R = AUDIO_L;
+
+dac dac (
+	.clk_i(clk_aud),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+
+arcade_inputs inputs (
+	.clk         ( clk_core    ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b11       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
+
+endmodule
--- a/Hardware/LagunaRacer_MiST/rtl/build_id.tcl
+++ b/Hardware/LagunaRacer_MiST/rtl/build_id.tcl
@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
--- a/Hardware/LagunaRacer_MiST/rtl/invaders.vhd
+++ b/Hardware/LagunaRacer_MiST/rtl/invaders.vhd
@ -0,0 +1,227 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		Pedal           : in  std_logic_vector(3 downto 0);
+		Steering        : in  std_logic_vector(7 downto 0);
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: entity work.mw8080
+		port map(
+			Rst_n => Rst_n,--Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+--IN0
+	GDB0(3 downto 0) <= Pedal;
+	GDB0(4) <= not Fire;	-- fire
+	GDB0(5) <= '1';	-- UNUSED
+	GDB0(6) <= not Coin;	-- coin
+	GDB0(7) <= not Sel1Player;	-- start
+--IN1
+	GDB1 <= Steering;
+--IN2
+	GDB2 <= DIP;
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(4) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(2) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(3) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
--- a/Hardware/LagunaRacer_MiST/rtl/mw8080.vhd
+++ b/Hardware/LagunaRacer_MiST/rtl/mw8080.vhd
@ -0,0 +1,335 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
--- a/Hardware/LagunaRacer_MiST/rtl/pll.qip
+++ b/Hardware/LagunaRacer_MiST/rtl/pll.qip
@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
--- a/Hardware/LagunaRacer_MiST/rtl/pll.vhd
+++ b/Hardware/LagunaRacer_MiST/rtl/pll.vhd
@ -0,0 +1,414 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire6_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire6_bv(0 DOWNTO 0) <= "0";
+	sub_wire6    <= To_stdlogicvector(sub_wire6_bv);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c0    <= sub_wire2;
+	c2    <= sub_wire3;
+	sub_wire4    <= inclk0;
+	sub_wire5    <= sub_wire6(0 DOWNTO 0) & sub_wire4;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 1125,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 416,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 1125,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 832,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 1125,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 208,
+		clk2_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire5,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "4.992000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "4.99200000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1125"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "208"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
--- a/Hardware/LagunaRacer_MiST/rtl/roms/lagunar_e.hex
+++ b/Hardware/LagunaRacer_MiST/rtl/roms/lagunar_e.hex
@ -0,0 +1,66 @@
+:020000040000FA
+:20000000C2FC1701200036FF0915C206183E01323C20C921B220347EFE0BC81F3E05323DDA
+:20002000203E0ADA28183E02D305C9003A9E200707E603D6052F5F160021B01819CDA81A5E
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+:2003C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3D
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+:20046000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9C
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+:2004C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3C
+:2004E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1C
+:20050000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB
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+:20056000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9B
+:20058000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7B
+:2005A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5B
+:2005C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3B
+:2005E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1B
+:20060000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA
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+:20064000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBA
+:20066000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9A
+:20068000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A
+:2006A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5A
+:2006C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A
+:2006E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1A
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+:00000001FF
--- a/Hardware/LagunaRacer_MiST/rtl/roms/lagunar_f.hex
+++ b/Hardware/LagunaRacer_MiST/rtl/roms/lagunar_f.hex
@ -0,0 +1,66 @@
+:020000040000FA
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+:00000001FF
--- a/Hardware/LagunaRacer_MiST/rtl/roms/lagunar_g.hex
+++ b/Hardware/LagunaRacer_MiST/rtl/roms/lagunar_g.hex
@ -0,0 +1,66 @@
+:020000040000FA
+:20000000151400150000150000150000150314000015000015000015140015140015143F68
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--- a/Hardware/LagunaRacer_MiST/rtl/roms/lagunar_h.hex
+++ b/Hardware/LagunaRacer_MiST/rtl/roms/lagunar_h.hex
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--- a/Hardware/LagunaRacer_MiST/rtl/sound/EngineSound.vhd
+++ b/Hardware/LagunaRacer_MiST/rtl/sound/EngineSound.vhd
@ -0,0 +1,159 @@
+-- Motor sound generator for Kee Games Sprint 1
+-- Identical circuits are used in a number of other related games
+-- (c) 2017 James Sweet
+--
+-- Original circuit used a 555 configured as an astable oscillator with the frequency controlled by
+-- a four bit binary value. The output of this oscillator drives a counter configured to produce an
+-- irregular thumping simulating the sound of an engine.
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity EngineSound is 
+generic(
+			constant Freq_tune : integer := 50 -- Value from 0-100 used to tune the overall engine sound frequency
+			);
+port(		
+			Clk_5			: in  std_logic; 
+			Ena_3k		: in  std_logic;
+			EngineData	: in	std_logic_vector(3 downto 0);
+			Motor			: out std_logic_vector(5 downto 0)
+			);
+end EngineSound;
+
+architecture rtl of EngineSound is
+
+signal RPM_val 				: integer range 1 to 350;
+signal Ramp_term_unfilt		: integer range 1 to 80000;
+signal Ramp_Count 			: integer range 0 to 80000;
+signal Ramp_term				: integer range 1 to 80000;
+signal Freq_mod				: integer range 0 to 400;
+signal Motor_Clk				: std_logic;
+
+signal Counter_A				: std_logic;
+signal Counter_B 				: unsigned(2 downto 0);
+signal Counter_A_clk			: std_logic;
+
+signal Motor_prefilter 		: unsigned(1 downto 0);
+signal Motor_filter_t1 		: unsigned(3 downto 0);
+signal Motor_filter_t2 		: unsigned(3 downto 0);
+signal Motor_filter_t3 		: unsigned(3 downto 0);
+signal Motor_filtered		: unsigned(5 downto 0);
+
+
+begin
+
+-- The frequency of the oscillator is set by a 4 bit binary value controlled by the game CPU
+-- in the real hardware this is a 555 coupled to a 4 bit resistor DAC used to pull the frequency.
+-- The output of this DAC has a capacitor to smooth out the frequency variation.
+-- The constants assigned to RPM_val can be tweaked to adjust the frequency curve
+
+Speed_select: process(Clk_5)
+begin
+	if rising_edge(Clk_5) then
+		case EngineData is
+			when "0000" => RPM_val <= 280; 
+			when "0001" => RPM_val <= 245; 
+			when "0010" => RPM_val <= 230;
+			when "0011" => RPM_val <= 205; 
+			when "0100" => RPM_val <= 190; 
+			when "0101" => RPM_val <= 175;
+			when "0110" => RPM_val <= 160;
+			when "0111" => RPM_val <= 145;
+ 			when "1000" => RPM_val <= 130;
+			when "1001" => RPM_val <= 115;
+			when "1010" => RPM_val <= 100;
+			when "1011" => RPM_val <= 85;
+			when "1100" => RPM_val <= 70;
+			when "1101" => RPM_val <= 55;
+			when "1110" => RPM_val <= 40;
+			when "1111" => RPM_val <= 25; 
+		end case;
+	end if;
+end process;
+
+
+-- There is a RC filter between the frequency control DAC and the 555 to smooth out the transitions between the
+-- 16 possible states. We can simulate a reasonable approximation of that behavior using a linear slope which is
+-- not truly accurate but should be close enough.
+RC_filt: process(Clk_5, ena_3k, ramp_term_unfilt)
+begin
+	if rising_edge(Clk_5) then
+		if ena_3k = '1' then
+			if ramp_term_unfilt > ramp_term then
+				ramp_term <= ramp_term + 5;
+			elsif ramp_term_unfilt = ramp_term then
+				ramp_term <= ramp_term;
+			else
+				ramp_term <= ramp_term - 3;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+-- Ramp_term terminates the ramp count, the higher this value, the longer the ramp will count up and the lower
+-- the frequency. RPM_val is multiplied by a constant which can be adjusted by changing the value of freq_tune
+-- to simulate the function of the frequency adjustment pot in the original hardware.
+ramp_term_unfilt <= ((200 - freq_tune) * RPM_val);
+
+-- Variable frequency oscillator roughly approximating the function of a 555 astable oscillator
+Ramp_osc: process(Clk_5)
+begin
+	if rising_edge(Clk_5) then
+		motor_clk <= '1';
+		ramp_count <= ramp_count + 1;
+		if ramp_count > ramp_term then
+			ramp_count <= 0;
+			motor_clk <= '0';
+		end if;
+	end if;
+end process;
+		
+
+-- 7492 counter with XOR on two of the outputs creates lumpy engine sound from smooth pulse train
+-- 7492 has two sections, one div-by-2 and one div-by-6.
+Engine_counter: process(motor_clk, Counter_A_clk, Counter_B)
+begin
+	if rising_edge(motor_clk) then
+		Counter_B <= Counter_B + '1';
+	end if;
+	Counter_A_clk <= Counter_B(0) xor Counter_B(2);
+	if rising_edge(counter_A_clk) then 
+		Counter_A <= (not Counter_A);
+	end if;
+end process;
+motor_prefilter <= ('0' & Counter_B(2)) + ('0' & Counter_B(1)) + ('0' & Counter_A);
+
+-- Very simple low pass filter, borrowed from MikeJ's Asteroids code
+Engine_filter: process(Clk_5)
+begin
+	if rising_edge(Clk_5) then
+		if (ena_3k = '1') then
+			motor_filter_t1 <= ("00" & motor_prefilter) + ("00" & motor_prefilter);
+			motor_filter_t2 <= motor_filter_t1;
+			motor_filter_t3 <= motor_filter_t2;
+		end if;
+		motor_filtered <= ("00" & motor_filter_t1) +
+								('0'  & motor_filter_t2 & '0') +
+								("00" & motor_filter_t3);
+	end if;
+end process;	
+
+motor <= std_logic_vector(motor_filtered);
+
+end rtl;
--- a/Hardware/LagunaRacer_MiST/rtl/sound/screech.vhd
+++ b/Hardware/LagunaRacer_MiST/rtl/sound/screech.vhd
@ -0,0 +1,73 @@
+-- Tire screech sound generator for Kee Games Sprint 1
+-- Identical circuit is used in a number of related Kee/Atari games 
+-- (c) 2017 James Sweet
+--
+-- Original circuit used a 7414 Schmitt trigger oscillator operating at approximately
+-- 1.2kHz producing a sawtooth with the frequency modulated slightly by the pseudo-random 
+-- noise generator. This is an extension of work initially done in Verilog by Jonas Elofsson.
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity tire_screech is 
+generic(
+			constant Inc1 : integer := 24; -- These constants can be adjusted to tune the frequency and modulation
+			constant Inc2 : integer := 34;
+			constant Dec1 : integer := 23;
+			constant Dec2 : integer := 12
+			);
+port(		
+			Clk			: in  std_logic;  -- 750kHz from the horizontal line counter chain works well here
+			Noise			: in	std_logic;  -- Output from LFSR pseudo-random noise generator
+			Screech_out	: out std_logic	-- Screech output - single bit
+			);
+end tire_screech;
+
+architecture rtl of tire_screech is
+
+signal Screech_count	: integer range 1000 to 11000;
+signal Screech_state	: std_logic;
+
+begin
+
+Screech: process(Clk, Screech_state)
+begin
+	if rising_edge(Clk) then
+		if screech_state = '1' then -- screech_state is 1, counter is rising
+			if noise = '1' then 	-- Noise signal from LFSR, when high increases the slope of the rising ramp
+				screech_count <= screech_count + inc2;
+			else 						-- When Noise is low, decreas the slope of the ramp
+				screech_count <= screech_count + inc1; 
+			end if;
+			if screech_count > 10000 then -- Reverse the ramp direction when boundary value of 10,000 is reached
+				screech_state <= '0';
+			end if;
+		elsif screech_state = '0' then -- screech_state is now low, decrement the counter (ramp down)
+			if noise = '1' then 
+				screech_count <= screech_count - dec2; -- Slope is influenced by the Noise signal
+			else
+				screech_count <= screech_count - dec1;
+			end if;
+			if screech_count < 1000 then -- Reverse the ramp direction again when the lower boundary of 1,000 is crossed
+				screech_state <= '1';
+			end if;
+		end if;
+	end if;
+screech_out <= screech_state;
+end process;
+
+end rtl;
--- a/Hardware/LagunaRacer_MiST/rtl/sound/sprint1_sound.vhd
+++ b/Hardware/LagunaRacer_MiST/rtl/sound/sprint1_sound.vhd
@ -0,0 +1,215 @@
+-- Audio for Sprint 1
+-- modified for 280zzap
+-- First attempt at modeling the analog sound circuits used in Sprint 1, may be room for improvement as
+-- I do not have a real board to compare.
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity audio is 
+port(		
+			Clk_5			: in  std_logic;
+			Motor1_n		: in	std_logic;
+			Skid1			: in  std_logic;
+			Crash_n			: in  std_logic;
+			NoiseReset_n	        : in  std_logic;
+			motorspeed              : in	std_logic_vector(3 downto 0);
+			Audio1			: out std_logic_vector(7 downto 0)
+			);
+end audio;
+
+architecture rtl of audio is
+
+signal H4				: std_logic;
+signal V2				: std_logic;
+
+signal Noise			: std_logic;
+signal Noise_Shift	: std_logic_vector(15 downto 0);
+signal Shift_in  		: std_logic;
+
+signal Screech_count	: integer range 1000 to 11000;
+signal Screech_state	: std_logic;
+signal Screech_snd1	: std_logic;
+signal Screech1		: std_logic_vector(3 downto 0);
+
+signal Crash			: std_logic_vector(3 downto 0);
+signal Bang				: std_logic_vector(3 downto 0);
+
+signal Mtr1_Freq		: std_logic_vector(3 downto 0);
+signal Motor1_speed	: std_logic_vector(3 downto 0);
+signal Motor1_snd_o	: std_logic_vector(5 downto 0);
+signal Motor1_snd		: std_logic_vector(5 downto 0);
+signal P1_audio		: std_logic_vector(6 downto 0);
+
+signal ena_count		: std_logic_vector(11 downto 0);
+signal ena_3k			: std_logic;
+
+signal bang_prefilter     : std_logic_vector(3 downto 0);
+signal bang_filter_t1     : std_logic_vector(3 downto 0);
+signal bang_filter_t2     : std_logic_vector(3 downto 0);
+signal bang_filter_t3     : std_logic_vector(3 downto 0);
+signal bang_filtered      : std_logic_vector(5 downto 0);
+
+signal h_counter                : std_logic_vector(9 downto 0) := (others => '0');
+signal HCount			: std_logic_vector(8 downto 0);
+
+begin
+
+hcount <= h_counter(9 downto 1);
+
+H_count: process(Clk_5)
+begin
+        if rising_edge(Clk_5) then
+                if h_counter = "1111111111" then
+                        h_counter <= "0100000000";
+                else
+                        h_counter <= h_counter + 1;
+                end if;
+        end if;
+end process;
+
+
+-- HCount
+-- (0) 1H 	3 MHz
+-- (1) 2H   1.5MHz
+-- (2) 4H	750 kHz
+-- (3) 8H	375 kHz
+-- (4) 16H	187 kHz
+-- (5) 32H	93 kHz
+-- (6) 64H	46 kHz
+-- (7) 128H 23 kHz
+-- (8) 256H 12 kHz
+
+-- HCount
+-- (0) 1H 	2.5 MHz
+-- (1) 2H       1.25MHz
+-- (2) 4H	625  kHz
+-- (3) 8H	312 kHz
+-- (4) 16H	156  kHz
+-- (5) 32H	78 kHz
+-- (6) 64H	39 kHz
+-- (7) 128H 19 kHz
+-- (8) 256H 9 kHz
+
+--H4 <= HCount(2);
+--V2 <= HCount(3); -- not correct
+H4 <= HCount(2); -- 750kHz??
+V2 <= HCount(5); -- not correct
+
+-- Generate the 3kHz clock enable used by the filter
+Enable: process(Clk_5)
+begin
+	if rising_edge(Clk_5) then
+		ena_count <= ena_count + "1";
+		ena_3k <= '0';
+		--if (ena_count(11 downto 0) = "000000000000") then
+		if (ena_count(11 downto 0) = "110101010101") then
+			ena_3k <= '1';
+			ena_count<="000000000000";
+		end if;
+	end if;
+end process;
+
+
+-- LFSR that generates pseudo-random noise
+Noise_gen: process(NoiseReset_n, V2)
+begin
+	if (noisereset_n = '0') then
+		noise_shift <= (others => '0');
+		noise <= '0';
+	elsif rising_edge(V2) then
+		shift_in <= not(noise_shift(6) xor noise_shift(8));
+		noise_shift <= shift_in & noise_shift(15 downto 1);
+		noise <= noise_shift(0); 
+	end if;
+end process;
+
+
+-- Tire screech sound
+Screech_gen1: entity work.tire_screech
+generic map( -- These values can be tweaked to tune the screech sound
+		Inc1 => 24, -- Ramp increase rate when noise = 0
+		Inc2 => 33, -- Ramp increase rate when noise = 1
+		Dec1 => 29, -- Ramp decrease rate when noise = 0
+		Dec2 => 16  -- Ramp decrease rate when noise = 1
+		)
+port map(
+		Clk => H4,
+		Noise => noise,
+		Screech_out => screech_snd1
+		);
+		
+	
+-- Convert screech from 1 bit to 4 bits wide and enable via skid1  signal
+Screech_ctrl: process(screech_snd1, Skid1)
+begin
+	if (Skid1 and screech_snd1) = '1' then
+		screech1 <= "1111";
+	else
+		screech1 <= "0000";
+	end if;
+end process;
+		
+	
+--Crash_sound: process(crash_n, motorspeed, noise)		
+--begin
+--	if crash_n = '0' then
+--		crash <= not motorspeed(3 downto 0);
+--	end if;
+--	if noise = '1' then
+--		bang_prefilter <= crash;
+--	else
+--		bang_prefilter <= "0000";
+--	end if;
+--end process;
+
+
+---- Very simple low pass filter, borrowed from MikeJ's Asteroids code
+Crash_filter: process(Clk_5)
+begin
+	if rising_edge(Clk_5) then
+		if (ena_3k = '1') then
+			bang_filter_t1 <= bang_prefilter;
+			bang_filter_t2 <= bang_filter_t1;
+			bang_filter_t3 <= bang_filter_t2;
+		end if;
+		bang_filtered <=  ("00" & bang_filter_t1) +
+								('0'  & bang_filter_t2 & '0') +
+								("00" & bang_filter_t3);
+	end if;
+end process;	
+
+Motor1: entity work.EngineSound 
+generic map( 
+		Freq_tune => 40 -- Tuning pot for engine sound frequency
+		)
+port map(		
+		Clk_5 => clk_5, 
+		Ena_3k => ena_3k,
+		EngineData => motorspeed,
+		Motor => Motor1_Snd_o
+		);
+	
+Motor1_Snd <= Motor1_Snd_o when Motor1_n = '0' else (others => '0');
+-- Audio mixer, also mutes sound in attract mode
+--Audio1 <= '0' & ('0' & motor1_snd) + ('0' & screech1 & '0') + ('0' & bang_filtered);
+--Audio1 <= '0' & ('0' & motor1_snd) + ("00" & screech1) ;
+Audio1 <= ('0' & motor1_snd & '0') + ('0' & screech1 & '0');
+		
+
+	
+end rtl;
--- a/Hardware/LagunaRacer_MiST/rtl/spram.vhd
+++ b/Hardware/LagunaRacer_MiST/rtl/spram.vhd
@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
--- a/Hardware/LagunaRacer_MiST/rtl/sprom.vhd
+++ b/Hardware/LagunaRacer_MiST/rtl/sprom.vhd
@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
--- a/Hardware/LagunaRacer_MiST/rtl/spy_hunter_control.vhd
+++ b/Hardware/LagunaRacer_MiST/rtl/spy_hunter_control.vhd
@ -0,0 +1,161 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity spy_hunter_control is
+port(
+ clock_40     	: in std_logic;
+ reset        	: in std_logic;
+ vsync 			: in std_logic;
+ 
+ gas_plus     	: in std_logic;
+ gas_minus     : in std_logic;
+ steering_plus : in std_logic;
+ steering_minus: in std_logic;
+ steering      : out std_logic_vector(7 downto 0);
+ gas           : out std_logic_vector(7 downto 0)
+  );
+end spy_hunter_control;
+ 
+ 
+architecture struct of spy_hunter_control is
+ signal steering_r    : std_logic_vector(7 downto 0);
+ --signal steering_plus    : std_logic;
+ signal steering_plus_r  : std_logic;
+ --signal steering_minus   : std_logic;
+ signal steering_minus_r : std_logic;
+ signal steering_timer   : std_logic_vector(5 downto 0);
+ 
+ signal gas_r    : std_logic_vector(7 downto 0);
+ --signal gas_plus    : std_logic;
+ signal gas_plus_r  : std_logic;
+ --signal gas_minus   : std_logic;
+ signal gas_minus_r : std_logic;
+ signal gas_timer   : std_logic_vector(5 downto 0);
+ signal vsync_r : std_logic;
+ begin-- absolute position decoder simulation
+--
+--  steering :
+--       thresholds        median
+--   F5 <  left 8   < 34    30
+--   35 <  left 7   < 3C    38
+--   3D <  left 6   < 44    40
+--   45 <  left 5   < 4C    48     
+--   4D <  left 4   < 54    50
+--   45 <  left 3   < 5C    58
+--   5D <  left 2   < 64    60
+--   65 <  left 1   < 6C    68
+--   6D < centrered < 74    70
+--   75 <  right 1  < 7C    78
+--   7D <  right 2  < 84    80
+--   85 <  right 3  < 8C    88
+--   8D <  right 4  < 94    90
+--   95 <  right 5  < 9C    98
+--   9D <  right 6  < A4    A0
+--   A5 <  right 7  < AC    A8
+--   AD <  right 8  < F4    BO
+
+-- gas :
+--         threshold          median
+--    00 < gas pedal 00 < 3B   (39)  3E-5
+--    3C < gas pedal 01 < 40    3E
+--    41 < gas pedal 02 < 45    43
+--    46 < gas pedal 03 < 4A    48      
+--    4B < gas pedal 04 < 4F    4D
+--    50 < gas pedal 05 < 54    52
+--    55 < gas pedal 06 < 59    57
+--    5A < gas pedal 07 < 5E    5C
+--    5F < gas pedal 08 < 63    61
+--     ...
+--    FA < gas pedal 27 < FE    FC
+--    FF = gas pedal 28        (FF)  FC+4
+
+
+gas <= gas_r;
+steering <= steering_r;
+
+process (clock_40, reset)
+begin
+	if reset = '1' then 	
+		gas_r <= x"39";
+		steering_r <= x"70";
+	else
+
+		if rising_edge(clock_40) then
+			gas_plus_r       <= gas_plus;
+			gas_minus_r      <= gas_minus;
+			steering_plus_r  <= steering_plus;
+			steering_minus_r <= steering_minus;
+			vsync_r          <= vsync;
+			
+			-- gas increase/decrease as long as btn is pushed
+			-- keep current value when no btn is pushed
+			if gas_r < x"39" then
+				gas_r <= x"39";
+			else 		
+				if (gas_plus_r = not gas_plus)  or
+					(gas_minus_r = not gas_minus) then
+						gas_timer <= (others => '0');
+				else
+					if vsync_r ='0' and vsync = '1' then 
+						if (gas_timer >= 5 and gas_plus_r = '1') or
+						   (gas_timer >= 2 and gas_minus_r = '1') then --tune inc/dec rate
+							gas_timer <= (others => '0');
+						else
+							gas_timer <= gas_timer + 1;
+						end if;
+					end if;
+				end if;
+	
+				if vsync_r ='0' and vsync = '1' and gas_timer = 0 then	
+					if gas_plus = '1' then
+						if gas_r >= x"FC" then gas_r <= x"FF"; else gas_r <= gas_r + 5; end if;
+					elsif gas_minus = '1' then
+						if gas_r <= x"3E" then gas_r <= x"39"; else gas_r <= gas_r - 5; end if;
+					end if;
+				end if;
+				
+			end if;
+		
+			-- steering increase/decrease as long as btn is pushed
+			-- return to center value when no btn is pushed
+			if steering_r < x"30" then
+				steering_r <= x"30";
+			elsif steering_r > x"B0" then
+				steering_r <= x"B0"; 
+			else
+				if (steering_plus_r = not steering_plus)  or
+					(steering_minus_r = not steering_minus) then
+						steering_timer <= (others => '0');
+				else
+					if vsync_r ='0' and vsync = '1' then 
+						if (steering_timer >= 5 and (steering_minus_r = '1' or  steering_plus_r = '1')) or   -- tune btn pushed   rate
+						   (steering_timer >= 2 and (steering_minus_r = '0' and steering_plus_r = '0')) then -- tune btn released rate
+							steering_timer <= (others => '0');
+						else
+							steering_timer <= steering_timer + 1;
+						end if;
+					end if;
+				end if;
+				
+				if vsync_r ='0' and vsync = '1' and steering_timer = 0 then	
+					if steering_plus = '1' then 
+						if steering_r >= x"A8" then steering_r <= x"B0"; else steering_r <= steering_r + 8; end if;
+					elsif steering_minus = '1' then
+						if steering_r <= x"38" then steering_r <= x"30"; else steering_r <= steering_r - 8; end if;
+					else
+						if steering_r <= x"68" then steering_r <= steering_r + 8; end if;						
+						if steering_r >= x"78" then steering_r <= steering_r - 8; end if;
+						if (steering_r > x"68") and (steering_r < x"78") then steering_r <= x"70"; end if;						
+					end if;
+				end if;
+
+			end if;
+		
+		end if;
+		
+	end if;
+end process;	
+
+end struct;