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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-02-04 15:33:06 +00:00

Irem M52: add original timings for Moon Patrol, blank and sound board fixes

This commit is contained in:
Gyorgy Szombathelyi
2020-12-26 22:13:02 +01:00
parent 54e35f7558
commit 0f82d1f50a
10 changed files with 204 additions and 31 deletions

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@@ -201,6 +201,7 @@ set_global_assignment -name VHDL_FILE src/sprite_pkg_body.vhd
set_global_assignment -name VHDL_FILE src/sprite_pkg.vhd
set_global_assignment -name VHDL_FILE src/video_controller_pkg_body.vhd
set_global_assignment -name VHDL_FILE src/video_controller_pkg.vhd
set_global_assignment -name VHDL_FILE src/iremm52_video_controller.vhd
set_global_assignment -name VHDL_FILE src/video_controller.vhd
set_global_assignment -name VHDL_FILE src/moon_patrol_sound_board.vhd
set_global_assignment -name VHDL_FILE src/moon_patrol_sound_prog.vhd

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@@ -25,7 +25,8 @@ entity Graphics is
graphics_i : in to_GRAPHICS_t;
graphics_o : out from_GRAPHICS_t;
palmode : in std_logic;
video_i : in from_VIDEO_t;
video_o : out to_VIDEO_t
);
@@ -68,29 +69,46 @@ begin
graphics_o.vblank <= video_o_s.vblank;
--graphics_o.vblank <= from_video_ctl.vblank;
pace_video_controller_inst : entity work.pace_video_controller
generic map
(
CONFIG => PACE_VIDEO_CONTROLLER_TYPE,
DELAY => PACE_VIDEO_PIPELINE_DELAY,
H_SIZE => PACE_VIDEO_H_SIZE,
V_SIZE => PACE_VIDEO_V_SIZE,
L_CROP => PACE_VIDEO_L_CROP,
R_CROP => PACE_VIDEO_R_CROP,
H_SCALE => PACE_VIDEO_H_SCALE,
V_SCALE => PACE_VIDEO_V_SCALE,
H_SYNC_POL => PACE_VIDEO_H_SYNC_POLARITY,
V_SYNC_POL => PACE_VIDEO_V_SYNC_POLARITY,
BORDER_RGB => PACE_VIDEO_BORDER_RGB
)
-- pace_video_controller_inst : entity work.pace_video_controller
-- generic map
-- (
-- CONFIG => PACE_VIDEO_CONTROLLER_TYPE,
-- DELAY => PACE_VIDEO_PIPELINE_DELAY,
-- H_SIZE => PACE_VIDEO_H_SIZE,
-- V_SIZE => PACE_VIDEO_V_SIZE,
-- L_CROP => PACE_VIDEO_L_CROP,
-- R_CROP => PACE_VIDEO_R_CROP,
-- H_SCALE => PACE_VIDEO_H_SCALE,
-- V_SCALE => PACE_VIDEO_V_SCALE,
-- H_SYNC_POL => PACE_VIDEO_H_SYNC_POLARITY,
-- V_SYNC_POL => PACE_VIDEO_V_SYNC_POLARITY,
-- BORDER_RGB => PACE_VIDEO_BORDER_RGB
-- )
-- port map
-- (
-- -- clocking etc
-- video_i => video_i,
--
-- -- register interface
-- reg_i.h_scale => "000",
-- reg_i.v_scale => "000",
-- -- video data signals (in)
-- rgb_i => rgb_data,
--
-- -- video control signals (out)
-- video_ctl_o => from_video_ctl,
--
-- -- VGA signals (out)
-- video_o => video_o_s
-- );
pace_video_controller_inst : entity work.iremm52_video_controller
port map
(
-- clocking etc
video_i => video_i,
-- register interface
reg_i.h_scale => "000",
reg_i.v_scale => "000",
palmode => palmode,
-- video data signals (in)
rgb_i => rgb_data,

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@@ -0,0 +1,141 @@
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.video_controller_pkg.all;
use work.platform_variant_pkg.all;
entity iremm52_video_controller is
port
(
-- clocking etc
video_i : in from_VIDEO_t;
palmode : in std_logic;
-- video input data
rgb_i : in RGB_t;
-- control signals (out)
video_ctl_o : out from_VIDEO_CTL_t;
-- video output control & data
video_o : out to_VIDEO_t
);
end iremm52_video_controller;
architecture SYN of iremm52_video_controller is
alias clk : std_logic is video_i.clk;
alias clk_ena : std_logic is video_i.clk_ena;
alias reset : std_logic is video_i.reset;
signal hcnt : unsigned(9 downto 0);
signal vcnt : unsigned(8 downto 0);
signal hsync : std_logic;
signal vsync : std_logic;
signal hblank : std_logic;
signal hblank1 : std_logic;
signal vblank : std_logic;
begin
-------------------
-- Video scanner --
-------------------
-- hcnt [x080..x0FF-x100..x1FF] => 128+256 = 384 pixels, 384/6.144Mhz => 1 line is 62.5us (16.000KHz)
-- vcnt [x0E6..x0FF-x100..x1FF] => 26+256 = 282 lines, 1 frame is 260 x 62.5us = 17.625ms (56.74Hz)
process (reset, clk, clk_ena)
begin
if reset='1' then
hcnt <= (others=>'0');
vcnt <= '0'&X"FC";
elsif rising_edge(clk) and clk_ena = '1'then
hcnt <= hcnt + 1;
if hcnt = "01"&x"FF" then
hcnt <= "00"&x"80";
vcnt <= vcnt + 1;
if vcnt = '1'&x"FF" then
if palmode = '1' then
vcnt <= '0'&x"C8"; -- 312 lines/PAL 50 Hz
else
vcnt <= '0'&x"E6"; -- from M52 schematics
end if;
end if;
end if;
end if;
end process;
process (reset, clk, clk_ena)
begin
if reset = '1' then
hsync <= '0';
vsync <= '0';
hblank <= '0';
hblank1 <= '0';
vblank <= '1';
elsif rising_edge(clk) and clk_ena = '1' then
-- display blank
if hcnt = "01"&x"0B" then
hblank <= '0';
if vcnt = '1'&x"00" then
vblank <= '0';
end if;
end if;
if hcnt = "00"&x"FF" then
hblank1 <= '0';
end if;
if hcnt = "01"&x"FF" then
hblank <= '1';
hblank1 <= '1';
end if;
if hcnt = "00"&x"87" then
if vcnt = '1'&x"FF" then
vblank <= '1';
end if;
end if;
-- display sync
if hcnt = "00"&x"A3" then
hsync <= '1';
if vcnt = '0'&x"F0" then
vsync <= '1';
end if;
end if;
if hcnt = "00"&x"C9" then
hsync <= '0';
if vcnt = '0'&x"F2" then
vsync <= '0';
end if;
end if;
-- registered rgb output
if hblank = '1' or vblank = '1' then
video_o.rgb <= RGB_BLACK;
else
video_o.rgb <= rgb_i;
end if;
end if;
end process;
video_o.hsync <= hsync;
video_o.vsync <= vsync;
video_o.hblank <= hblank;
video_o.vblank <= vblank;
video_ctl_o.stb <= '1';
video_ctl_o.x <= '0'&std_logic_vector(hcnt);
video_ctl_o.y <= "00"&std_logic_vector(vcnt);
-- blank signal goes to tilemap/spritectl
video_ctl_o.hblank <= hblank1;
video_ctl_o.vblank <= vblank;
-- pass-through for tile/bitmap & sprite controllers
video_ctl_o.clk <= clk;
video_ctl_o.clk_ena <= clk_ena;
-- for video DACs and TFT output
video_o.clk <= clk;
end SYN;

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@@ -238,7 +238,11 @@ adpcm_clocks : process(clock_E, ay1_port_b_do)
variable dn : integer range -32768 to 32767;
variable adpcm_signal_n : integer range -32768 to 32767;
begin
if rising_edge(clock_E) then
if reset = '1' then
adpcm_vclk <= '0';
clock_div_a := 0;
clock_div_b := 0;
elsif rising_edge(clock_E) then
if clock_div_a = 37 then -- 24kHz
clock_div_a := 0;

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@@ -50,7 +50,7 @@ architecture SYN of mpatrol is
signal video_o : to_VIDEO_t;
--MIST
signal audio : std_logic;
signal status : std_logic_vector(31 downto 0);
signal status : std_logic_vector(63 downto 0);
signal joystick1 : std_logic_vector(31 downto 0);
signal joystick2 : std_logic_vector(31 downto 0);
signal joystick : std_logic_vector(7 downto 0);
@@ -69,6 +69,7 @@ architecture SYN of mpatrol is
constant CONF_STR : string :=
"MPATROL;;"&
"O12,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;"&
"OB,Video timings,Original,PAL;"&
"O34,Patrol cars,5,3,2,1;"&
"O56,New car at,10/30/50K,20/40/60K,10K,Never;"&
"OA,Freeze,Disable,Enable;"&
@@ -260,6 +261,7 @@ switches_i( 3 downto 2) <= not status(6 downto 5); -- New car
pace_inst : entity work.pace
port map (
clkrst_i => clkrst_i,
palmode => status(11),
buttons_i => buttons_i,
switches_i => switches_i,
leds_o => open,
@@ -286,8 +288,8 @@ mist_video: work.mist.mist_video
SPI_SS3 => SPI_SS3,
SPI_DI => SPI_DI,
HSync => video_o.hsync,
VSync => video_o.vsync,
HSync => not video_o.hsync,
VSync => not video_o.vsync,
R => video_o.rgb.r(9 downto 4),
G => video_o.rgb.g(9 downto 4),
B => video_o.rgb.b(9 downto 4),

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@@ -15,6 +15,7 @@ entity PACE is
(
-- clocks and resets
clkrst_i : in from_CLKRST_t;
palmode : in std_logic;
-- misc I/O
buttons_i : in from_BUTTONS_t;
@@ -134,6 +135,7 @@ begin
graphics_o => from_graphics,
-- video (incl. clk)
palmode => palmode,
video_i => video_i,
video_o => video_o
);

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@@ -71,9 +71,9 @@ begin
if rising_edge(clk) then
if clk_ena = '1' then
x := unsigned(reg_i.x) + PACE_VIDEO_PIPELINE_DELAY - 3;
y := 254 - unsigned(reg_i.y) - 16;
x := '1'&x"00" + unsigned(reg_i.x) + PACE_VIDEO_PIPELINE_DELAY - 3;
y := '1'&x"00" + 254 - unsigned(reg_i.y) - 15;
if video_ctl.hblank = '1' then
xMat := false;

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@@ -37,7 +37,8 @@ begin
ctl_o.tile_a(ctl_o.tile_a'left downto 12) <= (others => '0');
-- screen rotation
x <= video_ctl.x when unsigned(y) < 192 else
-- x <= video_ctl.x when unsigned(y) < 192 else
x <= video_ctl.x when unsigned(y) < '1'&x"C0" else
std_logic_vector(unsigned(video_ctl.x) + not unsigned(scroll));
-- when rot_en = '0' else not video_ctl.y;
--y <= not video_ctl.y when rot_en = '0' else 32 + video_ctl.x;
@@ -95,7 +96,7 @@ begin
ctl_o.rgb.b <= pal_rgb(2) & "00";
ctl_o.set <= '0'; -- default
-- lines 0-6 are opaque apparently
if unsigned(y) < 7*8 or
if unsigned(y) < '1'&x"38" or
pel /= "00" then
-- pal_rgb(0)(7 downto 5) /= "000" or
-- pal_rgb(1)(7 downto 5) /= "000" or

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@@ -241,7 +241,11 @@ adpcm_clocks : process(clock_E, ay1_port_b_do)
variable dn : integer range -32768 to 32767;
variable adpcm_signal_n : integer range -32768 to 32767;
begin
if rising_edge(clock_E) then
if reset='1' then
adpcm_vclk <= '0';
clock_div_a := 0;
clock_div_b := 0;
elsif rising_edge(clock_E) then
if clock_div_a = 37 then -- 24kHz
clock_div_a := 0;

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@@ -744,7 +744,7 @@ if rising_edge(clock_36) and pix_ena = '1' then
end if;
-- vcnt : [230-511] 282 lines
if vcnt = 230 then vblank <= '1';
if vcnt = 200 or vcnt = 230 then vblank <= '1';
elsif vcnt = 256 then vblank <= '0';
end if;