mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-03-03 18:06:03 +00:00
Merge branch 'master' of https://github.com/Gehstock/Mist_FPGA
This commit is contained in:
Marcel
31
Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.qpf
Normal file
31
Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.qpf
Normal file
@@ -0,0 +1,31 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel MegaCore Function License Agreement, or other
|
||||
# applicable license agreement, including, without limitation,
|
||||
# that your use is for the sole purpose of programming logic
|
||||
# devices manufactured by Intel and sold by Intel or its
|
||||
# authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
|
||||
# Date created = 04:04:47 October 16, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.1"
|
||||
DATE = "04:04:47 October 16, 2017"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "Alpha68k"
|
||||
225
Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.qsf
Normal file
225
Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.qsf
Normal file
@@ -0,0 +1,225 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
# Date created = 05:08:48 November 15, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# Arcade-Scramble_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
|
||||
set_location_assignment PIN_54 -to CLOCK_27
|
||||
set_location_assignment PIN_144 -to VGA_R[5]
|
||||
set_location_assignment PIN_143 -to VGA_R[4]
|
||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
||||
set_location_assignment PIN_137 -to VGA_R[1]
|
||||
set_location_assignment PIN_135 -to VGA_R[0]
|
||||
set_location_assignment PIN_133 -to VGA_B[5]
|
||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_90 -to SPI_SS4
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_4 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_6 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_8 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_10 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_11 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_28 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_50 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_30 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_32 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
|
||||
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY Alpha68k_MiST
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# ----------------------
|
||||
# start ENTITY(Alpha68k)
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(Alpha68k)
|
||||
# --------------------
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name ENABLE_NCE_PIN OFF
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE output_files/cpu.stp
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name FORCE_SYNCH_CLEAR ON
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Alpha68k_MiST.sv
|
||||
set_global_assignment -name QIP_FILE rtl/pll_mist.qip
|
||||
set_global_assignment -name VERILOG_FILE rtl/video_timing.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Alpha68k.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/math.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/dual_port_ram.vhd
|
||||
set_global_assignment -name VERILOG_FILE rtl/chip_select.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
|
||||
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
|
||||
set_global_assignment -name QIP_FILE ../../common/CPU/68000/FX68k/fx68k.qip
|
||||
set_global_assignment -name QIP_FILE ../../common/Sound/JT12/hdl/jt03.qip
|
||||
set_global_assignment -name QIP_FILE ../../common/Sound/jtopl/jt2413.qip
|
||||
set_global_assignment -name QIP_FILE ../../common/Sound/JT49/jt49.qip
|
||||
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
|
||||
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
|
||||
set_global_assignment -name CDF_FILE output_files/Alpha68k.cdf
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/cpu.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/cpu2.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/fg.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/mcu.stp
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
138
Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.sdc
Normal file
138
Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.sdc
Normal file
@@ -0,0 +1,138 @@
|
||||
## Generated SDC file "vectrex_MiST.out.sdc"
|
||||
|
||||
## Copyright (C) 1991-2013 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
|
||||
|
||||
## DATE "Sun Jun 24 12:53:00 2018"
|
||||
|
||||
##
|
||||
## DEVICE "EP3C25E144C8"
|
||||
##
|
||||
|
||||
# Clock constraints
|
||||
|
||||
# Automatically constrain PLL and other generated clocks
|
||||
derive_pll_clocks -create_base_clocks
|
||||
|
||||
# Automatically calculate clock uncertainty to jitter and other effects.
|
||||
derive_clock_uncertainty
|
||||
|
||||
# tsu/th constraints
|
||||
|
||||
# tco constraints
|
||||
|
||||
# tpd constraints
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
|
||||
|
||||
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
|
||||
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
|
||||
|
||||
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
|
||||
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
set_output_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
|
||||
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
|
||||
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
|
||||
set_output_delay -add_delay -clock [get_clocks $sdram_clk] 1.000 [get_ports {LED}]
|
||||
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
|
||||
|
||||
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
set_multicycle_path -from {Alpha68k:Alpha68k|T80pa:z80|T80:u0|*} -setup 2
|
||||
set_multicycle_path -from {Alpha68k:Alpha68k|T80pa:z80|T80:u0|*} -hold 1
|
||||
|
||||
set_multicycle_path -to {VGA_*[*]} -setup 2
|
||||
set_multicycle_path -to {VGA_*[*]} -hold 1
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
118
Arcade_MiST/Alpha Densi M68000 Hardware/README.md
Normal file
118
Arcade_MiST/Alpha Densi M68000 Hardware/README.md
Normal file
@@ -0,0 +1,118 @@
|
||||
|
||||
# Alpha Denshi M68000 FPGA Implementation
|
||||
|
||||
FPGA compatible core of Alpha Denshi M68000 (ALPHA68K96V based) arcade hardware written by [**Darren Olafson**](https://twitter.com/Darren__O).
|
||||
|
||||
FPGA implementation has been verified against schematics for Sky Adventure. PCB measurements taken from Gang Wars (ALPHA-68K96V) and Sky Soldiers (ALPHA-96KII).
|
||||
|
||||
Sky Adventure (bootleg) PCB purchased by [**Darren Olafson**](https://twitter.com/Darren__O) / [**atrac17**](https://github.com/atrac17). Gang Wars, Sky Soldiers, and The Next Space (authentic) PCBs purchased by [**atrac17**](https://github.com/atrac17).
|
||||
|
||||
The intent is for this core to be a 1:1 playable implementation of Alpha Denshi M68000 arcade hardware. Currently in **beta state**, this core is in active development with assistance from [**atrac17**](https://github.com/atrac17).
|
||||
|
||||
MiST port, new SDRAM controller, some fixes and enhancements by Gyorgy Szombathelyi.
|
||||
|
||||
## Supported Games
|
||||
|
||||
| Title | PCB<br>Number | Status | Released | ROM Set |
|
||||
|-------|---------------|---------|----------|---------|
|
||||
| [**Gang Wars**](https://en.wikipedia.org/wiki/Gang_Wars_(video_game)) | ALPHA-68K96V (GW) | Implemented | Yes | .249 merged set |
|
||||
| [**Super Champion Baseball**](https://snk.fandom.com/wiki/Super_Champion_Baseball) | ALPHA-68K96V (GW) | Implemented | Yes | .249 (**sbasebalj** only) |
|
||||
| [**Sky Adventure**](https://snk.fandom.com/wiki/Sky_Adventure) | ALPHA-68K96V (GW) | Implemented | Yes | .249 merged set |
|
||||
| [**バトル フィールド**](https://en.wikipedia.org/wiki/Time_Soldiers)<br>Time Soldiers | ALPHA-68K96II (SS) | Implemented | Yes | .249 merged set |
|
||||
| [**Sky Soldiers**](https://en.wikipedia.org/wiki/Sky_Soldiers) | ALPHA-68K96II (SS) | Implemented | Yes | .249 merged set |
|
||||
| [**Gold Medalist**](https://snk.fandom.com/wiki/Gold_Medalist) | ALPHA-68K96II (SS) | Implemented | No | .249 (**goldmedl** only) |
|
||||
| [**Paddle Mania**](https://snk.fandom.com/wiki/Paddle_Mania) | ALPHA-68K96I | **W.I.P** | No | N/A |
|
||||
| [**The Next Space**](https://snk.fandom.com/wiki/The_Next_Space) | A8004-1 | **Separate<br>Repository** | No | N/A |
|
||||
| [**Super Stingray**](https://segaretro.org/Super_Stingray) | N/A | **W.I.P** | No | N/A |
|
||||
| [**Kyros no Yakata**](http://www.hardcoregaming101.net/kyros-desolator/) | N/A | **W.I.P** | No | N/A |
|
||||
| [**Mahjong Block Jongbou**](https://snk.fandom.com/wiki/Jongbou) | ALPHA-68K96N | **W.I.P** | No | N/A |
|
||||
|
||||
## External Modules
|
||||
|
||||
|Name| Purpose | Author |
|
||||
|----|---------|--------|
|
||||
| [**fx68k**](https://github.com/ijor/fx68k) | [**Motorola 68000 CPU**](https://en.wikipedia.org/wiki/Motorola_68000) | Jorge Cwik |
|
||||
| [**t80**](https://opencores.org/projects/t80) | [**Zilog Z80 CPU**](https://en.wikipedia.org/wiki/Zilog_Z80) | Daniel Wallner |
|
||||
| [**jt2413**](https://github.com/jotego/jtopl) | [**Yamaha OPL-L**](https://en.wikipedia.org/wiki/Yamaha_YM2413) | Jose Tejada |
|
||||
| [**jt03**](https://github.com/jotego/jt12) | [**Yamaha OPN**](https://en.wikipedia.org/wiki/Yamaha_YM2203) | Jose Tejada |
|
||||
|
||||
# PCB Check List
|
||||
|
||||
<br>
|
||||
|
||||
FPGA implementation has been verified against [**schematics**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/ALPHA68K-96V_Schematics.pdf) for Sky Adventure. The schematics are improperly labeled Prehistoric Isle (hand written), this was discovered during development of the [**Prehistoric Isle FPGA implementation**](https://github.com/va7deo/PrehistoricIsle). PCB measurements taken from Gang Wars (ALPHA-68K96V) and Sky Adventure (ALPHA-68K96II).
|
||||
|
||||
### Clock Information
|
||||
|
||||
H-Sync | V-Sync | Source | PCB<br>Number |
|
||||
------------|-------------|----------|----------------|
|
||||
15.625kHz | 59.185606Hz | [**DSLogic+**](FILLME) | ALPHA-68K96V (GW) |
|
||||
15.625kHz | 59.185606Hz | [**DSLogic+**](FILLME) | ALPHA-68K96II (SS) |
|
||||
|
||||
### Crystal Oscillators
|
||||
|
||||
- MAME documentation for the Alpha96k.cpp states that ALPHA-68K96II hardware runs the M68000 at 8.00 MHZ. The actual frequency for the M68000 is 9.00 MHZ based on board readings from Sky Soldier.
|
||||
|
||||
Location | PCB<br>Number | Freq (MHz) | Use |
|
||||
------------------------|--------------------|------------|----------------------------------------------------------------------------------------------|
|
||||
X-1 (24 MHZ) | ALPHA-68K96V (GW) | 24.000 | Z80 CLK (6MHZ)<br><br>YM2203 (CLK 3 MHZ)<br><br>Sprite CLK (12 MHZ)<br><br>Pixel CLK (6 MHZ) |
|
||||
X-2 (20 MHZ) | ALPHA-68K96V (GW) | 20.000 | M68000 CLK (10 MHZ) |
|
||||
X-3 (3.579545 MHz) | ALPHA-68K96V (GW) | 3.579545 | YM2413 CLK (3.579545 MHz) |
|
||||
X-1 (3.579545 MHz) | ALPHA-68K96II (SS) | 24.000 | YM2413 CLK (3.579545 MHz) |
|
||||
X-2 (18 MHZ) | ALPHA-68K96II (SS) | 18.000 | M68000 CLK (9 MHZ) |
|
||||
X-3 (24 MHZ) | ALPHA-68K96II (SS) | 3.579545 | Z80 CLK (6MHZ)<br><br>YM2203 (CLK 3 MHZ)<br><br>Sprite CLK (12 MHZ)<br><br>Pixel CLK (6 MHZ) |
|
||||
|
||||
**Pixel clock:** 6.00 MHz
|
||||
|
||||
**Estimated geometry:**
|
||||
|
||||
383 pixels/line
|
||||
|
||||
263 pixels/line
|
||||
|
||||
### Main Components
|
||||
|
||||
Location | PCB<br>Number | Chip | Use |
|
||||
---------|---------------|------|-----|
|
||||
68000D | ALPHA-68K96V (GW) | [**Motorola 68000 CPU**](https://en.wikipedia.org/wiki/Motorola_68000) | Main CPU |
|
||||
Z80B | ALPHA-68K96V (GW) | [**Zilog Z80 CPU**](https://en.wikipedia.org/wiki/Zilog_Z80) | Sound CPU |
|
||||
YM2203 | ALPHA-68K96V (GW) | [**Yamaha YM2203**](https://en.wikipedia.org/wiki/Yamaha_YM2203) | OPN |
|
||||
YM2413 | ALPHA-68K96V (GW) | [**Yamaha YM2413**](https://en.wikipedia.org/wiki/Yamaha_YM2413) | OPL-L |
|
||||
|
||||
Location | PCB<br>Number | Chip | Use |
|
||||
---------|---------------|------|-----|
|
||||
68000-10 | ALPHA-68K96II (SS) | [**Motorola 68000 CPU**](https://en.wikipedia.org/wiki/Motorola_68000) | Main CPU |
|
||||
Z80B | ALPHA-68K96II (SS) | [**Zilog Z80 CPU**](https://en.wikipedia.org/wiki/Zilog_Z80) | Sound CPU |
|
||||
YM2203 | ALPHA-68K96II (SS) | [**Yamaha YM2203**](https://en.wikipedia.org/wiki/Yamaha_YM2203) | OPN |
|
||||
YM2413 | ALPHA-68K96II (SS) | [**Yamaha YM2413**](https://en.wikipedia.org/wiki/Yamaha_YM2413) | OPL-L |
|
||||
|
||||
### Custom Components
|
||||
|
||||
Location | PCB<br>Number | Chip | Use |
|
||||
---------|---------------|------|-----|
|
||||
SP85<br><br>ALPHA-8511<br><br>ALPHA-8411 | ALPHA-68K96V (GW)<br><br>ALPHA-68K96II (SS)<br><br>ALPHA-68K96V (SA) | [**SP85N**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/ALPHA68K-96V_Schematics.pdf) | Coin Handling<br><br>Dipswitch Handling<br><br>Screen Inversion Handling |
|
||||
SNKCLK | ALPHA-68K96V (GW) | [**SNK CLK**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/ALPHA68K-96V_Schematics.pdf) | Counter |
|
||||
INPUT 84 | ALPHA-68K96II | [**ALPHA-INPUT 84**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/ALPHA68K-96V_Schematics.pdf) | Rotary Handling |
|
||||
INPUT 87 | ALPHA-68K96V (GW) | [**ALPHA-INPUT 87**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/ALPHA68K-96V_Schematics.pdf) | Input Handling |
|
||||
ALPHA-8921 | ALPHA-68K96V (GW) | [**ALPHA-8921**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/ALPHA68K-96V_Schematics.pdf) | GFX Muxing |
|
||||
|
||||
### SP85 / ALPHA-8511 / ALPHA-8411 Handling
|
||||
|
||||
The SP85N or ALPHA-8511/8411 utilized on Alpha Denshi M68000 hardware for I/O handling appears to be closely related to the Motorola M68705p5. Early Alpha Denshi M68000 hardware utilized the M68705 before SNK / Alpha Denshi moved to a custom component. It's possible this is a rebadged custom.<br><br>
|
||||
There is a known dump for the ALPHA-8511 (possibly a M68705 from a bootleg) used on Super Stingray and a dump of the M68705 used on the Kyros no Yakata bootleg. The program code from the Kyros no Yakata bootleg may match the original ALPHA-8511 program code according to mame documentation.<br><br>
|
||||
The Sky Adventure bootleg purchased also uses a M68705p5 which is dumpable and will be submitted to mame along with the ROMs. Disassembly of the program code will be done for analysis based on current MCU implementation.<br><br>
|
||||
[**Readings have been pulled from the Gang Wars SP85N**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/Gang%20Wars/SP85N_Readings/SP85N_Gang_Wars_Readings.png) revealed that the MCU pushes 15 interrupts per second, mame's driver for Alpha68k has this coded as 100 or 120 interrupts per second.
|
||||
|
||||
# Core Features
|
||||
|
||||
### Rotary Joystick Support
|
||||
|
||||
- Rotary control is supported via gamepad L and R buttons, or right stick on dual-stick gamepads.
|
||||
|
||||
# Support
|
||||
|
||||
Please consider showing support for this and future projects via [**Darren's Ko-fi**](https://ko-fi.com/darreno) and [**atrac17's Patreon**](https://www.patreon.com/atrac17). While it isn't necessary, it's greatly appreciated.
|
||||
|
||||
# Licensing
|
||||
|
||||
Contact the author for special licensing needs. Otherwise follow the GPLv2 license attached.
|
||||
36
Arcade_MiST/Alpha Densi M68000 Hardware/clean.bat
Normal file
36
Arcade_MiST/Alpha Densi M68000 Hardware/clean.bat
Normal file
@@ -0,0 +1,36 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
del /s *~
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
rmdir /s /q hc_output
|
||||
rmdir /s /q .qsys_edit
|
||||
rmdir /s /q hps_isw_handoff
|
||||
rmdir /s /q sys\.qsys_edit
|
||||
rmdir /s /q sys\vip
|
||||
for /d %%i in (sys\*_sim) do rmdir /s /q "%%i"
|
||||
for /d %%i in (rtl\*_sim) do rmdir /s /q "%%i"
|
||||
del build_id.v
|
||||
del c5_pin_model_dump.txt
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del /s *.qws
|
||||
del /s *.ppf
|
||||
del /s *.ddb
|
||||
del /s *.csv
|
||||
del /s *.cmp
|
||||
del /s *.sip
|
||||
del /s *.spd
|
||||
del /s *.bsf
|
||||
del /s *.f
|
||||
del /s *.sopcinfo
|
||||
del /s *.xml
|
||||
del *.cdf
|
||||
del *.rpt
|
||||
del /s new_rtl_netlist
|
||||
del /s old_rtl_netlist
|
||||
pause
|
||||
73
Arcade_MiST/Alpha Densi M68000 Hardware/meta/Gang Wars.mra
Normal file
73
Arcade_MiST/Alpha Densi M68000 Hardware/meta/Gang Wars.mra
Normal file
@@ -0,0 +1,73 @@
|
||||
<misterromdescription>
|
||||
<name>Gang Wars</name>
|
||||
<setname>gangwars</setname>
|
||||
<rbf>alpha68k</rbf>
|
||||
<mameversion>0249</mameversion>
|
||||
<year>1989</year>
|
||||
<manufacturer>Alpha Denshi Co.</manufacturer>
|
||||
<region>World</region>
|
||||
<joystick>8-Way</joystick>
|
||||
|
||||
<switches default="ff,ff" base="16" page_id="1" page_name="Switches">
|
||||
<!-- IN3 -->
|
||||
<dip name="Lives" bits="3" ids="4,3"/>
|
||||
<dip name="Timer Speed" bits="4" ids="Slow,Normal"/>
|
||||
<dip name="Difficulty" bits="5,6" ids="Hardest,Hard,Easy,Normal"/>
|
||||
<dip name="Demo Sounds" bits="7" ids="Off,On"/>
|
||||
<!-- IN4 -->
|
||||
<dip name="Coin Slots" bits="8" ids="1,2"/>
|
||||
<dip name="Coinage" bits="9,11" ids="5/1,3/1,2/1,1/5,1/4,1/3,1/2,1/1"/>
|
||||
<dip name="Flip Screen" bits="12" ids="On,Off"/>
|
||||
<dip name="Freeze" bits="13" ids="On,Off"/>
|
||||
</switches>
|
||||
|
||||
<buttons names="Kick,Punch,Jump,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start"/>
|
||||
|
||||
<rom index="0" zip="gangwars.zip" md5="None">
|
||||
|
||||
<part>01 3A</part>
|
||||
|
||||
<!-- maincpu - starts at 0x0 -->
|
||||
<interleave output="16">
|
||||
<part name="gw-ver1-e1.19c" crc="7752478e" map="01"/>
|
||||
<part name="gw-ver1-e2.19d" crc="c2f3b85e" map="10"/>
|
||||
</interleave>
|
||||
<interleave output="16">
|
||||
<part name="gw-ver1-e3.18c" crc="2a5fe86e" map="01"/>
|
||||
<part name="gw-ver1-e4.18d" crc="c8b60c53" map="10"/>
|
||||
</interleave>
|
||||
|
||||
<!-- audiocpu - starts at 0x80000 -->
|
||||
<part name="gw-12.10f" crc="e6d6c9cf"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="gw-11.11f" crc="7b9f2608"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="gw-10.13f" crc="eb305d42"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="gw-9.15f" crc="84e5c946"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
|
||||
<!-- gfx1 - starts at 0x100000 -->
|
||||
<part name="gw-13.4l" crc="b75bf1d0"/>
|
||||
<part repeat="0xF0000"> FF</part>
|
||||
|
||||
<!-- gfx2 - starts at 0x200000 -->
|
||||
<interleave output="32">
|
||||
<part name="guernica-c3.17h" crc="281a4138" map="0001"/>
|
||||
<part name="guernica-c2.18h" crc="2fcbea97" map="0010"/>
|
||||
<part name="guernica-c1.20h" crc="b0fd1c23" map="0100"/>
|
||||
<part name="guernica-c0.21h" crc="e60c9882" map="1000"/>
|
||||
</interleave>
|
||||
<interleave output="32">
|
||||
<part name="gw-5.21f" crc="9ef36031" map="0001"/>
|
||||
<part name="gw-6.20f" crc="ddbbcda7" map="0010"/>
|
||||
<part name="gw-7.18f" crc="4656d377" map="0100"/>
|
||||
<part name="gw-8.17f" crc="798ed82a" map="1000"/>
|
||||
</interleave>
|
||||
|
||||
<!-- mcu - starts at 0x480000 -->
|
||||
<!-- <part name="alpha.mcu" crc=""/> -->
|
||||
|
||||
<!-- Total 0x481000 bytes - 4612 kBytes -->
|
||||
</rom>
|
||||
</misterromdescription>
|
||||
@@ -0,0 +1,71 @@
|
||||
<misterromdescription>
|
||||
<name>Gold Medalist (Set 1, Alpha68k II PCB)</name>
|
||||
<setname>goldmedl</setname>
|
||||
<rbf>alpha68k</rbf>
|
||||
<mameversion>0249</mameversion>
|
||||
<year>1988</year>
|
||||
<manufacturer>Alpha Denshi Co.</manufacturer>
|
||||
<region>World</region>
|
||||
<joystick>8-Way</joystick>
|
||||
|
||||
<switches default="ff,ff" base="16" page_id="1" page_name="Switches">
|
||||
<!-- IN3 -->
|
||||
<dip name="Event Select" bits="2" ids="On,Off"/>
|
||||
<dip name="100M Dash Speed" bits="5" ids="10 Beats,14 Beats"/>
|
||||
<dip name="Computer Demonstration" bits="6" ids="Off,On"/>
|
||||
<dip name="4 Player Cabinet" bits="3" ids="Table,4P"/>
|
||||
<dip name="2 Player Cabinet" bits="7" ids="Table,2P"/>
|
||||
<!-- IN4 -->
|
||||
<dip name="Difficulty" bits="8,9" ids="Very Hard,Hard,Normal,Easy"/>
|
||||
<dip name="Coinage" bits="10,12" ids="A 3C/2C B 8C/1C,A 2C/3C B 7C/1C,A 1C/6C B 6C/1C,A 1C/5C B 5C/1C,A 1C/4C B 4C/1C,A 1C/3C B 3C/1C,A 1C/2C B 2C/1C,A 1C/1C B 1C/1C"/>
|
||||
<dip name="Demo Sounds" bits="13" ids="On,Off"/>
|
||||
</switches>
|
||||
|
||||
<buttons names="Run/Spin/Power,Run/Spin/Hit Power,Jump/Jab/Throw Angle,P1 Start,P2 Start,P3 Start,P4 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start,Select,R1,L1"/>
|
||||
|
||||
<rom index="0" zip="goldmedl.zip" md5="None">
|
||||
|
||||
<part>07 0E</part>
|
||||
|
||||
<!-- maincpu - starts at 0x0 -->
|
||||
<interleave output="16">
|
||||
<part name="gm.3" crc="ddf0113c" map="01"/>
|
||||
<part name="gm.4" crc="16db4326" map="10"/>
|
||||
</interleave>
|
||||
<interleave output="16">
|
||||
<part name="gm.1" crc="54a11e28" map="01"/>
|
||||
<part name="gm.2" crc="4b6a13e4" map="10"/>
|
||||
</interleave>
|
||||
<part repeat="0x40000"> FF</part>
|
||||
|
||||
<!-- audiocpu - starts at 0x80000 -->
|
||||
<part name="38.bin" crc="4bf251b8"/>
|
||||
<part name="39.bin" crc="1d92be86"/>
|
||||
<part name="40.bin" crc="8dafc4e8"/>
|
||||
<part name="1.bin" crc="1e78062c"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
|
||||
<!-- gfx1 - starts at 0x100000 -->
|
||||
<interleave output="16">
|
||||
<part name="gm.5" crc="667f33f1" map="01"/>
|
||||
<part name="gm.6" crc="56020b13" map="10"/>
|
||||
</interleave>
|
||||
<part repeat="0xF0000"> FF</part>
|
||||
|
||||
<!-- gfx2 - starts at 0x200000 -->
|
||||
<interleave output="32">
|
||||
<part name="goldchr3.c46" crc="6faaa07a" map="0001"/>
|
||||
<part name="goldchr2.c45" crc="e6b0aa2c" map="0010"/>
|
||||
<part name="goldchr1.c44" crc="55db41cd" map="0100"/>
|
||||
<part name="goldchr0.c43" crc="76572c3f" map="1000"/>
|
||||
</interleave>
|
||||
|
||||
<!-- mcu - starts at 0x400000 -->
|
||||
<!-- <part name="alpha.mcu" crc=""/> -->
|
||||
|
||||
<!-- Total 0x401000 bytes - 4100 kBytes -->
|
||||
</rom>
|
||||
</misterromdescription>
|
||||
@@ -0,0 +1,63 @@
|
||||
<misterromdescription>
|
||||
<name>Sky Adventure (World)</name>
|
||||
<setname>skyadvnt</setname>
|
||||
<rbf>alpha68k</rbf>
|
||||
<mameversion>0249</mameversion>
|
||||
<year>1989</year>
|
||||
<manufacturer>Alpha Denshi Co.</manufacturer>
|
||||
<region>World</region>
|
||||
<joystick>8-Way</joystick>
|
||||
<rotation>vertical (cw)</rotation>
|
||||
|
||||
<switches default="ff,ff" base="16" page_id="1" page_name="Switches">
|
||||
<!-- IN3 -->
|
||||
<dip name="Lives" bits="2,3" ids="5,4,2,3"/>
|
||||
<dip name="Difficulty" bits="5,6" ids="Hardest,Hard,Easy,Normal"/>
|
||||
<dip name="Demo Sounds" bits="7" ids="Off,On"/>
|
||||
<!-- IN4 -->
|
||||
<dip name="Coinage" bits="9,11" ids="A 3C/2C B 8C/1C,A 1C/4C B 4C/1C,A 1C/6C B 6C/1C,A 1C/2C B 2C/1C,A 2C/3C B 7C/1C,A 1C/3C B 3C/1C,A 1C/5C B 5C/1C,A 1C/1C B 1C/1C"/>
|
||||
<dip name="Flip Screen" bits="12" ids="On,Off"/>
|
||||
<dip name="Freeze" bits="13" ids="On,Off"/>
|
||||
</switches>
|
||||
|
||||
<buttons names="Normal Weapon,Special Weapon,-,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start"/>
|
||||
|
||||
<rom index="0" zip="skyadvnt.zip" md5="None">
|
||||
|
||||
<part>80 34</part>
|
||||
|
||||
<!-- maincpu - starts at 0x0 -->
|
||||
<interleave output="16">
|
||||
<part name="sa1.bin" crc="c2b23080" map="01"/>
|
||||
<part name="sa2.bin" crc="06074e72" map="10"/>
|
||||
</interleave>
|
||||
<part repeat="0x40000"> FF</part>
|
||||
|
||||
<!-- audiocpu - starts at 0x80000 -->
|
||||
<part name="sa.3" crc="3d0b32e0"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="sa.4" crc="c2e3c30c"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="sa.5" crc="11cdb868"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="sa.6" crc="237d93fd"/>
|
||||
<part repeat="0x18000"> FF</part>
|
||||
|
||||
<!-- gfx1 - starts at 0x100000 -->
|
||||
<part name="sa.7" crc="ea26e9c5"/>
|
||||
<part repeat="0xF8000"> FF</part>
|
||||
|
||||
<!-- gfx2 - starts at 0x200000 -->
|
||||
<interleave output="32">
|
||||
<part name="sachr3" crc="a986b8d5" map="0001"/>
|
||||
<part name="sachr2" crc="504b07ae" map="0010"/>
|
||||
<part name="sachr1" crc="e734dccd" map="0100"/>
|
||||
<part name="sachr0" crc="e281b204" map="1000"/>
|
||||
</interleave>
|
||||
|
||||
<!-- mcu - starts at 0x400000 -->
|
||||
<!-- <part name="alpha.mcu" crc=""/> -->
|
||||
|
||||
<!-- Total 0x401000 bytes - 4100 kBytes -->
|
||||
</rom>
|
||||
</misterromdescription>
|
||||
@@ -0,0 +1,95 @@
|
||||
<misterromdescription>
|
||||
<name>Sky Soldiers (US)</name>
|
||||
<setname>skysoldr</setname>
|
||||
<rbf>alpha68k</rbf>
|
||||
<mameversion>0249</mameversion>
|
||||
<year>1988</year>
|
||||
<manufacturer>Alpha Denshi Co.</manufacturer>
|
||||
<region>US</region>
|
||||
<joystick>8-Way</joystick>
|
||||
<rotation>vertical (cw)</rotation>
|
||||
|
||||
<switches default="ff,ff" base="16" page_id="1" page_name="Switches">
|
||||
<!-- IN3 -->
|
||||
<dip name="Flip Screen" bits="2" ids="On,Off"/>
|
||||
<dip name="Difficulty" bits="3,4" ids="Hardest,Easy,Normal,Hard"/>
|
||||
<dip name="Language" bits="5" ids="English,Japanese"/>
|
||||
<dip name="Manufacturer" bits="6" ids="Romstar,SNK"/>
|
||||
<dip name="Invulnerability" bits="7" ids="On,Off"/>
|
||||
<!-- IN4 -->
|
||||
<dip name="Coinage" bits="8,10" ids="A 3C/2C B 8C/1C,A 2C/3C B 7C/1C,A 1C/6C B 6C/1C,A 1C/5C B 5C/1C,A 1C/4C B 4C/1C,A 1C/3C B 3C/1C,A 1C/2C B 2C/1C,A 1C/1C B 1C/1C"/>
|
||||
<dip name="Demo Sounds" bits="11" ids="On,Off"/>
|
||||
<dip name="Lives" bits="12,13" ids="6,5,4,3"/>
|
||||
</switches>
|
||||
|
||||
<buttons names="Cannon System,Missle System,-,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start"/>
|
||||
|
||||
<rom index="0" zip="skysoldr.zip" md5="None">
|
||||
|
||||
<part>85 0C</part>
|
||||
|
||||
<!-- maincpu - starts at 0x0 -->
|
||||
<interleave output="16">
|
||||
<part name="ss.3" crc="7b88aa2e" map="01" length="0x10000"/>
|
||||
<part name="ss.4" crc="f0283d43" map="10" length="0x10000"/>
|
||||
</interleave>
|
||||
<interleave output="16">
|
||||
<part name="ss.1" crc="20e9dbc7" map="01" length="0x10000"/>
|
||||
<part name="ss.2" crc="486f3432" map="10" length="0x10000"/>
|
||||
</interleave>
|
||||
<interleave output="16">
|
||||
<part name="ss.3" crc="7b88aa2e" map="01" offset="0x10000" length="0x10000"/>
|
||||
<part name="ss.4" crc="f0283d43" map="10" offset="0x10000" length="0x10000"/>
|
||||
</interleave>
|
||||
<interleave output="16">
|
||||
<part name="ss.1" crc="20e9dbc7" map="01" offset="0x10000" length="0x10000"/>
|
||||
<part name="ss.2" crc="486f3432" map="10" offset="0x10000" length="0x10000"/>
|
||||
</interleave>
|
||||
|
||||
<!-- audiocpu - starts at 0x80000 -->
|
||||
<part name="ss.7" crc="b711fad4"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="ss.8" crc="e5cf7b37"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="ss.9" crc="76124ca2"/>
|
||||
<part repeat="0x30000"> FF</part>
|
||||
|
||||
<!-- gfx1 - starts at 0x100000 -->
|
||||
<interleave output="16">
|
||||
<part name="ss.5" crc="928ba287" map="01"/>
|
||||
<part name="ss.6" crc="93b30b55" map="10"/>
|
||||
</interleave>
|
||||
<part repeat="0xF0000"> FF</part>
|
||||
|
||||
<!-- gfx2 - starts at 0x200000 -->
|
||||
<interleave output="32">
|
||||
<part name="ss.10" crc="e48c1623" map="0001"/>
|
||||
<part name="ss.11" crc="6c63e9c5" map="0010"/>
|
||||
<part name="ss.12" crc="63bb4e89" map="0100"/>
|
||||
<part name="ss.13" crc="3506c06b" map="1000"/>
|
||||
</interleave>
|
||||
<interleave output="32">
|
||||
<part name="ss.14" crc="190c8704" map="0001"/>
|
||||
<part name="ss.15" crc="55f71ab1" map="0010"/>
|
||||
<part name="ss.16" crc="138179f7" map="0100"/>
|
||||
<part name="ss.17" crc="a7f524e0" map="1000"/>
|
||||
</interleave>
|
||||
<interleave output="32">
|
||||
<part name="ss.18" crc="cb6ff33a" map="0001"/>
|
||||
<part name="ss.19" crc="312a21f5" map="0010"/>
|
||||
<part name="ss.20" crc="268cc7b4" map="0100"/>
|
||||
<part name="ss.21" crc="cb7bf5fe" map="1000"/>
|
||||
</interleave>
|
||||
<interleave output="32">
|
||||
<part name="ss.22" crc="e69b4485" map="0001"/>
|
||||
<part name="ss.23" crc="923c19c2" map="0010"/>
|
||||
<part name="ss.24" crc="f63b8417" map="0100"/>
|
||||
<part name="ss.25" crc="65138016" map="1000"/>
|
||||
</interleave>
|
||||
|
||||
<!-- mcu - starts at 0x400000 -->
|
||||
<!-- <part name="alpha.mcu" crc=""/> -->
|
||||
|
||||
<!-- Total 0x401000 bytes - 4100 kBytes -->
|
||||
</rom>
|
||||
</misterromdescription>
|
||||
@@ -0,0 +1,68 @@
|
||||
<misterromdescription>
|
||||
<name>Super Champion Baseball (J)</name>
|
||||
<setname>sbasebalj</setname>
|
||||
<rbf>alpha68k</rbf>
|
||||
<year>1989</year>
|
||||
<manufacturer>Alpha Denshi Co.</manufacturer>
|
||||
<region>US</region>
|
||||
<joystick>8-Way</joystick>
|
||||
|
||||
<switches default="ff,ff" base="16" page_id="1" page_name="Switches">
|
||||
<!-- IN3 -->
|
||||
<dip name="Freeze" bits="2" ids="On,Off"/>
|
||||
<dip name="Flip Screen" bits="3" ids="On,Off"/>
|
||||
<dip name="Game Time" bits="6,7" ids="3:30,2:30,3:00,2:00"/>
|
||||
<!-- IN4 -->
|
||||
<dip name="Difficulty" bits="8,9" ids="Hardest,Hard,Easy,Normal"/>
|
||||
<dip name="Coinage" bits="10,11" ids="Free Play,1/2,2/1,1/1"/>
|
||||
<dip name="Continue Price" bits="12" ids="Coinage,1/1"/>
|
||||
<dip name="Demo Sounds" bits="13" ids="Off,On"/>
|
||||
</switches>
|
||||
|
||||
<buttons names="Swing/Pitch/Field,Steal/Pick Off/Run,Time-Out,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start"/>
|
||||
|
||||
<rom index="0" zip="sbasebal.zip" md5="None">
|
||||
|
||||
<part>02 3A</part>
|
||||
|
||||
<!-- maincpu - starts at 0x0 -->
|
||||
<interleave output="16">
|
||||
<part name="sb-j-1.c19" crc="c46a3c03" map="01"/>
|
||||
<part name="sb-j-2.e19" crc="a8ec2287" map="10"/>
|
||||
</interleave>
|
||||
<part repeat="0x40000"> FF</part>
|
||||
|
||||
<!-- audiocpu - starts at 0x80000 -->
|
||||
<part name="sb-3.g9" crc="89e12f25"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="sb-4.g11" crc="cca2555d"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="sb-5.g13" crc="f45ee36f"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="sb-6.g15" crc="651c9472"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
|
||||
<!-- gfx1 - starts at 0x100000 -->
|
||||
<part name="sb-7.l3" crc="8f3c2e25"/>
|
||||
<part repeat="0xF0000"> FF</part>
|
||||
|
||||
<!-- gfx2 - starts at 0x200000 -->
|
||||
<interleave output="32">
|
||||
<part name="kcb-chr3.h21" crc="719071c7" map="0001"/>
|
||||
<part name="kcb-chr2.h19" crc="014f0f90" map="0010"/>
|
||||
<part name="kcb-chr1.h18" crc="a5ce1e10" map="0100"/>
|
||||
<part name="kcb-chr0.h16" crc="b8a1a088" map="1000"/>
|
||||
</interleave>
|
||||
<interleave output="32">
|
||||
<part name="kcb-chr3.h21" crc="719071c7" map="0001"/>
|
||||
<part name="kcb-chr2.h19" crc="014f0f90" map="0010"/>
|
||||
<part name="kcb-chr1.h18" crc="a5ce1e10" map="0100"/>
|
||||
<part name="kcb-chr0.h16" crc="b8a1a088" map="1000"/>
|
||||
</interleave>
|
||||
|
||||
<!-- mcu - starts at 0x400000 -->
|
||||
<!-- <part name="alpha.mcu" crc=""/> -->
|
||||
|
||||
<!-- Total 0x401000 bytes - 4100 kBytes -->
|
||||
</rom>
|
||||
</misterromdescription>
|
||||
@@ -0,0 +1,83 @@
|
||||
<misterromdescription>
|
||||
<name>Time Soldiers (US Rev 3)</name>
|
||||
<setname>timesold</setname>
|
||||
<rbf>alpha68k</rbf>
|
||||
<mameversion>0249</mameversion>
|
||||
<year>1987</year>
|
||||
<manufacturer>Alpha Denshi Co.</manufacturer>
|
||||
<region>US</region>
|
||||
<joystick>Rotary</joystick>
|
||||
<rotation>vertical (cw)</rotation>
|
||||
|
||||
<switches default="ff,ff" base="16" page_id="1" page_name="Switches">
|
||||
<!-- IN3 -->
|
||||
<dip name="Flip Screen" bits="2" ids="On,Off"/>
|
||||
<dip name="Difficulty" bits="3,4" ids="Easy,Hard,Normal"/>
|
||||
<dip name="Language" bits="5" ids="English,Japanese"/>
|
||||
<dip name="Unused" bits="6" ids="On,Off"/>
|
||||
<dip name="Invulnerability" bits="7" ids="On,Off"/>
|
||||
<!-- IN4 -->
|
||||
<dip name="Coinage" bits="8,10" ids="A 3C/2C B 8C/1C,A 2C/3C B 7C/1C,A 1C/6C B 6C/1C,A 1C/5C B 5C/1C,A 1C/4C B 4C/1C,A 1C/3C B 3C/1C,A 1C/2C B 2C/1C,A 1C/1C B 1C/1C"/>
|
||||
<dip name="Demo Sounds" bits="11" ids="On,Off"/>
|
||||
<dip name="Lives" bits="12,13" ids="6,5,4,3"/>
|
||||
</switches>
|
||||
|
||||
<buttons names="Shot,Weapon,-,P1 Start,P2 Start,Coin A,Coin B,Pause,Rotate CW,Rotate CCW" default="A,B,X,Y,R,L,Start,Select,R1,L1"/>
|
||||
|
||||
|
||||
<rom index="0" zip="timesold.zip" md5="None">
|
||||
|
||||
<part>86 01</part>
|
||||
|
||||
<!-- maincpu - starts at 0x0 -->
|
||||
<interleave output="16">
|
||||
<part name="bf.3" crc="a491e533" map="01"/>
|
||||
<part name="bf.4" crc="34ebaccc" map="10"/>
|
||||
</interleave>
|
||||
<interleave output="16">
|
||||
<part name="bf.1" crc="158f4cb3" map="01"/>
|
||||
<part name="bf.2" crc="af01a718" map="10"/>
|
||||
</interleave>
|
||||
<part repeat="0x40000"> FF</part>
|
||||
|
||||
<!-- audiocpu - starts at 0x80000 -->
|
||||
<part name="bf.7" crc="f8b293b5"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="bf.8" crc="8a43497b"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="bf.9" crc="1408416f"/>
|
||||
<part repeat="0x30000"> FF</part>
|
||||
|
||||
<!-- gfx1 - starts at 0x100000 -->
|
||||
<interleave output="16">
|
||||
<part name="bf.5" crc="3cec2f55" map="01"/>
|
||||
<part name="bf.6" crc="086a364d" map="10"/>
|
||||
</interleave>
|
||||
<part repeat="0xF0000"> FF</part>
|
||||
|
||||
<!-- gfx2 - starts at 0x200000 -->
|
||||
<interleave output="32">
|
||||
<part name="bf.10" crc="613313ba" map="0001"/>
|
||||
<part name="bf.11" crc="92b42eba" map="0010"/>
|
||||
<part name="bf.12" crc="7ca8bb32" map="0100"/>
|
||||
<part name="bf.13" crc="56a3a26a" map="1000"/>
|
||||
</interleave>
|
||||
<interleave output="32">
|
||||
<part name="bf.14" crc="efda5c45" map="0001"/>
|
||||
<part name="bf.15" crc="ba3b9f5a" map="0010"/>
|
||||
<part name="bf.16" crc="2aa74125" map="0100"/>
|
||||
<part name="bf.17" crc="6b37d048" map="1000"/>
|
||||
</interleave>
|
||||
<interleave output="32">
|
||||
<part name="bf.18" crc="e886146a" map="0001"/>
|
||||
<part name="bf.19" crc="8994bf10" map="0010"/>
|
||||
<part name="bf.20" crc="bab6a7c5" map="0100"/>
|
||||
<part name="bf.21" crc="bc3b3944" map="1000"/>
|
||||
</interleave>
|
||||
|
||||
<!-- mcu - starts at 0x380000 -->
|
||||
<!-- <part name="alpha.mcu" crc=""/> -->
|
||||
|
||||
<!-- Total 0x381000 bytes - 3588 kBytes -->
|
||||
</rom>
|
||||
</misterromdescription>
|
||||
@@ -0,0 +1,68 @@
|
||||
<misterromdescription>
|
||||
<name>Super Champion Baseball (US)</name>
|
||||
<setname>sbasebal</setname>
|
||||
<rbf>alpha68k</rbf>
|
||||
<year>1989</year>
|
||||
<manufacturer>Alpha Denshi Co.</manufacturer>
|
||||
<region>US</region>
|
||||
<joystick>8-Way</joystick>
|
||||
|
||||
<switches default="ff,ff" base="16" page_id="1" page_name="Switches">
|
||||
<!-- IN3 -->
|
||||
<dip name="Freeze" bits="2" ids="On,Off"/>
|
||||
<dip name="Flip Screen" bits="3" ids="On,Off"/>
|
||||
<dip name="Game Time" bits="6,7" ids="3:30,2:30,3:00,2:00"/>
|
||||
<!-- IN4 -->
|
||||
<dip name="Difficulty" bits="8,9" ids="Hardest,Hard,Easy,Normal"/>
|
||||
<dip name="Coinage" bits="10,11" ids="Free Play,1/2,2/1,1/1"/>
|
||||
<dip name="Continue Price" bits="12" ids="Coinage,1/1"/>
|
||||
<dip name="Demo Sounds" bits="13" ids="Off,On"/>
|
||||
</switches>
|
||||
|
||||
<buttons names="Swing/Pitch/Field,Steal/Pick Off/Run,Time-Out,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start"/>
|
||||
|
||||
<rom index="0" zip="sbasebal.zip" md5="None">
|
||||
|
||||
<part>03 3A</part>
|
||||
|
||||
<!-- maincpu - starts at 0x0 -->
|
||||
<interleave output="16">
|
||||
<part name="snksb1.c19" crc="304fef2d" map="01"/>
|
||||
<part name="snksb2.e19" crc="35821339" map="10"/>
|
||||
</interleave>
|
||||
<part repeat="0x40000"> FF</part>
|
||||
|
||||
<!-- audiocpu - starts at 0x80000 -->
|
||||
<part name="sb-3.g9" crc="89e12f25"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="sb-4.g11" crc="cca2555d"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="sb-5.g13" crc="f45ee36f"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
<part name="sb-6.g15" crc="651c9472"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
|
||||
<!-- gfx1 - starts at 0x100000 -->
|
||||
<part name="sb-7.l3" crc="8f3c2e25"/>
|
||||
<part repeat="0xF0000"> FF</part>
|
||||
|
||||
<!-- gfx2 - starts at 0x200000 -->
|
||||
<interleave output="32">
|
||||
<part name="kcb-chr3.h21" crc="719071c7" map="0001"/>
|
||||
<part name="kcb-chr2.h19" crc="014f0f90" map="0010"/>
|
||||
<part name="kcb-chr1.h18" crc="a5ce1e10" map="0100"/>
|
||||
<part name="kcb-chr0.h16" crc="b8a1a088" map="1000"/>
|
||||
</interleave>
|
||||
<interleave output="32">
|
||||
<part name="kcb-chr3.h21" crc="719071c7" map="0001"/>
|
||||
<part name="kcb-chr2.h19" crc="014f0f90" map="0010"/>
|
||||
<part name="kcb-chr1.h18" crc="a5ce1e10" map="0100"/>
|
||||
<part name="kcb-chr0.h16" crc="b8a1a088" map="1000"/>
|
||||
</interleave>
|
||||
|
||||
<!-- mcu - starts at 0x400000 -->
|
||||
<!-- <part name="alpha.mcu" crc=""/> -->
|
||||
|
||||
<!-- Total 0x401000 bytes - 4100 kBytes -->
|
||||
</rom>
|
||||
</misterromdescription>
|
||||
1263
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/Alpha68k.sv
Normal file
1263
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/Alpha68k.sv
Normal file
File diff suppressed because it is too large
Load Diff
345
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/Alpha68k_MiST.sv
Normal file
345
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/Alpha68k_MiST.sv
Normal file
@@ -0,0 +1,345 @@
|
||||
//============================================================================
|
||||
// Alpha Densi M68000 HW top-level for MiST
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//============================================================================
|
||||
|
||||
module Alpha68k_MiST
|
||||
(
|
||||
output LED,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
inout SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input SPI_SS4,
|
||||
input CONF_DATA0,
|
||||
input CLOCK_27,
|
||||
|
||||
output [12:0] SDRAM_A,
|
||||
inout [15:0] SDRAM_DQ,
|
||||
output SDRAM_DQML,
|
||||
output SDRAM_DQMH,
|
||||
output SDRAM_nWE,
|
||||
output SDRAM_nCAS,
|
||||
output SDRAM_nRAS,
|
||||
output SDRAM_nCS,
|
||||
output [1:0] SDRAM_BA,
|
||||
output SDRAM_CLK,
|
||||
output SDRAM_CKE
|
||||
);
|
||||
|
||||
`include "build_id.v"
|
||||
`include "defs.v"
|
||||
|
||||
`define CORE_NAME "GANGWARS"
|
||||
|
||||
localparam CONF_STR = {
|
||||
`CORE_NAME, ";;",
|
||||
"O2,Rotate Controls,Off,On;",
|
||||
"O34,Scanlines,Off,25%,50%,75%;",
|
||||
"O5,Blending,Off,On;",
|
||||
"O6,Joystick Swap,Off,On;",
|
||||
"DIP;",
|
||||
"T0,Reset;",
|
||||
"V,v1.20.",`BUILD_DATE
|
||||
};
|
||||
|
||||
wire rotate = status[2];
|
||||
wire [1:0] scanlines = status[4:3];
|
||||
wire blend = status[5];
|
||||
wire joyswap = status[6];
|
||||
|
||||
wire [7:0] dsw1 = status[23:16];
|
||||
wire [7:0] dsw2 = status[31:24];
|
||||
reg [7:0] dsw_m68k, dsw_sp85;
|
||||
reg [7:0] p1, p2;
|
||||
wire flipped;
|
||||
wire key_service = m_fire1[4];
|
||||
wire key_test = m_fire1[3];
|
||||
reg [3:0] pcb;
|
||||
reg [7:0] brd;
|
||||
reg tate;
|
||||
|
||||
always @(*) begin
|
||||
|
||||
if ( pcb == GOLDMEDL ) begin
|
||||
// special case gold medal
|
||||
// controls are active low
|
||||
p1 = {m_one_player, m_three_players, m_fire2[1], m_fire1[1], m_fire2[2], m_fire2[0], m_fire1[2], m_fire1[0]} ;
|
||||
p2 = {m_two_players, m_four_players, m_fire4[1], m_fire3[1], m_fire4[2], m_fire4[0], m_fire3[2], m_fire3[0]} ;
|
||||
|
||||
dsw_m68k = ~{dsw1[7:2], ~key_test, ~key_service};
|
||||
dsw_sp85 = dsw2[7:0];
|
||||
end else begin
|
||||
// non inverted - active low
|
||||
p1 = ~{ m_one_player, m_fire1[2:0], m_right1, m_left1, m_down1, m_up1};
|
||||
p2 = ~{ m_two_players, m_fire2[2:0], m_right2, m_left2, m_down2, m_up2};
|
||||
|
||||
dsw_m68k = {dsw1[7:2], ~key_test, ~key_service};
|
||||
dsw_sp85 = dsw2[7:0];
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
wire rot1_cw = m_fire1[7] | m_right1B | m_up1B; // R
|
||||
wire rot1_ccw = m_fire1[6] | m_left1B | m_down1B; // L
|
||||
wire rot2_cw = m_fire2[7] | m_right2B | m_up2B; // R
|
||||
wire rot2_ccw = m_fire2[6] | m_left2B | m_down2B; // L
|
||||
|
||||
wire [11:0] rotary1;
|
||||
wire [11:0] rotary2;
|
||||
|
||||
rotary_ctrl rot1(clk_72, reset, rot1_cw, rot1_ccw, rotary1);
|
||||
rotary_ctrl rot2(clk_72, reset, rot2_cw, rot2_ccw, rotary2);
|
||||
|
||||
assign LED = ~ioctl_downl;
|
||||
assign SDRAM_CLK = clk_72;
|
||||
assign SDRAM_CKE = 1;
|
||||
|
||||
wire clk_72;
|
||||
wire pll_locked;
|
||||
pll_mist pll(
|
||||
.inclk0(CLOCK_27),
|
||||
.c0(clk_72),
|
||||
.locked(pll_locked)
|
||||
);
|
||||
|
||||
// reset generation
|
||||
reg reset = 1;
|
||||
reg rom_loaded = 0;
|
||||
always @(posedge clk_72) begin
|
||||
reg ioctl_downlD;
|
||||
ioctl_downlD <= ioctl_downl;
|
||||
|
||||
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
|
||||
reset <= status[0] | buttons[1] | ~rom_loaded | ioctl_downl;
|
||||
if (ioctl_wr) begin
|
||||
if (ioctl_addr == 0) begin
|
||||
tate <= ioctl_dout[7];
|
||||
pcb <= ioctl_dout[3:0];
|
||||
end
|
||||
else if (ioctl_addr == 1) brd <= ioctl_dout;
|
||||
end
|
||||
end
|
||||
|
||||
// ARM connection
|
||||
wire [63:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [31:0] joystick_0;
|
||||
wire [31:0] joystick_1;
|
||||
wire scandoublerD;
|
||||
wire ypbpr;
|
||||
wire no_csync;
|
||||
wire key_strobe;
|
||||
wire key_pressed;
|
||||
wire [7:0] key_code;
|
||||
wire [6:0] core_mod;
|
||||
|
||||
user_io #(
|
||||
.STRLEN($size(CONF_STR)>>3),
|
||||
.ROM_DIRECT_UPLOAD(1))
|
||||
user_io(
|
||||
.clk_sys (clk_72 ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
.SPI_MISO (SPI_DO ),
|
||||
.SPI_MOSI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.no_csync (no_csync ),
|
||||
.core_mod (core_mod ),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.joystick_0 (joystick_0 ),
|
||||
.joystick_1 (joystick_1 ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
wire ioctl_downl;
|
||||
wire [7:0] ioctl_index;
|
||||
wire ioctl_wr;
|
||||
wire [24:0] ioctl_addr;
|
||||
wire [7:0] ioctl_dout;
|
||||
|
||||
data_io #(.ROM_DIRECT_UPLOAD(1)) data_io(
|
||||
.clk_sys ( clk_72 ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS2 ( SPI_SS2 ),
|
||||
.SPI_SS4 ( SPI_SS4 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.SPI_DO ( SPI_DO ),
|
||||
.ioctl_download( ioctl_downl ),
|
||||
.ioctl_index ( ioctl_index ),
|
||||
.ioctl_wr ( ioctl_wr ),
|
||||
.ioctl_addr ( ioctl_addr ),
|
||||
.ioctl_dout ( ioctl_dout )
|
||||
);
|
||||
|
||||
wire [15:0] laudio, raudio;
|
||||
wire hs, vs;
|
||||
wire blankn = ~(hb | vb);
|
||||
wire hb, vb;
|
||||
wire [7:0] r,b,g;
|
||||
|
||||
Alpha68k Alpha68k
|
||||
(
|
||||
.pll_locked ( pll_locked ),
|
||||
.clk_sys ( clk_72 ),
|
||||
.reset ( reset ),
|
||||
.pcb ( pcb ),
|
||||
.brd ( brd ),
|
||||
|
||||
.flip_in ( 1'b0 ), // usually a DIP can be used to flip screen
|
||||
.flipped ( flipped ),
|
||||
.p1 ( p1 ),
|
||||
.p2 ( p2 ),
|
||||
.dsw_m68k ( dsw_m68k ),
|
||||
.dsw_sp85 ( dsw_sp85 ),
|
||||
.coin_a ( m_coin1 ),
|
||||
.coin_b ( m_coin2 ),
|
||||
.rotary1 ( rotary1 ),
|
||||
.rotary2 ( rotary2 ),
|
||||
|
||||
.hbl ( hb ),
|
||||
.vbl ( vb ),
|
||||
.hsync ( hs ),
|
||||
.vsync ( vs ),
|
||||
.r ( r ),
|
||||
.g ( g ),
|
||||
.b ( b ),
|
||||
|
||||
.audio_l ( laudio ),
|
||||
.audio_r ( raudio ),
|
||||
|
||||
.rom_download ( ioctl_downl),
|
||||
.ioctl_addr ( ioctl_addr - 2'd2 ),
|
||||
.ioctl_wr ( ioctl_wr ),
|
||||
.ioctl_dout ( ioctl_dout ),
|
||||
|
||||
.SDRAM_A ( SDRAM_A ),
|
||||
.SDRAM_BA ( SDRAM_BA ),
|
||||
.SDRAM_DQ ( SDRAM_DQ ),
|
||||
.SDRAM_DQML ( SDRAM_DQML ),
|
||||
.SDRAM_DQMH ( SDRAM_DQMH ),
|
||||
.SDRAM_nCS ( SDRAM_nCS ),
|
||||
.SDRAM_nCAS ( SDRAM_nCAS ),
|
||||
.SDRAM_nRAS ( SDRAM_nRAS ),
|
||||
.SDRAM_nWE ( SDRAM_nWE )
|
||||
);
|
||||
|
||||
mist_video #(.COLOR_DEPTH(6),.SD_HCNT_WIDTH(10)) mist_video(
|
||||
.clk_sys(clk_72),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_SS3(SPI_SS3),
|
||||
.SPI_DI(SPI_DI),
|
||||
.R(blankn ? r[7:2] : 6'd0),
|
||||
.G(blankn ? g[7:2] : 6'd0),
|
||||
.B(blankn ? b[7:2] : 6'd0),
|
||||
.HSync(~hs),
|
||||
.VSync(~vs),
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_HS(VGA_HS),
|
||||
.no_csync(no_csync),
|
||||
.rotate({~flipped,rotate}),
|
||||
.ce_divider(3'd5), // pix clock = 72/6
|
||||
.blend(blend),
|
||||
.scandoubler_disable(scandoublerD),
|
||||
.scanlines(scanlines),
|
||||
.ypbpr(ypbpr)
|
||||
);
|
||||
|
||||
dac #(16) dacl(
|
||||
.clk_i(clk_72),
|
||||
.res_n_i(1),
|
||||
.dac_i({~laudio[15], laudio[14:0]}),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
|
||||
dac #(16) dacr(
|
||||
.clk_i(clk_72),
|
||||
.res_n_i(1),
|
||||
.dac_i({~raudio[15], raudio[14:0]}),
|
||||
.dac_o(AUDIO_R)
|
||||
);
|
||||
|
||||
// Common inputs
|
||||
wire m_up1, m_down1, m_left1, m_right1, m_up1B, m_down1B, m_left1B, m_right1B;
|
||||
wire m_up2, m_down2, m_left2, m_right2, m_up2B, m_down2B, m_left2B, m_right2B;
|
||||
wire m_up3, m_down3, m_left3, m_right3, m_up3B, m_down3B, m_left3B, m_right3B;
|
||||
wire m_up4, m_down4, m_left4, m_right4, m_up4B, m_down4B, m_left4B, m_right4B;
|
||||
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
|
||||
wire [11:0] m_fire1, m_fire2, m_fire3, m_fire4;
|
||||
|
||||
arcade_inputs inputs (
|
||||
.clk ( clk_72 ),
|
||||
.key_strobe ( key_strobe ),
|
||||
.key_pressed ( key_pressed ),
|
||||
.key_code ( key_code ),
|
||||
.joystick_0 ( joystick_0 ),
|
||||
.joystick_1 ( joystick_1 ),
|
||||
.rotate ( rotate ),
|
||||
.orientation ( {~flipped, tate} ),
|
||||
.joyswap ( joyswap ),
|
||||
.oneplayer ( 1'b0 ),
|
||||
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
|
||||
.player1 ( {m_up1B, m_down1B, m_left1B, m_right1B, m_fire1, m_up1, m_down1, m_left1, m_right1} ),
|
||||
.player2 ( {m_up2B, m_down2B, m_left2B, m_right2B, m_fire2, m_up2, m_down2, m_left2, m_right2} ),
|
||||
.player3 ( {m_up3B, m_down3B, m_left3B, m_right3B, m_fire3, m_up3, m_down3, m_left3, m_right3} ),
|
||||
.player4 ( {m_up4B, m_down4B, m_left4B, m_right4B, m_fire4, m_up4, m_down4, m_left4, m_right4} )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
module rotary_ctrl
|
||||
(
|
||||
input clk_sys,
|
||||
input reset,
|
||||
input cw,
|
||||
input ccw,
|
||||
output reg [11:0] rotary
|
||||
);
|
||||
|
||||
reg cw_last, ccw_last;
|
||||
always @ (posedge clk_sys) begin
|
||||
if (reset) begin
|
||||
rotary <= 12'h1;
|
||||
end else begin
|
||||
cw_last <= cw;
|
||||
ccw_last <= ccw;
|
||||
if (cw & ~cw_last)
|
||||
rotary <= { rotary[0], rotary[11:1] };
|
||||
|
||||
if (ccw & ~ccw_last)
|
||||
rotary <= { rotary[10:0], rotary[11] };
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
35
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/build_id.tcl
Normal file
35
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/build_id.tcl
Normal file
@@ -0,0 +1,35 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
285
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/chip_select.v
Normal file
285
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/chip_select.v
Normal file
@@ -0,0 +1,285 @@
|
||||
//
|
||||
|
||||
module chip_select
|
||||
(
|
||||
input [3:0] pcb,
|
||||
|
||||
|
||||
input [23:0] m68k_a,
|
||||
input m68k_as_n,
|
||||
input m68k_rw,
|
||||
input m68k_uds_n,
|
||||
input m68k_lds_n,
|
||||
|
||||
input [15:0] z80_addr,
|
||||
input MREQ_n,
|
||||
input IORQ_n,
|
||||
input RD_n,
|
||||
input WR_n,
|
||||
input M1_n,
|
||||
input RFSH_n,
|
||||
|
||||
// M68K selects
|
||||
output reg m68k_rom_cs,
|
||||
output reg m68k_rom_2_cs,
|
||||
output reg m68k_ram_cs,
|
||||
output reg m68k_spr_cs,
|
||||
output reg m68k_pal_cs,
|
||||
output reg m68k_fg_ram_cs,
|
||||
output reg m68k_sp85_cs,
|
||||
|
||||
output reg input_p1_cs,
|
||||
output reg m68k_dsw_cs,
|
||||
|
||||
output reg m68k_rotary2_cs,
|
||||
output reg m68k_rotary_msb_cs,
|
||||
|
||||
output reg vbl_int_clr_cs,
|
||||
output reg cpu_int_clr_cs,
|
||||
output reg watchdog_clr_cs,
|
||||
|
||||
output reg m68k_latch_cs,
|
||||
|
||||
// Z80 selects
|
||||
output reg z80_rom_cs,
|
||||
output reg z80_ram_cs,
|
||||
|
||||
output reg z80_latch_cs,
|
||||
output reg z80_latch_clr_cs,
|
||||
output reg z80_dac_cs,
|
||||
output reg z80_ym2413_cs, // OPN YM2413
|
||||
output reg z80_ym2203_cs, // OPLL YM2203
|
||||
output reg z80_bank_set_cs,
|
||||
output reg z80_banked_cs
|
||||
);
|
||||
|
||||
`include "defs.v"
|
||||
|
||||
function m68k_cs;
|
||||
input [23:0] start_address;
|
||||
input [23:0] end_address;
|
||||
begin
|
||||
m68k_cs = ( m68k_a[23:0] >= start_address && m68k_a[23:0] <= end_address) & !m68k_as_n & !(m68k_uds_n & m68k_lds_n);
|
||||
end
|
||||
endfunction
|
||||
|
||||
function z80_mem_cs;
|
||||
input [15:0] base_address;
|
||||
input [7:0] width;
|
||||
begin
|
||||
z80_mem_cs = ( z80_addr >> width == base_address >> width ) & !MREQ_n & RFSH_n;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function z80_io_cs;
|
||||
input [7:0] address_lo;
|
||||
begin
|
||||
z80_io_cs = ( z80_addr[7:0] == address_lo ) && !IORQ_n ;
|
||||
end
|
||||
endfunction
|
||||
|
||||
//-- board config 6 bits
|
||||
// 00 = II
|
||||
// 01 = III
|
||||
// 11 = V
|
||||
//mcu id 00 = don't care
|
||||
// 01 = 0x8814
|
||||
// 10 = 0x8512
|
||||
// 11 = 0x8713
|
||||
//coin 0 = 0x2222 / 1 = 0x2423
|
||||
//invert 0 = input not inverted / 1 = inverted
|
||||
|
||||
always @ (*) begin
|
||||
// Memory mapping based on PCB type
|
||||
m68k_rom_cs = 0;
|
||||
m68k_ram_cs = 0;
|
||||
m68k_latch_cs = 0;
|
||||
input_p1_cs = 0;
|
||||
m68k_dsw_cs = 0;
|
||||
m68k_fg_ram_cs = 0;
|
||||
m68k_spr_cs = 0;
|
||||
m68k_rotary2_cs = 0;
|
||||
m68k_rotary_msb_cs = 0;
|
||||
m68k_sp85_cs = 0;
|
||||
m68k_pal_cs = 0;
|
||||
m68k_rom_2_cs = 0;
|
||||
cpu_int_clr_cs = 0;
|
||||
vbl_int_clr_cs = 0;
|
||||
watchdog_clr_cs = 0;
|
||||
z80_rom_cs = 0;
|
||||
z80_ram_cs = 0;
|
||||
z80_banked_cs = 0;
|
||||
z80_latch_cs = 0;
|
||||
z80_latch_clr_cs = 0;
|
||||
z80_dac_cs = 0;
|
||||
z80_ym2413_cs = 0;
|
||||
z80_ym2203_cs = 0;
|
||||
z80_bank_set_cs = 0;
|
||||
|
||||
// reset microcontroller interrupt
|
||||
cpu_int_clr_cs = m68k_cs( 24'h0d8000, 24'h0dffff ) & m68k_rw; // tst.b $d8000.l
|
||||
|
||||
// reset vblank interrupt
|
||||
vbl_int_clr_cs = m68k_cs( 24'h0e0000, 24'h0e7fff ) & m68k_rw; // tst.b $e0000.l
|
||||
|
||||
case (pcb)
|
||||
SKYADV, SKYADVU, GANGWARS, SBASEBALJ, SBASEBAL: begin
|
||||
m68k_rom_cs = m68k_cs( 24'h000000, 24'h03ffff ) ;
|
||||
|
||||
m68k_ram_cs = m68k_cs( 24'h040000, 24'h043fff ) ;
|
||||
|
||||
m68k_latch_cs = m68k_cs( 24'h080000, 24'h080001 ) & !m68k_rw ;
|
||||
|
||||
input_p1_cs = m68k_cs( 24'h080000, 24'h080001 ) & m68k_rw ;
|
||||
|
||||
m68k_dsw_cs = m68k_cs( 24'h0c0000, 24'h0c0001 ) ;
|
||||
|
||||
m68k_fg_ram_cs = m68k_cs( 24'h100000, 24'h100fff ) ;
|
||||
|
||||
m68k_spr_cs = m68k_cs( 24'h200000, 24'h207fff ) ;
|
||||
|
||||
m68k_rotary2_cs = 0 ;
|
||||
|
||||
m68k_rotary_msb_cs = 0;
|
||||
|
||||
m68k_sp85_cs = m68k_cs( 24'h300000, 24'h303fff ) ;
|
||||
|
||||
m68k_pal_cs = m68k_cs( 24'h400000, 24'h401fff ) ;
|
||||
|
||||
m68k_rom_2_cs = m68k_cs( 24'h800000, 24'h83ffff ) ;
|
||||
|
||||
// reset watchdog interrupt ( implement? )
|
||||
watchdog_clr_cs = m68k_cs( 24'h0e8000, 24'h0effff ) ; // tst.b $e8000.l
|
||||
|
||||
z80_rom_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] < 16'h8000 );
|
||||
z80_ram_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] >= 16'h8000 && z80_addr[15:0] < 16'h8800 );
|
||||
z80_banked_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] >= 16'hc000 );
|
||||
|
||||
// read latch. latch is active on all i/o reads
|
||||
z80_latch_cs = (!IORQ_n) && (!RD_n) ;
|
||||
|
||||
z80_latch_clr_cs = ( z80_addr[3:1] == 3'b000 ) && ( !IORQ_n ) && (!WR_n);
|
||||
|
||||
// only the lower 4 bits are used to decode port
|
||||
// 0x08-0x09
|
||||
z80_dac_cs = ( z80_addr[3:1] == 3'b100 ) && ( !IORQ_n ) && (!WR_n) ; // 8 bit DAC
|
||||
|
||||
// 0x0a-0x0b
|
||||
z80_ym2413_cs = ( z80_addr[3:1] == 3'b101 ) && ( !IORQ_n ) && (!WR_n);
|
||||
|
||||
// 0x0c-0x0d
|
||||
z80_ym2203_cs = ( z80_addr[3:1] == 3'b110 ) && ( !IORQ_n ) && (!WR_n);
|
||||
|
||||
// 0x0E-0x0F
|
||||
z80_bank_set_cs = ( z80_addr[3:1] == 3'b111 ) && ( !IORQ_n ) && (!WR_n); // select latches z80 D[4:0]
|
||||
end
|
||||
|
||||
GOLDMEDL: begin
|
||||
m68k_rom_cs = m68k_cs( 24'h000000, 24'h03ffff ) ;
|
||||
|
||||
m68k_ram_cs = m68k_cs( 24'h040000, 24'h040fff ) ;
|
||||
|
||||
m68k_latch_cs = m68k_cs( 24'h080000, 24'h080001 ) & !m68k_rw ;
|
||||
|
||||
input_p1_cs = m68k_cs( 24'h080000, 24'h080001 ) & m68k_rw ;
|
||||
|
||||
|
||||
m68k_dsw_cs = m68k_cs( 24'h0c0000, 24'h0c007f ) ;
|
||||
|
||||
m68k_rotary2_cs = 0 ;
|
||||
|
||||
m68k_rotary_msb_cs = 0;
|
||||
|
||||
m68k_fg_ram_cs = m68k_cs( 24'h100000, 24'h100fff ) ;
|
||||
|
||||
m68k_spr_cs = m68k_cs( 24'h200000, 24'h207fff ) ;
|
||||
|
||||
m68k_sp85_cs = m68k_cs( 24'h300000, 24'h303fff ) ;
|
||||
|
||||
m68k_pal_cs = m68k_cs( 24'h400000, 24'h400fff ) ;
|
||||
|
||||
m68k_rom_2_cs = m68k_cs( 24'h800000, 24'h83ffff ) ;
|
||||
|
||||
// reset watchdog interrupt ( implement? )
|
||||
watchdog_clr_cs = 0; //m68k_cs( 24'h0e8000, 24'h0effff ) ; // tst.b $e8000.l
|
||||
|
||||
z80_rom_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] < 16'h8000 );
|
||||
z80_ram_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] >= 16'h8000 && z80_addr[15:0] < 16'h8800 );
|
||||
z80_banked_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] >= 16'hc000 );
|
||||
|
||||
// read latch. latch is active on all i/o reads
|
||||
z80_latch_cs = (!IORQ_n) && (!RD_n) ;
|
||||
|
||||
z80_latch_clr_cs = ( z80_addr[3:1] == 3'b000 ) && ( !IORQ_n ) && (!WR_n);
|
||||
|
||||
// only the lower 4 bits are used to decode port
|
||||
// 0x08-0x09
|
||||
z80_dac_cs = ( z80_addr[3:1] == 3'b100 ) && ( !IORQ_n ) && (!WR_n) ; // 8 bit DAC
|
||||
|
||||
// 0x0a-0x0b
|
||||
z80_ym2413_cs = ( z80_addr[3:1] == 3'b101 ) && ( !IORQ_n ) && (!WR_n);
|
||||
|
||||
// 0x0c-0x0d
|
||||
z80_ym2203_cs = ( z80_addr[3:1] == 3'b110 ) && ( !IORQ_n ) && (!WR_n);
|
||||
|
||||
// 0x0E-0x0F
|
||||
z80_bank_set_cs = ( z80_addr[3:1] == 3'b111 ) && ( !IORQ_n ) && (!WR_n); // select latches z80 D[4:0]
|
||||
end
|
||||
|
||||
SKYSOLDR, TIMESOLD, BATFIELD: begin
|
||||
m68k_rom_cs = m68k_cs( 24'h000000, 24'h03ffff ) ;
|
||||
|
||||
m68k_ram_cs = m68k_cs( 24'h040000, 24'h040fff ) ;
|
||||
|
||||
m68k_latch_cs = m68k_cs( 24'h080000, 24'h080001 ) & !m68k_rw ;
|
||||
|
||||
input_p1_cs = m68k_cs( 24'h080000, 24'h080001 ) & m68k_rw ;
|
||||
|
||||
// dsw / CN1 rotary / Ver II text banking
|
||||
m68k_dsw_cs = m68k_cs( 24'h0c0000, 24'h0c007f ) ;
|
||||
|
||||
m68k_rotary2_cs = m68k_cs( 24'h0c8000, 24'h0c8001 ) & m68k_rw;
|
||||
|
||||
m68k_rotary_msb_cs = m68k_cs( 24'h0d0000, 24'h0d0001 ) ;
|
||||
|
||||
m68k_fg_ram_cs = m68k_cs( 24'h100000, 24'h100fff ) ;
|
||||
|
||||
m68k_spr_cs = m68k_cs( 24'h200000, 24'h207fff ) ;
|
||||
|
||||
m68k_sp85_cs = m68k_cs( 24'h300000, 24'h303fff ) ;
|
||||
|
||||
m68k_pal_cs = m68k_cs( 24'h400000, 24'h400fff ) ;
|
||||
|
||||
m68k_rom_2_cs = m68k_cs( 24'h800000, 24'h83ffff ) ;
|
||||
|
||||
// reset watchdog interrupt ( implement? )
|
||||
watchdog_clr_cs = 0; //m68k_cs( 24'h0e8000, 24'h0effff ) ; // tst.b $e8000.l
|
||||
|
||||
z80_rom_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] < 16'h8000 );
|
||||
z80_ram_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] >= 16'h8000 && z80_addr[15:0] < 16'h8800 );
|
||||
z80_banked_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] >= 16'hc000 );
|
||||
|
||||
// read latch. latch is active on all i/o reads
|
||||
z80_latch_cs = (!IORQ_n) && (!RD_n) ;
|
||||
|
||||
z80_latch_clr_cs = ( z80_addr[3:1] == 3'b000 ) && ( !IORQ_n ) && (!WR_n);
|
||||
|
||||
// only the lower 4 bits are used to decode port
|
||||
// 0x08-0x09
|
||||
z80_dac_cs = ( z80_addr[3:1] == 3'b100 ) && ( !IORQ_n ) && (!WR_n) ; // 8 bit DAC
|
||||
|
||||
// 0x0a-0x0b
|
||||
z80_ym2413_cs = ( z80_addr[3:1] == 3'b101 ) && ( !IORQ_n ) && (!WR_n);
|
||||
|
||||
// 0x0c-0x0d
|
||||
z80_ym2203_cs = ( z80_addr[3:1] == 3'b110 ) && ( !IORQ_n ) && (!WR_n);
|
||||
|
||||
// 0x0E-0x0F
|
||||
z80_bank_set_cs = ( z80_addr[3:1] == 3'b111 ) && ( !IORQ_n ) && (!WR_n); // select latches z80 D[4:0]
|
||||
end
|
||||
default:;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
9
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/defs.v
Normal file
9
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/defs.v
Normal file
@@ -0,0 +1,9 @@
|
||||
localparam SKYADV = 0;
|
||||
localparam GANGWARS = 1;
|
||||
localparam SBASEBALJ = 2;
|
||||
localparam SBASEBAL = 3;
|
||||
localparam SKYADVU = 4;
|
||||
localparam SKYSOLDR = 5;
|
||||
localparam TIMESOLD = 6;
|
||||
localparam GOLDMEDL = 7;
|
||||
localparam BATFIELD = 8;
|
||||
117
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/dual_port_ram.vhd
Normal file
117
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/dual_port_ram.vhd
Normal file
@@ -0,0 +1,117 @@
|
||||
-- __ __ __ __ __ __
|
||||
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
|
||||
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
|
||||
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
|
||||
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
|
||||
-- ______ ______ __ ______ ______ ______
|
||||
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
|
||||
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
|
||||
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
|
||||
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
|
||||
--
|
||||
-- https://joshbassett.info
|
||||
-- https://twitter.com/nullobject
|
||||
-- https://github.com/nullobject
|
||||
--
|
||||
-- Copyright (c) 2020 Josh Bassett
|
||||
--
|
||||
-- Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
-- of this software and associated documentation files (the "Software"), to deal
|
||||
-- in the Software without restriction, including without limitation the rights
|
||||
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
-- copies of the Software, and to permit persons to whom the Software is
|
||||
-- furnished to do so, subject to the following conditions:
|
||||
--
|
||||
-- The above copyright notice and this permission notice shall be included in all
|
||||
-- copies or substantial portions of the Software.
|
||||
--
|
||||
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
-- SOFTWARE.
|
||||
|
||||
-- 2022-05-24 Changed to use word count instead of address width
|
||||
-- and renamed ports to match quartus IP naming
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
--use work.common.all;
|
||||
use work.math.all;
|
||||
|
||||
library altera_mf;
|
||||
use altera_mf.altera_mf_components.all;
|
||||
|
||||
entity dual_port_ram is
|
||||
generic (
|
||||
LEN : natural := 8192;
|
||||
DATA_WIDTH : natural := 8
|
||||
);
|
||||
port (
|
||||
-- port A
|
||||
clock_a : in std_logic;
|
||||
address_a : in unsigned(ilog2(LEN)-1 downto 0);
|
||||
data_a : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
q_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
||||
wren_a : in std_logic := '0';
|
||||
|
||||
-- port B
|
||||
clock_b : in std_logic;
|
||||
address_b : in unsigned(ilog2(LEN)-1 downto 0);
|
||||
data_b : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
q_b : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
||||
wren_b : in std_logic := '0'
|
||||
);
|
||||
end dual_port_ram;
|
||||
|
||||
architecture arch of dual_port_ram is
|
||||
|
||||
begin
|
||||
altsyncram_component : altsyncram
|
||||
generic map (
|
||||
address_reg_b => "CLOCK1",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_input_b => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
clock_enable_output_b => "BYPASS",
|
||||
indata_reg_b => "CLOCK1",
|
||||
intended_device_family => "Cyclone V",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => LEN,
|
||||
numwords_b => LEN,
|
||||
operation_mode => "BIDIR_DUAL_PORT",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_aclr_b => "NONE",
|
||||
outdata_reg_a => "UNREGISTERED",
|
||||
outdata_reg_b => "UNREGISTERED",
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
|
||||
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
|
||||
width_a => DATA_WIDTH,
|
||||
width_b => DATA_WIDTH,
|
||||
width_byteena_a => 1,
|
||||
width_byteena_b => 1,
|
||||
widthad_a => ilog2(LEN),
|
||||
widthad_b => ilog2(LEN),
|
||||
wrcontrol_wraddress_reg_b => "CLOCK1"
|
||||
)
|
||||
port map (
|
||||
address_a => std_logic_vector(address_a),
|
||||
address_b => std_logic_vector(address_b),
|
||||
clock0 => clock_a,
|
||||
clock1 => clock_b,
|
||||
data_a => data_a,
|
||||
data_b => data_b,
|
||||
wren_a => wren_a,
|
||||
wren_b => wren_b,
|
||||
q_a => q_a,
|
||||
q_b => q_b
|
||||
);
|
||||
|
||||
|
||||
end architecture arch;
|
||||
72
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/math.vhd
Normal file
72
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/math.vhd
Normal file
@@ -0,0 +1,72 @@
|
||||
-- __ __ __ __ __ __
|
||||
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
|
||||
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
|
||||
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
|
||||
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
|
||||
-- ______ ______ __ ______ ______ ______
|
||||
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
|
||||
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
|
||||
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
|
||||
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
|
||||
--
|
||||
-- https://joshbassett.info
|
||||
-- https://twitter.com/nullobject
|
||||
-- https://github.com/nullobject
|
||||
--
|
||||
-- Copyright (c) 2020 Josh Bassett
|
||||
--
|
||||
-- Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
-- of this software and associated documentation files (the "Software"), to deal
|
||||
-- in the Software without restriction, including without limitation the rights
|
||||
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
-- copies of the Software, and to permit persons to whom the Software is
|
||||
-- furnished to do so, subject to the following conditions:
|
||||
--
|
||||
-- The above copyright notice and this permission notice shall be included in all
|
||||
-- copies or substantial portions of the Software.
|
||||
--
|
||||
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
-- SOFTWARE.
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
package math is
|
||||
-- calculates the log2 of the given number
|
||||
function ilog2(n : natural) return natural;
|
||||
|
||||
-- Masks the given range of bits for a vector.
|
||||
--
|
||||
-- Only the bits between the MSB and LSB (inclusive) will be kept, all other
|
||||
-- bits will be masked out.
|
||||
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector;
|
||||
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector;
|
||||
end package math;
|
||||
|
||||
package body math is
|
||||
function ilog2(n : natural) return natural is
|
||||
begin
|
||||
return natural(ceil(log2(real(n))));
|
||||
end ilog2;
|
||||
|
||||
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector is
|
||||
variable n : natural;
|
||||
variable mask : std_logic_vector(data'length-1 downto 0);
|
||||
begin
|
||||
n := (2**(msb-lsb+1))-1;
|
||||
mask := std_logic_vector(shift_left(to_unsigned(n, mask'length), lsb));
|
||||
return std_logic_vector(shift_right(unsigned(data AND mask), lsb));
|
||||
end mask_bits;
|
||||
|
||||
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector is
|
||||
begin
|
||||
return std_logic_vector(resize(unsigned(mask_bits(data, msb, lsb)), size));
|
||||
end mask_bits;
|
||||
end package body math;
|
||||
4
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/pll_mist.qip
Normal file
4
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/pll_mist.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_mist.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]
|
||||
309
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/pll_mist.v
Normal file
309
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/pll_mist.v
Normal file
@@ -0,0 +1,309 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll_mist.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2014 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll_mist (
|
||||
inclk0,
|
||||
c0,
|
||||
locked);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output locked;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire5 = 1'h0;
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire c0 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire sub_wire3 = inclk0;
|
||||
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire4),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.activeclock (),
|
||||
.areset (1'b0),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 3,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 8,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_mist",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_UNUSED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "72.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "72.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
449
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/sdram.sv
Normal file
449
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/sdram.sv
Normal file
@@ -0,0 +1,449 @@
|
||||
//
|
||||
// sdram.v
|
||||
//
|
||||
// sdram controller implementation for the MiST board
|
||||
// https://github.com/mist-devel/mist-board
|
||||
//
|
||||
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2019-2022 Gyorgy Szombathelyi
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
|
||||
module sdram (
|
||||
|
||||
// interface to the MT48LC16M16 chip
|
||||
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
|
||||
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
|
||||
output reg SDRAM_DQML, // two byte masks
|
||||
output reg SDRAM_DQMH, // two byte masks
|
||||
output reg [1:0] SDRAM_BA, // two banks
|
||||
output SDRAM_nCS, // a single chip select
|
||||
output SDRAM_nWE, // write enable
|
||||
output SDRAM_nRAS, // row address select
|
||||
output SDRAM_nCAS, // columns address select
|
||||
|
||||
// cpu/chipset interface
|
||||
input init_n, // init signal after FPGA config to initialize RAM
|
||||
input clk, // sdram clock
|
||||
|
||||
// 1st bank
|
||||
input port1_req,
|
||||
output reg port1_ack,
|
||||
input port1_we,
|
||||
input [23:1] port1_a,
|
||||
input [1:0] port1_ds,
|
||||
input [15:0] port1_d,
|
||||
output reg [15:0] port1_q,
|
||||
|
||||
// cpu1 rom/ram
|
||||
input [21:1] cpu1_rom_addr,
|
||||
input cpu1_rom_cs,
|
||||
output reg [15:0] cpu1_rom_q,
|
||||
output reg cpu1_rom_valid,
|
||||
|
||||
input cpu1_ram_req,
|
||||
output reg cpu1_ram_ack,
|
||||
input [21:1] cpu1_ram_addr,
|
||||
input cpu1_ram_we,
|
||||
input [1:0] cpu1_ram_ds,
|
||||
input [15:0] cpu1_ram_d,
|
||||
output reg [15:0] cpu1_ram_q,
|
||||
|
||||
// cpu2 rom
|
||||
input [21:1] cpu2_addr,
|
||||
input cpu2_rom_cs,
|
||||
output reg [15:0] cpu2_q,
|
||||
output reg cpu2_valid,
|
||||
// cpu3 rom
|
||||
input [21:1] cpu3_addr,
|
||||
input cpu3_rom_cs,
|
||||
output reg [15:0] cpu3_q,
|
||||
output reg cpu3_valid,
|
||||
// cpu4 rom
|
||||
input [21:1] cpu4_addr,
|
||||
input cpu4_rom_cs,
|
||||
output reg [15:0] cpu4_q,
|
||||
output reg cpu4_valid,
|
||||
|
||||
// 2nd bank
|
||||
input port2_req,
|
||||
output reg port2_ack,
|
||||
input port2_we,
|
||||
input [23:1] port2_a,
|
||||
input [1:0] port2_ds,
|
||||
input [15:0] port2_d,
|
||||
output reg [31:0] port2_q,
|
||||
|
||||
input [22:2] gfx1_addr,
|
||||
output reg [31:0] gfx1_q,
|
||||
input [22:2] gfx2_addr,
|
||||
output reg [31:0] gfx2_q,
|
||||
input [22:2] gfx3_addr,
|
||||
output reg [31:0] gfx3_q,
|
||||
|
||||
input [22:2] sp_addr,
|
||||
input sp_req,
|
||||
output reg sp_ack,
|
||||
output reg [31:0] sp_q
|
||||
);
|
||||
|
||||
parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
|
||||
|
||||
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
|
||||
localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
|
||||
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
|
||||
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
|
||||
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
|
||||
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
|
||||
|
||||
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
|
||||
|
||||
// 64ms/8192 rows = 7.8us
|
||||
localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// ------------------------ cycle state machine ------------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
/*
|
||||
SDRAM state machine for 2 bank interleaved access
|
||||
2 words burst, CL2
|
||||
cmd issued registered
|
||||
0 RAS0 cas1 - data0 read burst terminated
|
||||
1 ras0
|
||||
2 data1 returned
|
||||
3 CAS0 data1 returned
|
||||
4 RAS1 cas0
|
||||
5 ras1
|
||||
6 CAS1 data0 returned
|
||||
*/
|
||||
|
||||
localparam STATE_RAS0 = 3'd0; // first state in cycle
|
||||
localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
|
||||
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
|
||||
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
|
||||
localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
|
||||
localparam STATE_READ1 = 3'd3;
|
||||
localparam STATE_DS1b = 3'd0;
|
||||
localparam STATE_READ1b = 3'd4;
|
||||
localparam STATE_LAST = 3'd6;
|
||||
|
||||
reg [2:0] t;
|
||||
|
||||
always @(posedge clk) begin
|
||||
t <= t + 1'd1;
|
||||
if (t == STATE_LAST) t <= STATE_RAS0;
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// --------------------------- startup/reset ---------------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
|
||||
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
|
||||
reg [4:0] reset;
|
||||
reg init = 1'b1;
|
||||
always @(posedge clk, negedge init_n) begin
|
||||
if(!init_n) begin
|
||||
reset <= 5'h1f;
|
||||
init <= 1'b1;
|
||||
end else begin
|
||||
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
|
||||
init <= !(reset == 0);
|
||||
end
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// ------------------ generate ram control signals ---------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// all possible commands
|
||||
localparam CMD_INHIBIT = 4'b1111;
|
||||
localparam CMD_NOP = 4'b0111;
|
||||
localparam CMD_ACTIVE = 4'b0011;
|
||||
localparam CMD_READ = 4'b0101;
|
||||
localparam CMD_WRITE = 4'b0100;
|
||||
localparam CMD_BURST_TERMINATE = 4'b0110;
|
||||
localparam CMD_PRECHARGE = 4'b0010;
|
||||
localparam CMD_AUTO_REFRESH = 4'b0001;
|
||||
localparam CMD_LOAD_MODE = 4'b0000;
|
||||
|
||||
reg [3:0] sd_cmd; // current command sent to sd ram
|
||||
reg [15:0] sd_din;
|
||||
// drive control signals according to current command
|
||||
assign SDRAM_nCS = sd_cmd[3];
|
||||
assign SDRAM_nRAS = sd_cmd[2];
|
||||
assign SDRAM_nCAS = sd_cmd[1];
|
||||
assign SDRAM_nWE = sd_cmd[0];
|
||||
|
||||
reg [24:1] addr_latch[3];
|
||||
reg [24:1] addr_latch_next[2];
|
||||
reg [21:1] addr_last[1:5];
|
||||
reg [22:2] addr_last2[5];
|
||||
reg [15:0] din_next;
|
||||
reg [15:0] din_latch[2];
|
||||
reg oe_next;
|
||||
reg [1:0] oe_latch;
|
||||
reg we_next;
|
||||
reg [1:0] we_latch;
|
||||
reg [1:0] ds_next;
|
||||
reg [1:0] ds[2];
|
||||
|
||||
reg port1_state;
|
||||
reg port2_state;
|
||||
reg cpu1_ram_req_state;
|
||||
reg sp_state;
|
||||
|
||||
localparam PORT_NONE = 3'd0;
|
||||
localparam PORT_CPU1_ROM = 3'd1;
|
||||
localparam PORT_CPU1_RAM = 3'd2;
|
||||
localparam PORT_CPU2 = 3'd3;
|
||||
localparam PORT_CPU3 = 3'd4;
|
||||
localparam PORT_CPU4 = 3'd5;
|
||||
localparam PORT_GFX1 = 3'd1;
|
||||
localparam PORT_GFX2 = 3'd2;
|
||||
localparam PORT_GFX3 = 3'd3;
|
||||
localparam PORT_SP = 3'd4;
|
||||
localparam PORT_REQ = 3'd6;
|
||||
|
||||
reg [2:0] next_port[2];
|
||||
reg [2:0] port[2];
|
||||
|
||||
reg refresh;
|
||||
reg [10:0] refresh_cnt;
|
||||
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
|
||||
|
||||
// PORT1: bank 0,1
|
||||
always @(*) begin
|
||||
next_port[0] = PORT_NONE;
|
||||
addr_latch_next[0] = addr_latch[0];
|
||||
ds_next = 2'b00;
|
||||
{ oe_next, we_next } = 2'b00;
|
||||
din_next = 0;
|
||||
|
||||
if (refresh) begin
|
||||
// nothing
|
||||
end else if (port1_req ^ port1_state) begin
|
||||
next_port[0] = PORT_REQ;
|
||||
addr_latch_next[0] = { 1'b0, port1_a };
|
||||
ds_next = port1_ds;
|
||||
{ oe_next, we_next } = { ~port1_we, port1_we };
|
||||
din_next = port1_d;
|
||||
end else if (cpu2_addr != addr_last[PORT_CPU2] && cpu2_rom_cs) begin
|
||||
next_port[0] = PORT_CPU2;
|
||||
addr_latch_next[0] = { 3'd0, cpu2_addr };
|
||||
ds_next = 2'b11;
|
||||
{ oe_next, we_next } = 2'b10;
|
||||
end else if (/*cpu1_rom_addr != addr_last[PORT_CPU1_ROM] &&*/ cpu1_rom_cs && !cpu1_rom_valid) begin
|
||||
next_port[0] = PORT_CPU1_ROM;
|
||||
addr_latch_next[0] = { 3'd0, cpu1_rom_addr };
|
||||
ds_next = 2'b11;
|
||||
{ oe_next, we_next } = 2'b10;
|
||||
end else if (cpu1_ram_req ^ cpu1_ram_req_state) begin
|
||||
next_port[0] = PORT_CPU1_RAM;
|
||||
addr_latch_next[0] = { 2'b01, 1'b1, cpu1_ram_addr };
|
||||
ds_next = cpu1_ram_ds;
|
||||
{ oe_next, we_next } = { ~cpu1_ram_we, cpu1_ram_we };
|
||||
din_next = cpu1_ram_d;
|
||||
end else if (cpu3_addr != addr_last[PORT_CPU3] && cpu3_rom_cs) begin
|
||||
next_port[0] = PORT_CPU3;
|
||||
addr_latch_next[0] = { 3'd0, cpu3_addr };
|
||||
ds_next = 2'b11;
|
||||
{ oe_next, we_next } = 2'b10;
|
||||
end else if (cpu4_addr != addr_last[PORT_CPU4] && cpu4_rom_cs) begin
|
||||
next_port[0] = PORT_CPU4;
|
||||
addr_latch_next[0] = { 3'd0, cpu4_addr };
|
||||
ds_next = 2'b11;
|
||||
{ oe_next, we_next } = 2'b10;
|
||||
end
|
||||
end
|
||||
|
||||
// PORT1: bank 2,3
|
||||
always @(*) begin
|
||||
if (port2_req ^ port2_state) begin
|
||||
next_port[1] = PORT_REQ;
|
||||
addr_latch_next[1] = { 1'b1, port2_a };
|
||||
end else if (gfx1_addr != addr_last2[PORT_GFX1]) begin
|
||||
next_port[1] = PORT_GFX1;
|
||||
addr_latch_next[1] = { 2'b10, gfx1_addr, 1'b0 };
|
||||
end else if (gfx2_addr != addr_last2[PORT_GFX2]) begin
|
||||
next_port[1] = PORT_GFX2;
|
||||
addr_latch_next[1] = { 2'b10, gfx2_addr, 1'b0 };
|
||||
end else if (gfx3_addr != addr_last2[PORT_GFX3]) begin
|
||||
next_port[1] = PORT_GFX3;
|
||||
addr_latch_next[1] = { 2'b10, gfx3_addr, 1'b0 };
|
||||
end else if (sp_req ^ sp_state) begin
|
||||
next_port[1] = PORT_SP;
|
||||
addr_latch_next[1] = { 2'b10, sp_addr, 1'b0 };
|
||||
end else begin
|
||||
next_port[1] = PORT_NONE;
|
||||
addr_latch_next[1] = addr_latch[1];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
// permanently latch ram data to reduce delays
|
||||
sd_din <= SDRAM_DQ;
|
||||
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
|
||||
sd_cmd <= CMD_NOP; // default: idle
|
||||
refresh_cnt <= refresh_cnt + 1'd1;
|
||||
|
||||
if(init) begin
|
||||
{ cpu1_rom_valid, cpu2_valid, cpu3_valid, cpu4_valid } <= 0;
|
||||
// initialization takes place at the end of the reset phase
|
||||
if(t == STATE_RAS0) begin
|
||||
|
||||
if(reset == 15) begin
|
||||
sd_cmd <= CMD_PRECHARGE;
|
||||
SDRAM_A[10] <= 1'b1; // precharge all banks
|
||||
end
|
||||
|
||||
if(reset == 10 || reset == 8) begin
|
||||
sd_cmd <= CMD_AUTO_REFRESH;
|
||||
end
|
||||
|
||||
if(reset == 2) begin
|
||||
sd_cmd <= CMD_LOAD_MODE;
|
||||
SDRAM_A <= MODE;
|
||||
SDRAM_BA <= 2'b00;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
if (!cpu1_rom_cs) cpu1_rom_valid <= 0;
|
||||
if (cpu2_addr != addr_last[PORT_CPU2] && cpu2_rom_cs) cpu2_valid <= 0;
|
||||
if (cpu3_addr != addr_last[PORT_CPU3] && cpu3_rom_cs) cpu3_valid <= 0;
|
||||
if (cpu4_addr != addr_last[PORT_CPU4] && cpu4_rom_cs) cpu4_valid <= 0;
|
||||
|
||||
// RAS phase
|
||||
// bank 0,1
|
||||
if(t == STATE_RAS0) begin
|
||||
addr_latch[0] <= addr_latch_next[0];
|
||||
port[0] <= next_port[0];
|
||||
{ oe_latch[0], we_latch[0] } <= 2'b00;
|
||||
|
||||
if (next_port[0] != PORT_NONE) begin
|
||||
sd_cmd <= CMD_ACTIVE;
|
||||
SDRAM_A <= addr_latch_next[0][22:10];
|
||||
SDRAM_BA <= addr_latch_next[0][24:23];
|
||||
end
|
||||
addr_last[next_port[0]] <= addr_latch_next[0][21:1];
|
||||
ds[0] <= ds_next;
|
||||
{ oe_latch[0], we_latch[0] } <= { oe_next, we_next };
|
||||
din_latch[0] <= din_next;
|
||||
|
||||
if (next_port[0] == PORT_REQ) port1_state <= port1_req;
|
||||
if (next_port[0] == PORT_CPU1_RAM) cpu1_ram_req_state <= cpu1_ram_req;
|
||||
end
|
||||
|
||||
// bank 2,3
|
||||
if(t == STATE_RAS1) begin
|
||||
refresh <= 1'b0;
|
||||
addr_latch[1] <= addr_latch_next[1];
|
||||
{ oe_latch[1], we_latch[1] } <= 2'b00;
|
||||
port[1] <= next_port[1];
|
||||
|
||||
if (next_port[1] != PORT_NONE) begin
|
||||
sd_cmd <= CMD_ACTIVE;
|
||||
SDRAM_A <= addr_latch_next[1][22:10];
|
||||
SDRAM_BA <= addr_latch_next[1][24:23];
|
||||
addr_last2[next_port[1]] <= addr_latch_next[1][22:2];
|
||||
if (next_port[1] == PORT_REQ) begin
|
||||
{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
|
||||
ds[1] <= port2_ds;
|
||||
din_latch[1] <= port2_d;
|
||||
port2_state <= port2_req;
|
||||
end else begin
|
||||
{ oe_latch[1], we_latch[1] } <= 2'b10;
|
||||
ds[1] <= 2'b11;
|
||||
end
|
||||
end
|
||||
if (next_port[1] == PORT_SP) sp_state <= sp_req;
|
||||
|
||||
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
|
||||
refresh <= 1'b1;
|
||||
refresh_cnt <= 0;
|
||||
sd_cmd <= CMD_AUTO_REFRESH;
|
||||
end
|
||||
end
|
||||
|
||||
// CAS phase
|
||||
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
|
||||
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
|
||||
if (we_latch[0]) begin
|
||||
SDRAM_DQ <= din_latch[0];
|
||||
case(port[0])
|
||||
PORT_REQ: port1_ack <= port1_req;
|
||||
PORT_CPU1_RAM: cpu1_ram_ack <= cpu1_ram_req;
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
|
||||
SDRAM_BA <= addr_latch[0][24:23];
|
||||
end
|
||||
|
||||
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
|
||||
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
|
||||
if (we_latch[1]) begin
|
||||
SDRAM_DQ <= din_latch[1];
|
||||
port2_ack <= port2_req;
|
||||
end
|
||||
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
|
||||
SDRAM_BA <= addr_latch[1][24:23];
|
||||
end
|
||||
|
||||
// Data returned
|
||||
if(t == STATE_READ0 && oe_latch[0]) begin
|
||||
case(port[0])
|
||||
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
|
||||
PORT_CPU1_ROM: begin cpu1_rom_q <= sd_din; cpu1_rom_valid <= 1; end
|
||||
PORT_CPU1_RAM: begin cpu1_ram_q <= sd_din; cpu1_ram_ack <= cpu1_ram_req; end
|
||||
PORT_CPU2: begin cpu2_q <= sd_din; cpu2_valid <= 1; end
|
||||
PORT_CPU3: begin cpu3_q <= sd_din; cpu3_valid <= 1; end
|
||||
PORT_CPU4: begin cpu4_q <= sd_din; cpu4_valid <= 1; end
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
|
||||
if(t == STATE_READ1 && oe_latch[1]) begin
|
||||
case(port[1])
|
||||
PORT_REQ : port2_q[15:0] <= sd_din;
|
||||
PORT_GFX1 : gfx1_q[15:0] <= sd_din;
|
||||
PORT_GFX2 : gfx2_q[15:0] <= sd_din;
|
||||
PORT_GFX3 : gfx3_q[15:0] <= sd_din;
|
||||
PORT_SP : sp_q[15:0] <= sd_din;
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
|
||||
if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
|
||||
|
||||
if(t == STATE_READ1b && oe_latch[1]) begin
|
||||
case(port[1])
|
||||
PORT_REQ : begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
|
||||
PORT_GFX1 : begin gfx1_q[31:16] <= sd_din; end
|
||||
PORT_GFX2 : begin gfx2_q[31:16] <= sd_din; end
|
||||
PORT_GFX3 : begin gfx3_q[31:16] <= sd_din; end
|
||||
PORT_SP : begin sp_q[31:16] <= sd_din; sp_ack <= sp_req; end
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
99
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/video_timing.v
Normal file
99
Arcade_MiST/Alpha Densi M68000 Hardware/rtl/video_timing.v
Normal file
@@ -0,0 +1,99 @@
|
||||
|
||||
module video_timing
|
||||
(
|
||||
input clk,
|
||||
input clk_pix,
|
||||
input reset,
|
||||
|
||||
input signed [3:0] hs_offset,
|
||||
input signed [3:0] vs_offset,
|
||||
|
||||
input signed [3:0] hs_width,
|
||||
input signed [3:0] vs_width,
|
||||
input hbl_shift,
|
||||
|
||||
output [8:0] hc,
|
||||
output [8:0] vc,
|
||||
|
||||
output reg hsync,
|
||||
output reg vsync,
|
||||
|
||||
output reg hbl,
|
||||
output reg vbl
|
||||
);
|
||||
|
||||
wire [8:0] h_ofs = 0;
|
||||
wire [8:0] HBL_START = hbl_shift ? 9'd262 : 9'd266 ;
|
||||
wire [8:0] HBL_END = hbl_shift ? 9'd6 : 9'd10 ;
|
||||
wire [8:0] HS_START = HBL_START + 9'd41 + $signed(hs_offset);
|
||||
wire [8:0] HS_END = HBL_START + 9'd73 + $signed(hs_offset) + $signed(hs_width);
|
||||
wire [8:0] HTOTAL = 9'd383;
|
||||
|
||||
wire [8:0] v_ofs = 0;
|
||||
wire [8:0] VBL_START = 9'd240 ;
|
||||
wire [8:0] VBL_END = 9'd16 ;
|
||||
wire [8:0] VS_START = VBL_START + 9'd13 + $signed(vs_offset);
|
||||
wire [8:0] VS_END = VBL_START + 9'd21 + $signed(vs_offset) + $signed(vs_width);
|
||||
wire [8:0] VTOTAL = 9'd263 ;
|
||||
|
||||
|
||||
reg [8:0] v;
|
||||
reg [8:0] h;
|
||||
|
||||
assign vc = v - v_ofs;
|
||||
assign hc = h - h_ofs;
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (reset) begin
|
||||
h <= 0;
|
||||
v <= 0;
|
||||
|
||||
hbl <= 0;
|
||||
vbl <= 0;
|
||||
|
||||
hsync <= 0;
|
||||
vsync <= 0;
|
||||
end else if ( clk_pix == 1 ) begin
|
||||
// counter
|
||||
if (h == HTOTAL) begin
|
||||
h <= 0;
|
||||
v <= v + 1'd1;
|
||||
|
||||
if ( v == VTOTAL ) begin
|
||||
v <= 0;
|
||||
end
|
||||
end else begin
|
||||
h <= h + 1'd1;
|
||||
end
|
||||
|
||||
// h signals
|
||||
if ( h == HBL_START ) begin
|
||||
hbl <= 1;
|
||||
end else if ( h == HBL_END ) begin
|
||||
hbl <= 0;
|
||||
end
|
||||
|
||||
// v signals
|
||||
if ( v == VBL_START ) begin
|
||||
vbl <= 1;
|
||||
end else if ( v == VBL_END ) begin
|
||||
vbl <= 0;
|
||||
end
|
||||
|
||||
if ( v == (VS_START ) ) begin
|
||||
vsync <= 1;
|
||||
end else if ( v == (VS_END ) ) begin
|
||||
vsync <= 0;
|
||||
end
|
||||
|
||||
if ( h == (HS_START ) ) begin
|
||||
hsync <= 1;
|
||||
end else if ( h == (HS_END ) ) begin
|
||||
hsync <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
0
common/Sound/JT12/hdl/adpcm/gen_lingain.py
Normal file → Executable file
0
common/Sound/JT12/hdl/adpcm/gen_lingain.py
Normal file → Executable file
@@ -31,11 +31,7 @@ module jt10_adpcm(
|
||||
output signed [15:0] pcm
|
||||
);
|
||||
|
||||
localparam sigw = 13; // 1 bit more than the actual signal width so
|
||||
localparam shift = 3; //16-sigw;
|
||||
// there is room for overflow
|
||||
wire signed [sigw-1:0] max_pos = { 2'b00, {sigw-2{1'b1}} };
|
||||
wire signed [sigw-1:0] max_neg = { 2'b11, {sigw-2{1'b0}} };
|
||||
localparam sigw = 12;
|
||||
|
||||
reg signed [sigw-1:0] x1, x2, x3, x4, x5, x6;
|
||||
reg signed [sigw-1:0] inc4;
|
||||
@@ -44,13 +40,13 @@ reg [5:0] step_next, step_1p;
|
||||
reg sign2, sign3, sign4, sign5, xsign5;
|
||||
|
||||
// All outputs from stage 1
|
||||
assign pcm = { {16-sigw{x1[sigw-1]}}, x1 } <<< shift;
|
||||
assign pcm = { {16-sigw{x1[sigw-1]}}, x1 };
|
||||
|
||||
// This could be decomposed in more steps as the pipeline
|
||||
// has room for it
|
||||
always @(*) begin
|
||||
casez( data[2:0] )
|
||||
3'b0??: step_next = step1==6'd0 ? 6'd0 : (step1-6'd1);
|
||||
3'b0??: step_next = step1==6'd0 ? 6'd0 : (step1-1'd1);
|
||||
3'b100: step_next = step1+6'd2;
|
||||
3'b101: step_next = step1+6'd5;
|
||||
3'b110: step_next = step1+6'd7;
|
||||
@@ -93,9 +89,9 @@ always @( posedge clk or negedge rst_n )
|
||||
end else if(cen) begin
|
||||
// I
|
||||
sign2 <= data[3];
|
||||
x2 <= clr ? {sigw{1'b0}} : x1;
|
||||
x2 <= clr ? {sigw-1{1'b0}} : x1;
|
||||
step2 <= clr ? 6'd0 : (chon ? step_1p : step1);
|
||||
chon2 <= chon;
|
||||
chon2 <= ~clr && chon;
|
||||
lut_addr2 <= { step1, data[2:0] };
|
||||
// II 2's complement of inc2 if necessary
|
||||
sign3 <= sign2;
|
||||
@@ -103,30 +99,22 @@ always @( posedge clk or negedge rst_n )
|
||||
step3 <= step2;
|
||||
chon3 <= chon2;
|
||||
// III
|
||||
sign4 <= sign3;
|
||||
inc4 <= sign3 ? ~inc3_long + 1 : inc3_long;
|
||||
//sign4 <= sign3;
|
||||
inc4 <= sign3 ? ~inc3_long + 1'd1 : inc3_long;
|
||||
x4 <= x3;
|
||||
step4 <= step3;
|
||||
chon4 <= chon3;
|
||||
// IV
|
||||
sign5 <= sign4;
|
||||
xsign5 <= x4[sigw-1];
|
||||
//sign5 <= sign4;
|
||||
//xsign5 <= x4[sigw-1];
|
||||
x5 <= chon4 ? x4 + inc4 : x4;
|
||||
step5 <= step4;
|
||||
// V
|
||||
// if( xsign5!=x5[sigw-1] && sign5!=x5[sigw-1] ) begin // enable limiter
|
||||
// if( sign5 ) // it was negative
|
||||
// x6 <= {1'b1, {sigw-1{1'b0}}};
|
||||
// else // it was positive
|
||||
// x6 <= {1'b0, {sigw-1{1'b1}}};
|
||||
// end else
|
||||
x6 <= x5;
|
||||
if( x5 > max_pos) x6 <= max_pos;
|
||||
if( x5 < max_neg) x6 <= max_neg;
|
||||
step6 <= step5;
|
||||
// VI: close the loop
|
||||
x1 <= x6;
|
||||
step1 <= step6;
|
||||
end
|
||||
|
||||
endmodule // jt10_adpcm
|
||||
endmodule // jt10_adpcm
|
||||
|
||||
@@ -33,7 +33,7 @@ module jt10_adpcm_acc(
|
||||
|
||||
input en_sum,
|
||||
input signed [15:0] pcm_in, // 18.5 kHz
|
||||
output signed [15:0] pcm_out // 55.5 kHz
|
||||
output reg signed [15:0] pcm_out // 55.5 kHz
|
||||
);
|
||||
|
||||
wire signed [17:0] pcm_in_long = en_sum ? { {2{pcm_in[15]}}, pcm_in } : 18'd0;
|
||||
@@ -62,7 +62,7 @@ always @(posedge clk or negedge rst_n)
|
||||
last <= 18'd0;
|
||||
end else if(cen) begin
|
||||
if( match )
|
||||
acc <= en_ch[0] ? pcm_in_long : ( pcm_in_long + acc );
|
||||
acc <= cur_ch[0] ? pcm_in_long : ( pcm_in_long + acc );
|
||||
if( adv ) begin
|
||||
// step = diff * (1/4+1/16+1/64+1/128)
|
||||
step <= { {2{step_full[22]}}, step_full[22:7] }; // >>>7;
|
||||
|
||||
@@ -60,6 +60,7 @@ reg [5:0] done_sr, zero;
|
||||
reg roe_n1, decon1;
|
||||
|
||||
reg clr1, clr2, clr3, clr4, clr5, clr6;
|
||||
reg skip1, skip2, skip3, skip4, skip5, skip6;
|
||||
|
||||
// All outputs from stage 1
|
||||
assign addr_out = addr1[20:1];
|
||||
@@ -69,7 +70,8 @@ assign roe_n = roe_n1;
|
||||
assign clr = clr1;
|
||||
assign decon = decon1;
|
||||
|
||||
wire active5 = { cur_ch[1:0], cur_ch[5:2] } == en_ch;
|
||||
// Two cycles early: 0 0 1 1 2 2 3 3 4 4 5 5
|
||||
wire active5 = (en_ch[1] && cur_ch[4]) || (en_ch[2] && cur_ch[5]) || (en_ch[2] && cur_ch[0]) || (en_ch[3] && cur_ch[1]) || (en_ch[4] && cur_ch[2]) || (en_ch[5] && cur_ch[3]);//{ cur_ch[3:0], cur_ch[5:4] } == en_ch;
|
||||
wire sumup5 = on5 && !done5 && active5;
|
||||
reg sumup6;
|
||||
|
||||
@@ -103,8 +105,7 @@ wire [11:0] addr1_cmp = addr1[20:9];
|
||||
assign start_top = {bank1, start1};
|
||||
assign end_top = {bank1, end1};
|
||||
|
||||
reg [5:0] cur_ch, addr_ch_dec;
|
||||
reg [5:0] en_ch;
|
||||
reg [5:0] addr_ch_dec;
|
||||
|
||||
always @(*)
|
||||
case(addr_ch)
|
||||
@@ -128,13 +129,16 @@ always @(posedge clk or negedge rst_n)
|
||||
start4 <= 'd0; start5 <= 'd0; start6 <= 'd0;
|
||||
end1 <= 'd0; end2 <= 'd0; end3 <= 'd0;
|
||||
end4 <= 'd0; end5 <= 'd0; end6 <= 'd0;
|
||||
skip1 <= 'd0; skip2 <= 'd0; skip3 <= 'd0;
|
||||
skip4 <= 'd0; skip5 <= 'd0; skip6 <= 'd0;
|
||||
end else if( cen ) begin
|
||||
addr2 <= addr1;
|
||||
on2 <= aoff ? 1'b0 : (aon | on1);
|
||||
clr2 <= aoff || (aon && !on1); // Each time a A-ON is sent the address counter restarts
|
||||
on2 <= aoff ? 1'b0 : (aon | (on1 && ~done1));
|
||||
clr2 <= aoff || aon || done1; // Each time a A-ON is sent the address counter restarts
|
||||
start2 <= (up_start && up1) ? addr_in[11:0] : start1;
|
||||
end2 <= (up_end && up1) ? addr_in[11:0] : end1;
|
||||
bank2 <= ((up_end | up_start) && up1) ? addr_in[15:12] : bank1;
|
||||
bank2 <= (up_start && up1) ? addr_in[15:12] : bank1;
|
||||
skip2 <= skip1;
|
||||
|
||||
addr3 <= addr2; // clr2 ? {start2,9'd0} : addr2;
|
||||
on3 <= on2;
|
||||
@@ -142,6 +146,7 @@ always @(posedge clk or negedge rst_n)
|
||||
start3 <= start2;
|
||||
end3 <= end2;
|
||||
bank3 <= bank2;
|
||||
skip3 <= skip2;
|
||||
|
||||
addr4 <= addr3;
|
||||
on4 <= on3;
|
||||
@@ -149,14 +154,16 @@ always @(posedge clk or negedge rst_n)
|
||||
start4 <= start3;
|
||||
end4 <= end3;
|
||||
bank4 <= bank3;
|
||||
skip4 <= skip3;
|
||||
|
||||
addr5 <= addr4;
|
||||
on5 <= on4;
|
||||
clr5 <= clr4;
|
||||
done5 <= addr4[20:9] == end4; // && addr4[8:0]==~9'b0;
|
||||
done5 <= addr4[20:9] == end4 && addr4[8:0]==~9'b0 && ~(clr4 && on4);
|
||||
start5 <= start4;
|
||||
end5 <= end4;
|
||||
bank5 <= bank4;
|
||||
skip5 <= skip4;
|
||||
// V
|
||||
addr6 <= addr5;
|
||||
on6 <= on5;
|
||||
@@ -166,8 +173,9 @@ always @(posedge clk or negedge rst_n)
|
||||
end6 <= end5;
|
||||
bank6 <= bank5;
|
||||
sumup6 <= sumup5;
|
||||
skip6 <= skip5;
|
||||
|
||||
addr1 <= clr6 ? {start6,9'd0} : (sumup6 ? addr6+21'd1 :addr6);
|
||||
addr1 <= (clr6 && on6) ? {start6,9'd0} : (sumup6 && ~skip6 ? addr6+21'd1 :addr6);
|
||||
on1 <= on6;
|
||||
done1 <= done6;
|
||||
start1 <= start6;
|
||||
@@ -176,6 +184,7 @@ always @(posedge clk or negedge rst_n)
|
||||
decon1 <= sumup6;
|
||||
bank1 <= bank6;
|
||||
clr1 <= clr6;
|
||||
skip1 <= (clr6 && on6) ? 1'b1 : sumup6 ? 1'b0 : skip6;
|
||||
end
|
||||
|
||||
endmodule // jt10_adpcm_cnt
|
||||
|
||||
@@ -24,7 +24,7 @@
|
||||
module jt10_adpcm_dbrom(
|
||||
input clk, // CPU clock
|
||||
input [5:0] db,
|
||||
output [8:0] lin
|
||||
output reg [8:0] lin
|
||||
);
|
||||
|
||||
reg [8:0] mem[0:63];
|
||||
|
||||
@@ -44,8 +44,8 @@ always @(posedge clk or negedge rst_n)
|
||||
cycle <= 'd0;
|
||||
end else if(cen) begin
|
||||
if( start ) begin
|
||||
cycle <= {dw{1'd1}};
|
||||
r <= 'd0;
|
||||
cycle <= ~16'd0;
|
||||
r <= 16'd0;
|
||||
d <= a;
|
||||
end else if(cycle[0]) begin
|
||||
cycle <= { 1'b0, cycle[dw-1:1] };
|
||||
|
||||
@@ -28,7 +28,7 @@ module jt10_adpcm_drvA(
|
||||
|
||||
output [19:0] addr, // real hardware has 10 pins multiplexed through RMPX pin
|
||||
output [3:0] bank,
|
||||
output reg roe_n, // ADPCM-A ROM output enable
|
||||
output roe_n, // ADPCM-A ROM output enable
|
||||
|
||||
// Control Registers
|
||||
input [5:0] atl, // ADPCM Total Level
|
||||
@@ -49,8 +49,9 @@ module jt10_adpcm_drvA(
|
||||
output [5:0] flags,
|
||||
input [5:0] clr_flags,
|
||||
|
||||
output reg signed [15:0] pcm55_l,
|
||||
output reg signed [15:0] pcm55_r
|
||||
output signed [15:0] pcm55_l,
|
||||
output signed [15:0] pcm55_r,
|
||||
input [5:0] ch_enable
|
||||
);
|
||||
|
||||
/* verilator tracing_on */
|
||||
@@ -89,7 +90,7 @@ end
|
||||
reg match; // high when cur_ch==en_ch, but calculated one clock cycle ahead
|
||||
// so it can be latched
|
||||
wire [5:0] cur_next = { cur_ch[4:0], cur_ch[5] };
|
||||
wire [5:0] en_next = {en_ch[4:0], en_ch[5] };
|
||||
wire [5:0] en_next = { en_ch[0], en_ch[5:1] };
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
if( !rst_n ) begin
|
||||
@@ -190,7 +191,7 @@ jt10_adpcm_acc u_acc_left(
|
||||
.en_ch ( en_ch ),
|
||||
.match ( match ),
|
||||
// left/right enable
|
||||
.en_sum ( lr[1] ),
|
||||
.en_sum ( lr[1] && (ch_enable & cur_ch) ),
|
||||
|
||||
.pcm_in ( pcm_att ), // 18.5 kHz
|
||||
.pcm_out( pre_pcm55_l ) // 55.5 kHz
|
||||
@@ -205,7 +206,7 @@ jt10_adpcm_acc u_acc_right(
|
||||
.en_ch ( en_ch ),
|
||||
.match ( match ),
|
||||
// left/right enable
|
||||
.en_sum ( lr[0] ),
|
||||
.en_sum ( lr[0] && (ch_enable & cur_ch) ),
|
||||
|
||||
.pcm_in ( pcm_att ), // 18.5 kHz
|
||||
.pcm_out( pre_pcm55_r ) // 55.5 kHz
|
||||
|
||||
@@ -28,6 +28,7 @@ module jt10_adpcm_drvB(
|
||||
input acmd_on_b, // Control - Process start, Key On
|
||||
input acmd_rep_b, // Control - Repeat
|
||||
input acmd_rst_b, // Control - Reset
|
||||
input acmd_up_b, // Control - New command received
|
||||
input [ 1:0] alr_b, // Left / Right
|
||||
input [15:0] astart_b, // Start address
|
||||
input [15:0] aend_b, // End address
|
||||
@@ -38,7 +39,7 @@ module jt10_adpcm_drvB(
|
||||
// memory
|
||||
output [23:0] addr,
|
||||
input [ 7:0] data,
|
||||
output roe_n,
|
||||
output reg roe_n,
|
||||
|
||||
output reg signed [15:0] pcm55_l,
|
||||
output reg signed [15:0] pcm55_r
|
||||
@@ -46,6 +47,8 @@ module jt10_adpcm_drvB(
|
||||
|
||||
wire nibble_sel;
|
||||
wire adv; // advance to next reading
|
||||
wire clr_dec;
|
||||
wire chon;
|
||||
|
||||
// `ifdef SIMULATION
|
||||
// real fsample;
|
||||
@@ -57,13 +60,14 @@ wire adv; // advance to next reading
|
||||
// end
|
||||
// `endif
|
||||
|
||||
always @(posedge clk) roe_n <= ~adv;
|
||||
always @(posedge clk) roe_n <= ~(adv & cen55);
|
||||
|
||||
jt10_adpcmb_cnt u_cnt(
|
||||
.rst_n ( rst_n ),
|
||||
.clk ( clk ),
|
||||
.cen ( cen55 ),
|
||||
.delta_n ( adeltan_b ),
|
||||
.acmd_up_b ( acmd_up_b ),
|
||||
.clr ( acmd_rst_b ),
|
||||
.on ( acmd_on_b ),
|
||||
.astart ( astart_b ),
|
||||
@@ -72,8 +76,10 @@ jt10_adpcmb_cnt u_cnt(
|
||||
.addr ( addr ),
|
||||
.nibble_sel ( nibble_sel ),
|
||||
// Flag control
|
||||
.chon ( chon ),
|
||||
.clr_flag ( clr_flag ),
|
||||
.flag ( flag ),
|
||||
.clr_dec ( clr_dec ),
|
||||
.adv ( adv )
|
||||
);
|
||||
|
||||
@@ -89,7 +95,8 @@ jt10_adpcmb u_decoder(
|
||||
.cen ( cen ),
|
||||
.adv ( adv & cen55 ),
|
||||
.data ( din ),
|
||||
.chon ( acmd_on_b ),
|
||||
.chon ( chon ),
|
||||
.clr ( clr_dec ),
|
||||
.pcm ( pcmdec )
|
||||
);
|
||||
|
||||
@@ -98,7 +105,7 @@ jt10_adpcmb_interpol u_interpol(
|
||||
.rst_n ( rst_n ),
|
||||
.clk ( clk ),
|
||||
.cen ( cen ),
|
||||
.cen55 ( cen55 ),
|
||||
.cen55 ( cen55 && chon ),
|
||||
.adv ( adv ),
|
||||
.pcmdec ( pcmdec ),
|
||||
.pcmout ( pcminter )
|
||||
@@ -121,4 +128,4 @@ always @(posedge clk) if(cen55) begin
|
||||
pcm55_r <= alr_b[0] ? pcmgain : 16'd0;
|
||||
end
|
||||
|
||||
endmodule // jt10_adpcm_drvB
|
||||
endmodule // jt10_adpcm_drvB
|
||||
|
||||
@@ -50,7 +50,7 @@ always @(*)
|
||||
default: up_ch_dec = 6'd0;
|
||||
endcase
|
||||
|
||||
wire [5:0] en_ch2 = { en_ch[4:0], en_ch[5] }; // shift the bits to fit in the pipeline slot correctly
|
||||
//wire [5:0] en_ch2 = { en_ch[4:0], en_ch[5] }; // shift the bits to fit in the pipeline slot correctly
|
||||
|
||||
reg [6:0] db5;
|
||||
always @(*)
|
||||
@@ -91,7 +91,7 @@ always @(posedge clk or negedge rst_n)
|
||||
lracl4 <= lracl3;
|
||||
// IV: new data is accepted here
|
||||
lracl5 <= lracl4;
|
||||
db5 <= { 1'b0, ~lracl4[5:0] } + {1'b0, ~atl};
|
||||
db5 <= { 2'b0, ~lracl4[4:0] } + {1'b0, ~atl};
|
||||
// V
|
||||
lracl6 <= lracl5;
|
||||
lin6 <= lin_5b;
|
||||
@@ -147,7 +147,7 @@ always @(posedge clk or negedge rst_n)
|
||||
// III, shift by 0 or 1
|
||||
if( shcnt_mod3 ) begin
|
||||
pcm4 <= pcm3>>>1;
|
||||
shcnt4 <= shcnt3-1;
|
||||
shcnt4 <= shcnt3-1'd1;
|
||||
end else begin
|
||||
pcm4 <= pcm3;
|
||||
shcnt4 <= shcnt3;
|
||||
@@ -155,7 +155,7 @@ always @(posedge clk or negedge rst_n)
|
||||
// IV, shift by 0 or 1
|
||||
if( shcnt_mod4 ) begin
|
||||
pcm5 <= pcm4>>>1;
|
||||
shcnt5 <= shcnt4-1;
|
||||
shcnt5 <= shcnt4-1'd1;
|
||||
end else begin
|
||||
pcm5 <= pcm4;
|
||||
shcnt5 <= shcnt4;
|
||||
@@ -163,7 +163,7 @@ always @(posedge clk or negedge rst_n)
|
||||
// V, shift by 0 or 1
|
||||
if( shcnt_mod5 ) begin
|
||||
pcm6 <= pcm5>>>1;
|
||||
shcnt6 <= shcnt5-1;
|
||||
shcnt6 <= shcnt5-1'd1;
|
||||
end else begin
|
||||
pcm6 <= pcm5;
|
||||
shcnt6 <= shcnt5;
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* This file is part of JT12.
|
||||
|
||||
|
||||
|
||||
JT12 program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
@@ -19,6 +19,8 @@
|
||||
Date: 21-03-2019
|
||||
*/
|
||||
|
||||
//altera message_off 10030
|
||||
|
||||
// ADPCM-A uses a LUT because it is very sensitive to rounding
|
||||
// it looks like the original algorithm also used a table
|
||||
|
||||
@@ -33,107 +35,107 @@ module jt10_adpcma_lut(
|
||||
reg [11:0] lut[0:391];
|
||||
|
||||
initial begin
|
||||
lut[9'o00_0] = 12'd0002; lut[9'o00_1] = 12'd0006; lut[9'o00_2] = 12'd0012; lut[9'o00_3] = 12'd0016;
|
||||
lut[9'o00_4] = 12'd0022; lut[9'o00_5] = 12'd0026; lut[9'o00_6] = 12'd0032; lut[9'o00_7] = 12'd0036;
|
||||
lut[9'o01_0] = 12'd0002; lut[9'o01_1] = 12'd0006; lut[9'o01_2] = 12'd0012; lut[9'o01_3] = 12'd0016;
|
||||
lut[9'o01_4] = 12'd0023; lut[9'o01_5] = 12'd0027; lut[9'o01_6] = 12'd0033; lut[9'o01_7] = 12'd0037;
|
||||
lut[9'o02_0] = 12'd0002; lut[9'o02_1] = 12'd0007; lut[9'o02_2] = 12'd0013; lut[9'o02_3] = 12'd0020;
|
||||
lut[9'o02_4] = 12'd0025; lut[9'o02_5] = 12'd0032; lut[9'o02_6] = 12'd0036; lut[9'o02_7] = 12'd0043;
|
||||
lut[9'o03_0] = 12'd0002; lut[9'o03_1] = 12'd0007; lut[9'o03_2] = 12'd0015; lut[9'o03_3] = 12'd0022;
|
||||
lut[9'o03_4] = 12'd0027; lut[9'o03_5] = 12'd0034; lut[9'o03_6] = 12'd0042; lut[9'o03_7] = 12'd0047;
|
||||
lut[9'o04_0] = 12'd0002; lut[9'o04_1] = 12'd0010; lut[9'o04_2] = 12'd0016; lut[9'o04_3] = 12'd0024;
|
||||
lut[9'o04_4] = 12'd0031; lut[9'o04_5] = 12'd0037; lut[9'o04_6] = 12'd0045; lut[9'o04_7] = 12'd0053;
|
||||
lut[9'o05_0] = 12'd0003; lut[9'o05_1] = 12'd0011; lut[9'o05_2] = 12'd0017; lut[9'o05_3] = 12'd0025;
|
||||
lut[9'o05_4] = 12'd0034; lut[9'o05_5] = 12'd0042; lut[9'o05_6] = 12'd0050; lut[9'o05_7] = 12'd0056;
|
||||
lut[9'o06_0] = 12'd0003; lut[9'o06_1] = 12'd0012; lut[9'o06_2] = 12'd0021; lut[9'o06_3] = 12'd0030;
|
||||
lut[9'o06_4] = 12'd0037; lut[9'o06_5] = 12'd0046; lut[9'o06_6] = 12'd0055; lut[9'o06_7] = 12'd0064;
|
||||
lut[9'o07_0] = 12'd0003; lut[9'o07_1] = 12'd0013; lut[9'o07_2] = 12'd0023; lut[9'o07_3] = 12'd0033;
|
||||
lut[9'o07_4] = 12'd0042; lut[9'o07_5] = 12'd0052; lut[9'o07_6] = 12'd0062; lut[9'o07_7] = 12'd0072;
|
||||
lut[9'o10_0] = 12'd0004; lut[9'o10_1] = 12'd0014; lut[9'o10_2] = 12'd0025; lut[9'o10_3] = 12'd0035;
|
||||
lut[9'o10_4] = 12'd0046; lut[9'o10_5] = 12'd0056; lut[9'o10_6] = 12'd0067; lut[9'o10_7] = 12'd0077;
|
||||
lut[9'o11_0] = 12'd0004; lut[9'o11_1] = 12'd0015; lut[9'o11_2] = 12'd0027; lut[9'o11_3] = 12'd0040;
|
||||
lut[9'o11_4] = 12'd0051; lut[9'o11_5] = 12'd0062; lut[9'o11_6] = 12'd0074; lut[9'o11_7] = 12'd0105;
|
||||
lut[9'o12_0] = 12'd0005; lut[9'o12_1] = 12'd0017; lut[9'o12_2] = 12'd0031; lut[9'o12_3] = 12'd0043;
|
||||
lut[9'o12_4] = 12'd0056; lut[9'o12_5] = 12'd0070; lut[9'o12_6] = 12'd0102; lut[9'o12_7] = 12'd0114;
|
||||
lut[9'o13_0] = 12'd0005; lut[9'o13_1] = 12'd0020; lut[9'o13_2] = 12'd0034; lut[9'o13_3] = 12'd0047;
|
||||
lut[9'o13_4] = 12'd0062; lut[9'o13_5] = 12'd0075; lut[9'o13_6] = 12'd0111; lut[9'o13_7] = 12'd0124;
|
||||
lut[9'o14_0] = 12'd0006; lut[9'o14_1] = 12'd0022; lut[9'o14_2] = 12'd0037; lut[9'o14_3] = 12'd0053;
|
||||
lut[9'o14_4] = 12'd0070; lut[9'o14_5] = 12'd0104; lut[9'o14_6] = 12'd0121; lut[9'o14_7] = 12'd0135;
|
||||
lut[9'o15_0] = 12'd0006; lut[9'o15_1] = 12'd0024; lut[9'o15_2] = 12'd0042; lut[9'o15_3] = 12'd0060;
|
||||
lut[9'o15_4] = 12'd0075; lut[9'o15_5] = 12'd0113; lut[9'o15_6] = 12'd0131; lut[9'o15_7] = 12'd0147;
|
||||
lut[9'o16_0] = 12'd0007; lut[9'o16_1] = 12'd0026; lut[9'o16_2] = 12'd0045; lut[9'o16_3] = 12'd0064;
|
||||
lut[9'o16_4] = 12'd0103; lut[9'o16_5] = 12'd0122; lut[9'o16_6] = 12'd0141; lut[9'o16_7] = 12'd0160;
|
||||
lut[9'o17_0] = 12'd0010; lut[9'o17_1] = 12'd0030; lut[9'o17_2] = 12'd0051; lut[9'o17_3] = 12'd0071;
|
||||
lut[9'o17_4] = 12'd0112; lut[9'o17_5] = 12'd0132; lut[9'o17_6] = 12'd0153; lut[9'o17_7] = 12'd0173;
|
||||
lut[9'o20_0] = 12'd0011; lut[9'o20_1] = 12'd0033; lut[9'o20_2] = 12'd0055; lut[9'o20_3] = 12'd0077;
|
||||
lut[9'o20_4] = 12'd0122; lut[9'o20_5] = 12'd0144; lut[9'o20_6] = 12'd0166; lut[9'o20_7] = 12'd0210;
|
||||
lut[9'o21_0] = 12'd0012; lut[9'o21_1] = 12'd0036; lut[9'o21_2] = 12'd0062; lut[9'o21_3] = 12'd0106;
|
||||
lut[9'o21_4] = 12'd0132; lut[9'o21_5] = 12'd0156; lut[9'o21_6] = 12'd0202; lut[9'o21_7] = 12'd0226;
|
||||
lut[9'o22_0] = 12'd0013; lut[9'o22_1] = 12'd0041; lut[9'o22_2] = 12'd0067; lut[9'o22_3] = 12'd0115;
|
||||
lut[9'o22_4] = 12'd0143; lut[9'o22_5] = 12'd0171; lut[9'o22_6] = 12'd0217; lut[9'o22_7] = 12'd0245;
|
||||
lut[9'o23_0] = 12'd0014; lut[9'o23_1] = 12'd0044; lut[9'o23_2] = 12'd0074; lut[9'o23_3] = 12'd0124;
|
||||
lut[9'o23_4] = 12'd0155; lut[9'o23_5] = 12'd0205; lut[9'o23_6] = 12'd0235; lut[9'o23_7] = 12'd0265;
|
||||
lut[9'o24_0] = 12'd0015; lut[9'o24_1] = 12'd0050; lut[9'o24_2] = 12'd0102; lut[9'o24_3] = 12'd0135;
|
||||
lut[9'o24_4] = 12'd0170; lut[9'o24_5] = 12'd0223; lut[9'o24_6] = 12'd0255; lut[9'o24_7] = 12'd0310;
|
||||
lut[9'o25_0] = 12'd0016; lut[9'o25_1] = 12'd0054; lut[9'o25_2] = 12'd0111; lut[9'o25_3] = 12'd0147;
|
||||
lut[9'o25_4] = 12'd0204; lut[9'o25_5] = 12'd0242; lut[9'o25_6] = 12'd0277; lut[9'o25_7] = 12'd0335;
|
||||
lut[9'o26_0] = 12'd0020; lut[9'o26_1] = 12'd0060; lut[9'o26_2] = 12'd0121; lut[9'o26_3] = 12'd0161;
|
||||
lut[9'o26_4] = 12'd0222; lut[9'o26_5] = 12'd0262; lut[9'o26_6] = 12'd0323; lut[9'o26_7] = 12'd0363;
|
||||
lut[9'o27_0] = 12'd0021; lut[9'o27_1] = 12'd0065; lut[9'o27_2] = 12'd0131; lut[9'o27_3] = 12'd0175;
|
||||
lut[9'o27_4] = 12'd0240; lut[9'o27_5] = 12'd0304; lut[9'o27_6] = 12'd0350; lut[9'o27_7] = 12'd0414;
|
||||
lut[9'o30_0] = 12'd0023; lut[9'o30_1] = 12'd0072; lut[9'o30_2] = 12'd0142; lut[9'o30_3] = 12'd0211;
|
||||
lut[9'o30_4] = 12'd0260; lut[9'o30_5] = 12'd0327; lut[9'o30_6] = 12'd0377; lut[9'o30_7] = 12'd0446;
|
||||
lut[9'o31_0] = 12'd0025; lut[9'o31_1] = 12'd0100; lut[9'o31_2] = 12'd0154; lut[9'o31_3] = 12'd0227;
|
||||
lut[9'o31_4] = 12'd0302; lut[9'o31_5] = 12'd0355; lut[9'o31_6] = 12'd0431; lut[9'o31_7] = 12'd0504;
|
||||
lut[9'o32_0] = 12'd0027; lut[9'o32_1] = 12'd0107; lut[9'o32_2] = 12'd0166; lut[9'o32_3] = 12'd0246;
|
||||
lut[9'o32_4] = 12'd0325; lut[9'o32_5] = 12'd0405; lut[9'o32_6] = 12'd0464; lut[9'o32_7] = 12'd0544;
|
||||
lut[9'o33_0] = 12'd0032; lut[9'o33_1] = 12'd0116; lut[9'o33_2] = 12'd0202; lut[9'o33_3] = 12'd0266;
|
||||
lut[9'o33_4] = 12'd0353; lut[9'o33_5] = 12'd0437; lut[9'o33_6] = 12'd0523; lut[9'o33_7] = 12'd0607;
|
||||
lut[9'o34_0] = 12'd0034; lut[9'o34_1] = 12'd0126; lut[9'o34_2] = 12'd0217; lut[9'o34_3] = 12'd0311;
|
||||
lut[9'o34_4] = 12'd0402; lut[9'o34_5] = 12'd0474; lut[9'o34_6] = 12'd0565; lut[9'o34_7] = 12'd0657;
|
||||
lut[9'o35_0] = 12'd0037; lut[9'o35_1] = 12'd0136; lut[9'o35_2] = 12'd0236; lut[9'o35_3] = 12'd0335;
|
||||
lut[9'o35_4] = 12'd0434; lut[9'o35_5] = 12'd0533; lut[9'o35_6] = 12'd0633; lut[9'o35_7] = 12'd0732;
|
||||
lut[9'o36_0] = 12'd0042; lut[9'o36_1] = 12'd0150; lut[9'o36_2] = 12'd0256; lut[9'o36_3] = 12'd0364;
|
||||
lut[9'o36_4] = 12'd0471; lut[9'o36_5] = 12'd0577; lut[9'o36_6] = 12'd0705; lut[9'o36_7] = 12'd1013;
|
||||
lut[9'o37_0] = 12'd0046; lut[9'o37_1] = 12'd0163; lut[9'o37_2] = 12'd0277; lut[9'o37_3] = 12'd0414;
|
||||
lut[9'o37_4] = 12'd0531; lut[9'o37_5] = 12'd0646; lut[9'o37_6] = 12'd0762; lut[9'o37_7] = 12'd1077;
|
||||
lut[9'o40_0] = 12'd0052; lut[9'o40_1] = 12'd0176; lut[9'o40_2] = 12'd0322; lut[9'o40_3] = 12'd0446;
|
||||
lut[9'o40_4] = 12'd0573; lut[9'o40_5] = 12'd0717; lut[9'o40_6] = 12'd1043; lut[9'o40_7] = 12'd1167;
|
||||
lut[9'o41_0] = 12'd0056; lut[9'o41_1] = 12'd0213; lut[9'o41_2] = 12'd0347; lut[9'o41_3] = 12'd0504;
|
||||
lut[9'o41_4] = 12'd0641; lut[9'o41_5] = 12'd0776; lut[9'o41_6] = 12'd1132; lut[9'o41_7] = 12'd1267;
|
||||
lut[9'o42_0] = 12'd0063; lut[9'o42_1] = 12'd0231; lut[9'o42_2] = 12'd0377; lut[9'o42_3] = 12'd0545;
|
||||
lut[9'o42_4] = 12'd0713; lut[9'o42_5] = 12'd1061; lut[9'o42_6] = 12'd1227; lut[9'o42_7] = 12'd1375;
|
||||
lut[9'o43_0] = 12'd0070; lut[9'o43_1] = 12'd0250; lut[9'o43_2] = 12'd0430; lut[9'o43_3] = 12'd0610;
|
||||
lut[9'o43_4] = 12'd0771; lut[9'o43_5] = 12'd1151; lut[9'o43_6] = 12'd1331; lut[9'o43_7] = 12'd1511;
|
||||
lut[9'o44_0] = 12'd0075; lut[9'o44_1] = 12'd0271; lut[9'o44_2] = 12'd0464; lut[9'o44_3] = 12'd0660;
|
||||
lut[9'o44_4] = 12'd1053; lut[9'o44_5] = 12'd1247; lut[9'o44_6] = 12'd1442; lut[9'o44_7] = 12'd1636;
|
||||
lut[9'o45_0] = 12'd0104; lut[9'o45_1] = 12'd0314; lut[9'o45_2] = 12'd0524; lut[9'o45_3] = 12'd0734;
|
||||
lut[9'o45_4] = 12'd1144; lut[9'o45_5] = 12'd1354; lut[9'o45_6] = 12'd1564; lut[9'o45_7] = 12'd1774;
|
||||
lut[9'o46_0] = 12'd0112; lut[9'o46_1] = 12'd0340; lut[9'o46_2] = 12'd0565; lut[9'o46_3] = 12'd1013;
|
||||
lut[9'o46_4] = 12'd1240; lut[9'o46_5] = 12'd1466; lut[9'o46_6] = 12'd1713; lut[9'o46_7] = 12'd2141;
|
||||
lut[9'o47_0] = 12'd0122; lut[9'o47_1] = 12'd0366; lut[9'o47_2] = 12'd0633; lut[9'o47_3] = 12'd1077;
|
||||
lut[9'o47_4] = 12'd1344; lut[9'o47_5] = 12'd1610; lut[9'o47_6] = 12'd2055; lut[9'o47_7] = 12'd2321;
|
||||
lut[9'o50_0] = 12'd0132; lut[9'o50_1] = 12'd0417; lut[9'o50_2] = 12'd0704; lut[9'o50_3] = 12'd1171;
|
||||
lut[9'o50_4] = 12'd1456; lut[9'o50_5] = 12'd1743; lut[9'o50_6] = 12'd2230; lut[9'o50_7] = 12'd2515;
|
||||
lut[9'o51_0] = 12'd0143; lut[9'o51_1] = 12'd0452; lut[9'o51_2] = 12'd0761; lut[9'o51_3] = 12'd1270;
|
||||
lut[9'o51_4] = 12'd1577; lut[9'o51_5] = 12'd2106; lut[9'o51_6] = 12'd2415; lut[9'o51_7] = 12'd2724;
|
||||
lut[9'o52_0] = 12'd0155; lut[9'o52_1] = 12'd0510; lut[9'o52_2] = 12'd1043; lut[9'o52_3] = 12'd1376;
|
||||
lut[9'o52_4] = 12'd1731; lut[9'o52_5] = 12'd2264; lut[9'o52_6] = 12'd2617; lut[9'o52_7] = 12'd3152;
|
||||
lut[9'o53_0] = 12'd0170; lut[9'o53_1] = 12'd0551; lut[9'o53_2] = 12'd1131; lut[9'o53_3] = 12'd1512;
|
||||
lut[9'o53_4] = 12'd2073; lut[9'o53_5] = 12'd2454; lut[9'o53_6] = 12'd3034; lut[9'o53_7] = 12'd3415;
|
||||
lut[9'o54_0] = 12'd0204; lut[9'o54_1] = 12'd0615; lut[9'o54_2] = 12'd1226; lut[9'o54_3] = 12'd1637;
|
||||
lut[9'o54_4] = 12'd2250; lut[9'o54_5] = 12'd2661; lut[9'o54_6] = 12'd3272; lut[9'o54_7] = 12'd3703;
|
||||
lut[9'o55_0] = 12'd0221; lut[9'o55_1] = 12'd0665; lut[9'o55_2] = 12'd1330; lut[9'o55_3] = 12'd1774;
|
||||
lut[9'o55_4] = 12'd2437; lut[9'o55_5] = 12'd3103; lut[9'o55_6] = 12'd3546; lut[9'o55_7] = 12'd3777;
|
||||
lut[9'o56_0] = 12'd0240; lut[9'o56_1] = 12'd0740; lut[9'o56_2] = 12'd1441; lut[9'o56_3] = 12'd2141;
|
||||
lut[9'o56_4] = 12'd2642; lut[9'o56_5] = 12'd3342; lut[9'o56_6] = 12'd3777; lut[9'o56_7] = 12'd3777;
|
||||
lut[9'o57_0] = 12'd0260; lut[9'o57_1] = 12'd1021; lut[9'o57_2] = 12'd1561; lut[9'o57_3] = 12'd2322;
|
||||
lut[9'o57_4] = 12'd3063; lut[9'o57_5] = 12'd3624; lut[9'o57_6] = 12'd3777; lut[9'o57_7] = 12'd3777;
|
||||
lut[9'o60_0] = 12'd0302; lut[9'o60_1] = 12'd1106; lut[9'o60_2] = 12'd1712; lut[9'o60_3] = 12'd2516;
|
||||
lut[9'o60_4] = 12'd3322; lut[9'o60_5] = 12'd3777; lut[9'o60_6] = 12'd3777; lut[9'o60_7] = 12'd3777;
|
||||
lut[9'o00_0] = 12'o0002; lut[9'o00_1] = 12'o0006; lut[9'o00_2] = 12'o0012; lut[9'o00_3] = 12'o0016;
|
||||
lut[9'o00_4] = 12'o0022; lut[9'o00_5] = 12'o0026; lut[9'o00_6] = 12'o0032; lut[9'o00_7] = 12'o0036;
|
||||
lut[9'o01_0] = 12'o0002; lut[9'o01_1] = 12'o0006; lut[9'o01_2] = 12'o0012; lut[9'o01_3] = 12'o0016;
|
||||
lut[9'o01_4] = 12'o0023; lut[9'o01_5] = 12'o0027; lut[9'o01_6] = 12'o0033; lut[9'o01_7] = 12'o0037;
|
||||
lut[9'o02_0] = 12'o0002; lut[9'o02_1] = 12'o0007; lut[9'o02_2] = 12'o0013; lut[9'o02_3] = 12'o0020;
|
||||
lut[9'o02_4] = 12'o0025; lut[9'o02_5] = 12'o0032; lut[9'o02_6] = 12'o0036; lut[9'o02_7] = 12'o0043;
|
||||
lut[9'o03_0] = 12'o0002; lut[9'o03_1] = 12'o0007; lut[9'o03_2] = 12'o0015; lut[9'o03_3] = 12'o0022;
|
||||
lut[9'o03_4] = 12'o0027; lut[9'o03_5] = 12'o0034; lut[9'o03_6] = 12'o0042; lut[9'o03_7] = 12'o0047;
|
||||
lut[9'o04_0] = 12'o0002; lut[9'o04_1] = 12'o0010; lut[9'o04_2] = 12'o0016; lut[9'o04_3] = 12'o0024;
|
||||
lut[9'o04_4] = 12'o0031; lut[9'o04_5] = 12'o0037; lut[9'o04_6] = 12'o0045; lut[9'o04_7] = 12'o0053;
|
||||
lut[9'o05_0] = 12'o0003; lut[9'o05_1] = 12'o0011; lut[9'o05_2] = 12'o0017; lut[9'o05_3] = 12'o0025;
|
||||
lut[9'o05_4] = 12'o0034; lut[9'o05_5] = 12'o0042; lut[9'o05_6] = 12'o0050; lut[9'o05_7] = 12'o0056;
|
||||
lut[9'o06_0] = 12'o0003; lut[9'o06_1] = 12'o0012; lut[9'o06_2] = 12'o0021; lut[9'o06_3] = 12'o0030;
|
||||
lut[9'o06_4] = 12'o0037; lut[9'o06_5] = 12'o0046; lut[9'o06_6] = 12'o0055; lut[9'o06_7] = 12'o0064;
|
||||
lut[9'o07_0] = 12'o0003; lut[9'o07_1] = 12'o0013; lut[9'o07_2] = 12'o0023; lut[9'o07_3] = 12'o0033;
|
||||
lut[9'o07_4] = 12'o0042; lut[9'o07_5] = 12'o0052; lut[9'o07_6] = 12'o0062; lut[9'o07_7] = 12'o0072;
|
||||
lut[9'o10_0] = 12'o0004; lut[9'o10_1] = 12'o0014; lut[9'o10_2] = 12'o0025; lut[9'o10_3] = 12'o0035;
|
||||
lut[9'o10_4] = 12'o0046; lut[9'o10_5] = 12'o0056; lut[9'o10_6] = 12'o0067; lut[9'o10_7] = 12'o0077;
|
||||
lut[9'o11_0] = 12'o0004; lut[9'o11_1] = 12'o0015; lut[9'o11_2] = 12'o0027; lut[9'o11_3] = 12'o0040;
|
||||
lut[9'o11_4] = 12'o0051; lut[9'o11_5] = 12'o0062; lut[9'o11_6] = 12'o0074; lut[9'o11_7] = 12'o0105;
|
||||
lut[9'o12_0] = 12'o0005; lut[9'o12_1] = 12'o0017; lut[9'o12_2] = 12'o0031; lut[9'o12_3] = 12'o0043;
|
||||
lut[9'o12_4] = 12'o0056; lut[9'o12_5] = 12'o0070; lut[9'o12_6] = 12'o0102; lut[9'o12_7] = 12'o0114;
|
||||
lut[9'o13_0] = 12'o0005; lut[9'o13_1] = 12'o0020; lut[9'o13_2] = 12'o0034; lut[9'o13_3] = 12'o0047;
|
||||
lut[9'o13_4] = 12'o0062; lut[9'o13_5] = 12'o0075; lut[9'o13_6] = 12'o0111; lut[9'o13_7] = 12'o0124;
|
||||
lut[9'o14_0] = 12'o0006; lut[9'o14_1] = 12'o0022; lut[9'o14_2] = 12'o0037; lut[9'o14_3] = 12'o0053;
|
||||
lut[9'o14_4] = 12'o0070; lut[9'o14_5] = 12'o0104; lut[9'o14_6] = 12'o0121; lut[9'o14_7] = 12'o0135;
|
||||
lut[9'o15_0] = 12'o0006; lut[9'o15_1] = 12'o0024; lut[9'o15_2] = 12'o0042; lut[9'o15_3] = 12'o0060;
|
||||
lut[9'o15_4] = 12'o0075; lut[9'o15_5] = 12'o0113; lut[9'o15_6] = 12'o0131; lut[9'o15_7] = 12'o0147;
|
||||
lut[9'o16_0] = 12'o0007; lut[9'o16_1] = 12'o0026; lut[9'o16_2] = 12'o0045; lut[9'o16_3] = 12'o0064;
|
||||
lut[9'o16_4] = 12'o0103; lut[9'o16_5] = 12'o0122; lut[9'o16_6] = 12'o0141; lut[9'o16_7] = 12'o0160;
|
||||
lut[9'o17_0] = 12'o0010; lut[9'o17_1] = 12'o0030; lut[9'o17_2] = 12'o0051; lut[9'o17_3] = 12'o0071;
|
||||
lut[9'o17_4] = 12'o0112; lut[9'o17_5] = 12'o0132; lut[9'o17_6] = 12'o0153; lut[9'o17_7] = 12'o0173;
|
||||
lut[9'o20_0] = 12'o0011; lut[9'o20_1] = 12'o0033; lut[9'o20_2] = 12'o0055; lut[9'o20_3] = 12'o0077;
|
||||
lut[9'o20_4] = 12'o0122; lut[9'o20_5] = 12'o0144; lut[9'o20_6] = 12'o0166; lut[9'o20_7] = 12'o0210;
|
||||
lut[9'o21_0] = 12'o0012; lut[9'o21_1] = 12'o0036; lut[9'o21_2] = 12'o0062; lut[9'o21_3] = 12'o0106;
|
||||
lut[9'o21_4] = 12'o0132; lut[9'o21_5] = 12'o0156; lut[9'o21_6] = 12'o0202; lut[9'o21_7] = 12'o0226;
|
||||
lut[9'o22_0] = 12'o0013; lut[9'o22_1] = 12'o0041; lut[9'o22_2] = 12'o0067; lut[9'o22_3] = 12'o0115;
|
||||
lut[9'o22_4] = 12'o0143; lut[9'o22_5] = 12'o0171; lut[9'o22_6] = 12'o0217; lut[9'o22_7] = 12'o0245;
|
||||
lut[9'o23_0] = 12'o0014; lut[9'o23_1] = 12'o0044; lut[9'o23_2] = 12'o0074; lut[9'o23_3] = 12'o0124;
|
||||
lut[9'o23_4] = 12'o0155; lut[9'o23_5] = 12'o0205; lut[9'o23_6] = 12'o0235; lut[9'o23_7] = 12'o0265;
|
||||
lut[9'o24_0] = 12'o0015; lut[9'o24_1] = 12'o0050; lut[9'o24_2] = 12'o0102; lut[9'o24_3] = 12'o0135;
|
||||
lut[9'o24_4] = 12'o0170; lut[9'o24_5] = 12'o0223; lut[9'o24_6] = 12'o0255; lut[9'o24_7] = 12'o0310;
|
||||
lut[9'o25_0] = 12'o0016; lut[9'o25_1] = 12'o0054; lut[9'o25_2] = 12'o0111; lut[9'o25_3] = 12'o0147;
|
||||
lut[9'o25_4] = 12'o0204; lut[9'o25_5] = 12'o0242; lut[9'o25_6] = 12'o0277; lut[9'o25_7] = 12'o0335;
|
||||
lut[9'o26_0] = 12'o0020; lut[9'o26_1] = 12'o0060; lut[9'o26_2] = 12'o0121; lut[9'o26_3] = 12'o0161;
|
||||
lut[9'o26_4] = 12'o0222; lut[9'o26_5] = 12'o0262; lut[9'o26_6] = 12'o0323; lut[9'o26_7] = 12'o0363;
|
||||
lut[9'o27_0] = 12'o0021; lut[9'o27_1] = 12'o0065; lut[9'o27_2] = 12'o0131; lut[9'o27_3] = 12'o0175;
|
||||
lut[9'o27_4] = 12'o0240; lut[9'o27_5] = 12'o0304; lut[9'o27_6] = 12'o0350; lut[9'o27_7] = 12'o0414;
|
||||
lut[9'o30_0] = 12'o0023; lut[9'o30_1] = 12'o0072; lut[9'o30_2] = 12'o0142; lut[9'o30_3] = 12'o0211;
|
||||
lut[9'o30_4] = 12'o0260; lut[9'o30_5] = 12'o0327; lut[9'o30_6] = 12'o0377; lut[9'o30_7] = 12'o0446;
|
||||
lut[9'o31_0] = 12'o0025; lut[9'o31_1] = 12'o0100; lut[9'o31_2] = 12'o0154; lut[9'o31_3] = 12'o0227;
|
||||
lut[9'o31_4] = 12'o0302; lut[9'o31_5] = 12'o0355; lut[9'o31_6] = 12'o0431; lut[9'o31_7] = 12'o0504;
|
||||
lut[9'o32_0] = 12'o0027; lut[9'o32_1] = 12'o0107; lut[9'o32_2] = 12'o0166; lut[9'o32_3] = 12'o0246;
|
||||
lut[9'o32_4] = 12'o0325; lut[9'o32_5] = 12'o0405; lut[9'o32_6] = 12'o0464; lut[9'o32_7] = 12'o0544;
|
||||
lut[9'o33_0] = 12'o0032; lut[9'o33_1] = 12'o0116; lut[9'o33_2] = 12'o0202; lut[9'o33_3] = 12'o0266;
|
||||
lut[9'o33_4] = 12'o0353; lut[9'o33_5] = 12'o0437; lut[9'o33_6] = 12'o0523; lut[9'o33_7] = 12'o0607;
|
||||
lut[9'o34_0] = 12'o0034; lut[9'o34_1] = 12'o0126; lut[9'o34_2] = 12'o0217; lut[9'o34_3] = 12'o0311;
|
||||
lut[9'o34_4] = 12'o0402; lut[9'o34_5] = 12'o0474; lut[9'o34_6] = 12'o0565; lut[9'o34_7] = 12'o0657;
|
||||
lut[9'o35_0] = 12'o0037; lut[9'o35_1] = 12'o0136; lut[9'o35_2] = 12'o0236; lut[9'o35_3] = 12'o0335;
|
||||
lut[9'o35_4] = 12'o0434; lut[9'o35_5] = 12'o0533; lut[9'o35_6] = 12'o0633; lut[9'o35_7] = 12'o0732;
|
||||
lut[9'o36_0] = 12'o0042; lut[9'o36_1] = 12'o0150; lut[9'o36_2] = 12'o0256; lut[9'o36_3] = 12'o0364;
|
||||
lut[9'o36_4] = 12'o0471; lut[9'o36_5] = 12'o0577; lut[9'o36_6] = 12'o0705; lut[9'o36_7] = 12'o1013;
|
||||
lut[9'o37_0] = 12'o0046; lut[9'o37_1] = 12'o0163; lut[9'o37_2] = 12'o0277; lut[9'o37_3] = 12'o0414;
|
||||
lut[9'o37_4] = 12'o0531; lut[9'o37_5] = 12'o0646; lut[9'o37_6] = 12'o0762; lut[9'o37_7] = 12'o1077;
|
||||
lut[9'o40_0] = 12'o0052; lut[9'o40_1] = 12'o0176; lut[9'o40_2] = 12'o0322; lut[9'o40_3] = 12'o0446;
|
||||
lut[9'o40_4] = 12'o0573; lut[9'o40_5] = 12'o0717; lut[9'o40_6] = 12'o1043; lut[9'o40_7] = 12'o1167;
|
||||
lut[9'o41_0] = 12'o0056; lut[9'o41_1] = 12'o0213; lut[9'o41_2] = 12'o0347; lut[9'o41_3] = 12'o0504;
|
||||
lut[9'o41_4] = 12'o0641; lut[9'o41_5] = 12'o0776; lut[9'o41_6] = 12'o1132; lut[9'o41_7] = 12'o1267;
|
||||
lut[9'o42_0] = 12'o0063; lut[9'o42_1] = 12'o0231; lut[9'o42_2] = 12'o0377; lut[9'o42_3] = 12'o0545;
|
||||
lut[9'o42_4] = 12'o0713; lut[9'o42_5] = 12'o1061; lut[9'o42_6] = 12'o1227; lut[9'o42_7] = 12'o1375;
|
||||
lut[9'o43_0] = 12'o0070; lut[9'o43_1] = 12'o0250; lut[9'o43_2] = 12'o0430; lut[9'o43_3] = 12'o0610;
|
||||
lut[9'o43_4] = 12'o0771; lut[9'o43_5] = 12'o1151; lut[9'o43_6] = 12'o1331; lut[9'o43_7] = 12'o1511;
|
||||
lut[9'o44_0] = 12'o0075; lut[9'o44_1] = 12'o0271; lut[9'o44_2] = 12'o0464; lut[9'o44_3] = 12'o0660;
|
||||
lut[9'o44_4] = 12'o1053; lut[9'o44_5] = 12'o1247; lut[9'o44_6] = 12'o1442; lut[9'o44_7] = 12'o1636;
|
||||
lut[9'o45_0] = 12'o0104; lut[9'o45_1] = 12'o0314; lut[9'o45_2] = 12'o0524; lut[9'o45_3] = 12'o0734;
|
||||
lut[9'o45_4] = 12'o1144; lut[9'o45_5] = 12'o1354; lut[9'o45_6] = 12'o1564; lut[9'o45_7] = 12'o1774;
|
||||
lut[9'o46_0] = 12'o0112; lut[9'o46_1] = 12'o0340; lut[9'o46_2] = 12'o0565; lut[9'o46_3] = 12'o1013;
|
||||
lut[9'o46_4] = 12'o1240; lut[9'o46_5] = 12'o1466; lut[9'o46_6] = 12'o1713; lut[9'o46_7] = 12'o2141;
|
||||
lut[9'o47_0] = 12'o0122; lut[9'o47_1] = 12'o0366; lut[9'o47_2] = 12'o0633; lut[9'o47_3] = 12'o1077;
|
||||
lut[9'o47_4] = 12'o1344; lut[9'o47_5] = 12'o1610; lut[9'o47_6] = 12'o2055; lut[9'o47_7] = 12'o2321;
|
||||
lut[9'o50_0] = 12'o0132; lut[9'o50_1] = 12'o0417; lut[9'o50_2] = 12'o0704; lut[9'o50_3] = 12'o1171;
|
||||
lut[9'o50_4] = 12'o1456; lut[9'o50_5] = 12'o1743; lut[9'o50_6] = 12'o2230; lut[9'o50_7] = 12'o2515;
|
||||
lut[9'o51_0] = 12'o0143; lut[9'o51_1] = 12'o0452; lut[9'o51_2] = 12'o0761; lut[9'o51_3] = 12'o1270;
|
||||
lut[9'o51_4] = 12'o1577; lut[9'o51_5] = 12'o2106; lut[9'o51_6] = 12'o2415; lut[9'o51_7] = 12'o2724;
|
||||
lut[9'o52_0] = 12'o0155; lut[9'o52_1] = 12'o0510; lut[9'o52_2] = 12'o1043; lut[9'o52_3] = 12'o1376;
|
||||
lut[9'o52_4] = 12'o1731; lut[9'o52_5] = 12'o2264; lut[9'o52_6] = 12'o2617; lut[9'o52_7] = 12'o3152;
|
||||
lut[9'o53_0] = 12'o0170; lut[9'o53_1] = 12'o0551; lut[9'o53_2] = 12'o1131; lut[9'o53_3] = 12'o1512;
|
||||
lut[9'o53_4] = 12'o2073; lut[9'o53_5] = 12'o2454; lut[9'o53_6] = 12'o3034; lut[9'o53_7] = 12'o3415;
|
||||
lut[9'o54_0] = 12'o0204; lut[9'o54_1] = 12'o0615; lut[9'o54_2] = 12'o1226; lut[9'o54_3] = 12'o1637;
|
||||
lut[9'o54_4] = 12'o2250; lut[9'o54_5] = 12'o2661; lut[9'o54_6] = 12'o3272; lut[9'o54_7] = 12'o3703;
|
||||
lut[9'o55_0] = 12'o0221; lut[9'o55_1] = 12'o0665; lut[9'o55_2] = 12'o1330; lut[9'o55_3] = 12'o1774;// Not sure if these should clip at 11 bits or not
|
||||
lut[9'o55_4] = 12'o2437; lut[9'o55_5] = 12'o3103; lut[9'o55_6] = 12'o3546; lut[9'o55_7] = 12'o4212;//12'o3777;
|
||||
lut[9'o56_0] = 12'o0240; lut[9'o56_1] = 12'o0740; lut[9'o56_2] = 12'o1441; lut[9'o56_3] = 12'o2141;
|
||||
lut[9'o56_4] = 12'o2642; lut[9'o56_5] = 12'o3342; lut[9'o56_6] = 12'o4043; lut[9'o56_7] = 12'o4543;//12'o3777; lut[9'o56_7] = 12'o3777;
|
||||
lut[9'o57_0] = 12'o0260; lut[9'o57_1] = 12'o1021; lut[9'o57_2] = 12'o1561; lut[9'o57_3] = 12'o2322;
|
||||
lut[9'o57_4] = 12'o3063; lut[9'o57_5] = 12'o3624; lut[9'o57_6] = 12'o4364; lut[9'o57_7] = 12'o5125;//12'o3777; lut[9'o57_7] = 12'o3777;
|
||||
lut[9'o60_0] = 12'o0302; lut[9'o60_1] = 12'o1106; lut[9'o60_2] = 12'o1712; lut[9'o60_3] = 12'o2516;
|
||||
lut[9'o60_4] = 12'o3322; lut[9'o60_5] = 12'o4126; lut[9'o60_6] = 12'o4732; lut[9'o60_7] = 12'o5536;//12'o3777; lut[9'o60_6] = 12'o3777; lut[9'o60_7] = 12'o3777;
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
always @(posedge clk or negedge rst_n)
|
||||
if(!rst_n)
|
||||
inc <= 'd0;
|
||||
else if(cen)
|
||||
|
||||
@@ -28,6 +28,7 @@ module jt10_adpcmb(
|
||||
input [3:0] data,
|
||||
input chon, // high if this channel is on
|
||||
input adv,
|
||||
input clr,
|
||||
output signed [15:0] pcm
|
||||
);
|
||||
|
||||
@@ -64,33 +65,43 @@ end
|
||||
// 666 kHz -> 18.5 kHz = 55.5/3 kHz
|
||||
|
||||
reg [3:0] data2;
|
||||
reg sign_data;
|
||||
reg sign_data2, sign_data3, sign_data4, sign_data5;
|
||||
|
||||
reg [3:0] adv2;
|
||||
reg need_clr;
|
||||
|
||||
wire [3:0] data_use = clr || ~chon ? 4'd0 : data;
|
||||
|
||||
always @( posedge clk or negedge rst_n )
|
||||
if( ! rst_n ) begin
|
||||
x1 <= 'd0; step1 <= 'd127;
|
||||
d2 <= 'd0; d3 <= 'd0; d4 <= 'd0;
|
||||
end else if(cen) begin
|
||||
need_clr <= 0;
|
||||
end else begin
|
||||
if( clr )
|
||||
need_clr <= 1'd1;
|
||||
if(cen) begin
|
||||
adv2 <= {1'b0,adv2[3:1]};
|
||||
// I
|
||||
if( adv ) begin
|
||||
d2 <= {data[2:0],1'b1};
|
||||
sign_data <= data[3];
|
||||
if( adv ) begin
|
||||
d2 <= {data_use[2:0],1'b1};
|
||||
sign_data2 <= data_use[3];
|
||||
adv2[3] <= 1'b1;
|
||||
end
|
||||
// II multiply and obtain the offset
|
||||
d3 <= { {xw-16{1'b0}}, d2l[18:3] }; // xw bits
|
||||
next_step3<= step2l[22:6];
|
||||
sign_data3<=sign_data2;
|
||||
// III 2's complement of d3 if necessary
|
||||
d4 <= sign_data ? ~d3+1 : d3;
|
||||
d4 <= sign_data3 ? ~d3+1'd1 : d3;
|
||||
sign_data4<=sign_data3;
|
||||
// IV Advance the waveform
|
||||
next_x5 <= x1+d4;
|
||||
sign_data5<=sign_data4;
|
||||
// V: limit or reset outputs
|
||||
if( chon ) begin // update values if needed
|
||||
if( adv2[0] ) begin
|
||||
if( sign_data == x1[xw-1] && (x1[xw-1]!=next_x5[xw-1]) )
|
||||
if( sign_data5 == x1[xw-1] && (x1[xw-1]!=next_x5[xw-1]) )
|
||||
x1 <= x1[xw-1] ? limneg : limpos;
|
||||
else
|
||||
x1 <= next_x5;
|
||||
@@ -105,8 +116,16 @@ always @( posedge clk or negedge rst_n )
|
||||
end else begin
|
||||
x1 <= 'd0;
|
||||
step1 <= 'd127;
|
||||
end
|
||||
if( need_clr ) begin
|
||||
x1 <= 'd0;
|
||||
step1 <= 'd127;
|
||||
next_step3 <= 'd127;
|
||||
d2 <= 'd0; d3 <= 'd0; d4 <= 'd0;
|
||||
next_x5 <= 'd0;
|
||||
need_clr <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule // jt10_adpcm
|
||||
@@ -30,6 +30,7 @@ module jt10_adpcmb_cnt(
|
||||
input [15:0] delta_n,
|
||||
input clr,
|
||||
input on,
|
||||
input acmd_up_b,
|
||||
// Address
|
||||
input [15:0] astart,
|
||||
input [15:0] aend,
|
||||
@@ -37,8 +38,10 @@ module jt10_adpcmb_cnt(
|
||||
output reg [23:0] addr,
|
||||
output reg nibble_sel,
|
||||
// Flag
|
||||
output reg chon,
|
||||
output reg flag,
|
||||
input clr_flag,
|
||||
output reg clr_dec,
|
||||
|
||||
output reg adv
|
||||
);
|
||||
@@ -51,19 +54,22 @@ always @(posedge clk or negedge rst_n)
|
||||
cnt <= 'd0;
|
||||
adv <= 'b0;
|
||||
end else if(cen) begin
|
||||
if( clr ) begin
|
||||
if( clr) begin
|
||||
cnt <= 'd0;
|
||||
adv <= 'b0;
|
||||
end else begin
|
||||
if( on )
|
||||
{adv, cnt} <= {1'b0, cnt} + {1'b0, delta_n };
|
||||
else
|
||||
else begin
|
||||
cnt <= 'd0;
|
||||
adv <= 1'b1; // let the rest of the signal chain advance
|
||||
// when channel is off so all registers go to reset values
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg set_flag, last_set;
|
||||
reg restart;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
if(!rst_n) begin
|
||||
@@ -76,33 +82,41 @@ always @(posedge clk or negedge rst_n)
|
||||
end
|
||||
|
||||
// Address
|
||||
reg last_on;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
if(!rst_n) begin
|
||||
addr <= 'd0;
|
||||
nibble_sel <= 'b0;
|
||||
set_flag <= 'd0;
|
||||
end else if(cen) begin
|
||||
last_on <= on;
|
||||
|
||||
if( (on && !last_on) || clr ) begin
|
||||
chon <= 'b0;
|
||||
restart <= 'b0;
|
||||
clr_dec <= 'b1;
|
||||
end else if( !on || clr ) begin
|
||||
restart <= 'd0;
|
||||
chon <= 'd0;
|
||||
clr_dec <= 'd1;
|
||||
end else if( acmd_up_b && on ) begin
|
||||
restart <= 'd1;
|
||||
end else if( cen ) begin
|
||||
if( restart && adv ) begin
|
||||
addr <= {astart,8'd0};
|
||||
nibble_sel <= 'b0;
|
||||
end else if( on && adv ) begin
|
||||
if( addr[23:8] < aend ) begin
|
||||
restart <= 'd0;
|
||||
chon <= 'd1;
|
||||
clr_dec <= 'd0;
|
||||
end else if( chon && adv ) begin
|
||||
if( { addr, nibble_sel } != { aend, 8'hFF, 1'b1 } ) begin
|
||||
{ addr, nibble_sel } <= { addr, nibble_sel } + 25'd1;
|
||||
set_flag <= 'd0;
|
||||
end
|
||||
else begin
|
||||
end else if(arepeat) begin
|
||||
restart <= 'd1;
|
||||
clr_dec <= 'd1;
|
||||
end else begin
|
||||
set_flag <= 'd1;
|
||||
if(arepeat) begin
|
||||
addr <= {astart,8'd0};
|
||||
nibble_sel <= 'b0;
|
||||
end
|
||||
chon <= 'd0;
|
||||
clr_dec <= 'd1;
|
||||
end
|
||||
end
|
||||
end // cen
|
||||
|
||||
|
||||
endmodule // jt10_adpcmb_cnt
|
||||
endmodule // jt10_adpcmb_cnt
|
||||
|
||||
@@ -37,7 +37,8 @@ reg start_div=1'b0;
|
||||
reg [3:0] deltan, pre_dn;
|
||||
reg [stages-1:0] adv2;
|
||||
reg signed [15:0] pcminter;
|
||||
wire [15:0] step, next_step;
|
||||
wire [15:0] next_step;
|
||||
reg [15:0] step;
|
||||
reg step_sign, next_step_sign;
|
||||
|
||||
assign pcmout = pcminter;
|
||||
@@ -50,8 +51,8 @@ always @(posedge clk) if(cen55) begin
|
||||
if ( adv ) begin
|
||||
pre_dn <= 'd1;
|
||||
deltan <= pre_dn;
|
||||
end else
|
||||
pre_dn <= pre_dn + 1;
|
||||
end else if ( pre_dn != 4'hF )
|
||||
pre_dn <= pre_dn + 1'd1;
|
||||
end
|
||||
|
||||
|
||||
@@ -59,14 +60,13 @@ always @(posedge clk) if(cen) begin
|
||||
start_div <= 1'b0;
|
||||
if(adv2[1]) begin
|
||||
pcmlast <= pcmdec;
|
||||
pcminter <= pcmlast;
|
||||
end
|
||||
if(adv2[4]) begin
|
||||
pre_dx <= { pcmdec[15], pcmdec } - { pcmlast[15], pcmlast };
|
||||
end
|
||||
if( adv2[5] ) begin
|
||||
start_div <= 1'b1;
|
||||
delta_x <= pre_dx[16] ? ~pre_dx[15:0]+1 : pre_dx[15:0];
|
||||
delta_x <= pre_dx[16] ? ~pre_dx[15:0]+1'd1 : pre_dx[15:0];
|
||||
next_step_sign <= pre_dx[16];
|
||||
end
|
||||
end
|
||||
@@ -77,7 +77,7 @@ always @(posedge clk) if(cen55) begin
|
||||
step_sign <= next_step_sign;
|
||||
pcminter <= pcmlast;
|
||||
end
|
||||
else pcminter <= step_sign ? pcminter - step : pcminter + step;
|
||||
else pcminter <= ( (pcminter < pcmlast) == step_sign ) ? pcminter : step_sign ? pcminter - step : pcminter + step;
|
||||
end
|
||||
|
||||
jt10_adpcm_div #(.dw(16)) u_div(
|
||||
|
||||
@@ -39,6 +39,8 @@ module jt03(
|
||||
input [7:0] IOB_in,
|
||||
output [7:0] IOA_out,
|
||||
output [7:0] IOB_out,
|
||||
output IOA_oe,
|
||||
output IOB_oe,
|
||||
// Separated output
|
||||
output [ 7:0] psg_A,
|
||||
output [ 7:0] psg_B,
|
||||
@@ -47,11 +49,14 @@ module jt03(
|
||||
// combined output
|
||||
output [ 9:0] psg_snd,
|
||||
output signed [15:0] snd,
|
||||
output snd_sample
|
||||
output snd_sample,
|
||||
// Debug
|
||||
//input [ 7:0] debug_bus,
|
||||
output [ 7:0] debug_view
|
||||
);
|
||||
|
||||
jt12_top #(
|
||||
.use_lfo(0),.use_ssg(1), .num_ch(3), .use_pcm(0), .use_adpcm(0) )
|
||||
.use_lfo(0),.use_ssg(1), .num_ch(3), .use_pcm(0), .use_adpcm(0), .mask_div(0) )
|
||||
u_jt12(
|
||||
.rst ( rst ), // rst should be at least 6 clk&cen cycles long
|
||||
.clk ( clk ), // CPU clock
|
||||
@@ -64,10 +69,12 @@ u_jt12(
|
||||
.dout ( dout ),
|
||||
.irq_n ( irq_n ),
|
||||
// YM2203 I/O pins
|
||||
.IOA_out ( IOA_out ),
|
||||
.IOB_out ( IOB_out ),
|
||||
.IOA_in ( IOA_in ),
|
||||
.IOB_in ( IOB_in ),
|
||||
.IOA_out ( IOA_out ),
|
||||
.IOB_out ( IOB_out ),
|
||||
.IOA_oe ( IOA_oe ),
|
||||
.IOB_oe ( IOB_oe ),
|
||||
// Unused ADPCM pins
|
||||
.en_hifi_pcm ( 1'b0 ), // used only on YM2612 mode
|
||||
.adpcma_addr ( ), // real hardware has 10 pins multiplexed through RMPX pin
|
||||
@@ -91,7 +98,11 @@ u_jt12(
|
||||
|
||||
.snd_right ( snd ),
|
||||
.snd_left (),
|
||||
.snd_sample ( snd_sample )
|
||||
.snd_sample ( snd_sample ),
|
||||
|
||||
//.debug_bus ( debug_bus ),
|
||||
.debug_bus ( 8'd0 ),
|
||||
.debug_view ( debug_view )
|
||||
);
|
||||
|
||||
endmodule // jt03
|
||||
|
||||
@@ -20,7 +20,6 @@
|
||||
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// Use for YM2203
|
||||
// no left/right channels
|
||||
|
||||
@@ -91,7 +91,8 @@ u_jt12(
|
||||
.snd_left ( snd_left ),
|
||||
.snd_sample ( snd_sample ),
|
||||
// unused pins
|
||||
.en_hifi_pcm ( 1'b0 ) // used only on YM2612 mode
|
||||
.en_hifi_pcm ( 1'b0 ), // used only on YM2612 mode
|
||||
.debug_view ( )
|
||||
);
|
||||
|
||||
endmodule // jt03
|
||||
|
||||
@@ -75,6 +75,7 @@ jt12_top u_jt12(
|
||||
.psg_snd (),
|
||||
.snd_right ( snd_right ), // FM+PSG
|
||||
.snd_left ( snd_left ), // FM+PSG
|
||||
.snd_sample ( snd_sample )
|
||||
.snd_sample ( snd_sample ),
|
||||
.debug_view ( )
|
||||
);
|
||||
endmodule // jt03
|
||||
|
||||
@@ -18,19 +18,18 @@
|
||||
Date: 14-2-2017
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module jt12_div(
|
||||
input rst,
|
||||
input clk,
|
||||
input cen /* synthesis direct_enable */,
|
||||
input [1:0] div_setting,
|
||||
output reg clk_en, // after prescaler
|
||||
output reg clk_en_2, // cen divided by 2
|
||||
output reg clk_en_ssg,
|
||||
output reg clk_en_666, // 666 kHz
|
||||
output reg clk_en_111, // 111 kHz
|
||||
output reg clk_en_55 // 55 kHz
|
||||
input [1:0] div_setting,
|
||||
output reg clk_en, // after prescaler
|
||||
output reg clk_en_2, // cen divided by 2
|
||||
output reg clk_en_ssg,
|
||||
output reg clk_en_666, // 666 kHz
|
||||
output reg clk_en_111, // 111 kHz
|
||||
output reg clk_en_55 // 55 kHz
|
||||
);
|
||||
|
||||
parameter use_ssg=0;
|
||||
@@ -81,6 +80,17 @@ initial clk_en_666 = 1'b0;
|
||||
reg cen_55_int;
|
||||
reg [1:0] div2=2'b0;
|
||||
|
||||
reg pre_clk_en, pre_clk_en_2, pre_clk_en_ssg, pre_clk_en_666, pre_clk_en_111, pre_clk_en_55;
|
||||
|
||||
always @(negedge clk) begin // It's important to leave the negedge to use the physical clock enable input
|
||||
clk_en <= pre_clk_en;
|
||||
clk_en_2 <= pre_clk_en_2;
|
||||
clk_en_ssg <= pre_clk_en_ssg;
|
||||
clk_en_666 <= pre_clk_en_666;
|
||||
clk_en_111 <= pre_clk_en_111;
|
||||
clk_en_55 <= pre_clk_en_55;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
cen_int <= opn_cnt == 4'd0;
|
||||
cen_ssg_int <= ssg_cnt == 3'd0;
|
||||
@@ -88,18 +98,18 @@ always @(posedge clk) begin
|
||||
cen_adpcm3_int <= adpcm_cnt111 == 3'd0;
|
||||
cen_55_int <= adpcm_cnt55 == 3'd0;
|
||||
`ifdef FASTDIV
|
||||
// always enabled for fast sims (use with GYM output, timer will not work well)
|
||||
// always enabled for fast sims (use with GYM output, the timers will not work well)
|
||||
clk_en <= 1'b1;
|
||||
clk_en_ssg <= 1'b1;
|
||||
clk_en_666 <= 1'b1;
|
||||
clk_en_55 <= 1'b1;
|
||||
`else
|
||||
clk_en <= cen & cen_int;
|
||||
clk_en_2 <= cen && (div2==2'b00);
|
||||
clk_en_ssg <= use_ssg ? (cen & cen_ssg_int) : 1'b0;
|
||||
clk_en_666 <= cen & cen_adpcm_int;
|
||||
clk_en_111 <= cen & cen_adpcm_int & cen_adpcm3_int;
|
||||
clk_en_55 <= cen & cen_adpcm_int & cen_adpcm3_int & cen_55_int;
|
||||
pre_clk_en <= cen & cen_int;
|
||||
pre_clk_en_2 <= cen && (div2==2'b00);
|
||||
pre_clk_en_ssg <= use_ssg ? (cen & cen_ssg_int) : 1'b0;
|
||||
pre_clk_en_666 <= cen & cen_adpcm_int;
|
||||
pre_clk_en_111 <= cen & cen_adpcm_int & cen_adpcm3_int;
|
||||
pre_clk_en_55 <= cen & cen_adpcm_int & cen_adpcm3_int & cen_55_int;
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
@@ -1,4 +1,3 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
|
||||
/* This file is part of JT12.
|
||||
|
||||
@@ -1,4 +1,3 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
|
||||
/* This file is part of JT12.
|
||||
|
||||
@@ -18,7 +18,6 @@
|
||||
Date: 25-2-2017
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
|
||||
|
||||
@@ -18,7 +18,6 @@
|
||||
Date: 14-2-2017
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module jt12_mmr(
|
||||
input rst,
|
||||
@@ -52,6 +51,7 @@ module jt12_mmr(
|
||||
output reg fast_timers,
|
||||
input flag_A,
|
||||
input overflow_A,
|
||||
output reg [1:0] div_setting,
|
||||
// PCM
|
||||
output reg [8:0] pcm,
|
||||
output reg pcm_en,
|
||||
@@ -77,6 +77,7 @@ module jt12_mmr(
|
||||
output reg [15:0] adeltan_b, // Delta-N
|
||||
output reg [ 7:0] aeg_b, // Envelope Generator Control
|
||||
output reg [ 6:0] flag_ctl,
|
||||
output reg [ 6:0] flag_mask,
|
||||
// Operator
|
||||
output xuse_prevprev1,
|
||||
output xuse_internal,
|
||||
@@ -122,13 +123,11 @@ module jt12_mmr(
|
||||
// PSG interace
|
||||
output [3:0] psg_addr,
|
||||
output [7:0] psg_data,
|
||||
output reg psg_wr_n
|
||||
output reg psg_wr_n,
|
||||
input [7:0] debug_bus
|
||||
);
|
||||
|
||||
parameter use_ssg=0, num_ch=6, use_pcm=1, use_adpcm=0;
|
||||
|
||||
reg [1:0] div_setting;
|
||||
|
||||
parameter use_ssg=0, num_ch=6, use_pcm=1, use_adpcm=0, mask_div=1;
|
||||
|
||||
jt12_div #(.use_ssg(use_ssg)) u_div (
|
||||
.rst ( rst ),
|
||||
@@ -200,6 +199,13 @@ endgenerate
|
||||
|
||||
reg part;
|
||||
|
||||
`ifdef SIMULATION
|
||||
always @(posedge clk) if( write && rst ) begin
|
||||
$display("WARNING [JT12]: detected write request while in reset.\nThis is likely a glue-logic error in the CPU-FM module.");
|
||||
$finish;
|
||||
end
|
||||
`endif
|
||||
|
||||
// this runs at clk speed, no clock gating here
|
||||
// if I try to make this an async rst it fails to map it
|
||||
// as flip flops but uses latches instead. So I keep it as sync. reset
|
||||
@@ -266,6 +272,7 @@ always @(posedge clk) begin : memory_mapped_registers
|
||||
if( !addr[0] ) begin
|
||||
selected_register <= din;
|
||||
part <= addr[1];
|
||||
if (!mask_div)
|
||||
case(din)
|
||||
// clock divider: should work only for ym2203
|
||||
// and ym2608.
|
||||
@@ -374,7 +381,11 @@ always @(posedge clk) begin : memory_mapped_registers
|
||||
4'h9: adeltan_b[ 7:0] <= din;
|
||||
4'ha: adeltan_b[15:8] <= din;
|
||||
4'hb: aeg_b <= din;
|
||||
4'hc: flag_ctl <= {din[7],din[5:0]}; // this lasts a single clock cycle
|
||||
4'hc: begin
|
||||
flag_mask <= ~{din[7],din[5:0]};
|
||||
flag_ctl <= {din[7],din[5:0]}; // this lasts a single clock cycle
|
||||
end
|
||||
|
||||
default:;
|
||||
endcase
|
||||
end
|
||||
|
||||
@@ -1,4 +1,3 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
|
||||
/* This file is part of JT12.
|
||||
|
||||
@@ -1,4 +1,3 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
|
||||
/* This file is part of JT12.
|
||||
|
||||
@@ -24,7 +24,6 @@ http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc
|
||||
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
|
||||
|
||||
@@ -18,7 +18,6 @@
|
||||
Date: 14-10-2018
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// This implementation follows that of Alexey Khokholov (Nuke.YKT) in C language.
|
||||
|
||||
|
||||
@@ -18,7 +18,6 @@
|
||||
Date: 1-31-2017
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// stages must be greater than 2
|
||||
module jt12_sh #(parameter width=5, stages=24 )
|
||||
|
||||
@@ -18,7 +18,6 @@
|
||||
Date: 1-31-2017
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module jt12_sh24 #(parameter width=5 )
|
||||
(
|
||||
|
||||
@@ -18,7 +18,6 @@
|
||||
Date: 1-31-2017
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// stages must be greater than 2
|
||||
module jt12_sh_rst #(parameter width=5, stages=32, rstval=1'b0 )
|
||||
|
||||
@@ -23,7 +23,6 @@
|
||||
// Accumulates an arbitrary number of inputs with saturation
|
||||
// restart the sum when input "zero" is high
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module jt12_single_acc #(parameter
|
||||
win=14, // input data width
|
||||
|
||||
@@ -18,7 +18,6 @@
|
||||
Date: 1-31-2017
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/* The input is {op[1:0], ch[2:0]}
|
||||
it adds 1 to the channel and overflow to the operator correctly */
|
||||
|
||||
@@ -22,7 +22,6 @@
|
||||
Timer B = 2304*(256-NB)/Phi M
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module jt12_timers(
|
||||
input clk,
|
||||
@@ -101,8 +100,8 @@ module jt12_timer #(parameter
|
||||
output reg flag,
|
||||
output reg overflow
|
||||
);
|
||||
|
||||
reg last_load;
|
||||
/* verilator lint_off WIDTH */
|
||||
reg load_l;
|
||||
reg [CW-1:0] cnt, next;
|
||||
reg [FW-1:0] free_cnt, free_next;
|
||||
reg free_ov;
|
||||
@@ -113,7 +112,7 @@ always@(posedge clk, posedge rst)
|
||||
else /*if(cen)*/ begin
|
||||
if( clr_flag )
|
||||
flag <= 1'b0;
|
||||
else if(overflow) flag<=1'b1;
|
||||
else if( cen && zero && load && overflow ) flag<=1'b1;
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
@@ -121,21 +120,21 @@ always @(*) begin
|
||||
{overflow, next } = { 1'b0, cnt } + (FREE_EN ? free_ov : 1'b1);
|
||||
end
|
||||
|
||||
always @(posedge clk) if(cen && zero) begin : counter
|
||||
last_load <= load;
|
||||
if( (load && !last_load) || overflow ) begin
|
||||
cnt <= start_value;
|
||||
end
|
||||
else if( last_load ) cnt <= next;
|
||||
always @(posedge clk) begin
|
||||
load_l <= load;
|
||||
if( !load_l && load ) begin
|
||||
cnt <= start_value;
|
||||
end else if( cen && zero && load )
|
||||
cnt <= overflow ? start_value : next;
|
||||
end
|
||||
|
||||
// Free running counter
|
||||
always @(posedge clk) begin
|
||||
if( rst ) begin
|
||||
free_cnt <= {FW{1'b0}};
|
||||
end else if( cen&&zero ) begin
|
||||
free_cnt <= 0;
|
||||
end else if( cen && zero ) begin
|
||||
free_cnt <= free_cnt+1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
/* verilator lint_on WIDTH */
|
||||
endmodule
|
||||
|
||||
@@ -27,7 +27,7 @@ http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc
|
||||
module jt12_top (
|
||||
input rst, // rst should be at least 6 clk&cen cycles long
|
||||
input clk, // CPU clock
|
||||
input cen, // optional clock enable, it not needed leave as 1'b1
|
||||
(* direct_enable *) input cen, // optional clock enable, if not needed leave as 1'b1
|
||||
input [7:0] din,
|
||||
input [1:0] addr,
|
||||
input cs_n,
|
||||
@@ -50,6 +50,8 @@ module jt12_top (
|
||||
input [7:0] IOB_in,
|
||||
output [7:0] IOA_out,
|
||||
output [7:0] IOB_out,
|
||||
output IOA_oe,
|
||||
output IOB_oe,
|
||||
// Separated output
|
||||
output [ 7:0] psg_A,
|
||||
output [ 7:0] psg_B,
|
||||
@@ -64,7 +66,9 @@ module jt12_top (
|
||||
output [ 9:0] psg_snd,
|
||||
output signed [15:0] snd_right, // FM+PSG
|
||||
output signed [15:0] snd_left, // FM+PSG
|
||||
output snd_sample
|
||||
output snd_sample,
|
||||
input [ 7:0] debug_bus,
|
||||
output [ 7:0] debug_view
|
||||
);
|
||||
|
||||
// parameters to select the features for each chip type
|
||||
@@ -72,6 +76,7 @@ module jt12_top (
|
||||
parameter use_lfo=1, use_ssg=0, num_ch=6, use_pcm=1;
|
||||
parameter use_adpcm=0;
|
||||
parameter JT49_DIV=2;
|
||||
parameter mask_div=1;
|
||||
|
||||
wire flag_A, flag_B, busy;
|
||||
|
||||
@@ -162,10 +167,13 @@ wire [ 7:0] aeg_b; // Envelope Generator Control
|
||||
wire [ 5:0] adpcma_flags; // ADPMC-A read over flags
|
||||
wire adpcmb_flag;
|
||||
wire [ 6:0] flag_ctl;
|
||||
|
||||
wire [ 6:0] flag_mask;
|
||||
wire [ 1:0] div_setting;
|
||||
|
||||
wire clk_en_2, clk_en_666, clk_en_111, clk_en_55;
|
||||
|
||||
assign debug_view = { 4'd0, flag_B, flag_A, div_setting };
|
||||
|
||||
generate
|
||||
if( use_adpcm==1 ) begin: gen_adpcm
|
||||
wire rst_n;
|
||||
@@ -217,7 +225,7 @@ if( use_adpcm==1 ) begin: gen_adpcm
|
||||
.acmd_on_b ( acmd_on_b ), // Control - Process start, Key On
|
||||
.acmd_rep_b ( acmd_rep_b ), // Control - Repeat
|
||||
.acmd_rst_b ( acmd_rst_b ), // Control - Reset
|
||||
//.acmd_up_b ( acmd_up_b ), // Control - New command received
|
||||
.acmd_up_b ( acmd_up_b ), // Control - New command received
|
||||
.alr_b ( alr_b ), // Left / Right
|
||||
.astart_b ( astart_b ), // Start address
|
||||
.aend_b ( aend_b ), // End address
|
||||
@@ -268,6 +276,8 @@ end else begin : gen_adpcm_no
|
||||
assign adpcma_roe_n = 'b1;
|
||||
assign adpcmb_addr = 'd0;
|
||||
assign adpcmb_roe_n = 'd1;
|
||||
assign adpcma_flags = 0;
|
||||
assign adpcmb_flag = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
@@ -278,8 +288,8 @@ jt12_dout #(.use_ssg(use_ssg),.use_adpcm(use_adpcm)) u_dout(
|
||||
.flag_A ( flag_A ),
|
||||
.flag_B ( flag_B ),
|
||||
.busy ( busy ),
|
||||
.adpcma_flags ( adpcma_flags ),
|
||||
.adpcmb_flag ( adpcmb_flag ),
|
||||
.adpcma_flags ( adpcma_flags & flag_mask[5:0] ),
|
||||
.adpcmb_flag ( adpcmb_flag & flag_mask[6] ),
|
||||
.psg_dout ( psg_dout ),
|
||||
.addr ( addr ),
|
||||
.dout ( dout )
|
||||
@@ -287,7 +297,7 @@ jt12_dout #(.use_ssg(use_ssg),.use_adpcm(use_adpcm)) u_dout(
|
||||
|
||||
|
||||
/* verilator tracing_on */
|
||||
jt12_mmr #(.use_ssg(use_ssg),.num_ch(num_ch),.use_pcm(use_pcm), .use_adpcm(use_adpcm))
|
||||
jt12_mmr #(.use_ssg(use_ssg),.num_ch(num_ch),.use_pcm(use_pcm), .use_adpcm(use_adpcm), .mask_div(mask_div))
|
||||
u_mmr(
|
||||
.rst ( rst ),
|
||||
.clk ( clk ),
|
||||
@@ -345,6 +355,7 @@ jt12_mmr #(.use_ssg(use_ssg),.num_ch(num_ch),.use_pcm(use_pcm), .use_adpcm(use_a
|
||||
.adeltan_b ( adeltan_b ), // Delta-N
|
||||
.aeg_b ( aeg_b ), // Envelope Generator Control
|
||||
.flag_ctl ( flag_ctl ),
|
||||
.flag_mask ( flag_mask ),
|
||||
// Operator
|
||||
.xuse_prevprev1 ( xuse_prevprev1 ),
|
||||
.xuse_internal ( xuse_internal ),
|
||||
@@ -389,7 +400,9 @@ jt12_mmr #(.use_ssg(use_ssg),.num_ch(num_ch),.use_pcm(use_pcm), .use_adpcm(use_a
|
||||
// PSG interace
|
||||
.psg_addr ( psg_addr ),
|
||||
.psg_data ( psg_data ),
|
||||
.psg_wr_n ( psg_wr_n )
|
||||
.psg_wr_n ( psg_wr_n ),
|
||||
.debug_bus ( debug_bus ),
|
||||
.div_setting(div_setting)
|
||||
);
|
||||
|
||||
/* verilator tracing_on */
|
||||
@@ -442,7 +455,7 @@ endgenerate
|
||||
`ifndef NOSSG
|
||||
generate
|
||||
if( use_ssg==1 ) begin : gen_ssg
|
||||
jt49 #(.COMP(2'b00), .CLKDIV(JT49_DIV))
|
||||
jt49 #(.COMP(2'b01), .CLKDIV(JT49_DIV))
|
||||
u_psg( // note that input ports are not multiplexed
|
||||
.rst_n ( ~rst ),
|
||||
.clk ( clk ), // signal on positive edge
|
||||
@@ -457,11 +470,13 @@ generate
|
||||
.C ( psg_C ),
|
||||
.dout ( psg_dout ),
|
||||
.sel ( 1'b1 ), // half clock speed
|
||||
// Unused:
|
||||
.IOA_out ( IOA_out ),
|
||||
.IOB_out ( IOB_out ),
|
||||
.IOA_in ( IOA_in ),
|
||||
.IOB_in ( IOB_in ),
|
||||
.IOA_oe ( IOA_oe ),
|
||||
.IOB_oe ( IOB_oe ),
|
||||
// Unused:
|
||||
.sample ( )
|
||||
);
|
||||
assign snd_left = fm_snd_left + { 1'b0, psg_snd[9:0],5'd0};
|
||||
|
||||
@@ -39,14 +39,16 @@ module jt49 ( // note that input ports are not multiplexed
|
||||
|
||||
input [7:0] IOA_in,
|
||||
output [7:0] IOA_out,
|
||||
output IOA_oe,
|
||||
|
||||
input [7:0] IOB_in,
|
||||
output [7:0] IOB_out
|
||||
output [7:0] IOB_out,
|
||||
output IOB_oe
|
||||
);
|
||||
|
||||
parameter [2:0] COMP=3'b000;
|
||||
parameter [1:0] COMP=2'b00;
|
||||
parameter CLKDIV=3;
|
||||
wire [2:0] comp = COMP;
|
||||
wire [1:0] comp = COMP;
|
||||
|
||||
reg [7:0] regarray[15:0];
|
||||
wire [7:0] port_A, port_B;
|
||||
@@ -60,8 +62,10 @@ wire cen16, cen256;
|
||||
|
||||
assign IOA_out = regarray[14];
|
||||
assign IOB_out = regarray[15];
|
||||
assign port_A = !regarray[7][6] ? IOA_in : IOA_out;
|
||||
assign port_B = !regarray[7][7] ? IOB_in : IOB_out;
|
||||
assign port_A = IOA_in;
|
||||
assign port_B = IOB_in;
|
||||
assign IOA_oe = regarray[7][6];
|
||||
assign IOB_oe = regarray[7][7];
|
||||
assign sample = cen16;
|
||||
|
||||
jt49_cen #(.CLKDIV(CLKDIV)) u_cen(
|
||||
|
||||
@@ -42,12 +42,14 @@ module jt49_bus ( // note that input ports are not multiplexed
|
||||
|
||||
input [7:0] IOA_in,
|
||||
output [7:0] IOA_out,
|
||||
output IOA_oe,
|
||||
|
||||
input [7:0] IOB_in,
|
||||
output [7:0] IOB_out
|
||||
output [7:0] IOB_out,
|
||||
output IOB_oe
|
||||
);
|
||||
|
||||
parameter [2:0] COMP=3'b000;
|
||||
parameter [1:0] COMP=2'b00;
|
||||
|
||||
reg wr_n, cs_n;
|
||||
reg [3:0] addr;
|
||||
@@ -94,8 +96,10 @@ jt49 #(.COMP(COMP)) u_jt49( // note that input ports are not multiplexed
|
||||
.C ( C ),
|
||||
.IOA_in ( IOA_in ),
|
||||
.IOA_out( IOA_out ),
|
||||
.IOA_oe ( IOA_oe ),
|
||||
.IOB_in ( IOB_in ),
|
||||
.IOB_out( IOB_out )
|
||||
.IOB_out( IOB_out ),
|
||||
.IOB_oe ( IOB_oe )
|
||||
);
|
||||
|
||||
endmodule // jt49_bus
|
||||
@@ -21,7 +21,6 @@
|
||||
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// Compression vs dynamic range
|
||||
// 0 -> 43.6dB
|
||||
@@ -31,12 +30,12 @@
|
||||
|
||||
module jt49_exp(
|
||||
input clk,
|
||||
input [2:0] comp, // compression
|
||||
input [1:0] comp, // compression
|
||||
input [4:0] din,
|
||||
output reg [7:0] dout
|
||||
);
|
||||
|
||||
reg [7:0] lut[0:159];
|
||||
reg [7:0] lut[0:127];
|
||||
|
||||
always @(posedge clk)
|
||||
dout <= lut[ {comp,din} ];
|
||||
@@ -170,38 +169,6 @@ initial begin
|
||||
lut[125] = 8'd229;
|
||||
lut[126] = 8'd241;
|
||||
lut[127] = 8'd255;
|
||||
lut[128] = 8'd0;
|
||||
lut[129] = 8'd8;
|
||||
lut[130] = 8'd10;
|
||||
lut[131] = 8'd12;
|
||||
lut[132] = 8'd16;
|
||||
lut[133] = 8'd22;
|
||||
lut[134] = 8'd29;
|
||||
lut[135] = 8'd35;
|
||||
lut[136] = 8'd44;
|
||||
lut[137] = 8'd50;
|
||||
lut[138] = 8'd56;
|
||||
lut[139] = 8'd60;
|
||||
lut[140] = 8'd64;
|
||||
lut[141] = 8'd85;
|
||||
lut[142] = 8'd97;
|
||||
lut[143] = 8'd103;
|
||||
lut[144] = 8'd108;
|
||||
lut[145] = 8'd120;
|
||||
lut[146] = 8'd127;
|
||||
lut[147] = 8'd134;
|
||||
lut[148] = 8'd141;
|
||||
lut[149] = 8'd149;
|
||||
lut[150] = 8'd157;
|
||||
lut[151] = 8'd166;
|
||||
lut[152] = 8'd175;
|
||||
lut[153] = 8'd185;
|
||||
lut[154] = 8'd195;
|
||||
lut[155] = 8'd206;
|
||||
lut[156] = 8'd217;
|
||||
lut[157] = 8'd229;
|
||||
lut[158] = 8'd241;
|
||||
lut[159] = 8'd255;
|
||||
|
||||
end
|
||||
endmodule
|
||||
|
||||
@@ -21,7 +21,6 @@
|
||||
|
||||
*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module jt49_noise(
|
||||
(* direct_enable *) input cen,
|
||||
|
||||
27
common/Sound/jtopl/common.qip
Normal file
27
common/Sound/jtopl/common.qip
Normal file
@@ -0,0 +1,27 @@
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_acc.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_csr.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_div.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_cnt.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_comb.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_ctrl.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_final.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_pure.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_step.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_exprom.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_lfo.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_logsin.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_noise.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_op.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_comb.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_inc.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_rhy.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_sum.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pm.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_reg_ch.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_sh.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_sh_rst.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_single_acc.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_slot_cnt.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_timers.v]
|
||||
4
common/Sound/jtopl/jt2413.qip
Normal file
4
common/Sound/jtopl/jt2413.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) common.qip]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopll_mmr.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopll_reg.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt2413.v]
|
||||
@@ -1,30 +1,4 @@
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_acc.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_csr.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_div.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_lfo.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pm.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_cnt.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_comb.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_ctrl.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_final.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_pure.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_step.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_exprom.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_logsin.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_mmr.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_op.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_comb.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_inc.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_sum.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_rhy.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_reg.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_reg_ch.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_sh_rst.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_sh.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_single_acc.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_timers.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_noise.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_slot_cnt.v]
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) common.qip]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_mmr.v]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_reg.v]
|
||||
|
||||
@@ -1,2 +1,2 @@
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl2.v ]
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) jt26.qip ]
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) jt26.qip]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl2.v]
|
||||
|
||||
@@ -98,6 +98,13 @@ reg wave_mode, // 1 if waveform selection is enabled (OPL2)
|
||||
note_sel; // keyboard split, not implemented
|
||||
reg [ 4:0] rhy_kon;
|
||||
|
||||
`ifdef SIMULATION
|
||||
always @(posedge clk) if( write && rst ) begin
|
||||
$display("WARNING [JTOPL]: detected write request while in reset.\nThis is likely a glue-logic error in the CPU-FM module.");
|
||||
$finish;
|
||||
end
|
||||
`endif
|
||||
|
||||
// this runs at clk speed, no clock gating here
|
||||
// if I try to make this an async rst it fails to map it
|
||||
// as flip flops but uses latches instead. So I keep it as sync. reset
|
||||
|
||||
2
common/Sound/jtopl/jtopll.qip
Normal file
2
common/Sound/jtopl/jtopll.qip
Normal file
@@ -0,0 +1,2 @@
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) jt26.qip]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopll.v]
|
||||
Reference in New Issue
Block a user