github.com/Gehstock.Mist_FPGA
1
0
Fork 0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-02-03 15:12:39 +00:00
Code Issues Releases Wiki Activity

Donkey Kong: merge with DKJr

Browse Source
This commit is contained in:
Gyorgy Szombathelyi
2020-12-29 19:19:19 +01:00
parent 5f1ed68c38
commit 168e1d0312
10 changed files with 6441 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Arcade_MiST/Nintendo Radar Scope Hardware/Donkey Kong/DKong.qsf
View File

@@ -234,6 +234,7 @@ set_global_assignment -name USE_SIGNALTAP_FILE output_files/dl.stp
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dkong_MiST.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/dkong_top.v
set_global_assignment -name VERILOG_FILE rtl/dkong_dma.v
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VERILOG_FILE rtl/i8035ip.v
set_global_assignment -name VERILOG_FILE rtl/dkong_wav_sound.v

17
Arcade_MiST/Nintendo Radar Scope Hardware/Donkey Kong/README.txt
View File

@@ -2,10 +2,16 @@
--
-- Arcade: Donkey Kong port to MiST by Gehstock
-- 02 Mai 2019
--
--
-- Usage:
-- - Create ROM and ARC files from the MRA files using the MRA utility.
-- Example: mra -A -z /path/to/mame/roms "Donkey Kong.mra"
-- - Copy the ROM files to the root of the SD Card
-- - Copy the RBF and ARC files to the same folder on the SD Card
---------------------------------------------------------------------------------
-- A simulation model of Pacman hardware
-- // Copyright(c) 2003 - 2005 Katsumi Degawa , All rights reserved
-- FPGA DONKEY KONG TOP
-- Version : 4.00
-- Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
---------------------------------------------------------------------------------
--
-- Only Controls and OSD are rotated on Video output.
@@ -17,10 +23,7 @@
-- F2 : Start 2 players
-- F1 : Start 1 player
-- UP,DOWN,LEFT,RIGHT arrows : Movements
-- SPACE : Jump
-- CTRL : Jump
-- Joystick support.
---------------------------------------------------------------------------------
ToDo: Sound, Rotated Controls

6201
Arcade_MiST/Nintendo Radar Scope Hardware/Donkey Kong/meta/Donkey Kong Junior.mra Normal file
View File

File diff suppressed because it is too large Load Diff

3
Arcade_MiST/Nintendo Radar Scope Hardware/Donkey Kong/rtl/dkong_MiST.sv
View File

@@ -160,6 +160,7 @@ dkong_top dkong(
.I_S2(~m_two_players),
.I_C1(~m_coin1),
.I_DIP_SW(status[15:8]),
.I_DKJR(core_mod[0]),
.O_SOUND_DAT(audio),
.O_VGA_R(r),
.O_VGA_G(g),
@@ -212,6 +213,7 @@ wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire no_csync;
wire [6:0] core_mod;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
@@ -230,6 +232,7 @@ user_io(
.scandoubler_disable (scandoublerD),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.core_mod (core_mod ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),

43
Arcade_MiST/Nintendo Radar Scope Hardware/Donkey Kong/rtl/dkong_adec.v
View File

@@ -23,6 +23,7 @@ I_CLK24M,
I_CLK_EN_P,
I_CLK_EN_N,
I_RESET_n,
I_DKJR,
I_AB,
I_DB,
I_MREQ_n,
@@ -49,6 +50,7 @@ O_SW1_OE_n,
O_SW2_OE_n,
O_SW3_OE_n,
O_DIP_OE_n,
O_4H_Q,
O_5H_Q,
O_6H_Q,
O_3D_Q
@@ -59,6 +61,7 @@ input I_CLK24M;
input I_CLK_EN_P; // H_CNT[1] 3.072MHz
input I_CLK_EN_N;
input I_RESET_n;
input I_DKJR;
input [15:0]I_AB;
input [3:0]I_DB;
input I_MREQ_n;
@@ -83,9 +86,10 @@ output O_SW1_OE_n; // 7C00 H (R mode)
output O_SW2_OE_n; // 7C80 H (R mode)
output O_SW3_OE_n; // 7D00 H (R mode)
output O_DIP_OE_n; // 7D80 H (R mode)
output [1:0]O_4H_Q; // GFX (Characters) bank switch, sound
output [7:0]O_5H_Q; // FLIP,
output [7:0]O_6H_Q; // sound
output [3:0]O_3D_Q; // sound
output [4:0]O_3D_Q; // sound
output O_WAIT_n;
output O_NMI_n;
@@ -94,6 +98,7 @@ output O_NMI_n;
wire [3:0]W_2A1_Q,W_2A2_Q;
wire [7:0]W_4D_Q,W_2B_Q,W_2C_Q,W_2D_Q;
wire [7:0]W_1B_Q,W_1C_Q;
reg [1:0]W_4H_Q;
reg [7:0]W_5H_Q;
// CPU WAIT
@@ -139,7 +144,7 @@ logic_74xx138 U_4D(
);
assign O_ROM_CS_n = W_4D_Q[0]&W_4D_Q[1]&W_4D_Q[2]&W_4D_Q[3];
assign O_ROM_CS_n = I_DKJR ? &W_4D_Q[5:0] : &W_4D_Q[3:0];
// ADDR DEC 7000H - 7FFFH
@@ -236,6 +241,23 @@ logic_74xx138 U_1C(
);
//--- Parts 4H ---------
always@(posedge I_CLK24M or negedge I_RESET_n)
begin
if(I_RESET_n == 1'b0) begin
W_4H_Q <= 0;
end
else begin
if(W_1C_Q[1] == 1'b0) begin
case(I_AB[0])
3'h0 : W_4H_Q[0] <= I_DB[0]; // VROM signal
3'h1 : W_4H_Q[1] <= I_DB[0]; // SOUND 8035 PB6
endcase
end
end
end
//--- Parts 5H ---------
//reg [7:0]W_5H_Q;
@@ -284,18 +306,23 @@ begin
end
end
assign O_4H_Q = W_4H_Q;
assign O_5H_Q = W_5H_Q;
assign O_6H_Q = W_6H_Q;
// Parts 3D
reg [3:0]O_3D_Q;
reg [4:0]O_3D_Q;
always@(posedge W_1C_Q[0] or negedge I_RESET_n)
always@(posedge I_CLK24M or negedge I_RESET_n)
begin
if(! I_RESET_n) O_3D_Q <= 0;
else begin
O_3D_Q <= I_DB;
end
reg W_1C_Q0_D;
if(! I_RESET_n) O_3D_Q <= 0;
else begin
W_1C_Q0_D <= W_1C_Q[0];
if (!W_1C_Q0_D & W_1C_Q[0]) begin
O_3D_Q <= I_DB;
end
end
end

80
Arcade_MiST/Nintendo Radar Scope Hardware/Donkey Kong/rtl/dkong_dma.v Normal file
View File

@@ -0,0 +1,80 @@
//============================================================================
// Sprite DMA.
//
// Author: gaz68 (https://github.com/gaz68)
// October 2019
//
// Simplified sprite DMA. To Do: Implement full 8257 DMA controller.
// Added HRQ/HLDA - slingshot
//============================================================================
module dkong_dma
(
input I_CLK,
input I_CLK_EN,
input I_RSTn,
input I_DMA_TRIG,
input [7:0]I_DMA_DS,
input I_HLDA,
output reg O_HRQ,
output [9:0]O_DMA_AS,
output [9:0]O_DMA_AD,
output [7:0]O_DMA_DD,
output O_DMA_CES,
output O_DMA_CED
);
parameter dma_cnt_end = 10'h17F;
reg W_DMA_EN = 1'b0;
reg [10:0]W_DMA_CNT;
reg [7:0]W_DMA_DATA;
reg [9:0]DMA_ASr;
reg [9:0]DMA_ADr;
reg [7:0]DMA_DDr;
reg DMA_CESr, DMA_CEDr;
always @(posedge I_CLK)
if (I_CLK_EN) begin
reg old_trig;
old_trig <= I_DMA_TRIG;
if(~old_trig & I_DMA_TRIG)
begin
DMA_ASr <= 10'h100;
DMA_ADr <= 0;
W_DMA_CNT <= 0;
W_DMA_EN <= 1'b1;
DMA_CESr <= 1'b1;
DMA_CEDr <= 1'b1;
O_HRQ <= 1'b1;
end
else if(W_DMA_EN) begin
if (I_HLDA) begin
case(W_DMA_CNT[1:0])
1: DMA_DDr <= I_DMA_DS;
2: DMA_ASr <= DMA_ASr + 1'd1;
3: DMA_ADr <= DMA_ADr + 1'd1;
default:;
endcase
W_DMA_CNT <= W_DMA_CNT + 1'd1;
W_DMA_EN <= W_DMA_CNT==dma_cnt_end*4 ? 1'b0 : 1'b1;
end
end else
begin
O_HRQ <= 1'b0;
DMA_CESr <= 1'b0;
DMA_CEDr <= 1'b0;
end
end
assign O_DMA_AS = DMA_ASr;
assign O_DMA_AD = DMA_ADr;
assign O_DMA_DD = DMA_DDr;
assign O_DMA_CES = DMA_CESr;
assign O_DMA_CED = DMA_CEDr;
endmodule

19
Arcade_MiST/Nintendo Radar Scope Hardware/Donkey Kong/rtl/dkong_sound.v
View File

@@ -20,6 +20,7 @@
module dkong_sound(
input I_CLK,
input I_RST,
input I_DKJR,
input [7:0]I8035_DBI,
output [7:0]I8035_DBO,
input [7:0]I8035_PAI,
@@ -28,8 +29,8 @@ module dkong_sound(
input I8035_ALE,
input I8035_RDn,
input I8035_PSENn,
input [3:0]I_SOUND_DAT,
input [3:0]I_SOUND_CNT,
input [4:0]I_SOUND_DAT,
input [5:0]I_SOUND_CNT,
output I8035_INTn,
output I8035_T0,
output I8035_T1,
@@ -39,14 +40,16 @@ module dkong_sound(
input [7:0] ROM_D
);
assign I8035_PBO[6] = ~I_SOUND_CNT[5];
assign I8035_PBO[4] = ~I_SOUND_CNT[4];
assign I8035_T0 = ~I_SOUND_CNT[3];
assign I8035_T1 = ~I_SOUND_CNT[2];
assign I8035_PBO[5] = ~I_SOUND_CNT[1];
assign I8035_INTn = ~I_SOUND_CNT[0];
assign I8035_RSTn = I_RST;
assign I8035_PBO[4:0] = 5'b00000;
assign I8035_PBO[7:6] = 2'b00;
assign I8035_PBO[3:0] = 4'b0000;
assign I8035_PBO[7] = 1'b0;
//---- Parts 4FH -----------------------------
wire [10:0]S_ROM_A;
reg [7:0]L_ROM_A;
@@ -58,13 +61,13 @@ always@(posedge I_CLK) begin
if (!I8035_ALE & I8035_ALE_D) L_ROM_A <= I8035_DBI;
end
assign S_ROM_A = {I8035_PBI[2:0],L_ROM_A[7:0]};
assign ROM_A = {~I8035_PBI[6],I8035_PBI[2:0],L_ROM_A[7:0]};
assign ROM_A = {I_DKJR ? I8035_PBI[3] : I8035_PSENn,S_ROM_A};
//---- Parts 4C ------------------------------
reg S_D1_CS;
always@(posedge I_CLK) S_D1_CS <= I8035_PBI[6]&(~I8035_RDn);
always@(posedge I_CLK) S_D1_CS <= (I_DKJR | I8035_PBI[6])&(~I8035_RDn);
wire [7:0]S_D1 = S_D1_CS ? {4'h0,~I_SOUND_DAT[3:0]}: 8'h00 ;
wire [7:0]S_D1 = S_D1_CS ? {3'h0,~I_SOUND_DAT[4:0]}: 8'h00 ;
wire [7:0]S_PROG_DB;
wire [7:0]S_PROG_D = I8035_PSENn ? 8'h00 : S_PROG_DB ;
@@ -78,7 +81,7 @@ snd1 snd1 (
assign S_PROG_DB = ROM_D;
//---- DATA ROM 3H ---------------------------
wire S_D2_CS = (~I8035_PBI[6])&(~I8035_RDn);
wire S_D2_CS = (~I_DKJR & ~I8035_PBI[6])&(~I8035_RDn);
wire [7:0]S_DB2;
wire [7:0]S_D2 = S_D2_CS ? S_DB2 : 8'h00 ;

37
Arcade_MiST/Nintendo Radar Scope Hardware/Donkey Kong/rtl/dkong_soundboard.sv
View File

@@ -1,17 +1,19 @@
module dkong_soundboard(
input W_RESETn,
input W_CLK_24576M,
input W_W0_WE,
input W_W1_WE,
input W_CNF_EN,
input [5:0] W_6H_Q,
input W_5H_Q,
input W_3D_Q,
output [15:0] O_SOUND_DAT,
output [11:0] ROM_A,
input [7:0] ROM_D,
output [18:0] WAV_ROM_A,
input [7:0] WAV_ROM_DO
input W_CLK_24576M,
input W_RESETn,
input I_DKJR,
input W_W0_WE,
input W_W1_WE,
input W_CNF_EN,
input [6:0] W_6H_Q,
input W_5H_Q0,
input [1:0] W_4H_Q,
input [4:0] W_3D_Q,
output [15:0] O_SOUND_DAT,
output [11:0] ROM_A,
input [7:0] ROM_D,
output [18:0] WAV_ROM_A,
input [7:0] WAV_ROM_DO
);
wire [7:0]W_D_S_DAT;
@@ -64,6 +66,7 @@ dkong_sound Digtal_sound
(
.I_CLK(W_CLK_24576M),
.I_RST(W_RESETn),
.I_DKJR(I_DKJR),
.I8035_DBI(I8035_DBI),
.I8035_DBO(I8035_DBO),
.I8035_PAI(I8035_PAI),
@@ -76,8 +79,8 @@ dkong_sound Digtal_sound
.I8035_INTn(I8035_INTn),
.I8035_T0(I8035_T0),
.I8035_T1(I8035_T1),
.I_SOUND_DAT(W_3D_Q),
.I_SOUND_CNT({W_6H_Q[5:3],W_5H_Q}),
.I_SOUND_DAT(I_DKJR ? ~W_3D_Q : {1'b1, W_3D_Q[3:0]}),
.I_SOUND_CNT(I_DKJR ? {W_4H_Q[1],W_6H_Q[6:3],W_5H_Q0} : {2'b11,W_6H_Q[5:3],W_5H_Q0}),
.O_SOUND_DAT(W_D_S_DAT),
.ROM_A(ROM_A),
.ROM_D(ROM_D)
@@ -90,11 +93,11 @@ dkong_wav_sound Analog_sound
.I_CLK(W_CLK_24576M),
.I_RSTn(W_RESETn),
.I_SW(W_6H_Q[2:0])
.I_SW(I_DKJR ? 3'b000 : W_6H_Q[2:0])
);
// SOUND MIXER (WAV + DIG ) -----------------------
wire [8:0]sound_mix = {1'b0, WAV_ROM_DO} + {1'b0, W_D_S_DAT};
wire [8:0]sound_mix = {1'b0, I_DKJR ? 8'd0 : WAV_ROM_DO} + {1'b0, W_D_S_DAT};
assign O_SOUND_DAT = sound_mix[8:1];

86
Arcade_MiST/Nintendo Radar Scope Hardware/Donkey Kong/rtl/dkong_top.v
View File

@@ -11,6 +11,7 @@
// An author does no guarantee about this program.
// You can use this under your own risk.
//
// 2020-12-28 converted a big part to totally syncronous logic (by slingshot)
// 2004- 3- 3 first release.
// 2004- 6- 8 Quartus2 v4.0sp1 used (bug fix) K.Degawa
// 2004- 8-24 T80-IP was include. K.Degawa
@@ -34,6 +35,7 @@ module dkong_top
input I_S1,I_S2,I_C1,
input [7:0] I_DIP_SW,
input I_DKJR,
// VGA (VIDEO) IF
output [2:0]O_VGA_R,
@@ -52,7 +54,7 @@ module dkong_top
input DL_WR,
input [7:0] DL_DATA,
output [15:0] MAIN_CPU_A,
output reg [15:0] MAIN_CPU_A,
input [7:0] MAIN_CPU_DO,
output [11:0] SND_ROM_A,
input [7:0] SND_ROM_DO,
@@ -92,9 +94,10 @@ wire W_SW2_OEn ;
wire W_SW3_OEn ;
wire W_DIP_OEn ;
wire [1:0]W_4H_Q;
wire [7:0]W_5H_Q;
wire [7:0]W_6H_Q;
wire [3:0]W_3D_Q;
wire [4:0]W_3D_Q;
// RAM DATA
wire [7:0]W_RAM1_DO;
@@ -121,6 +124,8 @@ wire W_CPU_M1n;
wire W_CPU_NMIn;
wire W_CPU_IORQn;
wire W_CPU_MREQn;
wire W_CPU_BUSRQ;
wire W_CPU_BUSAKn;
wire W_CPU_RDn;
wire W_CPU_WRn;
wire [15:0]W_CPU_A;
@@ -138,7 +143,8 @@ wire W_CPU_CLK_EN_N = W_H_CNT[1:0] == 2'b11;
.WAIT_n(W_CPU_WAITn | (W_CPU_IORQn & W_CPU_MREQn)),
.INT_n(1'b1),
.NMI_n(W_CPU_NMIn),
.BUSRQ_n(1'b1),
.BUSRQ_n(~W_CPU_BUSRQ),
.BUSAK_n(W_CPU_BUSAKn),
.M1_n(W_CPU_M1n),
.IORQ_n(W_CPU_IORQn),
.MREQ_n(W_CPU_MREQn),
@@ -167,7 +173,20 @@ prog ROM(
.data(WB_ROM_DO)
);
*/
assign MAIN_CPU_A = W_CPU_A[13:0];
//assign MAIN_CPU_A = W_CPU_A[13:0];
always @(*) begin
case({!I_DKJR, W_CPU_A[15:11]})
6'h02: MAIN_CPU_A = {5'h06,W_CPU_A[10:0]}; // 0x1000-0x17FF -> 0x3000-0x37FF in ROM file
6'h03: MAIN_CPU_A = {5'h0B,W_CPU_A[10:0]}; // 0x1800-0x1FFF -> 0x5800-0x5FFF in ROM file
6'h05: MAIN_CPU_A = {5'h09,W_CPU_A[10:0]}; // 0x2800-0x2FFF -> 0x4800-0x4FFF in ROM file
6'h06: MAIN_CPU_A = {5'h02,W_CPU_A[10:0]}; // 0x3000-0x37FF -> 0x1000-0x17FF in ROM file
6'h07: MAIN_CPU_A = {5'h03,W_CPU_A[10:0]}; // 0x3800-0x3FFF -> 0x1800-0x1FFF in ROM file
6'h09: MAIN_CPU_A = {5'h05,W_CPU_A[10:0]}; // 0x4800-0x4FFF -> 0x2800-0x2FFF in ROM file
6'h0B: MAIN_CPU_A = {5'h07,W_CPU_A[10:0]}; // 0x5800-0x5FFF -> 0x3800-0x3FFF in ROM file
default: MAIN_CPU_A = W_CPU_A[15:0];
endcase
end
assign WB_ROM_DO = MAIN_CPU_DO;
//======== INT RAM Interface ==================================================
@@ -192,9 +211,17 @@ ram_1024_8 U_3B4B
.O_D(W_RAM2_DO)
);
//---- DMA ------------------------------------------
wire [1:0]W_OBJ_A_offset = W_H_CNT[8]+1'd1;
wire [9:0]W_OBJ_AB = {W_OBJ_A_offset[1:0],W_H_CNT[7:0]};
//=============== Sprite DMA ======================
wire [9:0]W_OBJ_AB = {W_2PSL, W_H_CNT[8:0]};
wire [9:0]W_DMA_A;
wire [7:0]W_DMA_D;
wire W_DMA_CE;
wire [9:0]W_DMA_AB;
wire [7:0]W_DMA_DB;
wire W_DMA_CEB;
ram_1024_8_8 U_3A4A
(
@@ -206,7 +233,41 @@ ram_1024_8_8 U_3A4A
.I_WEA(~W_CPU_WRn),
.O_DA(W_RAM3_DO),
// B Port
.I_CLKB(W_CLK_12288M),
.I_CLKB(I_CLK_24576M),
.I_ADDRB(W_DMA_A),
.I_DB(8'h00),
.I_CEB(W_DMA_CE),
.I_WEB(1'b0),
.O_DB(W_DMA_D)
);
dkong_dma sprite_dma
(
.I_CLK(I_CLK_24576M),
.I_CLK_EN(W_CPU_CLK_EN_P),// 3.072 Mhz
.I_DMA_TRIG(W_DREQ),
.I_DMA_DS(W_DMA_D),
.I_HLDA(~W_CPU_BUSAKn),
.O_HRQ(W_CPU_BUSRQ),
.O_DMA_AS(W_DMA_A),
.O_DMA_AD(W_DMA_AB),
.O_DMA_DD(W_DMA_DB),
.O_DMA_CES(W_DMA_CE),
.O_DMA_CED(W_DMA_CEB)
);
ram_1024_8_8 U_6PR
(
// A Port
.I_CLKA(I_CLK_24576M),
.I_ADDRA(W_DMA_AB),
.I_DA(W_DMA_DB),
.I_CEA(W_DMA_CEB),
.I_WEA(1'b1),
.O_DA(),
// B Port
.I_CLKB(I_CLK_24576M),
.I_ADDRB(W_OBJ_AB[9:0]),
.I_DB(8'h00),
.I_CEB(1'b1),
@@ -214,6 +275,7 @@ ram_1024_8_8 U_3A4A
.O_DB(W_OBJ_DI)
);
//=========== SW Interface ========================================================
wire [7:0]W_SW1 = W_SW1_OEn ? 8'h00: ~{1'b1,1'b1,1'b1,I_J1,I_D1,I_U1,I_L1,I_R1};
wire [7:0]W_SW2 = W_SW2_OEn ? 8'h00: ~{1'b1,1'b1,1'b1,I_J2,I_D2,I_U2,I_L2,I_R2};
wire [7:0]W_SW3 = W_SW3_OEn ? 8'h00: ~{I_C1,1'b1,1'b1,1'b1,I_S2,I_S1,1'b1,1'b1};
@@ -230,6 +292,7 @@ dkong_adec adec
.I_CLK_EN_P(W_CPU_CLK_EN_P),
.I_CLK_EN_N(W_CPU_CLK_EN_N),
.I_RESET_n(W_RESETn),
.I_DKJR(I_DKJR),
.I_AB(W_CPU_A),
.I_DB(WI_D),
.I_MREQ_n(W_CPU_MREQn),
@@ -255,6 +318,7 @@ dkong_adec adec
.O_SW2_OE_n(W_SW2_OEn),
.O_SW3_OE_n(W_SW3_OEn),
.O_DIP_OE_n(W_DIP_OEn),
.O_4H_Q(W_4H_Q),
.O_5H_Q(W_5H_Q),
.O_6H_Q(W_6H_Q),
.O_3D_Q(W_3D_Q)
@@ -262,6 +326,7 @@ dkong_adec adec
wire W_FLIPn = W_5H_Q[2];
wire W_2PSL = W_5H_Q[3];
wire W_DREQ = W_5H_Q[5]; // DMA Trigger
//=========== VIDEO MODULE ( Donkey Kong ) ===================================
//======== Assign Wire =========================================================
@@ -337,6 +402,7 @@ dkong_vram vram
.I_H_CNT(W_H_CNT),
.I_VF_CNT(W_VF_CNT),
.I_CMPBLK(W_C_BLANKn),
.I_4H_Q0(W_4H_Q[0]),
// Debug output
.O_DB(W_VRAM_DB),
.O_COL(W_VRAM_COL),
@@ -373,9 +439,11 @@ dkong_col_pal cpal
dkong_soundboard dkong_soundboard(
.W_CLK_24576M(W_CLK_24576M),
.W_RESETn(W_RESETn),
.I_DKJR(I_DKJR),
.O_SOUND_DAT(O_SOUND_DAT),
.W_6H_Q(W_6H_Q),
.W_5H_Q(W_5H_Q),
.W_5H_Q0(W_5H_Q[0]),
.W_4H_Q(W_4H_Q),
.W_3D_Q(W_3D_Q),
.ROM_A(SND_ROM_A),
.ROM_D(SND_ROM_DO),

5
Arcade_MiST/Nintendo Radar Scope Hardware/Donkey Kong/rtl/dkong_vram.v
View File

@@ -38,6 +38,7 @@ module dkong_vram(
input [9:0]I_H_CNT,
input [7:0]I_VF_CNT,
input I_CMPBLK,
input I_4H_Q0,
output [7:0]O_DB,
output reg [3:0]O_COL,
output [1:0]O_VID,
@@ -182,7 +183,7 @@ vid1 vid1 (
*/
dpram #(12,8) vid1 (
.clock_a(CLK_24M),
.address_a({1'b0,WO_DB[7:0],I_VF_CNT[2:0]}),
.address_a({I_4H_Q0,WO_DB[7:0],I_VF_CNT[2:0]}),
.q_a(W_3P_DO),
.clock_b(CLK_24M),
@@ -199,7 +200,7 @@ vid2 vid2 (
*/
dpram #(12,8) vid2 (
.clock_a(CLK_24M),
.address_a({1'b0,WO_DB[7:0],I_VF_CNT[2:0]}),
.address_a({I_4H_Q0,WO_DB[7:0],I_VF_CNT[2:0]}),
.q_a(W_3N_DO),
.clock_b(CLK_24M),