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Mappy HW: single RBF + MRA + common CPU

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Gyorgy Szombathelyi 2020-02-12 20:52:04 +01:00
parent a224f2554f
commit 174c2644a0
13 changed files with 317 additions and 4588 deletions
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6
Arcade_MiST/Namco Mappy Hardware/Mappy_Hardware.qsf
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@ -40,7 +40,7 @@
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
@ -228,9 +228,9 @@ set_global_assignment -name VERILOG_FILE rtl/wsg.v
set_global_assignment -name VERILOG_FILE rtl/ioctrl.v
set_global_assignment -name VERILOG_FILE rtl/hvgen.v
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VERILOG_FILE rtl/mc6809/mc6809i.v
set_global_assignment -name VERILOG_FILE rtl/mc6809/mc6809.v
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE ../../common/CPU/MC6809/mc6809i.v
set_global_assignment -name VERILOG_FILE ../../common/CPU/MC6809/mc6809.v
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

18
Arcade_MiST/Namco Mappy Hardware/README.txt
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@ -1,13 +1,15 @@
The Tower of Druaga/Mappy/Motos/DigDug II to Mist FPGA by Slingshot
Appropriate ROMs are required at the root of the SD Card:
DRUAGA.ROM
MAPPY.ROM
MOTOS.ROM
DIGDUG2.ROM
-- Usage:
-- - Create ROM and ARC files from the MRA files in the meta directory
-- using the MRA utility.
-- Example: mra -A -z /path/to/mame/roms motos.mra
-- - Copy the ROM files to the root of the SD Card
-- - Copy the RBF and ARC files to the same folder on the SD Card
--
-- MRA utility: https://github.com/sebdel/mra-tools-c/
--
--
---------------------------------------------------------------------------------
--
-- Arcade: The Tower of Druaga port to MiSTer by MiSTer-X

28
Arcade_MiST/Namco Mappy Hardware/meta/digdug2.mra Normal file
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@ -0,0 +1,28 @@
<misterromdescription>
<name>Dig Dug 2</name>
<setname>digdug2</setname>
<rbf>Druaga</rbf>
<switches>
<dip bits="19" name="Lives" ids="3,5"/>
<dip bits="20,21" name="Extend" ids="30k/80k,30k/100k,30k/120k,30k/150k"/>
<dip bits="22" name="Level Select" ids="Off,On"/>
</switches>
<rom index="1">
<part>03</part>
</rom>
<rom index="0" zip="digdug2.zip" md5="2e652e5d6a114b7bd21a96e954b7f148">
<part name="d23_3.1d"/>
<part name="d23_1.1b"/>
<part name="d21_6.3m"/>
<part name="d21_7.3n"/>
<part name="d21_4.1k"/>
<part name="d21_5.3b"/>
<part name="d21-7.5k"/>
<part name="d21-7.5k"/>
<part name="d21-7.5k"/>
<part name="d21-7.5k"/>
<part name="d21-6.4c"/>
<part name="d21-3.3m"/>
<part name="d21-5.5b"/>
</rom>
</misterromdescription>

25
Arcade_MiST/Namco Mappy Hardware/meta/druaga.mra Normal file
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@ -0,0 +1,25 @@
<misterromdescription>
<name>The Tower of Druaga</name>
<setname>druaga</setname>
<rbf>Druaga</rbf>
<switches>
<dip bits="8,9" name="Lives" ids="3,2,1,5"/>
</switches>
<rom index="1">
<part>01</part>
</rom>
<rom index="0" zip="todruaga.zip" md5="ef0d64d4d3fc4f594389d2b28c677c20">
<part name="td2_3.1d"/>
<part name="td2_1.1b"/>
<part name="td1_6.3m"/>
<part name="td1_6.3m"/>
<part name="td1_7.3n"/>
<part name="td1_7.3n"/>
<part name="td1_4.1k"/>
<part name="td1_5.3b"/>
<part name="td1-7.5k"/>
<part name="td1-6.4c"/>
<part name="td1-3.3m"/>
<part name="td1-5.5b"/>
</rom>
</misterromdescription>

34
Arcade_MiST/Namco Mappy Hardware/meta/mappy.mra Normal file
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@ -0,0 +1,34 @@
<misterromdescription>
<name>Mappy</name>
<setname>mappy</setname>
<switches>
<dip bits="10,12" name="Rank" ids="A,B,C,D,E,F,G,H"/>
<dip bits="17,18" name="Lives" ids="3,5,1,2"/>
<dip bits="14,16" name="Extend" ids="M1,M2,M3,M4,M5,M6,M7,None"/>
<dip bits="13" name="Demo Sound" ids="On,Off"/>
<dip bits="6" name="Round Progress" ids="Off,On"/>
</switches>
<rbf>Druaga</rbf>
<rom index="1">
<part>02</part>
</rom>
<rom index="0" zip="mappy.zip" md5="b276d97b0dc61ca668d140793fac44bf">
<part name="mpx_3.1d"/>
<part name="mpx_3.1d"/>
<part name="mp1_2.1c"/>
<part name="mpx_1.1b"/>
<part name="mp1_6.3m"/>
<part name="mp1_6.3m"/>
<part name="mp1_7.3n"/>
<part name="mp1_7.3n"/>
<part name="mp1_4.1k"/>
<part name="mp1_5.3b"/>
<part name="mp1-7.5k"/>
<part name="mp1-7.5k"/>
<part name="mp1-7.5k"/>
<part name="mp1-7.5k"/>
<part name="mp1-6.4c"/>
<part name="mp1-3.3m"/>
<part name="mp1-5.5b"/>
</rom>
</misterromdescription>

29
Arcade_MiST/Namco Mappy Hardware/meta/motos.mra Normal file
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@ -0,0 +1,29 @@
<misterromdescription>
<name>Motos</name>
<setname>motos</setname>
<rbf>Druaga</rbf>
<switches>
<dip bits="24" name="Rank" ids="A,B"/>
<dip bits="23" name="Lives" ids="3,5"/>
<dip bits="25,26" name="Extend" ids="10k/30k/ev.50k,20k/ev.50k,30k/ev.70k,20k/70k"/>
<dip bits="27" name="Demo Sound" ids="On,Off"/>
</switches>
<rom index="1">
<part>04</part>
</rom>
<rom index="0" zip="motos.zip" md5="446203961cff53598233d2c50db390d8">
<part name="mo1_3.1d"/>
<part name="mo1_1.1b"/>
<part name="mo1_6.3m"/>
<part name="mo1_7.3n"/>
<part name="mo1_4.1k"/>
<part name="mo1_5.3b"/>
<part name="mo1-7.5k"/>
<part name="mo1-7.5k"/>
<part name="mo1-7.5k"/>
<part name="mo1-7.5k"/>
<part name="mo1-6.4c"/>
<part name="mo1-3.3m"/>
<part name="mo1-5.5b"/>
</rom>
</misterromdescription>

244
Arcade_MiST/Namco Mappy Hardware/rtl/TheTowerofDruaga_mist.sv
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@ -28,28 +28,99 @@ module TheTowerofDruaga_mist (
);
// Uncomment one of these to load the default ROM:
`define CORE_NAME "DRUAGA"
//`define CORE_NAME "MAPPY"
//`define CORE_NAME "MOTOS"
//`define CORE_NAME "DIGDUG2"
//`define CORE_NAME "GROBDA"
//`define CORE_NAME "PHOZON"
`include "rtl\build_id.v"
`define CORE_NAME "DRUAGA"
wire [6:0] core_mod;
localparam CONF_STR = {
`CORE_NAME,";ROM;",
`CORE_NAME, ";ROM;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blend,Off,On;",
"DIP;",
"OU,Service Mode,Off,On;",
"OT,Freeze,Off,On;",
"T0,Reset;",
"V,v1.00.",`BUILD_DATE
};
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire dcFreeze = status[29];
wire dcService = status[30];
wire dcCabinet = 1'b0; // (upright only)
// The Tower of Druaga [t]
wire [1:0] dtLives = status[9:8];
// Mappy [m]
wire dmRoundP = status[6];
wire [2:0] dmRank = status[12:10];
wire dmDemoSnd = status[13];
wire [2:0] dmExtend = status[16:14];
wire [1:0] dmLives = status[18:17];
// DigDug2 [d]
wire ddLives = status[19];
wire [1:0] ddExtend = status[21:20];
wire ddLevelSel = status[22];
// Motos [o]
wire doLives = status[23];
wire doRank = status[24];
wire [1:0] doExtend = status[26:25];
wire doDemoSnd = status[27];
reg [7:0] DSW0;
reg [7:0] DSW1;
reg [7:0] DSW2;
reg [5:0] INP0;
reg [5:0] INP1;
reg [2:0] INP2;
always @(*) begin
INP0 = { m_fireB, m_fireA, m_left, m_down, m_right, m_up};
INP1 = { m_fire2B, m_fire2A, m_left2, m_down2, m_right2, m_up2 };
INP2 = { m_coin1 | m_coin2, m_two_players, m_one_player };
DSW0 = 0;
DSW1 = 0;
DSW2 = 0;
case (core_mod)
7'h0, 7'h1: // DRUAGA
begin
DSW0 = {2'd0,dtLives,4'd0};
DSW1 = {dcCabinet,6'd0,dcFreeze};
DSW2 = {DSW1[3:0],dcService,3'd0};
end
7'h2: // MAPPY
begin
DSW0 = {dcFreeze,dmRoundP,dmDemoSnd,2'd0,dmRank};
DSW1 = {dmLives,dmExtend,3'd0};
DSW2 = {{2{dcService,dcCabinet,2'd0}}};
end
7'h3: // DIGDUG2
begin
DSW0 = {2'd0,ddLives,5'd0};
DSW1 = {dcCabinet,3'd0,dcFreeze,ddLevelSel,ddExtend};
DSW2 = {DSW1[3:0],dcService,3'd0};
end
7'h4: // MOTOS
begin
DSW0 = {doDemoSnd,doExtend,doRank,doLives,3'd0};
DSW1 = {dcService,dcCabinet,6'd0};
DSW2 = {8'd0};
end
7'h5: ;// GROBDA
7'h6: ;// PHOZON
default: ;
endcase
end
assign LED = ~ioctl_downl;
assign AUDIO_R = AUDIO_L;
assign SDRAM_CLK = clock_48;
@ -70,24 +141,50 @@ wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [7:0] audio;
wire hs, vs;
wire hb, vb;
wire blankn = ~(hb | vb);
wire [2:0] r, g;
wire [1:0] b;
wire [14:0] rom_addr;
wire [15:0] rom_do;
wire [12:0] snd_addr;
wire [15:0] snd_do;
wire no_csync;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
user_io #(.STRLEN($size(CONF_STR)>>3))user_io(
.clk_sys (clock_48 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.core_mod (core_mod ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
/*
ROM map
00000-07FFF cpu0 32k 3.1d+1.1b (+2.1c in Mappy)
08000-0BFFF spchip0 16k 6.3m
0C000-0FFFF spchip1 16k 7.3m
10000-11FFF cpu1 8k 4.1k
12000-12FFF bgchip 4k 5.3b
13000-133FF spclut 1k 7.5k
13400-134FF bgclut 256b 6.4c
13500-135FF wave 256b 3.3m
13600-1361F palet 32b 5.5b
*/
data_io data_io(
.clk_sys ( clock_48 ),
@ -102,6 +199,11 @@ data_io data_io(
);
reg port1_req, port2_req;
wire [14:0] rom_addr;
wire [15:0] rom_do;
wire [12:0] snd_addr;
wire [15:0] snd_do;
sdram sdram(
.*,
.init_n ( pll_locked ),
@ -154,17 +256,16 @@ always @(posedge clock_48) begin
reset <= status[0] | buttons[1] | ioctl_downl | ~rom_loaded;
end
wire [7:0] DSW0 = 0;//{2'h0,status[7:6],4'h0};
wire [7:0] DSW1 = 0;
wire [7:0] DSW2 = 0;//{4'h0,status[8],3'h0};
wire [5:0] INP0 = { m_bomb, m_fire, m_left, m_down, m_right, m_up};
wire [5:0] INP1 = { m_bomb, m_fire, m_left, m_down, m_right, m_up};
wire [2:0] INP2 = { btn_coin, btn_two_players, btn_one_player };
wire PCLK, PCLK_EN;
wire [8:0] HPOS,VPOS;
wire [7:0] audio;
wire hs, vs;
wire hb, vb;
wire blankn = ~(hb | vb);
wire [2:0] r, g;
wire [1:0] b;
fpga_druaga fpga_druaga(
.MCLK(clock_48),
.CLKCPUx2(clock_6),
@ -218,32 +319,13 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.rotate ( {1'b1,status[2]} ),
.rotate ( { 1'b1, rotate } ),
.scandoubler_disable( scandoublerD ),
.scanlines ( status[4:3] ),
.blend ( status[5] ),
.scanlines ( scanlines ),
.blend ( blend ),
.ypbpr ( ypbpr )
);
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
.clk_sys (clock_48 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(.C_bits(16))dac(
.clk_i(clock_48),
.res_n_i(1),
@ -251,40 +333,24 @@ dac #(.C_bits(16))dac(
.dac_o(AUDIO_L)
);
// Rotated Normal
wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
//reg btn_fire3 = 0;
reg btn_coin = 0;
always @(posedge clock_48) begin
if(key_strobe) begin
case(key_code)
'h75: btn_up <= key_pressed; // up
'h72: btn_down <= key_pressed; // down
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
// 'h14: btn_fire3 <= key_pressed; // ctrl
'h11: btn_fire2 <= key_pressed; // alt
'h29: btn_fire1 <= key_pressed; // Space
endcase
end
end
arcade_inputs inputs (
.clk ( clock_48 ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( 2'b11 ),
.joyswap ( 1'b0 ),
.oneplayer ( 1'b1 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
endmodule

50
Arcade_MiST/Namco Mappy Hardware/rtl/ioctrl_0.v
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@ -1,40 +1,32 @@
//------------------------------------------
// I/O Chip for "Mappy/Druaga/DigDug2"
//
// Copyright (c) 2007 MiSTer-X
// Copyright (c) 2007,19 MiSTer-X
//------------------------------------------
// TODO: DSW2 = DIPSW[23:16]
case ( mema[4'h8] )
4'h1: begin
mema[4'h0] <= 0;
mema[4'h1] <= 0;
mema[4'h2] <= 0;
mema[4'h3] <= 0;
end
4'h3: begin
4'h1,4'h3: begin
credit_add = 0;
credit_sub = 0;
if ( iCSTART12[2] & ( credits < 99 ) ) begin
credit_add = 8'h01;
credits = credits + 1'd1;
credits = credits + 1;
end
if ( mema[4'h9] == 0 ) begin
if ( ( credits >= 2 ) & iCSTART12[1] ) begin
credit_sub = 8'h02;
credits = credits - 2'd1;
credits = credits - 2;
end else if ( ( credits >= 1 ) & iCSTART12[0] ) begin
credit_sub = 8'h01;
credits = credits - 1'd1;
credits = credits - 1;
end
end
mema[4'h0] <= credit_add;
mema[4'h1] <= credit_sub;
mema[4'h1] <= credit_sub | {7'd0,CSTART12[0]};
mema[4'h2] <= CREDIT_TENS;
mema[4'h3] <= CREDIT_ONES;
mema[4'h4] <= STKTRG12[3:0];
@ -65,21 +57,14 @@
mema[4'h7] <= 4'hD;
end
default: begin end
default:;
endcase
case ( memb[4'h8] )
4'h1: begin
memb[4'h0] <= 0;
memb[4'h1] <= 0;
memb[4'h2] <= 0;
memb[4'h3] <= 0;
end
4'h3: begin
4'h1,4'h3: begin
memb[4'h0] <= 0;
memb[4'h1] <= 0;
memb[4'h2] <= 0;
@ -91,15 +76,18 @@
end
4'h4: begin
memb[4'h0] <= DIPSW[11:8];
memb[4'h1] <= DIPSW[3:0];
memb[4'h2] <= DIPSW[7:4];
memb[4'h4] <= DIPSW[15:12];
memb[4'h6] <= DIPSW[7:4];
memb[4'h0] <= DIPSW[11: 8]; // (P0) DSW1 Mappy
memb[4'h1] <= DIPSW[15:12];
memb[4'h2] <= DIPSW[ 3: 0]; // (P1) DSW0
memb[4'h4] <= DIPSW[ 7: 4];
memb[4'h5] <={DIPSW[15:14],STKTRG12[ 5],iSTKTRG12[ 5]}; // (P2) DSW1 Druaga/DigDug2
memb[4'h6] <= DIPSW[23:20]; // IsMappy ? DIPSW[19:16] : DIPSW[11:8]
memb[4'h7] <={DIPSW[19:18],STKTRG12[11],iSTKTRG12[11]}; // (P3) DSW2
memb[4'h3] <= 0;
memb[4'h5] <= { DIPSW[3:2], STKTRG12[ 5], iSTKTRG12[ 5] };
memb[4'h7] <= { 2'b00, STKTRG12[11], iSTKTRG12[11] };
end
4'h5: begin
@ -113,7 +101,7 @@
memb[4'h7] <= 4'hD;
end
default: begin end
default:;
endcase

23
Arcade_MiST/Namco Mappy Hardware/rtl/ioctrl_1.v
View File

@ -1,17 +1,21 @@
//------------------------------------------
// I/O Chip for "Motos"
//
// Copyright (c) 2007 MiSTer-X
// Copyright (c) 2007,19 MiSTer-X
//------------------------------------------
// TODO: DSW2 = DIPSW[23:16]
case ( mema[4'h8] )
4'h1: begin
mema[4'h0] <= { 3'b00, CSTART12[2] };
mema[4'h0] <= { 3'd0, CSTART12[2] };
mema[4'h1] <= STKTRG12[3:0];
mema[4'h2] <= STKTRG12[9:6];
mema[4'h3] <= { CSTART12[1], CSTART12[0], STKTRG12[10], STKTRG12[4] };
mema[4'h4] <= STKTRG12[9:6];
mema[4'h5] <= STKTRG12[9:6];
mema[4'h6] <= STKTRG12[9:6];
mema[4'h7] <= STKTRG12[9:6];
mema[4'h9] <= 0;
end
4'h8: begin
@ -19,8 +23,8 @@
mema[4'h1] <= 4'h9;
end
default: begin end
default:;
endcase
@ -32,17 +36,18 @@
end
4'h9: begin
memb[4'h2] <= DIPSW[3:0];
memb[4'h4] <= DIPSW[7:4];
memb[4'h6] <= DIPSW[15:12];
memb[4'h0] <= 0;
memb[4'h1] <= 0;
memb[4'h2] <= 0;
memb[4'h3] <= 0;
memb[4'h4] <= 0;
memb[4'h5] <= 0;
memb[4'h6] <= 0;
memb[4'h7] <= 0;
end
default: begin end
default:;
endcase

80
Arcade_MiST/Namco Mappy Hardware/rtl/mc6809/mc6809.v
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@ -1,80 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:11:34 09/23/2016
// Design Name:
// Module Name: mc6809e
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mc6809(
input [7:0] D,
output [7:0] DOut,
output [15:0] ADDR,
output RnW,
output E,
output Q,
output BS,
output BA,
input nIRQ,
input nFIRQ,
input nNMI,
input EXTAL,
input XTAL,
input nHALT,
input nRESET,
input MRDY,
input nDMABREQ
, output [111:0] RegData
);
reg [1:0] clk_phase=2'b00;
wire CLK;
assign CLK=EXTAL;
wire LIC;
wire BUSY;
wire AVMA;
reg rE;
reg rQ;
assign E = rE;
assign Q = rQ;
mc6809i cpucore(.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ),
.nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESET), .nDMABREQ(nDMABREQ)
,.RegData(RegData)
);
always @(negedge CLK)
begin
case (clk_phase)
2'b00:
rE <= 0;
2'b01:
rQ <= 1;
2'b10:
rE <= 1;
2'b11:
rQ <= 0;
endcase
if (MRDY == 1'b1)
clk_phase <= clk_phase + 2'b01;
end
endmodule

4156
Arcade_MiST/Namco Mappy Hardware/rtl/mc6809/mc6809i.v
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102
Arcade_MiST/Namco Mappy Hardware/rtl/mems.v
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@ -1,102 +0,0 @@
module mems
(
input CPUCLKx2,
output [14:0] rom_addr,
input [7:0] rom_data,
input [15:0] MCPU_ADRS,
input MCPU_VMA,
input MCPU_WE,
input [7:0] MCPU_DO,
output [7:0] MCPU_DI,
output IO_CS,
input [7:0] IO_O,
input [15:0] SCPU_ADRS,
input SCPU_VMA,
input SCPU_WE,
input [7:0] SCPU_DO,
output [7:0] SCPU_DI,
output SCPU_WSG_WE,
input VCLKx4,
input [10:0] vram_a,
output [15:0] vram_d,
input [6:0] spra_a,
output [23:0] spra_d,
input ROMCL, // Downloaded ROM image
input [16:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
//wire [7:0] mrom_d;
wire [7:0] srom_d;
assign rom_addr = MCPU_ADRS[14:0];
//assign mrom_d = rom_data;
scpui_rom scpui_rom(
.clk(CPUCLKx2),
.addr(SCPU_ADRS[12:0]),
.data(srom_d)
);
wire mram_cs0 = ( MCPU_ADRS[15:11] == 5'b00000 ) & MCPU_VMA; // $0000-$07FF
wire mram_cs1 = ( MCPU_ADRS[15:11] == 5'b00001 ) & MCPU_VMA; // $0800-$0FFF
wire mram_cs2 = ( MCPU_ADRS[15:11] == 5'b00010 ) & MCPU_VMA; // $1000-$17FF
wire mram_cs3 = ( MCPU_ADRS[15:11] == 5'b00011 ) & MCPU_VMA; // $1800-$1FFF
wire mram_cs4 = ( MCPU_ADRS[15:11] == 5'b00100 ) & MCPU_VMA; // $2000-$27FF
wire mram_cs5 = ( MCPU_ADRS[15:10] == 6'b010000 ) & MCPU_VMA; // $4000-$43FF
assign IO_CS = ( MCPU_ADRS[15:11] == 5'b01001 ) & MCPU_VMA; // $4800-$4FFF
wire mrom_cs = ( MCPU_ADRS[15] ) & MCPU_VMA; // $8000-$FFFF
wire mram_w0 = ( mram_cs0 & MCPU_WE );
wire mram_w1 = ( mram_cs1 & MCPU_WE );
wire mram_w2 = ( mram_cs2 & MCPU_WE );
wire mram_w3 = ( mram_cs3 & MCPU_WE );
wire mram_w4 = ( mram_cs4 & MCPU_WE );
wire mram_w5 = ( mram_cs5 & MCPU_WE );
wire [7:0] mram_o0, mram_o1, mram_o2, mram_o3, mram_o4, mram_o5;
assign MCPU_DI = mram_cs0 ? mram_o0 :
mram_cs1 ? mram_o1 :
mram_cs2 ? mram_o2 :
mram_cs3 ? mram_o3 :
mram_cs4 ? mram_o4 :
mram_cs5 ? mram_o5 :
mrom_cs ? rom_data ://mrom_d :
IO_CS ? IO_O :
8'h0;
wire [10:0] mram_ad = MCPU_ADRS[10:0];
DPRAM_2048V main_ram0( CPUCLKx2, mram_ad, MCPU_DO, mram_o0, mram_w0, VCLKx4, vram_a, vram_d[7:0] );
DPRAM_2048V main_ram1( CPUCLKx2, mram_ad, MCPU_DO, mram_o1, mram_w1, VCLKx4, vram_a, vram_d[15:8] );
DPRAM_2048V main_ram2( CPUCLKx2, mram_ad, MCPU_DO, mram_o2, mram_w2, VCLKx4, { 4'b1111, spra_a }, spra_d[7:0] );
DPRAM_2048V main_ram3( CPUCLKx2, mram_ad, MCPU_DO, mram_o3, mram_w3, VCLKx4, { 4'b1111, spra_a }, spra_d[15:8] );
DPRAM_2048V main_ram4( CPUCLKx2, mram_ad, MCPU_DO, mram_o4, mram_w4, VCLKx4, { 4'b1111, spra_a }, spra_d[23:16] );
// (SCPU ADRS)
wire SCPU_CS_SREG = ( ( SCPU_ADRS[15:13] == 3'b000 ) & ( SCPU_ADRS[9:6] == 4'b0000 ) ) & SCPU_VMA;
wire srom_cs = ( SCPU_ADRS[15:13] == 3'b111 ) & SCPU_VMA; // $E000-$FFFF
wire sram_cs0 = (~SCPU_CS_SREG) & (~srom_cs) & SCPU_VMA; // $0000-$03FF
wire [7:0] sram_o0;
assign SCPU_DI = sram_cs0 ? sram_o0 :
srom_cs ? srom_d :
8'h0;
assign SCPU_WSG_WE = SCPU_CS_SREG & SCPU_WE;
DPRAM_2048 share_ram
(
CPUCLKx2, mram_ad, MCPU_DO, mram_o5, mram_w5,
CPUCLKx2, { 1'b0, SCPU_ADRS[9:0] }, SCPU_DO, sram_o0, sram_cs0 & SCPU_WE
);
endmodule

110
Arcade_MiST/Namco Mappy Hardware/rtl/regs.v
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@ -1,110 +0,0 @@
module regs
(
input MCPU_CLK,
input RESET,
input VBLANK,
input [15:0] MCPU_ADRS,
input MCPU_VMA,
input MCPU_WE,
input [15:0] SCPU_ADRS,
input SCPU_VMA,
input SCPU_WE,
output reg [7:0] SCROLL,
output MCPU_IRQ,
output reg MCPU_IRQEN,
output SCPU_IRQ,
output reg SCPU_IRQEN,
output SCPU_RESET,
output IO_RESET,
output reg PSG_ENABLE
);
// BG Scroll Register
wire MCPU_SCRWE = ( ( MCPU_ADRS[15:11] == 5'b00111 ) & MCPU_VMA & MCPU_WE );
always @ ( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) SCROLL <= 8'h0;
else if ( MCPU_SCRWE ) SCROLL <= MCPU_ADRS[10:3];
end
// MainCPU IRQ Generator
wire MCPU_IRQWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000001 ) & MCPU_VMA & MCPU_WE );
//wire MCPU_IRQWES = ( ( SCPU_ADRS[15:1] == 15'b001000000000001 ) & SCPU_VMA & SCPU_WE );
assign MCPU_IRQ = MCPU_IRQEN & VBLANK;
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
MCPU_IRQEN <= 1'b0;
end
else begin
if ( MCPU_IRQWE ) MCPU_IRQEN <= MCPU_ADRS[0];
// if ( MCPU_IRQWES ) MCPU_IRQEN <= SCPU_ADRS[0];
end
end
// SubCPU IRQ Generator
wire SCPU_IRQWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000000 ) & MCPU_VMA & MCPU_WE );
wire SCPU_IRQWES = ( ( SCPU_ADRS[15:1] == 15'b001000000000000 ) & SCPU_VMA & SCPU_WE );
assign SCPU_IRQ = SCPU_IRQEN & VBLANK;
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
SCPU_IRQEN <= 1'b0;
end
else begin
if ( SCPU_IRQWE ) SCPU_IRQEN <= MCPU_ADRS[0];
if ( SCPU_IRQWES ) SCPU_IRQEN <= SCPU_ADRS[0];
end
end
// SubCPU RESET Control
reg SCPU_RSTf = 1'b0;
wire SCPU_RSTWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000101 ) & MCPU_VMA & MCPU_WE );
wire SCPU_RSTWES = ( ( SCPU_ADRS[15:1] == 15'b001000000000101 ) & SCPU_VMA & SCPU_WE );
assign SCPU_RESET = ~SCPU_RSTf;
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
SCPU_RSTf <= 1'b0;
end
else begin
if ( SCPU_RSTWE ) SCPU_RSTf <= MCPU_ADRS[0];
if ( SCPU_RSTWES ) SCPU_RSTf <= SCPU_ADRS[0];
end
end
// I/O CHIP RESET Control
reg IOCHIP_RSTf = 1'b0;
wire IOCHIP_RSTWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000100 ) & MCPU_VMA & MCPU_WE );
assign IO_RESET = ~IOCHIP_RSTf;
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
IOCHIP_RSTf <= 1'b0;
end
else begin
if ( IOCHIP_RSTWE ) IOCHIP_RSTf <= MCPU_ADRS[0];
end
end
// Sound Enable Control
wire PSG_ENAWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000011 ) & MCPU_VMA & MCPU_WE );
wire PSG_ENAWES = ( ( SCPU_ADRS[15:1] == 15'b001000000000011 ) & SCPU_VMA & SCPU_WE );
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
PSG_ENABLE <= 1'b0;
end
else begin
if ( PSG_ENAWE ) PSG_ENABLE <= MCPU_ADRS[0];
if ( PSG_ENAWES ) PSG_ENABLE <= SCPU_ADRS[0];
end
end
endmodule