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LodeRunner: formatting cleanup

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This commit is contained in:
Gyorgy Szombathelyi 2020-03-02 11:32:52 +01:00
parent 102d1ffa0e
commit 1b80f5b041
19 changed files with 674 additions and 676 deletions
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192
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/Graphics.VHD
View File

@ -21,20 +21,20 @@ entity Graphics is
sprite_reg_i : in to_SPRITE_REG_t;
sprite_ctl_i : in to_SPRITE_CTL_t;
sprite_ctl_o : out from_SPRITE_CTL_t;
spr0_hit : out std_logic;
spr0_hit : out std_logic;
graphics_i : in to_GRAPHICS_t;
graphics_o : out from_GRAPHICS_t;
video_i : in from_VIDEO_t;
video_o : out to_VIDEO_t
video_i : in from_VIDEO_t;
video_o : out to_VIDEO_t
);
end Graphics;
architecture SYN of Graphics is
alias clk : std_logic is video_i.clk;
alias clk : std_logic is video_i.clk;
signal from_video_ctl : from_VIDEO_CTL_t;
signal bitmap_ctl_o_s : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
@ -43,21 +43,21 @@ architecture SYN of Graphics is
signal sprite_pri : std_logic;
signal rgb_data : RGB_t;
signal rgb_data : RGB_t;
-- before OSD is mixed in
signal video_o_s : to_VIDEO_t;
begin
-- dodgy OSD transparency...
video_o.clk <= video_o_s.clk;
video_o.clk <= video_o_s.clk;
video_o.rgb.r <= video_o_s.rgb.r;
video_o.rgb.g <= video_o_s.rgb.g;
video_o.rgb.b <= video_o_s.rgb.b;
video_o.hsync <= video_o_s.hsync;
video_o.vsync <= video_o_s.vsync;
video_o.hblank <= video_o_s.hblank;
video_o.vblank <= video_o_s.vblank;
video_o.hsync <= video_o_s.hsync;
video_o.vsync <= video_o_s.vsync;
video_o.hblank <= video_o_s.hblank;
video_o.vblank <= video_o_s.vblank;
graphics_o.y <= from_video_ctl.y;
-- should this be the 'real' vblank or the 'active' vblank?
@ -69,7 +69,7 @@ begin
pace_video_controller_inst : entity work.pace_video_controller
generic map
(
CONFIG => PACE_VIDEO_CONTROLLER_TYPE,
CONFIG => PACE_VIDEO_CONTROLLER_TYPE,
DELAY => PACE_VIDEO_PIPELINE_DELAY,
H_SIZE => PACE_VIDEO_H_SIZE,
V_SIZE => PACE_VIDEO_V_SIZE,
@ -86,17 +86,17 @@ begin
-- clocking etc
video_i => video_i,
-- register interface
reg_i.h_scale => "000",
reg_i.v_scale => "000",
-- register interface
reg_i.h_scale => "000",
reg_i.v_scale => "000",
-- video data signals (in)
rgb_i => rgb_data,
rgb_i => rgb_data,
-- video control signals (out)
video_ctl_o => from_video_ctl,
-- VGA signals (out)
video_o => video_o_s
video_o => video_o_s
);
pace_video_mixer_inst : entity work.pace_video_mixer
@ -113,140 +113,140 @@ begin
rgb_o => rgb_data
);
GEN_NO_BITMAPS : if PACE_VIDEO_NUM_BITMAPS = 0 generate
GEN_NO_BITMAPS : if PACE_VIDEO_NUM_BITMAPS = 0 generate
--bitmap_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0');
end generate GEN_NO_BITMAPS;
GEN_BITMAP_1 : if PACE_VIDEO_NUM_BITMAPS > 0 generate
forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_1)
end generate GEN_NO_BITMAPS;
GEN_BITMAP_1 : if PACE_VIDEO_NUM_BITMAPS > 0 generate
forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_1)
generic map
(
DELAY => PACE_VIDEO_PIPELINE_DELAY
)
port map
(
reset => video_i.reset,
video_ctl => from_video_ctl,
port map
(
reset => video_i.reset,
ctl_i => bitmap_ctl_i(1),
ctl_o => bitmap_ctl_o_s(1),
video_ctl => from_video_ctl,
ctl_i => bitmap_ctl_i(1),
ctl_o => bitmap_ctl_o_s(1),
graphics_i => graphics_i
);
end generate GEN_BITMAP_1;
);
end generate GEN_BITMAP_1;
GEN_BITMAP_2 : if PACE_VIDEO_NUM_BITMAPS > 1 generate
GEN_BITMAP_2 : if PACE_VIDEO_NUM_BITMAPS > 1 generate
forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_2)
forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_2)
generic map
(
DELAY => PACE_VIDEO_PIPELINE_DELAY
)
port map
(
reset => video_i.reset,
video_ctl => from_video_ctl,
port map
(
reset => video_i.reset,
ctl_i => bitmap_ctl_i(2),
ctl_o => bitmap_ctl_o_s(2),
video_ctl => from_video_ctl,
ctl_i => bitmap_ctl_i(2),
ctl_o => bitmap_ctl_o_s(2),
graphics_i => graphics_i
);
);
end generate GEN_BITMAP_2;
GEN_BITMAP_3 : if PACE_VIDEO_NUM_BITMAPS > 2 generate
GEN_BITMAP_3 : if PACE_VIDEO_NUM_BITMAPS > 2 generate
forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_3)
forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_3)
generic map
(
DELAY => PACE_VIDEO_PIPELINE_DELAY
)
port map
(
reset => video_i.reset,
video_ctl => from_video_ctl,
port map
(
reset => video_i.reset,
ctl_i => bitmap_ctl_i(3),
ctl_o => bitmap_ctl_o_s(3),
video_ctl => from_video_ctl,
ctl_i => bitmap_ctl_i(3),
ctl_o => bitmap_ctl_o_s(3),
graphics_i => graphics_i
);
);
end generate GEN_BITMAP_3;
bitmap_ctl_o <= bitmap_ctl_o_s;
GEN_NO_TILEMAPS : if PACE_VIDEO_NUM_TILEMAPS = 0 generate
GEN_NO_TILEMAPS : if PACE_VIDEO_NUM_TILEMAPS = 0 generate
--tilemap_ctl_o_s(1) <= ((others => '0'), (others => '0'), (others => '0'),
-- (others => (others => '0')), '0');
end generate GEN_NO_TILEMAPS;
GEN_TILEMAP_1 : if PACE_VIDEO_NUM_TILEMAPS > 0 generate
foreground_mapctl_inst : entity work.tilemapCtl(TILEMAP_1)
end generate GEN_NO_TILEMAPS;
GEN_TILEMAP_1 : if PACE_VIDEO_NUM_TILEMAPS > 0 generate
foreground_mapctl_inst : entity work.tilemapCtl(TILEMAP_1)
generic map
(
DELAY => PACE_VIDEO_PIPELINE_DELAY
)
port map
(
reset => video_i.reset,
video_ctl => from_video_ctl,
port map
(
reset => video_i.reset,
ctl_i => tilemap_ctl_i(1),
ctl_o => tilemap_ctl_o_s(1),
video_ctl => from_video_ctl,
ctl_i => tilemap_ctl_i(1),
ctl_o => tilemap_ctl_o_s(1),
graphics_i => graphics_i
);
);
end generate GEN_TILEMAP_1;
end generate GEN_TILEMAP_1;
GEN_TILEMAP_2 : if PACE_VIDEO_NUM_TILEMAPS > 1 generate
background_mapctl_inst : entity work.tilemapCtl(TILEMAP_2)
GEN_TILEMAP_2 : if PACE_VIDEO_NUM_TILEMAPS > 1 generate
background_mapctl_inst : entity work.tilemapCtl(TILEMAP_2)
generic map
(
DELAY => PACE_VIDEO_PIPELINE_DELAY
)
port map
(
reset => video_i.reset,
video_ctl => from_video_ctl,
port map
(
reset => video_i.reset,
ctl_i => tilemap_ctl_i(2),
ctl_o => tilemap_ctl_o_s(2),
video_ctl => from_video_ctl,
ctl_i => tilemap_ctl_i(2),
ctl_o => tilemap_ctl_o_s(2),
graphics_i => graphics_i
);
);
end generate GEN_TILEMAP_2;
end generate GEN_TILEMAP_2;
tilemap_ctl_o <= tilemap_ctl_o_s;
GEN_NO_SPRITES : if PACE_VIDEO_NUM_SPRITES = 0 generate
GEN_NO_SPRITES : if PACE_VIDEO_NUM_SPRITES = 0 generate
sprite_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0');
sprite_pri <= '0';
spr0_hit <= '0';
end generate GEN_NO_SPRITES;
GEN_SPRITES : if PACE_VIDEO_NUM_SPRITES > 0 generate
sprites_inst : sprite_array
end generate GEN_NO_SPRITES;
GEN_SPRITES : if PACE_VIDEO_NUM_SPRITES > 0 generate
sprites_inst : sprite_array
generic map
(
N_SPRITES => PACE_VIDEO_NUM_SPRITES,
DELAY => PACE_VIDEO_PIPELINE_DELAY
)
port map
(
reset => video_i.reset,
port map
(
reset => video_i.reset,
-- register interface
reg_i => sprite_reg_i,
@ -256,16 +256,16 @@ begin
graphics_i => graphics_i,
row_a => sprite_ctl_o_s.a,
row_d => sprite_ctl_i.d,
rgb => sprite_ctl_o_s.rgb,
set => sprite_ctl_o_s.set,
pri => sprite_pri,
spr0_set => spr0_hit
);
row_a => sprite_ctl_o_s.a,
row_d => sprite_ctl_i.d,
end generate GEN_SPRITES;
rgb => sprite_ctl_o_s.rgb,
set => sprite_ctl_o_s.set,
pri => sprite_pri,
spr0_set => spr0_hit
);
end generate GEN_SPRITES;
sprite_ctl_o <= sprite_ctl_o_s;

33
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/Inputs.VHD
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@ -5,20 +5,20 @@ library work;
use work.pace_pkg.all;
entity inputs is
generic
(
generic
(
NUM_DIPS : integer := 8;
NUM_INPUTS : integer := 2;
CLK_1US_DIV : natural := 30
);
NUM_INPUTS : integer := 2;
CLK_1US_DIV : natural := 30
);
port
(
clk : in std_logic;
reset : in std_logic;
jamma : in from_JAMMA_t;
dips : in std_logic_vector(NUM_DIPS-1 downto 0);
inputs : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1)
jamma : in from_JAMMA_t;
dips : in std_logic_vector(NUM_DIPS-1 downto 0);
inputs : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1)
);
end entity inputs;
@ -33,19 +33,18 @@ begin
inputmapper_inst : entity work.inputmapper
generic map
(
generic map
(
NUM_DIPS => NUM_DIPS,
NUM_INPUTS => NUM_INPUTS
)
NUM_INPUTS => NUM_INPUTS
)
port map
(
clk => clk,
rst_n => reset_n,
jamma => jamma,
dips => dips,
inputs => inputs
jamma => jamma,
dips => dips,
inputs => inputs
);
end architecture SYN;

4
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/LodeRunner_MiST.sv
View File

@ -1,12 +1,12 @@
module LodeRunner_MiST(
output LED,
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,

92
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/Sound_Board.vhd
View File

@ -17,7 +17,7 @@
-- Use at your own risk
---------------------------------------------------------------------------------
-- Version 0.0 -- 24/11/2017 --
-- initial version
-- initial version
---------------------------------------------------------------------------------
library ieee;
@ -167,7 +167,7 @@ ports_cs <= '1' when cpu_addr(15 downto 4) = X"000" else '0'; -- 0000-000F
adpcm_cs <= '1' when cpu_addr(14) = '0' and cpu_addr(11) = '1' and cpu_addr(1 downto 0) /= "00" else '0'; -- 0801-0802
irqraz_cs <= '1' when cpu_addr(14) = '0' and cpu_addr(11) = '1' and cpu_addr(1 downto 0) = "00" else '0'; -- 0800
rom_cs <= '1' when cpu_addr(14) = '1' else '0'; -- 4000-7FFF / C000-FFFF
-- write enables
wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0';
ports_we <= '1' when cpu_rw = '0' and ports_cs = '1' else '0';
@ -176,42 +176,42 @@ irqraz_we <= '1' when cpu_rw = '0' and irqraz_cs = '1' else '0';
-- mux cpu in data between roms/io/wram
cpu_di <=
wram_do when wram_cs = '1' else
port1_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"0" else
port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else
port1_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else
port2_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
snd_rom_do when rom_cs = '1' else X"55";
wram_do when wram_cs = '1' else
port1_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"0" else
port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else
port1_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else
port2_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
snd_rom_do when rom_cs = '1' else X"55";
process (clock_E)
begin
if rising_edge(clock_E) then
reset <= '0';
if reset_cnt /= 0 then
reset_cnt <= reset_cnt - 1;
reset <= '1';
end if;
if areset = '1' then
reset_cnt <= 1000000;
end if;
end if;
if rising_edge(clock_E) then
reset <= '0';
if reset_cnt /= 0 then
reset_cnt <= reset_cnt - 1;
reset <= '1';
end if;
if areset = '1' then
reset_cnt <= 1000000;
end if;
end if;
end process;
-- irq to cpu
process (reset, clock_E)
begin
if reset='1' then
cpu_irq <= '0';
select_sound_r(7) <= '1';
elsif rising_edge(clock_E) then
select_sound_r <= select_sound;
if select_sound_r(7) = '0' then
cpu_irq <= '1';
end if;
if irqraz_we = '1' then
cpu_irq <= '0';
end if;
end if;
if reset='1' then
cpu_irq <= '0';
select_sound_r(7) <= '1';
elsif rising_edge(clock_E) then
select_sound_r <= select_sound;
if select_sound_r(7) = '0' then
cpu_irq <= '1';
end if;
if irqraz_we = '1' then
cpu_irq <= '0';
end if;
end if;
end process;
-- cpu nmi
@ -272,7 +272,7 @@ begin
if clock_div_a = 37 then -- 24kHz
clock_div_a := 0;
case ay1_port_b_do(3 downto 2) is
case ay1_port_b_do(3 downto 2) is
when "00" => if clock_div_b = 5 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 4kHz
when "01" => if clock_div_b = 2 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 8kHz
when "10" => if clock_div_b = 3 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 6kHz
@ -281,7 +281,7 @@ begin
if clock_div_b = 0 then adpcm_vclk <= '1'; else adpcm_vclk <= '0'; end if;
else
clock_div_a := clock_div_a + 1;
clock_div_a := clock_div_a + 1;
end if;
if ay1_port_b_do(0) = '1' then
@ -330,23 +330,23 @@ end process;
-- audio mux
audio <= ("000"&ay1_audio) + ("000"&ay2_audio) + ('0'&std_logic_vector(to_unsigned((adpcm_signal)+2048,12)));
audio_out <= audio(12 downto 1);
-- microprocessor 6800/01/03
main_cpu : entity work.cpu68
port map(
clk => clock_E, -- E clock input (falling edge)
rst => reset, -- reset input (active high)
rw => cpu_rw, -- read not write output
vma => cpu_vma, -- valid memory address (active high)
address => cpu_addr, -- address bus output
data_in => cpu_di, -- data bus input
data_out => cpu_do, -- data bus output
hold => '0', -- hold input (active high) extend bus cycle
halt => '0', -- halt input (active high) grants DMA
irq => cpu_irq, -- interrupt request input (active high)
nmi => cpu_nmi, -- non maskable interrupt request input (active high)
test_alu => open,
test_cc => open
clk => clock_E, -- E clock input (falling edge)
rst => reset, -- reset input (active high)
rw => cpu_rw, -- read not write output
vma => cpu_vma, -- valid memory address (active high)
address => cpu_addr, -- address bus output
data_in => cpu_di, -- data bus input
data_out => cpu_do, -- data bus output
hold => '0', -- hold input (active high) extend bus cycle
halt => '0', -- halt input (active high) grants DMA
irq => cpu_irq, -- interrupt request input (active high)
nmi => cpu_nmi, -- non maskable interrupt request input (active high)
test_alu => open,
test_cc => open
);
--rom_cpu : entity work.snd_prg

2
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/bitmapctl_e.vhd
View File

@ -16,7 +16,7 @@ entity bitmapCtl is
);
port
(
reset : in std_logic;
reset : in std_logic;
-- video control signals
video_ctl : in from_VIDEO_CTL_t;

42
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/clk_div.vhd
View File

@ -2,16 +2,16 @@ library ieee;
use ieee.std_logic_1164.all;
entity clk_div is
generic
(
DIVISOR : natural
);
generic
(
DIVISOR : natural
);
port
(
clk : in std_logic;
reset : in std_logic;
clk_en : out std_logic
clk_en : out std_logic
);
end clk_div;
@ -19,21 +19,21 @@ architecture SYN of clk_div is
begin
process (clk, reset)
variable count : integer range 0 to DIVISOR-1;
begin
if reset = '1' then
count := 0;
clk_en <= '0';
elsif rising_edge(clk) then
clk_en <= '0';
if count = DIVISOR-1 then
clk_en <= '1';
count := 0;
else
count := count + 1;
end if;
end if;
end process;
process (clk, reset)
variable count : integer range 0 to DIVISOR-1;
begin
if reset = '1' then
count := 0;
clk_en <= '0';
elsif rising_edge(clk) then
clk_en <= '0';
if count = DIVISOR-1 then
clk_en <= '1';
count := 0;
else
count := count + 1;
end if;
end if;
end process;
end SYN;

44
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/input_mapper.vhd
View File

@ -6,21 +6,21 @@ library work;
use work.pace_pkg.all;
entity inputmapper is
generic
(
generic
(
NUM_DIPS : integer := 8;
NUM_INPUTS : integer := 2
);
port
(
NUM_INPUTS : integer := 2
);
port
(
clk : in std_logic;
rst_n : in std_logic;
jamma : in from_JAMMA_t;
jamma : in from_JAMMA_t;
-- user outputs
dips : in std_logic_vector(NUM_DIPS-1 downto 0);
inputs : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1)
);
dips : in std_logic_vector(NUM_DIPS-1 downto 0);
inputs : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1)
);
end inputmapper;
architecture SYN of inputmapper is
@ -28,7 +28,7 @@ architecture SYN of inputmapper is
begin
process (clk, rst_n)
variable jamma_v : from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1);
variable jamma_v : from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1);
begin
-- note: all inputs are active LOW
@ -45,27 +45,27 @@ begin
jamma_v(0).d(1) := jamma.p(2).start;
jamma_v(0).d(2) := '1';--jamma.service;
jamma_v(0).d(3) := jamma.coin(1);
--unused
--unused
--unused
--unused
--unused
--unused
--unused
--unused
jamma_v(1).d(0) := jamma.p(1).right;
jamma_v(1).d(1) := jamma.p(1).left;
jamma_v(1).d(2) := jamma.p(1).down;
jamma_v(1).d(3) := jamma.p(1).up;
--unused
--unused
jamma_v(1).d(5) := jamma.p(1).button(2);
--unused
--unused
jamma_v(1).d(7) := jamma.p(1).button(1);
jamma_v(2).d(0) := jamma.p(2).right;
jamma_v(2).d(0) := jamma.p(2).right;
jamma_v(2).d(1) := jamma.p(2).left;
jamma_v(2).d(2) := jamma.p(2).down;
jamma_v(2).d(3) := jamma.p(2).up;
jamma_v(2).d(4) := jamma.coin(2);
jamma_v(2).d(4) := jamma.coin(2);
jamma_v(2).d(5) := jamma.p(2).button(2);
--unused
--unused
jamma_v(2).d(7) := jamma.p(2).button(1);
end if; -- rising_edge (clk)

62
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/pace.vhd
View File

@ -12,7 +12,7 @@ use work.platform_pkg.all;
entity PACE is
port
(
-- clocks and resets
-- clocks and resets
clkrst_i : in from_CLKRST_t;
-- misc I/O
@ -29,8 +29,8 @@ entity PACE is
sound_data_o : out std_logic_vector(7 downto 0);
-- custom i/o
-- project_i : in from_PROJECT_IO_t;
-- project_o : out to_PROJECT_IO_t;
-- project_i : in from_PROJECT_IO_t;
-- project_o : out to_PROJECT_IO_t;
platform_i : in from_PLATFORM_IO_t;
platform_o : out to_PLATFORM_IO_t;
cpu_rom_addr : out std_logic_vector(14 downto 0);
@ -40,10 +40,10 @@ end entity PACE;
architecture SYN of PACE is
constant CLK_1US_COUNTS : integer :=
constant CLK_1US_COUNTS : integer :=
integer(27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY);
signal mapped_inputs : from_MAPPED_INPUTS_t(0 to PACE_INPUTS_NUM_BYTES-1);
signal mapped_inputs : from_MAPPED_INPUTS_t(0 to PACE_INPUTS_NUM_BYTES-1);
signal to_tilemap_ctl : to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
signal from_tilemap_ctl : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
@ -54,29 +54,29 @@ architecture SYN of PACE is
signal to_sprite_reg : to_SPRITE_REG_t;
signal to_sprite_ctl : to_SPRITE_CTL_t;
signal from_sprite_ctl : from_SPRITE_CTL_t;
signal spr0_hit : std_logic;
signal spr0_hit : std_logic;
signal to_graphics : to_GRAPHICS_t;
signal from_graphics : from_GRAPHICS_t;
signal from_graphics : from_GRAPHICS_t;
begin
inputs_inst : entity work.inputs
generic map
(
inputs_inst : entity work.inputs
generic map
(
NUM_DIPS => PACE_NUM_SWITCHES,
NUM_INPUTS => PACE_INPUTS_NUM_BYTES,
CLK_1US_DIV => CLK_1US_COUNTS
)
port map
(
clk => clkrst_i.clk(0),
reset => clkrst_i.rst(0),
jamma => inputs_i.jamma_n,
dips => switches_i,
inputs => mapped_inputs
);
NUM_INPUTS => PACE_INPUTS_NUM_BYTES,
CLK_1US_DIV => CLK_1US_COUNTS
)
port map
(
clk => clkrst_i.clk(0),
reset => clkrst_i.rst(0),
jamma => inputs_i.jamma_n,
dips => switches_i,
inputs => mapped_inputs
);
platform_inst : entity work.platform
generic map
@ -106,7 +106,7 @@ begin
sprite_reg_o => to_sprite_reg,
sprite_i => from_sprite_ctl,
sprite_o => to_sprite_ctl,
spr0_hit => spr0_hit,
spr0_hit => spr0_hit,
graphics_i => from_graphics,
graphics_o => to_graphics,
@ -116,9 +116,9 @@ begin
-- project_o => project_o,
platform_i => platform_i,
platform_o => platform_o,
cpu_rom_addr => cpu_rom_addr,
cpu_rom_do => cpu_rom_do
cpu_rom_addr => cpu_rom_addr,
cpu_rom_do => cpu_rom_do
);
graphics_inst : entity work.Graphics
@ -133,14 +133,14 @@ begin
sprite_reg_i => to_sprite_reg,
sprite_ctl_i => to_sprite_ctl,
sprite_ctl_o => from_sprite_ctl,
spr0_hit => spr0_hit,
spr0_hit => spr0_hit,
graphics_i => to_graphics,
graphics_o => from_graphics,
-- video (incl. clk)
video_i => video_i,
video_o => video_o
-- video (incl. clk)
video_i => video_i,
video_o => video_o
);
end SYN;

174
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/pace_pkg.vhd
View File

@ -6,9 +6,9 @@ library work;
package pace_pkg is
--
-- PACE constants which *MUST* be defined
--
--
-- PACE constants which *MUST* be defined
--
type PACETargetType is
(
@ -51,26 +51,26 @@ package pace_pkg is
PACE_TARGET_S6M_A0
);
type PACEFpgaVendor_t is
(
PACE_FPGA_VENDOR_ALTERA,
PACE_FPGA_VENDOR_XILINX,
PACE_FPGA_VENDOR_LATTICE
);
type PACEFpgaVendor_t is
(
PACE_FPGA_VENDOR_ALTERA,
PACE_FPGA_VENDOR_XILINX,
PACE_FPGA_VENDOR_LATTICE
);
type PACEFpgaFamily_t is
(
PACE_FPGA_FAMILY_CYCLONE1,
PACE_FPGA_FAMILY_CYCLONE2,
PACE_FPGA_FAMILY_CYCLONE3,
PACE_FPGA_FAMILY_CYCLONE4,
PACE_FPGA_FAMILY_CYCLONE5,
PACE_FPGA_FAMILY_CYCLONE6,
PACE_FPGA_FAMILY_STRATIX_III,
PACE_FPGA_FAMILY_SPARTAN3,
PACE_FPGA_FAMILY_SPARTAN3A,
PACE_FPGA_FAMILY_SPARTAN3E
);
type PACEFpgaFamily_t is
(
PACE_FPGA_FAMILY_CYCLONE1,
PACE_FPGA_FAMILY_CYCLONE2,
PACE_FPGA_FAMILY_CYCLONE3,
PACE_FPGA_FAMILY_CYCLONE4,
PACE_FPGA_FAMILY_CYCLONE5,
PACE_FPGA_FAMILY_CYCLONE6,
PACE_FPGA_FAMILY_STRATIX_III,
PACE_FPGA_FAMILY_SPARTAN3,
PACE_FPGA_FAMILY_SPARTAN3A,
PACE_FPGA_FAMILY_SPARTAN3E
);
type PACEJamma_t is
(
@ -82,7 +82,7 @@ package pace_pkg is
-- Types
type ByteArrayType is array (natural range <>) of std_logic_vector(7 downto 0);
type ByteArrayType is array (natural range <>) of std_logic_vector(7 downto 0);
type from_CLKRST_t is record
arst : std_logic;
@ -103,30 +103,30 @@ package pace_pkg is
constant PACE_NUM_LEDS : natural := 18;
subtype to_LEDS_t is std_logic_vector(PACE_NUM_LEDS-1 downto 0);
--
-- JAMMA interface data structures
-- - note: all signals are active LOW
--
--
-- JAMMA interface data structures
-- - note: all signals are active LOW
--
type from_JAMMA_player_t is record
start : std_logic;
up : std_logic;
down : std_logic;
left : std_logic;
right : std_logic;
button : std_logic_vector(1 to 5);
end record;
type from_JAMMA_player_t is record
start : std_logic;
up : std_logic;
down : std_logic;
left : std_logic;
right : std_logic;
button : std_logic_vector(1 to 5);
end record;
type from_JAMMA_player_a is array (natural range <>) of from_JAMMA_player_t;
type from_JAMMA_t is record
coin_cnt : std_logic_vector(1 to 2);
service : std_logic;
tilt : std_logic;
test : std_logic;
coin : std_logic_vector(1 to 2);
p : from_JAMMA_player_a(1 to 2);
end record;
type from_JAMMA_player_a is array (natural range <>) of from_JAMMA_player_t;
type from_JAMMA_t is record
coin_cnt : std_logic_vector(1 to 2);
service : std_logic;
tilt : std_logic;
test : std_logic;
coin : std_logic_vector(1 to 2);
p : from_JAMMA_player_a(1 to 2);
end record;
--
-- INPUTS
@ -134,7 +134,7 @@ package pace_pkg is
subtype analogue_in_t is std_logic_vector(9 downto 0);
type analogue_in_a is array (natural range <>) of analogue_in_t;
type from_INPUTS_t is record
type from_INPUTS_t is record
ps2_kclk : std_logic;
ps2_kdat : std_logic;
ps2_mclk : std_logic;
@ -150,38 +150,38 @@ package pace_pkg is
type from_MAPPED_INPUTS_t is array (natural range <>) of in8_t;
--
-- SRAM interface data structure
--
type from_SRAM_t is record
d : std_logic_vector(31 downto 0);
end record;
type to_SRAM_t is record
a : std_logic_vector(23 downto 0);
d : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0);
cs : std_logic;
oe : std_logic;
we : std_logic;
end record;
--
-- SRAM interface data structure
--
type from_SRAM_t is record
d : std_logic_vector(31 downto 0);
end record;
type to_SRAM_t is record
a : std_logic_vector(23 downto 0);
d : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0);
cs : std_logic;
oe : std_logic;
we : std_logic;
end record;
function NULL_TO_SRAM return to_SRAM_t;
--
-- FLASH interface data structure
--
type from_FLASH_t is record
d : std_logic_vector(15 downto 0);
end record;
type to_FLASH_t is record
a : std_logic_vector(21 downto 0);
d : std_logic_vector(15 downto 0);
we : std_logic;
cs : std_logic;
oe : std_logic;
end record;
--
-- FLASH interface data structure
--
type from_FLASH_t is record
d : std_logic_vector(15 downto 0);
end record;
type to_FLASH_t is record
a : std_logic_vector(21 downto 0);
d : std_logic_vector(15 downto 0);
we : std_logic;
cs : std_logic;
oe : std_logic;
end record;
function NULL_TO_FLASH return to_FLASH_t;
@ -250,7 +250,7 @@ package pace_pkg is
function NULL_TO_SOUND return to_SOUND_t;
--
--
-- OSD interface data structure
--
type from_OSD_t is record
@ -268,13 +268,13 @@ package pace_pkg is
function NULL_TO_OSD return to_OSD_t;
-- create a constant that automatically determines
-- whether this is simulation or synthesis
constant IN_SIMULATION : BOOLEAN := false
-- synthesis translate_off
or true
-- synthesis translate_on
;
constant IN_SYNTHESIS : boolean := not IN_SIMULATION;
end;
-- create a constant that automatically determines
-- whether this is simulation or synthesis
constant IN_SIMULATION : BOOLEAN := false
-- synthesis translate_off
or true
-- synthesis translate_on
;
constant IN_SYNTHESIS : boolean := not IN_SIMULATION;
end;

227
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/platform.vhd
View File

@ -40,7 +40,7 @@ entity platform is
sprite_reg_o : out to_SPRITE_REG_t;
sprite_i : in from_SPRITE_CTL_t;
sprite_o : out to_SPRITE_CTL_t;
spr0_hit : in std_logic;
spr0_hit : in std_logic;
-- various graphics information
graphics_i : in from_GRAPHICS_t;
@ -60,12 +60,12 @@ end platform;
architecture SYN of platform is
alias clk_sys : std_logic is clkrst_i.clk(0);
alias rst_sys : std_logic is clkrst_i.rst(0);
alias clk_video : std_logic is clkrst_i.clk(1);
alias clk_sys : std_logic is clkrst_i.clk(0);
alias rst_sys : std_logic is clkrst_i.rst(0);
alias clk_video : std_logic is clkrst_i.clk(1);
-- cpu signals
signal clk_3M072_en : std_logic;
signal clk_3M072_en : std_logic;
signal cpu_clk_en : std_logic;
signal cpu_a : std_logic_vector(15 downto 0);
signal cpu_d_i : std_logic_vector(7 downto 0);
@ -76,17 +76,17 @@ architecture SYN of platform is
signal cpu_irq : std_logic;
-- ROM signals
signal rom_cs : std_logic;
signal rom_cs : std_logic;
-- signal rom_d_o : std_logic_vector(7 downto 0);
-- keyboard signals
-- VRAM signals
signal vram_cs : std_logic;
signal vram_wr : std_logic;
signal vram_d_o : std_logic_vector(7 downto 0);
signal snd_cs : std_logic;
-- VRAM signals
signal vram_cs : std_logic;
signal vram_wr : std_logic;
signal vram_d_o : std_logic_vector(7 downto 0);
signal snd_cs : std_logic;
-- RAM signals
@ -97,8 +97,8 @@ architecture SYN of platform is
-- CRAM/SPRITE signals
signal cram_cs : std_logic;
signal cram_wr : std_logic;
signal cram_d_o : std_logic_vector(7 downto 0);
signal sprite_cs : std_logic;
signal cram_d_o : std_logic_vector(7 downto 0);
signal sprite_cs : std_logic;
-- misc signals
signal in_cs : std_logic;
@ -165,35 +165,35 @@ begin
wram_cs <= '1' when STD_MATCH(cpu_a, X"E"&"------------") else '0';
-- OUTPUT $XX00
snd_cs <= '1' when cpu_a(7 downto 0) = X"00" else '0';
snd_cs <= '1' when cpu_a(7 downto 0) = X"00" else '0';
-- INPUTS (I/O) $00-$04
in_cs <= '1' when STD_MATCH(cpu_a(7 downto 0), X"0"&"00--") else
'1' when STD_MATCH(cpu_a(7 downto 0), X"04") else
'0';
process (clk_sys, rst_sys) begin
if rst_sys = '1' then
sound_data_o <= X"FF";
elsif rising_edge(clk_sys) then
if cpu_clk_en = '1' and cpu_io_wr = '1' and snd_cs = '1' then
sound_data_o <= cpu_d_o;
end if;
end if;
end process;
process (clk_sys, rst_sys) begin
if rst_sys = '1' then
sound_data_o <= X"FF";
elsif rising_edge(clk_sys) then
if cpu_clk_en = '1' and cpu_io_wr = '1' and snd_cs = '1' then
sound_data_o <= cpu_d_o;
end if;
end if;
end process;
-- memory read mux
cpu_d_i <= in_d_o when (cpu_io_rd = '1' and in_cs = '1') else
cpu_rom_do when rom_cs = '1' else
vram_d_o when vram_cs = '1' else
cram_d_o when cram_cs = '1' else
wram_d_o when wram_cs = '1' else
(others => '1');
-- memory read mux
cpu_d_i <= in_d_o when (cpu_io_rd = '1' and in_cs = '1') else
cpu_rom_do when rom_cs = '1' else
vram_d_o when vram_cs = '1' else
cram_d_o when cram_cs = '1' else
wram_d_o when wram_cs = '1' else
(others => '1');
-- memory block write signals
vram_wr <= vram_cs and cpu_mem_wr;
cram_wr <= cram_cs and cpu_mem_wr;
wram_wr <= wram_cs and cpu_mem_wr;
vram_wr <= vram_cs and cpu_mem_wr;
cram_wr <= cram_cs and cpu_mem_wr;
wram_wr <= wram_cs and cpu_mem_wr;
-- sprite registers
sprite_reg_o.clk <= clk_sys;
@ -229,25 +229,27 @@ begin
cpu_inst : entity work.Z80
port map
(
clk => clk_sys,
clk_en => cpu_clk_en,
reset => cpu_rst,
clk => clk_sys,
clk_en => cpu_clk_en,
reset => cpu_rst,
addr => cpu_a,
datai => cpu_d_i,
datao => cpu_d_o,
addr => cpu_a,
datai => cpu_d_i,
datao => cpu_d_o,
mem_rd => open,
mem_wr => cpu_mem_wr,
io_rd => cpu_io_rd,
io_wr => cpu_io_wr,
mem_rd => open,
mem_wr => cpu_mem_wr,
io_rd => cpu_io_rd,
io_wr => cpu_io_wr,
intreq => cpu_irq,
intvec => cpu_d_i,
intack => open,
nmi => '0'
intreq => cpu_irq,
intvec => cpu_d_i,
intack => open,
nmi => '0'
);
cpu_rom_addr <= cpu_a(14 downto 0);
end block BLK_CPU;
BLK_INTERRUPTS : block
@ -256,18 +258,18 @@ begin
begin
process (clk_sys, rst_sys)
variable vblank_r : std_logic_vector(3 downto 0);
alias vblank_prev : std_logic is vblank_r(vblank_r'left);
alias vblank_um : std_logic is vblank_r(vblank_r'left-1);
process (clk_sys, rst_sys)
variable vblank_r : std_logic_vector(3 downto 0);
alias vblank_prev : std_logic is vblank_r(vblank_r'left);
alias vblank_um : std_logic is vblank_r(vblank_r'left-1);
-- 1us duty for VBLANK_INT
variable count : integer range 0 to CLK0_FREQ_MHz * 100;
begin
if rst_sys = '1' then
vblank_int <= '0';
vblank_r := (others => '0');
begin
if rst_sys = '1' then
vblank_int <= '0';
vblank_r := (others => '0');
count := count'high;
elsif rising_edge(clk_sys) then
elsif rising_edge(clk_sys) then
-- rising edge vblank only
if vblank_prev = '0' and vblank_um = '1' then
count := 0;
@ -279,8 +281,8 @@ begin
vblank_int <= '0';
end if;
vblank_r := vblank_r(vblank_r'left-1 downto 0) & graphics_i.vblank;
end if; -- rising_edge(clk_sys)
end process;
end if; -- rising_edge(clk_sys)
end process;
-- generate INT
cpu_irq <= vblank_int;
@ -323,7 +325,6 @@ begin
graphics_o.bit16(0) <= m62_hscroll;
end block BLK_SCROLL;
cpu_rom_addr <= cpu_a(14 downto 0);
BLK_GFX_ROMS : block
@ -339,19 +340,19 @@ cpu_rom_addr <= cpu_a(14 downto 0);
char_rom_inst : entity work.sprom
generic map
(
init_file => "./roms/" &
init_file => "./roms/" &
M62_CHAR_ROM(i) & ".hex",
widthad_a => 13
widthad_a => 13
)
port map
(
clock => clk_video,
address => tilemap_i(1).tile_a(12 downto 0),
q => chr_rom_d(i)
clock => clk_video,
address => tilemap_i(1).tile_a(12 downto 0),
q => chr_rom_d(i)
);
end generate GEN_CHAR_ROMS;
tilemap_o(1).tile_d(23 downto 0) <= chr_rom_d(0) & chr_rom_d(1) & chr_rom_d(2);
tilemap_o(1).tile_d(23 downto 0) <= chr_rom_d(0) & chr_rom_d(1) & chr_rom_d(2);
-- chr_rom_addr <= tilemap_i(1).tile_a(12 downto 0);
--tilemap_o(1).tile_d(23 downto 0) <= chr_rom_do;
@ -361,18 +362,18 @@ cpu_rom_addr <= cpu_a(14 downto 0);
sprite_rom_inst : entity work.dprom_2r
generic map
(
init_file => "./roms/" &
init_file => "./roms/" &
M62_SPRITE_ROM(i) & ".hex",
widthad_a => 13,
widthad_b => 13
widthad_a => 13,
widthad_b => 13
)
port map
(
clock => clk_video,
clock => clk_video,
address_a(12 downto 5) => sprite_i.a(12 downto 5),
address_a(4) => '0',
address_a(3 downto 0) => sprite_i.a(3 downto 0),
q_a => spr_rom_left(i),
q_a => spr_rom_left(i),
address_b(12 downto 5) => sprite_i.a(12 downto 5),
address_b(4) => '1',
address_b(3 downto 0) => sprite_i.a(3 downto 0),
@ -410,65 +411,63 @@ cpu_rom_addr <= cpu_a(14 downto 0);
vram_inst : entity work.dpram
generic map
(
init_file => "",
widthad_a => 11
init_file => "",
widthad_a => 11
)
port map
(
clock_b => clk_sys,
address_b => vram_a,
wren_b => vram_wr,
data_b => cpu_d_o,
q_b => vram_d_o,
clock_b => clk_sys,
address_b => vram_a,
wren_b => vram_wr,
data_b => cpu_d_o,
q_b => vram_d_o,
clock_a => clk_video,
address_a => tilemap_i(1).map_a(10 downto 0),
wren_a => '0',
data_a => (others => 'X'),
q_a => tilemap_o(1).map_d(7 downto 0)
clock_a => clk_video,
address_a => tilemap_i(1).map_a(10 downto 0),
wren_a => '0',
data_a => (others => 'X'),
q_a => tilemap_o(1).map_d(7 downto 0)
);
tilemap_o(1).map_d(15 downto 8) <= (others => '0');
cram_inst : entity work.dpram
generic map
(
init_file => "",
widthad_a => 11
init_file => "",
widthad_a => 11
)
port map
(
clock_b => clk_sys,
address_b => cram_a,
wren_b => cram_wr,
data_b => cpu_d_o,
q_b => cram_d_o,
clock_b => clk_sys,
address_b => cram_a,
wren_b => cram_wr,
data_b => cpu_d_o,
q_b => cram_d_o,
clock_a => clk_video,
address_a => tilemap_i(1).attr_a(10 downto 0),
wren_a => '0',
data_a => (others => 'X'),
q_a => tilemap_o(1).attr_d(7 downto 0)
clock_a => clk_video,
address_a => tilemap_i(1).attr_a(10 downto 0),
wren_a => '0',
data_a => (others => 'X'),
q_a => tilemap_o(1).attr_d(7 downto 0)
);
tilemap_o(1).attr_d(15 downto 8) <= (others => '0');
end block BLK_VRAM;
wram_inst : entity work.spram
generic map
(
widthad_a => 12
)
port map
(
clock => clk_sys,
address => cpu_a(11 downto 0),
data => cpu_d_o,
wren => wram_wr,
q => wram_d_o
);
end block BLK_VRAM;
wram_inst : entity work.spram
generic map
(
widthad_a => 12
)
port map
(
clock => clk_sys,
address => cpu_a(11 downto 0),
data => cpu_d_o,
wren => wram_wr,
q => wram_d_o
);
-- unused outputs
sprite_o.ld <= '0';

72
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/platform_pkg.vhd
View File

@ -8,15 +8,15 @@ use work.platform_variant_pkg.all;
use work.video_controller_pkg.all;
package platform_pkg is
-- constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_VGA_640x480_60Hz;
-- constant PACE_CLK0_DIVIDE_BY : natural := 3;
-- constant PACE_CLK0_MULTIPLY_BY : natural := 5; -- 24*5/3 = 40MHz
-- constant PACE_CLK1_DIVIDE_BY : natural := 19;
-- constant PACE_CLK1_MULTIPLY_BY : natural := 20; -- 24*20/19 = 25.263158MHz
-- constant PACE_VIDEO_H_SCALE : integer := 1;
-- constant PACE_VIDEO_V_SCALE : integer := 1;
-- constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '0';
-- constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '0';
-- constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_VGA_640x480_60Hz;
-- constant PACE_CLK0_DIVIDE_BY : natural := 3;
-- constant PACE_CLK0_MULTIPLY_BY : natural := 5; -- 24*5/3 = 40MHz
-- constant PACE_CLK1_DIVIDE_BY : natural := 19;
-- constant PACE_CLK1_MULTIPLY_BY : natural := 20; -- 24*20/19 = 25.263158MHz
-- constant PACE_VIDEO_H_SCALE : integer := 1;
-- constant PACE_VIDEO_V_SCALE : integer := 1;
-- constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '0';
-- constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '0';
-- constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_ARCADE_STD_336x240_60Hz;
-- constant PACE_CLK0_DIVIDE_BY : natural := 19;
@ -28,40 +28,40 @@ package platform_pkg is
-- constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '0';
-- constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '0';
constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_PAL_576x288_50Hz;
constant PACE_CLK0_DIVIDE_BY : natural := 27;
constant PACE_CLK0_MULTIPLY_BY : natural := 44; -- 27*44/27 = 44MHz
constant PACE_CLK1_DIVIDE_BY : natural := 27;
constant PACE_CLK1_MULTIPLY_BY : natural := 11; -- 27*11/27 = 11MHz
constant PACE_VIDEO_H_SCALE : integer := 1;
constant PACE_VIDEO_V_SCALE : integer := 1;
constant PACE_ENABLE_ADV724 : std_logic := '1';
constant USE_VIDEO_VBLANK_INTERRUPT : boolean := false;
constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '1';
constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '1';
constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_PAL_576x288_50Hz;
constant PACE_CLK0_DIVIDE_BY : natural := 27;
constant PACE_CLK0_MULTIPLY_BY : natural := 44; -- 27*44/27 = 44MHz
constant PACE_CLK1_DIVIDE_BY : natural := 27;
constant PACE_CLK1_MULTIPLY_BY : natural := 11; -- 27*11/27 = 11MHz
constant PACE_VIDEO_H_SCALE : integer := 1;
constant PACE_VIDEO_V_SCALE : integer := 1;
constant PACE_ENABLE_ADV724 : std_logic := '1';
constant USE_VIDEO_VBLANK_INTERRUPT : boolean := false;
constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '1';
constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '1';
constant PACE_VIDEO_BORDER_RGB : RGB_t := RGB_BLACK;
constant PACE_VIDEO_BORDER_RGB : RGB_t := RGB_BLACK;
constant M62_VIDEO_H_SIZE : integer := 384;
constant M62_VIDEO_H_OFFSET : integer := (512-M62_VIDEO_H_SIZE)/2;
constant M62_VIDEO_V_SIZE : integer := 256;
constant M62_VIDEO_H_SIZE : integer := 384;
constant M62_VIDEO_H_OFFSET : integer := (512-M62_VIDEO_H_SIZE)/2;
constant M62_VIDEO_V_SIZE : integer := 256;
constant PACE_VIDEO_NUM_BITMAPS : natural := 0;
constant PACE_VIDEO_NUM_TILEMAPS : natural := 1;
constant PACE_VIDEO_NUM_SPRITES : natural := 32;
constant PACE_VIDEO_H_SIZE : integer := M62_VIDEO_H_SIZE;
constant PACE_VIDEO_V_SIZE : integer := M62_VIDEO_V_SIZE;
constant PACE_VIDEO_L_CROP : integer := 0;
constant PACE_VIDEO_R_CROP : integer := PACE_VIDEO_L_CROP;
constant PACE_VIDEO_PIPELINE_DELAY : integer := 5;
constant PACE_VIDEO_NUM_BITMAPS : natural := 0;
constant PACE_VIDEO_NUM_TILEMAPS : natural := 1;
constant PACE_VIDEO_NUM_SPRITES : natural := 32;
constant PACE_VIDEO_H_SIZE : integer := M62_VIDEO_H_SIZE;
constant PACE_VIDEO_V_SIZE : integer := M62_VIDEO_V_SIZE;
constant PACE_VIDEO_L_CROP : integer := 0;
constant PACE_VIDEO_R_CROP : integer := PACE_VIDEO_L_CROP;
constant PACE_VIDEO_PIPELINE_DELAY : integer := 5;
constant PACE_INPUTS_NUM_BYTES : integer := 6;
constant PACE_INPUTS_NUM_BYTES : integer := 6;
constant CLK0_FREQ_MHz : natural :=
constant CLK0_FREQ_MHz : natural :=
27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY;
constant CPU_FREQ_MHz : natural := 3;
constant CPU_FREQ_MHz : natural := 3;
constant M62_CPU_CLK_ENA_DIVIDE_BY : natural := CLK0_FREQ_MHz / CPU_FREQ_MHz;
constant M62_CPU_CLK_ENA_DIVIDE_BY : natural := CLK0_FREQ_MHz / CPU_FREQ_MHz;
type from_PLATFORM_IO_t is record
not_used : std_logic;

18
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/platform_variant_pkg.vhd
View File

@ -36,11 +36,11 @@ package platform_variant_pkg is
2 => "lr-b-4c"
);
type pal_rgb_t is array (0 to 2) of std_logic_vector(7 downto 0);
type pal_a is array (natural range <>) of pal_rgb_t;
type pal_rgb_t is array (0 to 2) of std_logic_vector(7 downto 0);
type pal_a is array (natural range <>) of pal_rgb_t;
constant tile_pal : pal_a(0 to 255) :=
(
constant tile_pal : pal_a(0 to 255) :=
(
17 => (0=>"00000011", 1=>"11111111", 2=>"11111111"), -- 03FFFF
25 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
33 => (0=>"11111111", 1=>"11111111", 2=>"11111111"), -- FFFFFF
@ -200,11 +200,11 @@ package platform_variant_pkg is
251 => (0=>"10110111", 1=>"01110000", 2=>"01100010"), -- B77062
252 => (0=>"11001100", 1=>"01110000", 2=>"10000100"), -- CC7084
253 => (0=>"11110000", 1=>"10100110", 2=>"10010100"), -- F0A694
others => (others => "00000011")
others => (others => "00000011")
);
constant sprite_pal : pal_a(0 to 255) :=
(
constant sprite_pal : pal_a(0 to 255) :=
(
1 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
2 => (0=>"00000011", 1=>"11111111", 2=>"00000011"), -- 03FF03
3 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
@ -411,8 +411,8 @@ package platform_variant_pkg is
253 => (0=>"11111111", 1=>"11111111", 2=>"11111111"), -- FFFFFF
254 => (0=>"00000011", 1=>"10010100", 2=>"00000011"), -- 039403
255 => (0=>"11110000", 1=>"11110000", 2=>"11110000"), -- F0F0F0
others => (others => "00000011")
);
others => (others => "00000011")
);
-- table of sprite heights
type prom_a is array (natural range <>) of integer range 0 to 3;

185
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/sprite_array.vhd
View File

@ -16,9 +16,9 @@ entity sprite_array is
N_SPRITES : integer;
DELAY : integer
);
port
(
reset : in std_logic;
port
(
reset : in std_logic;
-- register interface
reg_i : in to_SPRITE_REG_t;
@ -29,7 +29,7 @@ entity sprite_array is
-- extra data
graphics_i : in to_GRAPHICS_t;
-- sprite data
-- sprite data
row_a : out SPRITE_ROW_A_t;
row_d : in SPRITE_ROW_D_t;
@ -38,49 +38,49 @@ entity sprite_array is
set : out std_logic;
pri : out std_logic;
spr0_set : out std_logic
);
);
end entity sprite_array;
architecture SYN of sprite_array is
type reg_a_t is array (natural range <>) of from_SPRITE_REG_t;
type reg_a_t is array (natural range <>) of from_SPRITE_REG_t;
type ctl_i_a_t is array (natural range <>) of to_SPRITE_CTL_t;
type ctl_o_a_t is array (natural range <>) of from_SPRITE_CTL_t;
alias clk : std_logic is video_ctl.clk;
alias clk_ena : std_logic is video_ctl.clk_ena;
signal reg_o : reg_a_t(0 to N_SPRITES-1);
alias clk : std_logic is video_ctl.clk;
alias clk_ena : std_logic is video_ctl.clk_ena;
signal reg_o : reg_a_t(0 to N_SPRITES-1);
signal ctl_i : ctl_i_a_t(0 to N_SPRITES-1);
signal ctl_o : ctl_o_a_t(0 to N_SPRITES-1);
signal ld_r : std_logic_vector(N_SPRITES-1 downto 0);
signal ld_r : std_logic_vector(N_SPRITES-1 downto 0);
begin
-- Sprite Data Load Arbiter
-- - enables each sprite controller during hblank
-- to allow loading of sprite row data into row buffer
process (clk, clk_ena, reset)
variable i : integer range 0 to N_SPRITES-1;
begin
if reset = '1' then
-- enable must be 1 clock behind address to latch data after fetch
--ld_r <= (N_SPRITES-1 => '1', others => '0');
-- Sprite Data Load Arbiter
-- - enables each sprite controller during hblank
-- to allow loading of sprite row data into row buffer
process (clk, clk_ena, reset)
variable i : integer range 0 to N_SPRITES-1;
begin
if reset = '1' then
-- enable must be 1 clock behind address to latch data after fetch
--ld_r <= (N_SPRITES-1 => '1', others => '0');
-- make ISE 9.2.03i happy...
ld_r(ld_r'left) <= '1';
ld_r(ld_r'left-1 downto 0) <= (others => '0');
i := 0;
elsif rising_edge(clk) and clk_ena = '1' then
ld_r <= ld_r(ld_r'left-1 downto 0) & ld_r(ld_r'left);
if i = N_SPRITES-1 then
i := 0;
else
i := i + 1;
end if;
ld_r(ld_r'left) <= '1';
ld_r(ld_r'left-1 downto 0) <= (others => '0');
i := 0;
elsif rising_edge(clk) and clk_ena = '1' then
ld_r <= ld_r(ld_r'left-1 downto 0) & ld_r(ld_r'left);
if i = N_SPRITES-1 then
i := 0;
else
i := i + 1;
end if;
row_a <= ctl_o(i).a;
end if;
end process;
end if;
end process;
-- sprite row data fan-out
GEN_ROW_D : for i in 0 to N_SPRITES-1 generate
@ -88,63 +88,63 @@ begin
ctl_i(i).d <= row_d;
end generate GEN_ROW_D;
-- Sprite Priority Encoder
-- - determines which sprite pixel (if any) is to be displayed
-- We can use a clocked process here because the tilemap
-- output is 1 clock behind at this point
process (clk, clk_ena)
variable spr_on_v : std_logic := '0';
variable spr_pri_v : std_logic := '0';
begin
if rising_edge(clk) and clk_ena = '1' then
spr_on_v := '0';
spr_pri_v := '0';
for i in 0 to N_SPRITES-1 loop
-- if highest priority = 0 and pixel on
if spr_pri_v = '0' and ctl_o(i).set = '1' then
-- if no sprite on or this priority = 1
if spr_on_v = '0' or reg_o(i).pri = '1' then
rgb <= ctl_o(i).rgb;
spr_on_v := '1'; -- flag as sprite on
spr_pri_v := reg_o(i).pri; -- store priority
end if;
end if;
end loop;
end if;
set <= spr_on_v;
pri <= spr_pri_v;
end process;
-- Sprite Priority Encoder
-- - determines which sprite pixel (if any) is to be displayed
-- We can use a clocked process here because the tilemap
-- output is 1 clock behind at this point
process (clk, clk_ena)
variable spr_on_v : std_logic := '0';
variable spr_pri_v : std_logic := '0';
begin
if rising_edge(clk) and clk_ena = '1' then
spr_on_v := '0';
spr_pri_v := '0';
for i in 0 to N_SPRITES-1 loop
-- if highest priority = 0 and pixel on
if spr_pri_v = '0' and ctl_o(i).set = '1' then
-- if no sprite on or this priority = 1
if spr_on_v = '0' or reg_o(i).pri = '1' then
rgb <= ctl_o(i).rgb;
spr_on_v := '1'; -- flag as sprite on
spr_pri_v := reg_o(i).pri; -- store priority
end if;
end if;
end loop;
end if;
set <= spr_on_v;
pri <= spr_pri_v;
end process;
-- for NES, and perhaps others
-- it's actually more complicated than this
-- but it'll do for now...
spr0_set <= ctl_o(0).set;
--
-- Component Instantiation
--
GEN_REGS : for i in 0 to N_SPRITES-1 generate
sptReg_inst : entity work.sptReg
generic map
(
INDEX => i
)
port map
(
reg_i => reg_i,
reg_o => reg_o(i)
);
-- for NES, and perhaps others
-- it's actually more complicated than this
-- but it'll do for now...
spr0_set <= ctl_o(0).set;
sptCtl_inst : entity work.spritectl
generic map
(
INDEX => i,
DELAY => DELAY
)
port map
(
--
-- Component Instantiation
--
GEN_REGS : for i in 0 to N_SPRITES-1 generate
sptReg_inst : entity work.sptReg
generic map
(
INDEX => i
)
port map
(
reg_i => reg_i,
reg_o => reg_o(i)
);
sptCtl_inst : entity work.spritectl
generic map
(
INDEX => i,
DELAY => DELAY
)
port map
(
-- sprite registers
reg_i => reg_o(i),
@ -157,8 +157,7 @@ begin
graphics_i => graphics_i
);
end generate GEN_REGS;
end SYN;
end generate GEN_REGS;
end SYN;

2
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/sprite_pkg.vhd
View File

@ -57,7 +57,7 @@ package sprite_pkg is
);
port
(
reset : in std_logic;
reset : in std_logic;
-- register interface
reg_i : in to_SPRITE_REG_t;

64
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/spritectl.vhd
View File

@ -11,13 +11,13 @@ use work.platform_pkg.all;
use work.platform_variant_pkg.all;
entity spritectl is
generic
(
INDEX : natural;
DELAY : integer
);
port
(
generic
(
INDEX : natural;
DELAY : integer
);
port
(
-- sprite registers
reg_i : in from_SPRITE_REG_t;
@ -28,8 +28,8 @@ entity spritectl is
ctl_i : in to_SPRITE_CTL_t;
ctl_o : out from_SPRITE_CTL_t;
graphics_i : in to_GRAPHICS_t
);
graphics_i : in to_GRAPHICS_t
);
end entity spritectl;
architecture SYN of spritectl is
@ -47,22 +47,22 @@ begin
flipData(31 downto 16) <= flip_1 (ctl_i.d(31 downto 16), reg_i.xflip);
flipData(15 downto 0) <= flip_1 (ctl_i.d(15 downto 0), reg_i.xflip);
process (clk, clk_ena)
process (clk, clk_ena)
variable rowStore : std_logic_vector(47 downto 0); -- saved row of spt to show during visibile period
variable pel : std_logic_vector(2 downto 0);
variable x : unsigned(video_ctl.x'range);
variable y : unsigned(video_ctl.y'range);
variable yMat : boolean; -- raster is between first and last line of sprite
variable xMat : boolean; -- raster in between left edge and end of line
variable rowStore : std_logic_vector(47 downto 0); -- saved row of spt to show during visibile period
variable pel : std_logic_vector(2 downto 0);
variable x : unsigned(video_ctl.x'range);
variable y : unsigned(video_ctl.y'range);
variable yMat : boolean; -- raster is between first and last line of sprite
variable xMat : boolean; -- raster in between left edge and end of line
variable height : unsigned(6 downto 0);
-- the width of rowCount determines the scanline multipler
-- - eg. (4 downto 0) is 1:1
-- (5 downto 0) is 2:1 (scan-doubling)
-- variable rowCount : unsigned(3+PACE_VIDEO_V_SCALE downto 0);
-- alias row : unsigned(4 downto 0) is
-- rowCount(rowCount'left downto rowCount'left-4);
variable height : unsigned(6 downto 0);
-- the width of rowCount determines the scanline multipler
-- - eg. (4 downto 0) is 1:1
-- (5 downto 0) is 2:1 (scan-doubling)
-- variable rowCount : unsigned(3+PACE_VIDEO_V_SCALE downto 0);
-- alias row : unsigned(4 downto 0) is
-- rowCount(rowCount'left downto rowCount'left-4);
variable rowCount : unsigned(height'range);
alias row : unsigned(rowCount'range) is rowCount;
-- which part of the sprite is being drawn
@ -71,11 +71,11 @@ begin
variable prom_i : integer range sprite_prom'range;
variable code : std_logic_vector(9 downto 0);
variable pal_i : std_logic_vector(7 downto 0);
variable pal_rgb : pal_rgb_t;
variable pal_rgb : pal_rgb_t;
begin
if rising_edge(clk) then
if rising_edge(clk) then
if clk_ena = '1' then
if video_ctl.hblank = '1' then
@ -104,7 +104,7 @@ begin
rowCount := (others => '0');
yMat := true;
elsif row = height then
yMat := false;
yMat := false;
end if;
case sprite_prom(prom_i) is
@ -132,19 +132,19 @@ begin
yMat := false;
end if;
-- sprites not visible before row 16
-- sprites not visible before row 16
if ctl_i.ld = '1' then
if yMat then
rowStore := flipData; -- load sprite data
rowStore := flipData; -- load sprite data
else
rowStore := (others => '0');
end if;
end if;
end if; -- hblank='1'
if video_ctl.stb = '1' then
if x = unsigned(video_ctl.x) then
-- count up at left edge of sprite
rowCount := rowCount + 1;
@ -153,7 +153,7 @@ begin
xMat := true;
--end if;
end if;
if xMat then
-- shift in next pixel
pel := rowStore(rowStore'left-32) & rowStore(rowStore'left-16) & rowStore(rowStore'left);

14
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/tilemapctl.vhd
View File

@ -10,9 +10,9 @@ use work.platform_variant_pkg.all;
use work.video_controller_pkg.all;
--
-- Irem M62 Tilemap Controller
-- Irem M62 Tilemap Controller
--
-- Tile data is 2 BPP.
-- Tile data is 2 BPP.
--
architecture TILEMAP_1 of tilemapCtl is
@ -32,7 +32,7 @@ architecture TILEMAP_1 of tilemapCtl is
begin
-- not used
ctl_o.map_a(ctl_o.map_a'left downto 11) <= (others => '0');
ctl_o.map_a(ctl_o.map_a'left downto 11) <= (others => '0');
ctl_o.attr_a(ctl_o.attr_a'left downto 11) <= (others => '0');
ctl_o.tile_a(ctl_o.tile_a'left downto 13) <= (others => '0');
@ -48,13 +48,13 @@ begin
variable tile_d_r : std_logic_vector(23 downto 0);
variable attr_d_r : std_logic_vector(7 downto 0);
variable pel : std_logic_vector(2 downto 0);
variable pel : std_logic_vector(2 downto 0);
variable pal_i : std_logic_vector(7 downto 0);
variable pal_rgb : pal_rgb_t;
variable pal_rgb : pal_rgb_t;
begin
if rising_edge(clk) then
if rising_edge(clk) then
if clk_ena = '1' then
-- 1st stage of pipeline
@ -99,7 +99,7 @@ begin
-- end if;
end if; -- clk_ena
end if; -- rising_edge_clk
end if; -- rising_edge_clk
end process;

2
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/tilemapctl_e.vhd
View File

@ -15,7 +15,7 @@ entity tilemapCtl is
);
port
(
reset : in std_logic;
reset : in std_logic;
-- video control signals
video_ctl : in from_VIDEO_CTL_t;

73
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/video_controller.vhd
View File

@ -8,31 +8,31 @@ use work.video_controller_pkg.all;
entity pace_video_controller is
generic
(
CONFIG : PACEVideoController_t := PACE_VIDEO_NONE;
DELAY : integer := 1;
H_SIZE : integer;
V_SIZE : integer;
CONFIG : PACEVideoController_t := PACE_VIDEO_NONE;
DELAY : integer := 1;
H_SIZE : integer;
V_SIZE : integer;
L_CROP : integer range 0 to 255;
R_CROP : integer range 0 to 255;
H_SCALE : integer;
V_SCALE : integer;
H_SCALE : integer;
V_SCALE : integer;
H_SYNC_POL : std_logic := '1';
V_SYNC_POL : std_logic := '1';
BORDER_RGB : RGB_t := RGB_BLACK
BORDER_RGB : RGB_t := RGB_BLACK
);
port
(
-- clocking etc
video_i : in from_VIDEO_t;
-- register interface
reg_i : in VIDEO_REG_t;
-- register interface
reg_i : in VIDEO_REG_t;
-- video input data
rgb_i : in RGB_t;
-- control signals (out)
video_ctl_o : out from_VIDEO_CTL_t;
-- control signals (out)
video_ctl_o : out from_VIDEO_CTL_t;
-- video output control & data
video_o : out to_VIDEO_t
@ -43,8 +43,8 @@ architecture SYN of pace_video_controller is
constant SIM_DELAY : time := 2 ns;
constant VIDEO_H_SIZE : integer := H_SIZE * H_SCALE;
constant VIDEO_V_SIZE : integer := V_SIZE * V_SCALE;
constant VIDEO_H_SIZE : integer := H_SIZE * H_SCALE;
constant VIDEO_V_SIZE : integer := V_SIZE * V_SCALE;
subtype reg_t is integer range 0 to 2047;
@ -100,13 +100,13 @@ architecture SYN of pace_video_controller is
begin
-- registers
reg_proc: process (reset, clk)
reg_proc: process (reset, clk)
begin
--if reset = '1' then
case CONFIG is
begin
--if reset = '1' then
case CONFIG is
when PACE_VIDEO_VGA_240x320_60Hz =>
when PACE_VIDEO_VGA_240x320_60Hz =>
-- P3M, clk=11.136MHz, clk_ena=5.568MHz
h_front_porch_r <= 272-240;
h_sync_r <= 5;
@ -258,26 +258,27 @@ begin
v_back_porch_r <= 13;
v_border_r <= (240-VIDEO_V_SIZE)/2;
when PACE_VIDEO_PAL_576x288_50Hz =>
-- pixclk=11 MHz
h_front_porch_r <= 2*6;
h_sync_r <= 2*28;
h_back_porch_r <= 2*30;
h_border_r <= (576-VIDEO_H_SIZE)/2;
v_front_porch_r <= 8;
v_sync_r <= 3;
v_back_porch_r <= 13;
v_border_r <= (288-VIDEO_V_SIZE)/2;
when others =>
null;
end case;
when PACE_VIDEO_PAL_576x288_50Hz =>
-- pixclk=11 MHz
h_front_porch_r <= 2*6;
h_sync_r <= 2*28;
h_back_porch_r <= 2*30;
h_border_r <= (576-VIDEO_H_SIZE)/2;
v_front_porch_r <= 8;
v_sync_r <= 3;
v_back_porch_r <= 13;
v_border_r <= (288-VIDEO_V_SIZE)/2;
h_video_r <= VIDEO_H_SIZE;
v_video_r <= VIDEO_V_SIZE;
border_rgb_r <= BORDER_RGB;
when others =>
null;
end case;
h_video_r <= VIDEO_H_SIZE;
v_video_r <= VIDEO_V_SIZE;
border_rgb_r <= BORDER_RGB;
--end if;
end process reg_proc;
--end if;
end process reg_proc;
-- register some arithmetic
init_proc: process (reset, clk, clk_ena)

48
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/video_controller_pkg.vhd
View File

@ -52,10 +52,10 @@ package video_controller_pkg is
constant RGB_CYAN : RGB_t := ((others=>'0'),(others=>'1'),(others=>'1'));
constant RGB_WHITE : RGB_t := ((others=>'1'),(others=>'1'),(others=>'1'));
type VIDEO_REG_t is record
h_scale : std_logic_vector(2 downto 0);
v_scale : std_logic_vector(2 downto 0);
end record;
type VIDEO_REG_t is record
h_scale : std_logic_vector(2 downto 0);
v_scale : std_logic_vector(2 downto 0);
end record;
type from_VIDEO_t is record
clk : std_logic;
@ -187,25 +187,25 @@ package video_controller_pkg is
);
end component pace_video_controller;
component tilemapCtl is
generic
(
DELAY : integer
);
port
(
reset : in std_logic;
-- video control signals
video_ctl : in from_VIDEO_CTL_t;
-- tilemap controller signals
ctl_i : in to_TILEMAP_CTL_t;
ctl_o : out from_TILEMAP_CTL_t;
graphics_i : in to_GRAPHICS_t
);
end component tilemapCtl;
component tilemapCtl is
generic
(
DELAY : integer
);
port
(
reset : in std_logic;
-- video control signals
video_ctl : in from_VIDEO_CTL_t;
-- tilemap controller signals
ctl_i : in to_TILEMAP_CTL_t;
ctl_o : out from_TILEMAP_CTL_t;
graphics_i : in to_GRAPHICS_t
);
end component tilemapCtl;
component bitmapCtl is
generic
@ -214,7 +214,7 @@ package video_controller_pkg is
);
port
(
reset : in std_logic;
reset : in std_logic;
-- video control signals
video_ctl : in from_VIDEO_CTL_t;