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https://github.com/Gehstock/Mist_FPGA.git
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commit
1b8fc108ef
@ -291,7 +291,7 @@ end
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wire [15:0] mA;
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wire [7:0] mD_out;
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wire m_rw;
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/*
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cpu09 u12G
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(
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.clk(~clk_49m),
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@ -306,14 +306,13 @@ cpu09 u12G
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.firq(0),
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.nmi(0)
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);
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*/
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/*
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// buggy (playfield scrolling is broken with this CPU)
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mc6809is u12G
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(
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.CLK(clk_49m),
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.fallE_en(n_me_en),
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.fallQ_en(n_mq_en),
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.CLK(clk_49m),
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.fallE_en(n_me_en),
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.fallQ_en(n_mq_en),
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.D(mD_in),
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.DOut(mD_out),
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.ADDR(mA),
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@ -325,7 +324,7 @@ mc6809is u12G
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.nRESET(n_res),
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.nDMABREQ(1'b1)
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);
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*/
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//Multiplex data inputs to primary MC6809E
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wire [7:0] mD_in =
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sndbrd_dir ? sndbrd_D:
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@ -1971,10 +1971,13 @@ begin
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else if (Inst1 == OPCODE_INH_SEX)
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begin
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a_nxt = {8{b[7]}};
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cc_nxt[CC_N_BIT] = b[7];
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cc_nxt[CC_Z_BIT] = {b == 8'H00};
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cc_nxt[CC_V_BIT] = 1'b0;
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rLIC = 1'b1; // Instruction done!
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rAVMA = 1'b1;
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CpuState_nxt = CPUSTATE_FETCH_I1;
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end
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end
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else if (Inst1 == OPCODE_INH_ABX)
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begin
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x_nxt = x + b;
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@ -1969,10 +1969,13 @@ begin
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else if (Inst1 == OPCODE_INH_SEX)
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begin
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a_nxt = {8{b[7]}};
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cc_nxt[CC_N_BIT] = b[7];
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cc_nxt[CC_Z_BIT] = {b == 8'H00};
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cc_nxt[CC_V_BIT] = 1'b0;
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rLIC = 1'b1; // Instruction done!
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rAVMA = 1'b1;
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CpuState_nxt = CPUSTATE_FETCH_I1;
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end
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end
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else if (Inst1 == OPCODE_INH_ABX)
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begin
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x_nxt = x + b;
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