github.com/Gehstock.Mist_FPGA
1
0
Fork 0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-19 01:16:58 +00:00
Code Issues Releases Wiki Activity

Kroozr: remove CTC prescaler divide/2 (why was it there?)

Browse Source
This commit is contained in:
Gyorgy Szombathelyi 2019-12-21 16:53:29 +01:00
parent cbc8260a3a
commit 264346ff3c
2 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Arcade_MiST/Midway MCR 2/Kozmik Kroozr_MiST/rtl/ctc_controler.vhd
View File

@ -60,7 +60,7 @@ begin
int_reg_1 <= '0';
int_reg_2 <= '0';
int_reg_3 <= '0';
load_data_r <= load_data;
load_data_r <= '0';
int_vector <= (others => '0');
else
if rising_edge(clock) then

5
Arcade_MiST/Midway MCR 2/Kozmik Kroozr_MiST/rtl/ctc_counter.vhd
View File

@ -70,7 +70,7 @@ begin
restart_on_next_trigger <= '0';
count_in <= (others=> '0');
zc_to_in <= '0';
clk_trg_r <= clk_trg;
clk_trg_r <= '0';
else
if rising_edge(clock) then
if clock_ena = '1' then
@ -132,7 +132,8 @@ begin
if ((control_word(6) = '1' and trigger = '1' ) or
(control_word(6) = '0' and count_ena = '1') ) and time_constant_loaded = '1' then
if prescale_in = 0 then
prescale_in <= '0'&prescale_max(7 downto 1); -- test divide by 2 !
prescale_in <= prescale_max;
-- prescale_in <= '0'&prescale_max(7 downto 1); -- test divide by 2 !
if count_in = 0 then
zc_to_in <= '1';
count_in <= count_max;