small fixes to compile cores

Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/CClimber_mist.sv

@@ -16,7 +16,7 @@ module CClimber_mist (
 	input         CLOCK_27
 );
 
-`include "rtl\build_id.sv" 
+`include "rtl\build_id.v" 
 
 localparam CONF_STR = {
 	"CClimber;;",

Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/DottoriKun.qsf

@@ -42,6 +42,7 @@
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:44:34  AUGUST 14, 2017"
 set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 
 # Pin & Location Assignments

Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/build_id.tcl

@@ -17,7 +17,7 @@ proc generateBuildID_Verilog {} {
 	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
 
 	# Create a Verilog file for output
-	set outputFileName "sys/build_id.v"
+	set outputFileName "rtl/build_id.v"
 	set outputFile [open $outputFileName "w"]
 
 	# Output the Verilog source

Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/clean.bat

@@ -4,7 +4,7 @@ del /s *.orig
 del /s *.rej
 rmdir /s /q db
 rmdir /s /q incremental_db
-rmdir /s /q output
+rmdir /s /q output_files
 rmdir /s /q simulation
 rmdir /s /q greybox_tmp
 del PLLJ_PLLSPE_INFO.txt

Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf

@@ -42,7 +42,7 @@
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:07:52  FEBRUARY 01, 2013"
 set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY Output
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:src/build_id.tcl"
 

Arcade_MiST/Non Arcade/RiverRaid_MiST(Clone)/RiverRaid.qsf

@@ -42,7 +42,7 @@
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:26:34  JANUARY 27, 2011"
 set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 
 # Pin & Location Assignments
 # ==========================

Arcade_MiST/Pacman Hardware/Eggor_MiST/Eggor.qsf

@@ -153,12 +153,7 @@ set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/PROM3_DST.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
 set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 set_global_assignment -name VHDL_FILE rtl/dac.vhd
 set_global_assignment -name QIP_FILE rtl/pll.qip

Arcade_MiST/Pacman Hardware/Eyes_MiST/Eyes.qsf

@@ -156,12 +156,7 @@ set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/PROM3_DST.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
 set_global_assignment -name QIP_FILE rtl/pll.qip
 set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 set_global_assignment -name VHDL_FILE rtl/dac.vhd