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Gehstock
2019-02-09 15:36:17 +01:00
parent 20ff9d3d14
commit 2aeee7f0b1
144 changed files with 6636 additions and 7999 deletions
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45
Computer_MiST/Jupiter Cantab - JupiterACE_MiST/ace.qsf
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@@ -44,25 +44,6 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY Output
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VERILOG_FILE rtl/glue.v
set_global_assignment -name VERILOG_FILE rtl/T80/tv80n.v
set_global_assignment -name VERILOG_FILE rtl/T80/tv80_reg.v
set_global_assignment -name VERILOG_FILE rtl/T80/tv80_mcode.v
set_global_assignment -name VERILOG_FILE rtl/T80/tv80_core.v
set_global_assignment -name VERILOG_FILE rtl/T80/tv80_alu.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ace_mist.sv
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v
set_global_assignment -name VERILOG_FILE rtl/jupiter_ace.v
set_global_assignment -name VERILOG_FILE rtl/keyboard.v
set_global_assignment -name VERILOG_FILE rtl/rom_ram.v
set_global_assignment -name VERILOG_FILE rtl/ps2_port.v
set_global_assignment -name VERILOG_FILE rtl/io_write_to_rom.v
# Pin & Location Assignments
# ==========================
@@ -202,14 +183,32 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulati
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(ace_mist)
# --------------------
set_global_assignment -name VERILOG_FILE rtl/sram.v
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ace_mist.sv
set_global_assignment -name VERILOG_FILE rtl/jupiter_ace.v
set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80pa.vhd
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v
set_global_assignment -name VERILOG_FILE rtl/keyboard.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video.sv
set_global_assignment -name VERILOG_FILE rtl/dpram.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80.vhd Normal file
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376
Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80_ALU.vhd Normal file
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@@ -0,0 +1,376 @@
--------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- Z80 compatible microprocessor core
--
-- Version : 0247
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
-- 0240 : Added GB operations
-- 0242 : Cleanup
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
WZ : in std_logic_vector(15 downto 0);
XY_State : in std_logic_vector(1 downto 0);
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, WZ, XY_State)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
if IR(2 downto 0) = "110" or XY_State /= "00" then
F_Out(Flag_X) <= WZ(11);
F_Out(Flag_Y) <= WZ(13);
else
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

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--------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0);
DOR : out std_logic_vector(127 downto 0);
DIRSet : in std_logic;
DIR : in std_logic_vector(127 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if rising_edge(Clk) then
if DIRSet = '1' then
RegsL(0) <= DIR( 7 downto 0);
RegsH(0) <= DIR( 15 downto 8);
RegsL(1) <= DIR( 23 downto 16);
RegsH(1) <= DIR( 31 downto 24);
RegsL(2) <= DIR( 39 downto 32);
RegsH(2) <= DIR( 47 downto 40);
RegsL(3) <= DIR( 55 downto 48);
RegsH(3) <= DIR( 63 downto 56);
RegsL(4) <= DIR( 71 downto 64);
RegsH(4) <= DIR( 79 downto 72);
RegsL(5) <= DIR( 87 downto 80);
RegsH(5) <= DIR( 95 downto 88);
RegsL(6) <= DIR(103 downto 96);
RegsH(6) <= DIR(111 downto 104);
RegsL(7) <= DIR(119 downto 112);
RegsH(7) <= DIR(127 downto 120);
elsif CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
DOR <= RegsH(7) & RegsL(7) & RegsH(6) & RegsL(6) & RegsH(5) & RegsL(5) & RegsH(4) & RegsL(4) & RegsH(3) & RegsL(3) & RegsH(2) & RegsL(2) & RegsH(1) & RegsL(1) & RegsH(0) & RegsL(0);
end;

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--
-- Z80 compatible microprocessor core, preudo-asynchronous top level (by Sorgelig)
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- File history :
--
-- v1.0: convert to preudo-asynchronous model with original Z80 timings.
--
-- v2.0: rewritten for more precise timings.
-- support for both CEN_n and CEN_p set to 1. Effective clock will be CLK/2.
--
-- v2.1: Output Address 0 during non-bus MCycle (fix ZX contention)
--
-- v2.2: Interrupt acknowledge cycle has been corrected
-- WAIT_n is broken in T80.vhd. Simulate correct WAIT_n locally.
--
-- v2.3: Output last used Address during non-bus MCycle seems more correct.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80pa is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CEN_p : in std_logic := '1';
CEN_n : in std_logic := '1';
WAIT_n : in std_logic := '1';
INT_n : in std_logic := '1';
NMI_n : in std_logic := '1';
BUSRQ_n : in std_logic := '1';
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
OUT0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
REG : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
DIRSet : in std_logic := '0';
DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
);
end T80pa;
architecture rtl of T80pa is
signal IntCycle_n : std_logic;
signal IntCycleD_n : std_logic_vector(1 downto 0);
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal BUSAK : std_logic;
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal CEN_pol : std_logic;
signal A_int : std_logic_vector(15 downto 0);
signal A_last : std_logic_vector(15 downto 0);
begin
A <= A_int when NoRead = '0' or Write = '1' else A_last;
BUSAK_n <= BUSAK;
u0 : work.T80
generic map(
Mode => Mode,
IOWait => 1
)
port map(
CEN => CEN_p and not CEN_pol,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => '1',
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK,
CLK_n => CLK,
A => A_int,
DInst => DI, -- valid at beginning of T3
DI => DI_Reg, -- latched at middle of T3
DO => DO,
REG => REG,
MC => MCycle,
TS => TState,
OUT0 => OUT0,
IntCycle_n => IntCycle_n,
DIRSet => DIRSet,
DIR => DIR
);
process(CLK)
begin
if rising_edge(CLK) then
if RESET_n = '0' then
WR_n <= '1';
RD_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
CEN_pol <= '0';
elsif CEN_p = '1' and CEN_pol = '0' then
CEN_pol <= '1';
if MCycle = "001" then
if TState = "010" then
IORQ_n <= '1';
MREQ_n <= '1';
RD_n <= '1';
end if;
else
if TState = "001" and IORQ = '1' then
WR_n <= not Write;
RD_n <= Write;
IORQ_n <= '0';
end if;
end if;
elsif CEN_n = '1' and CEN_pol = '1' then
if TState = "010" then
CEN_pol <= not WAIT_n;
else
CEN_pol <= '0';
end if;
if TState = "011" and BUSAK = '1' then
DI_Reg <= DI;
end if;
if MCycle = "001" then
if TState = "001" then
IntCycleD_n <= IntCycleD_n(0) & IntCycle_n;
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycleD_n(1);
A_last <= A_int;
end if;
if TState = "011" then
IntCycleD_n <= "11";
RD_n <= '1';
MREQ_n <= '0';
end if;
if TState = "100" then
MREQ_n <= '1';
end if;
else
if NoRead = '0' and IORQ = '0' then
if TState = "001" then
RD_n <= Write;
MREQ_n <= '0';
A_last <= A_int;
end if;
end if;
if TState = "010" then
WR_n <= not Write;
end if;
if TState = "011" then
WR_n <= '1';
RD_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
end if;
end if;
end if;
end if;
end process;
end;

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//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80_alu (/*AUTOARG*/
// Outputs
Q, F_Out,
// Inputs
Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In
);
parameter Mode = 0;
parameter Flag_C = 0;
parameter Flag_N = 1;
parameter Flag_P = 2;
parameter Flag_X = 3;
parameter Flag_H = 4;
parameter Flag_Y = 5;
parameter Flag_Z = 6;
parameter Flag_S = 7;
input Arith16;
input Z16;
input [3:0] ALU_Op ;
input [5:0] IR;
input [1:0] ISet;
input [7:0] BusA;
input [7:0] BusB;
input [7:0] F_In;
output [7:0] Q;
output [7:0] F_Out;
reg [7:0] Q;
reg [7:0] F_Out;
function [4:0] AddSub4;
input [3:0] A;
input [3:0] B;
input Sub;
input Carry_In;
begin
AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
end
endfunction // AddSub4
function [3:0] AddSub3;
input [2:0] A;
input [2:0] B;
input Sub;
input Carry_In;
begin
AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
end
endfunction // AddSub4
function [1:0] AddSub1;
input A;
input B;
input Sub;
input Carry_In;
begin
AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
end
endfunction // AddSub4
// AddSub variables (temporary signals)
reg UseCarry;
reg Carry7_v;
reg OverFlow_v;
reg HalfCarry_v;
reg Carry_v;
reg [7:0] Q_v;
reg [7:0] BitMask;
always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR)
begin
case (IR[5:3])
3'b000 : BitMask = 8'b00000001;
3'b001 : BitMask = 8'b00000010;
3'b010 : BitMask = 8'b00000100;
3'b011 : BitMask = 8'b00001000;
3'b100 : BitMask = 8'b00010000;
3'b101 : BitMask = 8'b00100000;
3'b110 : BitMask = 8'b01000000;
default: BitMask = 8'b10000000;
endcase // case(IR[5:3])
UseCarry = ~ ALU_Op[2] && ALU_Op[0];
{ HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) );
{ Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v);
{ Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v);
OverFlow_v = Carry_v ^ Carry7_v;
end // always @ *
reg [7:0] Q_t;
reg [8:0] DAA_Q;
always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB
or Carry_v or F_In or HalfCarry_v or IR or ISet
or OverFlow_v or Q_v or Z16)
begin
Q_t = 8'hxx;
DAA_Q = {9{1'bx}};
F_Out = F_In;
case (ALU_Op)
4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 :
begin
F_Out[Flag_N] = 1'b0;
F_Out[Flag_C] = 1'b0;
case (ALU_Op[2:0])
3'b000, 3'b001 : // ADD, ADC
begin
Q_t = Q_v;
F_Out[Flag_C] = Carry_v;
F_Out[Flag_H] = HalfCarry_v;
F_Out[Flag_P] = OverFlow_v;
end
3'b010, 3'b011, 3'b111 : // SUB, SBC, CP
begin
Q_t = Q_v;
F_Out[Flag_N] = 1'b1;
F_Out[Flag_C] = ~ Carry_v;
F_Out[Flag_H] = ~ HalfCarry_v;
F_Out[Flag_P] = OverFlow_v;
end
3'b100 : // AND
begin
Q_t[7:0] = BusA & BusB;
F_Out[Flag_H] = 1'b1;
end
3'b101 : // XOR
begin
Q_t[7:0] = BusA ^ BusB;
F_Out[Flag_H] = 1'b0;
end
default : // OR 3'b110
begin
Q_t[7:0] = BusA | BusB;
F_Out[Flag_H] = 1'b0;
end
endcase // case(ALU_OP[2:0])
if (ALU_Op[2:0] == 3'b111 )
begin // CP
F_Out[Flag_X] = BusB[3];
F_Out[Flag_Y] = BusB[5];
end
else
begin
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
end
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
if (Z16 == 1'b1 )
begin
F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC
end
end
else
begin
F_Out[Flag_Z] = 1'b0;
end // else: !if(Q_t[7:0] == 8'b00000000 )
F_Out[Flag_S] = Q_t[7];
case (ALU_Op[2:0])
3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP
;
default :
F_Out[Flag_P] = ~(^Q_t);
endcase // case(ALU_Op[2:0])
if (Arith16 == 1'b1 )
begin
F_Out[Flag_S] = F_In[Flag_S];
F_Out[Flag_Z] = F_In[Flag_Z];
F_Out[Flag_P] = F_In[Flag_P];
end
end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111
4'b1100 :
begin
// DAA
F_Out[Flag_H] = F_In[Flag_H];
F_Out[Flag_C] = F_In[Flag_C];
DAA_Q[7:0] = BusA;
DAA_Q[8] = 1'b0;
if (F_In[Flag_N] == 1'b0 )
begin
// After addition
// Alow > 9 || H == 1
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
begin
if ((DAA_Q[3:0] > 9) )
begin
F_Out[Flag_H] = 1'b1;
end
else
begin
F_Out[Flag_H] = 1'b0;
end
DAA_Q = DAA_Q + 6;
end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
// new Ahigh > 9 || C == 1
if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 )
begin
DAA_Q = DAA_Q + 96; // 0x60
end
end
else
begin
// After subtraction
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
begin
if (DAA_Q[3:0] > 5 )
begin
F_Out[Flag_H] = 1'b0;
end
DAA_Q[7:0] = DAA_Q[7:0] - 6;
end
if (BusA > 153 || F_In[Flag_C] == 1'b1 )
begin
DAA_Q = DAA_Q - 352; // 0x160
end
end // else: !if(F_In[Flag_N] == 1'b0 )
F_Out[Flag_X] = DAA_Q[3];
F_Out[Flag_Y] = DAA_Q[5];
F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8];
Q_t = DAA_Q[7:0];
if (DAA_Q[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_S] = DAA_Q[7];
F_Out[Flag_P] = ~ (^DAA_Q);
end // case: 4'b1100
4'b1101, 4'b1110 :
begin
// RLD, RRD
Q_t[7:4] = BusA[7:4];
if (ALU_Op[0] == 1'b1 )
begin
Q_t[3:0] = BusB[7:4];
end
else
begin
Q_t[3:0] = BusB[3:0];
end
F_Out[Flag_H] = 1'b0;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_S] = Q_t[7];
F_Out[Flag_P] = ~(^Q_t);
end // case: when 4'b1101, 4'b1110
4'b1001 :
begin
// BIT
Q_t[7:0] = BusB & BitMask;
F_Out[Flag_S] = Q_t[7];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
F_Out[Flag_P] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
F_Out[Flag_P] = 1'b0;
end
F_Out[Flag_H] = 1'b1;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = 1'b0;
F_Out[Flag_Y] = 1'b0;
if (IR[2:0] != 3'b110 )
begin
F_Out[Flag_X] = BusB[3];
F_Out[Flag_Y] = BusB[5];
end
end // case: when 4'b1001
4'b1010 :
// SET
Q_t[7:0] = BusB | BitMask;
4'b1011 :
// RES
Q_t[7:0] = BusB & ~ BitMask;
4'b1000 :
begin
// ROT
case (IR[5:3])
3'b000 : // RLC
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = BusA[7];
F_Out[Flag_C] = BusA[7];
end
3'b010 : // RL
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = F_In[Flag_C];
F_Out[Flag_C] = BusA[7];
end
3'b001 : // RRC
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = BusA[0];
F_Out[Flag_C] = BusA[0];
end
3'b011 : // RR
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = F_In[Flag_C];
F_Out[Flag_C] = BusA[0];
end
3'b100 : // SLA
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = 1'b0;
F_Out[Flag_C] = BusA[7];
end
3'b110 : // SLL (Undocumented) / SWAP
begin
if (Mode == 3 )
begin
Q_t[7:4] = BusA[3:0];
Q_t[3:0] = BusA[7:4];
F_Out[Flag_C] = 1'b0;
end
else
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = 1'b1;
F_Out[Flag_C] = BusA[7];
end // else: !if(Mode == 3 )
end // case: 3'b110
3'b101 : // SRA
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = BusA[7];
F_Out[Flag_C] = BusA[0];
end
default : // SRL
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = 1'b0;
F_Out[Flag_C] = BusA[0];
end
endcase // case(IR[5:3])
F_Out[Flag_H] = 1'b0;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
F_Out[Flag_S] = Q_t[7];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_P] = ~(^Q_t);
if (ISet == 2'b00 )
begin
F_Out[Flag_P] = F_In[Flag_P];
F_Out[Flag_S] = F_In[Flag_S];
F_Out[Flag_Z] = F_In[Flag_Z];
end
end // case: 4'b1000
default :
;
endcase // case(ALU_Op)
Q = Q_t;
end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
endmodule // T80_ALU

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//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80_reg (/*AUTOARG*/
// Outputs
DOBH, DOAL, DOCL, DOBL, DOCH, DOAH,
// Inputs
AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
);
input [2:0] AddrC;
output [7:0] DOBH;
input [2:0] AddrA;
input [2:0] AddrB;
input [7:0] DIH;
output [7:0] DOAL;
output [7:0] DOCL;
input [7:0] DIL;
output [7:0] DOBL;
output [7:0] DOCH;
output [7:0] DOAH;
input clk, CEN, WEH, WEL;
reg [7:0] RegsH [0:7];
reg [7:0] RegsL [0:7];
always @(posedge clk)
begin
if (CEN)
begin
if (WEH) RegsH[AddrA] <= DIH;
if (WEL) RegsL[AddrA] <= DIL;
end
end
assign DOAH = RegsH[AddrA];
assign DOAL = RegsL[AddrA];
assign DOBH = RegsH[AddrB];
assign DOBL = RegsL[AddrB];
assign DOCH = RegsH[AddrC];
assign DOCL = RegsL[AddrC];
// break out ram bits for waveform debug
wire [7:0] H = RegsH[2];
wire [7:0] L = RegsL[2];
endmodule

182
Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80n.v
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@@ -1,182 +0,0 @@
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// Negative-edge based wrapper allows memory wait_n signal to work
// correctly without resorting to asynchronous logic.
module tv80n (/*AUTOARG*/
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
);
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] dout;
reg mreq_n;
reg iorq_n;
reg rd_n;
reg wr_n;
reg nxt_mreq_n;
reg nxt_iorq_n;
reg nxt_rd_n;
reg nxt_wr_n;
wire cen;
wire intcycle_n;
wire no_read;
wire write;
wire iorq;
reg [7:0] di_reg;
wire [6:0] mcycle;
wire [6:0] tstate;
assign cen = 1;
tv80_core #(Mode, IOWait) i_tv80_core
(
.cen (cen),
.m1_n (m1_n),
.iorq (iorq),
.no_read (no_read),
.write (write),
.rfsh_n (rfsh_n),
.halt_n (halt_n),
.wait_n (wait_n),
.int_n (int_n),
.nmi_n (nmi_n),
.reset_n (reset_n),
.busrq_n (busrq_n),
.busak_n (busak_n),
.clk (clk),
.IntE (),
.stop (),
.A (A),
.dinst (di),
.di (di_reg),
.dout (dout),
.mc (mcycle),
.ts (tstate),
.intcycle_n (intcycle_n)
);
always @*
begin
nxt_mreq_n = 1;
nxt_rd_n = 1;
nxt_iorq_n = 1;
nxt_wr_n = 1;
if (mcycle[0])
begin
if (tstate[1] || tstate[2])
begin
nxt_rd_n = ~ intcycle_n;
nxt_mreq_n = ~ intcycle_n;
nxt_iorq_n = intcycle_n;
end
end // if (mcycle[0])
else
begin
if ((tstate[1] || tstate[2]) && !no_read && !write)
begin
nxt_rd_n = 1'b0;
nxt_iorq_n = ~ iorq;
nxt_mreq_n = iorq;
end
if (T2Write == 0)
begin
if (tstate[2] && write)
begin
nxt_wr_n = 1'b0;
nxt_iorq_n = ~ iorq;
nxt_mreq_n = iorq;
end
end
else
begin
if ((tstate[1] || (tstate[2] && !wait_n)) && write)
begin
nxt_wr_n = 1'b0;
nxt_iorq_n = ~ iorq;
nxt_mreq_n = iorq;
end
end // else: !if(T2write == 0)
end // else: !if(mcycle[0])
end // always @ *
always @(negedge clk)
begin
if (!reset_n)
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
end
else
begin
rd_n <= #1 nxt_rd_n;
wr_n <= #1 nxt_wr_n;
iorq_n <= #1 nxt_iorq_n;
mreq_n <= #1 nxt_mreq_n;
end // else: !if(!reset_n)
end // always @ (posedge clk or negedge reset_n)
always @(posedge clk)
begin
if (!reset_n)
begin
di_reg <= #1 0;
end
else
begin
if (tstate[2] && wait_n == 1'b1)
di_reg <= #1 di;
end // else: !if(!reset_n)
end // always @ (posedge clk)
endmodule // t80n

353
Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace.mif Normal file
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@@ -0,0 +1,353 @@
-- http://srecord.sourceforge.net/
--
-- Generated automatically by srec -o --mif
--
DEPTH = 8192;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: F3 21 00 3C 3E FC 18 20 D9 DD CB 3E 5E C3 EE 03 2A 3B 3C 73 23 C3 5F 08;
0018: 2A 3B 3C 2B 56 C3 59 08 E1 7E 32 3D 3C C3 AD 00 24 77 BE 28 FB A4 67 22;
0030: 18 3C F9 21 0D 01 18 03 C3 3A 01 11 24 3C 01 2D 00 ED B0 DD 21 00 3C FD;
0048: 21 C8 04 CD 24 0A AF 32 00 27 21 00 2C 7D E6 BF 0F 0F 0F 30 02 0F 0F 0F;
0060: 47 9F CB 18 47 9F A8 E6 F0 A8 77 2C 20 E7 11 FF 2F 21 FB 1F 01 08 00 ED;
0078: B8 EB 3E 5F 0E 07 CB 6F 28 03 70 2B 0D EB ED B8 EB 70 2B 3D 20 EE ED 56;
0090: 18 09 51 55 49 D4 00 00 04 9B 00 ED 7B 18 3C FB C3 F2 04 41 42 4F 52 D4;
00A8: 98 00 05 AD 00 FD E5 FD 21 B9 04 2A 37 3C 22 3B 3C 21 3E 3C 7E E6 B3 CB;
00C0: 56 77 28 1A CD B9 04 90 04 B3 08 4B 10 05 D2 0D 6B 08 10 16 B5 15 11 10;
00D8: 37 3C C1 08 0E 1A DD CB 3D 7E 20 1B CD 08 18 45 52 52 4F D2 CD B9 04 11;
00F0: 10 3D 3C 96 08 B3 09 95 0A 0E 1A DD 36 3D FF 2A 37 3C 01 0C 00 09 22 3B;
0108: 3C FD E1 18 8E E0 26 00 00 00 00 00 00 00 00 00 00 00 4C 3C 4C 3C 4F 3C;
0120: 51 3C 45 3C 5D 3C FF 00 0A 46 4F 52 54 C8 00 00 FF 1F 05 B5 11 49 3C 00;
0138: 00 00 F5 08 F5 C5 D5 E5 06 3E 10 FE 21 2B 3C 34 23 28 FC CD 10 03 21 28;
0150: 3C CB 46 28 21 A7 28 1E FE 20 38 14 CB 4E C4 07 08 CB 56 28 02 E6 9F CB;
0168: 5E 28 02 F6 80 CD 96 01 CD E6 01 CD 82 02 E1 D1 C1 F1 08 F1 FB C9 FE 0D;
0180: 20 14 21 00 27 22 22 3C 22 20 3C AF CD 98 01 21 E0 26 22 1E 3C C9 A7 C8;
0198: 08 2A 22 3C 7E A7 28 06 11 00 D9 19 30 28 ED 5B 24 3C 21 A0 DB 19 30 34;
01B0: 2A 1C 3C 01 20 00 09 ED 52 D5 D4 21 04 CD B0 02 D1 CD 2F 04 21 1E 3C 06;
01C8: 04 CD 43 04 10 FB CD 02 03 54 5D 23 22 22 3C 2B 2B 28 02 ED B8 08 12 13;
01E0: ED 53 20 3C AF C9 21 F0 01 16 00 5F 19 5E 19 E9 20 13 0C 1E 0A 37 1A 50;
01F8: 06 9C C9 15 14 D3 21 28 3C AE 77 C9 2A 20 3C 2B 7E A7 C8 22 20 3C 23 77;
0210: C9 2A 20 3C 23 ED 5B 22 3C A7 ED 52 C8 19 22 20 3C 7E 2B 77 C9 2A 20 3C;
0228: 23 22 20 3C CD 02 03 62 6B 1B 1A A7 C8 ED 53 20 3C 78 B1 28 02 ED B0 2B;
0240: 36 20 22 22 3C 0C C9 CD 04 02 28 08 06 1F CD 04 02 10 FB C9 2A 1E 3C ED;
0258: 5B 24 3C A7 ED 52 C8 CD 25 02 2A 1E 3C 11 E0 FF AF 19 BE 20 FC 22 1E 3C;
0270: CD F4 02 22 20 3C 3E A0 CD 7E 01 2A 20 3C 2B 22 20 3C 2A 20 3C 3A 28 3C;
0288: 1F 36 97 1F 30 02 36 C3 1F D0 36 C7 C9 CD 11 02 28 08 06 1F CD 11 02 10;
02A0: FB C9 CD B0 02 E0 E5 CD 25 02 E1 CD ED 02 18 C6 21 00 27 ED 5B 1E 3C A7;
02B8: ED 52 44 4D EB 23 AF ED B1 2B C9 2A 22 3C 2B 22 20 3C CD 2C 02 20 FB C9;
02D0: 21 28 3C CB EE CB 86 C9 21 00 27 ED 5B 24 3C CD FA 07 21 E0 26 22 24 3C;
02E8: 36 00 2A 24 3C 22 1E 3C 23 22 20 3C CD B0 02 3E 20 2B BE 28 FC 23 22 22;
0300: 3C C9 2A 22 3C ED 5B 20 3C A7 ED 52 44 4D 19 C9 CD 36 03 47 2A 26 3C AD;
0318: 28 0B AD 28 03 AF BD C0 68 26 20 18 0D 25 7C FE 1E 28 06 AF BC 20 03 26;
0330: 04 7D 22 26 3C C9 01 FE FE ED 50 5A CB 3A 9F E6 D8 CB 3A 38 02 3E 28 C6;
0348: 57 6F 7B F6 03 1E FF 2F E6 1F 57 28 0D 7D 1C 20 12 D6 08 CB 3A 30 FA 5F;
0360: 20 09 2D CB 00 30 06 ED 78 18 E4 1E FF 7B 3C C8 21 76 03 19 7E C9 76 68;
0378: 79 36 35 74 67 63 62 6A 75 37 34 72 66 78 6E 6B 69 38 33 65 64 7A 6D 6C;
0390: 6F 39 32 77 73 00 20 0D 70 30 31 71 61 00 56 48 59 07 01 54 47 43 42 4A;
03A8: 55 09 08 52 46 58 4E 4B 49 03 33 45 44 5A 4D 4C 4F 04 02 57 53 00 20 0D;
03C0: 50 05 0A 51 41 00 2F 5E 5B 26 25 3E 7D 3F 2A 2D 5D 27 24 3C 7B 60 2C 2B;
03D8: 7F 28 23 45 5C 3A 2E 3D 3B 29 40 57 7C 00 20 0D 22 5F 21 51 7E 00 28 05;
03F0: CD 7E 01 D9 C9 47 2A 29 3C 7C B5 78 28 01 E9 2A 1C 3C ED 5B 24 3C EB 37;
0408: ED 52 EB DC 21 04 FE 0D 28 04 77 23 18 06 23 7D E6 1F 20 FA 22 1C 3C D9;
0420: C9 F5 21 1C 3C CD 43 04 F1 2A 24 3C 11 20 24 A7 ED 52 44 4D 21 E0 FF 19;
0438: EB ED B0 06 20 2B 36 20 10 FB C9 7E D6 20 77 23 30 01 35 23 C9 EB 5E 16;
0450: 00 21 00 3C 19 EB D7 FD E9 48 45 52 C5 AA 00 04 62 04 ED 5B 37 3C D7 FD;
0468: E9 43 4F 4E 54 45 58 D4 5F 04 07 4D 04 33 43 55 52 52 45 4E D4 72 04 07;
0480: 4D 04 31 42 41 53 C5 7F 04 04 4D 04 3F 4D 04 3E 4D 04 39 50 41 C4 89 04;
0498: 03 F5 0F 01 27 BB 98 04 41 08 11 B6 04 D8 12 0A 0E 1A 21 3E 3C 7E E6 BB;
04B0: 77 FD E9 00 E8 FF B8 04 E1 E1 5E 23 56 23 E5 EB 5E 23 56 23 EB E9 C8 04;
04C8: 01 0B 00 ED 5B 3B 3C 2A 37 3C 09 ED 52 38 02 E7 02 01 00 00 CD 8C 0F CD;
04E0: E4 04 18 D5 3E FE DB FE 1F D8 3E 7F DB FE 1F D8 E7 03 CD B9 04 8C 05 06;
04F8: 05 36 05 76 12 F7 FF 4C 49 4E C5 A0 04 04 C3 0E C6 04 3D 06 EE 08 83 12;
0510: 07 00 4F 05 76 12 F1 FF A9 06 EE 08 83 12 07 00 64 05 76 12 E3 FF 1B 06;
0528: 1A 0C 83 12 03 00 B6 04 78 05 76 12 D3 FF 38 05 3A 3E 3C CB 77 20 0E CB;
0540: 67 20 0A CD 08 18 20 4F 4B A0 3E 0D CF FD E9 51 05 DF 1B 1A 2F DD A6 3E;
0558: E6 40 13 28 04 D7 11 4E 0F C3 BF 04 66 05 DF DD CB 3E 76 20 F4 FD E9 52;
0570: 45 54 59 50 C5 8B 05 06 7A 05 CD EA 02 CD 76 02 36 BF 18 10 51 55 45 52;
0588: D9 05 05 05 8E 05 CD D8 02 CD 76 02 21 28 3C CB C6 CB AE CB 6E 28 FC CD;
05A0: 25 02 FD E9 57 4F 52 C4 77 05 04 AD 05 DF 21 FE 27 06 FD 36 20 2B 10 FB;
05B8: D5 EB D7 D1 CD E1 05 04 05 28 03 01 FF 00 21 01 27 71 23 3E FC B9 30 01;
05D0: 4F 0C D5 C5 EB ED B0 C1 D1 0D CD DA 07 FD E9 1E 20 2A 24 3C 22 1E 3C 01;
05E8: 00 00 23 7E BB 28 FB A7 28 0E E5 03 23 7E A7 28 03 BB 20 F7 D1 AF B8 C9;
0600: D5 CD B0 02 E2 14 06 ED 5B 24 3C CD FA 07 22 24 3C D1 18 CD EB C1 01 00;
0618: 00 37 C9 1D 06 CD DF 05 50 59 D7 FD E9 56 4C 49 53 D4 AA 05 05 2F 06 3E;
0630: 0D CF 0E 00 18 0E 46 49 4E C4 2C 06 04 3F 06 CD DF 05 38 46 2A 33 3C 7E;
0648: 23 66 6F 7E E6 3F 28 2F A9 28 04 79 A7 20 28 D5 E5 CD E8 15 B1 28 17 41;
0660: 1A CD 07 08 13 AE E6 7F 23 20 12 10 F3 D1 13 D7 D1 CD DA 07 FD E9 CD FB;
0678: 17 76 CD E4 04 E1 D1 2B 7E 2B 6E 67 B5 20 C4 C3 8A 06 11 00 00 D7 FD E9;
0690: 45 58 45 43 55 54 C5 3C 06 07 9C 06 DF C3 BF 04 4E 55 4D 42 45 D2 99 06;
06A8: 06 AB 06 CD DF 05 38 DA C5 D5 CD 4C 07 20 05 11 06 10 18 58 DF 11 00 00;
06C0: D7 11 00 45 C1 C5 0A FE 2D 20 03 16 C5 03 D7 50 59 2B 2B CD 23 07 23 34;
06D8: 2B 30 F8 FE FE 20 3D CD 23 07 30 FB C6 30 CD 7B 07 20 04 1E 00 18 0E E6;
06F0: DF FE 45 20 27 E5 CD 4C 07 DF E1 20 1F CD 40 07;
0700: 28 0F 23 7E E6 7F 83 FA 1C 07 28 10 AE E6 7F AE 77 11 55 10 D7 D1 C1 CD;
0718: DA 07 FD E9 E1 E1 DF DF C3 8A 06 1A 13 D6 30 D8 FE 0A 3F D8 4F 7E E6 F0;
0730: C0 79 2B 2B 0E 03 ED 6F 23 0D 20 FA 35 2B BF C9 06 06 AF CD 2C 07 C0 10;
0748: F9 23 70 C9 D7 CD B9 04 6B 08 96 08 4B 10 2D 4A 0C 6B 08 A9 0D D2 08 D2;
0760: 0D 1F 0E 88 06 88 06 FF 08 8A 07 FF 08 DF 08 94 0D FF 08 79 08 85 08 0E;
0778: 1A DF 1A FE 20 C8 A7 C9 43 4F 4E 56 45 52 D4 A8 06 07 C3 0E 09 0E 6B 08;
0790: D2 08 96 08 B8 07 83 12 1B 00 85 08 8A 04 96 08 A8 0C 79 08 FF 08 8A 04;
07A8: 96 08 A8 0C EE 0D DF 08 76 12 D9 FF DF 08 B6 04 BA 07 DF 7B CD 07 08 C6;
07C0: D0 30 14 FE 0A 38 06 C6 EF 30 0C C6 0A DD BE 3F 30 05 16 00 5F D7 37 C3;
07D8: 21 0C 62 6B 03 09 E5 DD CB 3E 66 CC 7F 09 CD B0 02 D1 A7 ED 52 44 4D 2A;
07F0: 1E 3C 23 EB 38 05 28 02 ED B0 A7 ED 52 EB 7A B3 C8 36 20 23 1B 18 F7 E6;
0808: 7F FE 61 D8 FE 7B D0 E6 5F C9 56 49 D3 89 07 03 1A 08 DD CB 3E A6 FD E9;
0820: 49 4E 56 49 D3 17 08 05 2A 08 DD CB 3E E6 FD E9 46 41 53 D4 27 08 04 39;
0838: 08 FD 21 B9 04 FD E9 53 4C 4F D7 36 08 04 48 08 FD 21 C8 04 FD E9 2A 3B;
0850: 3C 2B 46 2B 4E 22 3B 3C C9 2B 5E 22 3B 3C C9 72 23 22 3B 3C C9 44 55 D0;
0868: 45 08 03 6D 08 DF D7 D7 FD E9 44 52 4F D0 6A 08 04 7B 08 DF FD E9 53 57;
0880: 41 D0 78 08 04 87 08 DF CD 4E 08 D7 50 59 D7 FD E9 43 C0 84 08 02 98 08;
0898: DF 1A 5F 16 00 D7 FD E9 43 A1 95 08 02 A7 08 DF CD 4E 08 79 12 FD E9 C0;
08B0: A4 08 01 B5 08 DF EB 5E 23 56 D7 FD E9 A1 B2 08 01 C3 08 DF CD 4E 08 EB;
08C8: 71 23 70 FD E9 3E D2 C0 08 02 D4 08 DF C1 D5 C5 FD E9 52 BE D1 08 02 E1;
08E0: 08 C1 D1 C5 D7 FD E9 3F 44 55 D0 DE 08 04 F0 08 DF D7 7A B3 C4 10 00 FD;
08F8: E9 52 4F D4 ED 08 03 C3 0E D2 08 85 08 DF 08 85 08 B6 04 4F 56 45 D2 FE;
0910: 08 04 C3 0E D2 08 6B 08 DF 08 85 08 B6 04 50 49 43 CB 11 09 04 27 09 CD;
0928: 4D 09 FD E9 52 4F 4C CC 24 09 04 35 09 CD 4D 09 EB 2A 37 3C ED 52 D2 D7;
0940: 04 62 6B 23 23 ED B0 ED 53 3B 3C FD E9 CD 4E 08 0B CB 21 CB 10 03 03 30;
0958: 02 E7 07 2A 3B 3C ED 42 E5 5E 23 56 D7 E1 C9 54 59 50 C5 32 09 04 70 09;
0970: CD 4E 08 DF CD 7F 09 FD E9 1A 4F 13 1A 47 13 78 B1 C8 1A 13 0B CF 18 F7;
0988: 3C A3 6D 09 02 8F 09 21 FF 27 22 1A 3C FD E9 23 BE 8C 09 02 9E 09 DF DF;
09A0: ED 5B 1A 3C D7 21 FF 27 A7 ED 52 EB D7 FD E9 AE 49 0A 01 C3 0E 8D 09 6B;
09B8: 08 0D 0C 88 06 E1 09 FF 08 4A 0A 9C 09 6E 09 73 0A B6 04 55 AE B2 09 02;
09D0: C3 0E 88 06 8D 09 E1 09 76 12 E8 FF 23 D3 CF 09 02 C3 0E F7 09 12 09 12;
09E8: 09 36 0E 1A 0C 8D 12 F3 FF B6 04 A3 E0 09 01 C3 0E 8A 04 96 08 C4 0C FF;
0A00: 08 07 0A 5C 0A B6 04 09 0A DF 7B C6 30 FE 3A 38 02 C6 07 5F D7 FD E9 43;
0A18: 4C D3 F6 09 03 1F 0A CD 24 0A FD E9 11 FF 26 2A 24 3C 01 20 00 09 2B ED;
0A30: B8 ED 43 2F 3C 21 00 24 22 1C 3C 13 EB 22 24 3C C3 FA 07 53 49 47 CE 9B;
0A48: 09 04 4C 0A DF CB 12 1E 2D 38 0C FD E9 48 4F 4C C4 1C 0A 04 5E 0A DF 2A;
0A60: 1A 3C 2D 28 04 22 1A 3C 73 FD E9 53 50 41 43 C5 5B 0A 05 75 0A 3E 20 CF;
0A78: FD E9 53 50 41 43 45 D3 72 0A 06 85 0A DF 1B CB 7A 20 ED 3E 20 CF 18 F6;
0A90: 43 D2 82 0A 02 97 0A 3E 0D CF FD E9 45 4D 49 D4 94 0A 04 A5 0A DF 7B CF;
0AA8: FD E9 46 AE A2 0A 02 B1 0A 2A 3B 3C 2B CB 7E CB BE 28 03 3E 2D CF 1E 00;
0AC0: 7E 3D FE 49 30 04 FE 3C 30 04 36 41 3C 5F 3E 40 96 38 09 47 04 3E 2E CF;
0AD8: 3E 30 10 FB 3E 40 BE 9F 2B B6 2B B6 2B B6 23 23 28 12 AF CD 32 07 C6 30;
0AF0: CF 23 7E FE 40 20 E5 3E 2E CF 18 E0 7B A7 20 05 3E 20 CF 18 0B D6 41 6F;
0B08: 9F 67 3E 45 CF CD 0E 18 DF DF FD E9 41 D4 AE 0A 02 1B 0B DF CD 4E 08 79;
0B20: CD 28 0B 22 1C 3C FD E9 C6 20 6F 26 01 29 29 29 29 29 16 00 7B E6 1F 5F;
0B38: 19 ED 5B 24 3C ED 52 19 D8 E7 09 50 4C 4F D4 18 0B 04 4C 0B CD 4E 08 DF;
0B50: DD 73 30 CB 3B CB 11 3E 16 93 DF DD 73 2F CB 3B CB 11 CD 28 0B 7E E6 78;
0B68: FE 10 7E 28 02 3E 10 5F 16 87 79 E6 03 47 28 07 2F C6 02 CE 03 57 43 79;
0B80: 0F 0F 0F 9F CB 59 20 04 AB 07 9F A8 A2 AB 77 FD E9 42 45 45 D0 49 0B 04;
0B98: C3 0E 12 09 4B 10 7D 85 08 7A 0D 0E 1A DF CD 4E 08 21 F9 00 09 2C F3 3E;
0BB0: 7F DB FE 0F 30 11 CD C9 0B 1B 7A D3 FE CD C9 0B B3 C2 AF 0B FB FD E9 E7;
0BC8: 03 45 4C 10 FE 05 0D C2 CB 0B C9 49 4E 4B 45 D9 97 0B 05 DD 0B CD 36 03;
0BE0: 5F 16 00 D7 FD E9 49 CE DA 0B 02 ED 0B CD 4E 08 16 00 ED 58 D7 FD E9 4F;
0BF8: 55 D4 EA 0B 03 FF 0B CD 4E 08 DF ED 59 FD E9 41 42 D3 FC 0B 03 C3 0E 6B;
0C10: 08 94 0D B6 04 30 BD 0C 0C 02 1C 0C DF 7A B3 FE 01 3E 00 57 17 5F D7 FD;
0C28: E9 30 BC 19 0C 02 30 0C DF CB 12 18 EC 30 BE 2D 0C 02 3C 0C DF 7A B3 28;
0C40: E0 CB 12 3F 18 DB BD 39 0C 01 C3 0E E1 0D 1A 0C B6 04 BE 49 0C 01 58 0C;
0C58: DF D5 DF E1 CD 99 0C 18 C0 BC 55 0C 01 C3 0E 85 08 56 0C B6 04 55 BC 64;
0C70: 0C 02 74 0C CD 4E 08 DF EB A7 ED 42 18 A3 44 BC 71 0C 02 85 0C DF D5 CD;
0C88: 4E 08 DF E1 A7 ED 52 28 E6 19 EB CD 99 0C DF 18 88 7C AA FA A0 0C ED 52;
0CA0: CB 14 C9 55 AA 82 0C 02 AA 0C DF CD 4E 08 21 00 00 3E 10 29 EB ED 6A EB;
0CB8: 30 04 09 30 01 13 3D 20 F2 EB 18 2F C6 0C DF D9 DF D5 DF E1 7C B5 3E 21;
0CD0: 20 03 EB 3E 11 D9 47 AF 67 6F 4F ED 6A 9F A7 ED 52 99 30 01 19 3F D9 EB;
0CE8: ED 6A EB ED 6A D9 10 EB EB D7 D9 E5 D7 D1 D7 FD E9 2F 4D 4F C4 A7 0C 04;
0D00: C3 0E 85 08 D2 08 E9 12 0D 0C 4B 10 00 FF 08 6B 08 E9 12 60 0E D2 08 0D;
0D18: 0C 8C 0D DF 08 94 0D 85 08 DF 08 94 0D 85 08 B6 04 2A 2F 4D 4F C4 FF 0C;
0D30: 05 C3 0E FF 08 D2 08 E9 12 0D 0C FF 08 6B 08 DF 08 60 0E D2 08 0D 0C A8;
0D48: 0C 76 12 C1 FF AF 30 0D 01 C3 0E 00 0D 85 08 79 08 B6 04 4D 4F C4 50 0D;
0D60: 03 C3 0E 00 0D 79 08 B6 04 AA 60 0D 01 C3 0E A8 0C 79 08 B6 04 2A AF 6C;
0D78: 0D 02 C3 0E 31 0D 85 08 79 08 B6 04 55 2F 4D 4F C4 79 0D 05 C3 0E C4 0C;
0D90: 79 08 B6 04 C3 0E 2E 0C 83 12 03 00 A9 0D B6 04 4E 45 47 41 54 C5 8B 0D;
0DA8: 06 AB 0D 01 02 00 18 0F 44 4E 45 47 41 54 C5 A8 0D 07 BC 0D 01 04 00 2A;
0DC0: 3B 3C A7 ED 42 78 9E 77 23 0D 20 F9 FD E9 AB B9 0D 01 D4 0D DF D5 DF E1;
0DD8: 19 EB D7 FD E9 AD D1 0D 01 C3 0E A9 0D D2 0D B6 04 44 AB E0 0D 02 F0 0D;
0DF0: DF D5 CD 4E 08 DF D5 DF EB 09 EB D7 C1 E1 ED 4A;
0E00: EB D7 FD E9 31 AB ED 0D 02 0B 0E DF 18 09 32 AB 08 0E 02 15 0E DF 13 13;
0E18: 18 14 31 AD 12 0E 02 21 0E DF 18 09 32 AD 1E 0E 02 2B 0E DF 1B 1B D7 FD;
0E30: E9 4F D2 28 0E 02 38 0E DF CD 4E 08 7B B1 5F 7A B0 57 D7 FD E9 41 4E C4;
0E48: 35 0E 03 4D 0E DF CD 4E 08 7B A1 5F 7A A0 57 D7 FD E9 58 4F D2 4A 0E 03;
0E60: 62 0E DF CD 4E 08 7B A9 5F 7A A8 57 D7 FD E9 4D 41 D8 5F 0E 03 C3 0E 12;
0E78: 09 12 09 65 0C 71 12 0F 00 4D 49 CE 74 0E 03 C3 0E 12 09 12 09 56 0C 83;
0E90: 12 03 00 85 08 79 08 B6 04 44 45 43 49 4D 41 CC 86 0E 07 A5 0E DD 36 3F;
0EA8: 0A FD E9 BA A2 0E 01 85 10 C3 0E 4B 10 0A 0E 1A 21 3E 3C 7E F6 44 77 FD;
0EC0: E9 E9 FF EB C3 BA 04 43 52 45 41 54 C5 AE 0E 06 C3 0E 4B 10 20 AB 05 FB;
0ED8: 0E 88 06 4E 0F 80 04 B3 08 6B 08 B3 08 4E 0F 60 04 85 08 C1 08 99 04 96;
0EF0: 08 5F 0F 11 10 EC 0F 4E 0F B6 04 FD 0E CD 2E 0F DF 1A 3D FE 3F 38 02 E7;
0F08: 06 C6 08 4F 06 00 CD 8C 0F 1A 4F 2A 37 3C D5 CD 9E 0F D1 1A 47 13 1A CD;
0F20: 07 08 77 23 10 F7 22 39 3C 2B CB FE FD E9 DD CB 3E 56 28 02 E7 0C 2A 37;
0F38: 3C ED 5B 39 3C AF ED 52 EB 73 23 72 67 6F 22 39 3C C9 AC CF 0E 01 C3 0E;
0F50: 83 0F 60 04 29 0E C1 08 B6 04 43 AC 4D 0F 02 C3 0E 4B 10 01 76 0F 60 04;
0F68: 1F 0E A5 08 B6 04 41 4C 4C 4F D4 5E 0F 05 78 0F CD 4E 08 2A 37 3C CD 9E;
0F80: 0F FD E9 C3 0E 4B 10 02 76 0F B6 04 21 1E 00 C5 09 ED 4B 3B 3C 09 C1 38;
0F98: 03 ED 72 D8 E7 01 EB 21 28 00 CD 8F 0F 2A 37 3C 09 22 37 3C 2A 3B 3C E5;
0FB0: 09 22 3B 3C E3 E5 A7 ED 52 44 4D E1 D1 C8 2B 1B ED B8 23 C9 56 41 52 49;
0FC8: 41 42 4C C5 75 0F 08 85 10 F0 0F 4E 0F B6 04 43 4F 4E 53 54 41 4E D4 CE;
0FE0: 0F 08 85 10 F5 0F 4E 0F B6 04 DC FE 18 02 D5 FF D7 FD E9 E3 FF EB 5E 23;
0FF8: 56 D7 FD E9 4C 49 54 45 52 41 CC E1 0F 47 08 11 11 10 4E 0F B6 04 02 FF;
1010: FF 13 10 06 01 E1 5E 23 56 23 E5 D7 10 F7 FD E9 41 53 43 49 C9 05 10 45;
1028: C3 0E 4B 10 20 AB 05 09 0E 96 08 0E 1A DD CB 3E 76 28 E3 CD B9 04 11 10;
1040: 4B 10 4E 0F 5F 0F B6 04 01 D6 FF 4D 10 E1 5E 16 00 06 01 18 C4 08 11 64;
1058: 10 85 08 4E 0F 4E 0F B6 04 04 FF FF 66 10 06 02 18 AB 44 45 46 49 4E 45;
1070: D2 27 10 07 85 10 85 10 60 04 4B 10 0C 83 0F 76 12 34 FE E6 FF CD F0 0F;
1088: D0 0E 6B 08 B3 08 60 04 29 0E C1 08 13 0E 9A 10 B6 04 9C 10 DF C3 C3 0E;
10A0: 43 41 4C CC 73 10 04 A9 10 DF EB E9 44 4F 45 53 BE F4 10 45 08 11 E8 10;
10B8: D8 12 0C CD 10 4B 10 CD 5F 0F 11 10 F0 0F 4E 0F 4B 10 0A B6 04 C3 0E 6B;
10D0: 08 29 0E B5 15 60 04 E1 0D 1F 0E 4E 0F 60 04 85 08 C1 08 B6 04 05 C5 FF;
10E8: B8 04 43 4F 4D 50 49 4C 45 D2 A6 10 08 85 10 08 11 60 11 60 04 4B 10 0B;
1100: 83 0F 76 12 B1 FD E3 FF DD CB 3E 76 20 02 E7 04 CD F0 0F 6B 08 B3 08 4E;
1118: 0F 76 12 78 FF 52 55 4E 53 BE B3 10 45 08 11 40 11 D8 12 0B 85 08 5F 0F;
1130: CD 10 11 10 42 11 4E 0F 4B 10 0A B6 04 05 DE FF B8 04 E1 D5 EB D7 42 4B;
1148: D1 D5 1B 1B CD 9E 15 D1 C5 C3 C3 0E 49 4D 4D 45 44 49 41 54 C5 24 11 09;
1160: C3 0E 80 04 B3 08 B3 08 0E 1A DF EB CB F6 FD E9 56 4F 43 41 42 55 4C 41;
1178: 52 D9 5F 11 0A 85 10 B5 11 80 04 B3 08 13 0E 4E 0F 88 06 5F 0F 60 04 11;
1190: 10 35 3C 6B 08 B3 08 4E 0F C1 08 B6 04 44 45 46 49 4E 49 54 49 4F 4E D3;
11A8: 7C 11 0B AD 11 2A 33 3C 22 31 3C FD E9 ED 53 33 3C FD E9 49 C6 E0 13 42;
11C0: 08 11 83 12 60 04 4B 10 02 83 0F B6 04 57 48 49 4C C5 BF 11 45 08 11 88;
11D8: 12 D8 12 01 60 04 4B 10 04 83 0F B6 04 45 4C 53 C5 D4 11 44 08 11 71 12;
11F0: D8 12 02 83 0F 25 12 60 04 29 0E 4B 10 02 B6 04 54 48 45 CE EB 11 44 08;
1208: 11 A4 12 D8 12 02 25 12 B6 04 42 45 47 49 CE 06 12 45 08 11 9F 12 60 04;
1220: 4B 10 01 B6 04 C3 0E 6B 08 60 04 85 08 E1 0D 1F 0E 85 08 C1 08 B6 04 C3;
1238: 0E 60 04 E1 0D 1F 0E 4E 0F B6 04 52 45 50 45 41 D4 19 12 46 08 11 76 12;
1250: D8 12 04 85 08 37 12 25 12 B6 04 55 4E 54 49 CC 4B 12 45 08 11 8D 12 D8;
1268: 12 01 37 12 B6 04 02 75 FF 78 12 02 CE FF 78 12 E1 5E 23 56 19 C3 BA 04;
1280: 02 39 FF 8F 12 02 46 FF 8F 12 02 CF FF 8F 12 CD 4E 08 78 B1 28 E2 E1 23;
1298: 23 C3 BA 04 00 74 FF B9 04 00 5D FF B9 04 44 CF 62 12 42 08 11 23 13 60;
12B0: 04 4B 10 03 B6 04 4C 4F 4F D0 AA 12 44 08 11 32 13 D8 12 03 37 12 B6 04;
12C8: 2B 4C 4F 4F D0 BC 12 45 08 11 3C 13 76 12 EA FF DA 12 DF E1 7E 23 E5 93;
12E0: B2 28 4A E7 05 C9 AA 11 01 EB 12 C1 D1 D5 C5 D7 FD E9 49 A7 E8 12 02 F9;
12F8: 12 21 04 00 18 09 CA F6 12 01 04 13 21 06 00 39 5E 23 56 D7 FD E9 4C 45;
1310: 41 56 C5 01 13 05 18 13 C1 E1 E1 E5 E5 C5 FD E9 00 84 FF 25 13 CD 4E 08;
1328: DF E1 D5 C5 E5 FD E9 02 85 FF 34 13 11 01 00 18 06 02 8D FF 3E 13 DF C1;
1340: E1 A7 ED 5A 7A D1 37 EA 58 13 D5 E5 07 30 01 EB CD 99 0C 3F 30 02 E1 E1;
1358: C5 9F C3 94 12 A8 D4 13 41 08 11 79 13 4B 10 29 60 04 85 08 83 0F 9F 13;
1370: 85 08 C1 08 B6 04 FF E5 FF 7B 13 E1 5E 23 56 13 C3 7C 12 2E A2 60 13 42;
1388: 08 11 96 13 4B 10 22 76 12 D6 FF FF EE FF 98 13 D1 CD 79 09 D5 FD E9 A1;
13A0: 13 DF D5 CD E1 05 62 6B 09 7E E1 BD 28 0A EB D7 11 78 05 CD 15 18 18 E9;
13B8: D5 C5 2A 37 3C CD 9E 0F C1 D1 D5 C5 EB ED B0 C1 50 59 D7 D1 CD DA 07 FD;
13D0: E9 DB CF 12 41 D7 13 DD CB 3E B6 FD E9 DD 15 13 01 E3 13 DD CB 3E F6 FD;
13E8: E9 45 58 49 D4 87 13 04 B8 04 52 45 44 45 46 49 4E C5 EF 13 08 FF 13 CD;
1400: 2E 0F 2A 31 3C 5E 23 56 EB 23 22 05 27 E5 CD C0 15 22 0D 27 ED 43 07 27;
1418: ED 53 0B 27 2A 37 3C ED 52 C2 DA 14 D1 D7 CD B9 04 10 16 3D 06 0E 1A DF;
1430: 21 AF C3 19 D2 CF 14 EB 22 03 27 CD C0 15 22 01 27 E5 ED 53 09 27 78 B1;
1448: ED 5B 07 27 28 04 7A B3 28 7D E1 ED 4B 0D 27 ED 42 EB 19 22 07 27 2A 0B;
1460: 27 19 ED 4B 09 27 A7 ED 42 22 0B 27 01 2E 00 09 CB 7C 20 0B ED 4B 3B 3C;
1478: 09 38 54 ED 72 30 50 2A 03 27 E5 2B 2B 46 2B 4E 2A 05 27 E5 2B 2B 70 2B;
1490: 71 E1 19 C1 A7 ED 42 22 05 27 ED 5B 01 27 2A 09 27 A7 ED 52 44 4D D5 C5;
14A8: CD DC 14 2A 0B 27 C1 09 44 4D E1 C5 CD 9E 0F EB 2A 0D 27 ED 4B 0B 27 09;
14C0: C1 C5 E5 ED B0 D1 C1 CD DC 14 CD F8 14 FD E9 2A 31 3C ED 5B 05 27 1B 73;
14D8: 23 72 E7 0B 2A 37 3C A7 ED 42 22 37 3C 2A 3B 3C ED 42 22 3B 3C ED 52 C8;
14F0: C5 44 4D E1 19 ED B0 C9 01 31 3C CD 57 15 CD 57;
1500: 15 01 40 3C 2A 37 3C 37 ED 42 D8 0A 17 03 30 FB 03 03 CD 57 15 03 CD 57;
1518: 15 CD FB 15 C3 0E 1C 85 10 16 08 11 13 B5 11 18 00 00 21 F9 FF 09 4E 23;
1530: 46 2B 09 44 4D 18 CD CD 57 15 CD 48 15 18 C5 CD 57 15 03 CD 57 15 18 BC;
1548: CD 57 15 21 B6 04 A7 ED 52 C8 CD 9E 15 18 F1 0A 5F 03 0A 57 0B CD 68 15;
1560: EB 7B 02 03 7A 02 03 C9 2A 01 27 A7 ED 52 62 6B D0 2A 09 27 ED 52 30 0C;
1578: 2A 0D 27 ED 52 38 13 2A 0B 27 19 C9 2A 03 27 ED 52 2A 07 27 D8 2A 05 27;
1590: 19 C9 2A 01 27 19 ED 5B 0D 27 A7 ED 52 C9 1B 1A 17 D0 1B 1B 1A 6F 26 00;
15A8: 3C 20 06 0A 6F 03 0A 67 03 09 44 4D C9 B7 15 DF EB CD E7 15 EB D7 FD E9;
15C0: E5 5E 23 56 CD FB 15 08 11 0B 85 10 08 00 00 01 00 00 18 07 E1 E5 23 23;
15D8: 4E 23 46 E1 E5 2B 2B 2B 2B 56 2B 5E 19 EB E1 2B 7C FE 3C 7E CB B7 38 02;
15F0: C6 02 2B 2B 2B 3D 20 FC C9 23 E5 E1 7E 23 E5 66 6F B4 C8 ED 52 E1 23 20;
1608: F0 D5 16 00 5E 19 D1 E9 C3 0E 1F 0E 29 0E B3 08 80 04 B3 08 C1 08 B6 04;
1620: CD B9 04 3D 06 0E 1A DF 21 AF C3 19 D8 E7 0D 46 4F 52 47 45 D4 FC 13 06;
1638: 3A 16 2A 31 3C ED 5B 33 3C A7 ED 52 C2 DA 14 CD 20 16 21 FB FF 19 22 39;
1650: 3C DD CB 3E D6 E7 FF 45 44 49 D4 37 16 04 60 16 CD 20 16 DD CB 3E DE 18;
1668: 0C 4C 49 53 D4 5D 16 04 72 16 CD 20 16 3E 0D CF DD CB 3E 5E D5 C4 D8 02;
1680: C1 0A 5F 03 0A 57 0B CD FB 15 C3 0E 0B 08 11 0D 85 10 1F 00 00 E7 0E 21;
1698: 02 00 18 18 D5 21 02 00 09 7E 23 66 6F 2B 2B 2B 6E 7D 07 9F 67 CD 0E 18;
16B0: D1 21 04 00 09 E5 C5 CD E4 17 D1 C1 CD E4 17 DD 36 14 01 DD 36 16 10 CD;
16C8: 08 17 38 06 DD 35 16 F2 C7 16 DD CB 3E 5E 20 10 38 28 21 26 3C 36 00 7E;
16E0: A7 28 FC CD E4 04 18 DB F5 DD CB 3E 9E C5 CD B9 04 78 05 06 05 0E 1A DD;
16F8: CB 3E DE CD D8 02 C1 F1 30 C1 DD CB 3E 9E FD E9 3A 14 3C 32 15 3C DD 36;
1710: 13 05 0A 5F 03 0A 57 03 CD FB 15 83 12 40 71 12 44 A4 12 48 9F 12 37 8D;
1728: 12 42 88 12 38 76 12 3C 23 13 2B 32 13 36 3C 13 33 E8 10 29 40 11 26 11;
1740: 10 3B 64 10 47 4B 10 51 79 13 62 96 13 63 B6 04 54 00 00 CD E1 17 DD 35;
1758: 13 20 B7 A7 C9 2A 14 3C 65 2C 18 0C 2A 14 3C 65 25 18 05 2A 14 3C 2D 65;
1770: 22 14 3C DD 36 13 01 DD 35 16 18 D7 CD DA 17 D7 11 B3 09 CD C1 17 CD 15;
1788: 18 18 CB CD DA 17 D7 CD DA 17 D7 11 AF 0A 18 EB 0A F5 CD E1 17 F1 CF 3E;
17A0: 20 CF 18 B2 CD 08 18 0D 3B 8D 37 C9 3E 29 18 02 3E 22 F5 C5 CD E1 17 D1;
17B8: CD 79 09 42 4B F1 CF A7 C9 3A 15 3C A7 F8 C5 47 3E 0D CF 04 05 28 05 3E;
17D0: 20 CF 10 FB DD 36 15 FF C1 C9 0A 5F 03 0A 57 03 C9 CD C1 17 EB 2B 7E CB;
17E8: 7F 20 05 CD E8 15 18 0B EB CD A2 15 13 1A 6F 13 1A 67 19 7E E6 7F CF CB;
1800: 7E 23 28 F7 3E 20 CF C9 E3 CD FB 17 E3 C9 11 B3 09 D5 EB D7 D1 C5 CD BF;
1818: 04 1B 18 1D 18 C1 C1 C9 FD E5 E5 FD E1 21 92 18 E5 21 00 E0 CB 79 28 02;
1830: 26 FC 13 FD 2B F3 AF 06 97 10 FE D3 FE EE 08 2C 20 01 24 20 F2 06 2B 10;
1848: FE D3 FE 69 01 08 3B 10 FE 79 D3 FE 06 38 C3 8A 18 79 CB 78 10 FE 30 04;
1860: 06 3D 10 FE D3 FE 06 3A C2 59 18 05 AF CB 15 C2 5C 18 1B FD 23 06 2E 3E;
1878: 7F DB FE 1F D0 7A FE FF D0 B3 28 0B FD 6E 00 7C AD 67 AF 37 C3 6D 18 6C;
1890: 18 F5 FD E1 08 06 3B 10 FE AF D3 FE 3E 7F DB FE 1F FB D2 F0 04 08 C9 F3;
18A8: FD E5 E5 FD E1 21 92 18 E5 61 08 AF 4F C0 2E 00 06 B8 CD 11 19 30 F6 3E;
18C0: DF B8 30 F2 2C 20 F1 06 CF CD 15 19 30 E7 78 FE D8 30 F4 CD 15 19 D0 CD;
18D8: FC 18 D0 3F C0 18 11 08 30 05 FD 75 00 18 05 FD 7E 00 AD C0 FD 23 1B 08;
18F0: CD FC 18 D0 7A B3 20 E7 7C FE 01 C9 2E 01 06 C7 CD 11 19 D0 3E E2 B8 CB;
1908: 15 D2 FE 18 7C AD 67 37 C9 CD 15 19 D0 3E 14 3D 20 FD A7 04 C8 3E 7F DB;
1920: FE 1F D0 A9 E6 10 28 F3 79 2F 4F 37 C9 53 41 56 C5 6F 16 04 C3 0E 10 1A;
1938: 4F 1A B6 04 42 53 41 56 C5 33 19 05 C3 0E 3D 1A 4F 1A B6 04 42 4C 4F 41;
1950: C4 43 19 05 C3 0E 3D 1A 74 1A B8 1A B6 04 56 45 52 49 46 D9 53 19 06 C3;
1968: 0E 10 1A 71 12 0F 00 42 56 45 52 49 46 D9 66 19 07 C3 0E 3D 1A 74 1A BE;
1980: 1A B6 04 4C 4F 41 C4 78 19 04 C3 0E 10 1A 0E 1A 2A 37 3C 22 0E 23 EB 21;
1998: CC FF 39 A7 ED 52 22 0C 23 CD B9 04 74 1A B8 1A 0E 1A ED 4B 37 3C 21 50;
19B0: 3C 22 01 27 23 22 09 27 2A 25 23 09 22 37 3C 21 AF C3 09 22 0B 27 ED 5B;
19C8: 29 23 19 ED 5B 4C 3C 22 4C 3C C5 D5 ED 73 0D 27 CD 04 15 C1 E1 CB 7E 23;
19E0: 28 FB 23 23 71 23 70 2A 37 3C 01 0C 00 09 22 3B 3C FD E9 C3 0E 4B 10 20;
19F8: AB 05 0E 1A CD 2E 0F DF 3E 20 12 11 0C 27 21 FF 27 CD FA 07 FD E9 FB 18;
1A10: C3 0E F3 19 0E 1A AF 32 01 23 21 51 3C 22 0E 23 EB 2A 37 3C A7 ED 52 22;
1A28: 0C 23 2A 4C 3C 22 10 23 21 31 3C 11 12 23 01 08 00 ED B0 FD E9 C3 0E F3;
1A40: 19 11 10 0C 23 C1 08 11 10 0E 23 C1 08 B6 04 51 1A 3A 02 23 A7 28 5F 2A;
1A58: 0C 23 7C B5 28 58 E5 11 19 00 21 01 23 4A CD 20 18 D1 2A 0E 23 0E FF CD;
1A70: 20 18 FD E9 76 1A 11 19 00 21 1A 23 4A 37 CD A7 18 30 F3 11 1A 23 1A A7;
1A88: 20 0B CD 08 18 0D 44 69 63 74 BA 18 0A CD 08 18 0D 42 79 74 65 73 BA 21;
1AA0: 01 23 01 0B 0B 18 02 1A CF 1A BE 20 01 0D 23 13 10 F5 20 C2 FD E9 E7 0A;
1AB8: BA 1A 06 FF 18 12 C0 1A 21 12 23 11 2B 23 06 08 1A 13 BE 23 20 E8 10 F8;
1AD0: 2A 0C 23 ED 5B 25 23 7C B5 28 04 ED 52 38 D7 2A 0E 23 7C B5 20 03 2A 27;
1AE8: 23 0E FF CB 18 CD A7 18 30 C4 FD E9 01 0F 3C AF 02 0D 20 FC 2A 3B 3C 11;
1B00: FC FF 2B 4E 77 19 23 22 3B 3C 2B 46 77 79 0F A8 E6 7F A8 32 02 3C CB B8;
1B18: CB B9 ED 43 00 3C 23 EB 19 C9 3E 09 B8 30 01 47 0E 04 23 23 23 AF ED 67;
1B30: 2B 0D 20 FA 23 10 F1 C6 FB E5 7E 88 27 77 23 38 F9 E1 C9 C5 E5 06 04 A7;
1B48: 3E 00 9E 27 77 23 10 F8 E1 C1 C9 0E 01 E5 D5 C5 79 E6 0F 47 A9 4F 0F 0F;
1B60: 81 0F 80 4F 06 04 AF C5 D5 E5 86 27 6F 1A 26 00 54 CB 14 A7 28 1B 5F CB;
1B78: 39 30 08 7D 83 27 6F 7C 8A 27 67 0C 0D 28 0A 7B 87 27 5F 7A 8F 27 57 18;
1B90: E6 EB E1 73 7A D1 C1 13 23 10 CC C1 D1 E1 C9 46 AD 89 19 02 C3 0E 0F 1D;
1BA8: 0E 1A 18 07 46 AB A3 1B 02 B3 1B CD F4 1A 79 90 F5 30 06 EB ED 44 DD 70;
1BC0: 00 47 C4 22 1B F1 30 01 EB 06 02 DD 4E 02 CB 11 DC 43 1B EB 10 F8 CD 53;
1BD8: 1B 1B 1A C6 68 CB 18 DD 70 02 C4 43 1B 1A A7 20 19 DD 35 00 DD 35 00 D5;
1BF0: 62 6B 2B 01 FF 03 B6 ED A8 10 FB EB 70 D1 20 E5;
1C00: FD E9 54 5D D5 01 04 00 ED B0 E1 1B 1A A7 28 11 FE 10 9F 3C 3C 47 DD 86;
1C18: 00 32 00 3C CD 22 1B 18 EB 3A 00 3C 3D FE BF 3C 30 13 FE 80 30 0D 47 3A;
1C30: 02 3C 4F 17 A9 E6 80 A8 12 FD E9 E7 08 01 00 04 71 23 10 FC FD E9 46 AA;
1C48: B0 1B 02 4D 1C CD F4 1A AF B8 9F A1 28 E7 E5 01 02 3C C5 06 03 4E 23 E3;
1C60: 23 CD 55 1B E3 10 F6 ED 4B 00 3C 78 81 D6 42 32 00 3C E1 D1 18 8E 46 AF;
1C78: 4A 1C 02 7D 1C CD F4 1A AF B8 28 B9 B9 28 B4 13 13 1A 1B 1B C6 01 27 08;
1C90: EB CD 43 1B EB E5 11 10 3C 01 04 00 ED B0 EB 2B 06 05 D5 7E 2B 5E 08 4F;
1CA8: 08 0C 0D 20 03 5F 18 1B C5 06 02 16 10 CB 23 17 CB 12 30 F9 14 91 27 1C;
1CC0: 30 FB 15 20 F8 81 27 1D 10 E9 C1 4B D1 0C 0D 28 17 E5 2B 2B CD 55 1B D5;
1CD8: 11 FB FF 19 11 03 3C 79 12 CD 53 1B D1 E1 23 04 10 B8 2A 00 3C 7C 95 C6;
1CF0: 40 21 08 3C 47 3A 0B 3C A7 20 03 05 05 2B DD 70 00 D1 C3 04 1C 46 4E 45;
1D08: 47 41 54 C5 7A 1C 07 11 1D DF 7A A7 28 02 EE 80 57 D7 FD E9 49 4E D4 0E;
1D20: 1D 03 24 1D 2A 3B 3C 2B 11 00 00 7E 07 FE 82 38 14 AF 2B CD 32 07 23 EB;
1D38: 44 4D 29 29 09 29 4F 06 00 09 EB 18 E6 2B 2B 72 2B 73 11 94 0D C3 BF 04;
1D50: 55 46 4C 4F 41 D4 21 1D 06 5B 1D DF EB 01 00 10 51 59 29 7B 8F 27 5F 7A;
1D68: 8F 27 57 CB 11 10 F3 D7 16 46 59 D7 2B 2B CD 40 07 FD E9 00 00 00 00 00;
1D80: 00 00 10 10 10 10 00 10 00 24 24 00 00 00 00 00 24 7E 24 24 7E 24 00 08;
1D98: 3E 28 3E 0A 3E 08 62 64 08 10 26 46 00 10 28 10 2A 44 3A 00 08 10 00 00;
1DB0: 00 00 00 04 08 08 08 08 04 00 20 10 10 10 10 20 00 00 14 08 3E 08 14 00;
1DC8: 00 08 08 3E 08 08 00 00 00 00 00 08 08 10 00 00 00 3E 00 00 00 00 00 00;
1DE0: 00 18 18 00 00 02 04 08 10 20 00 3C 46 4A 52 62 3C 00 18 28 08 08 08 3E;
1DF8: 00 3C 42 02 3C 40 7E 00 3C 42 0C 02 42 3C 00 08 18 28 48 7E 08 00 7E 40;
1E10: 7C 02 42 3C 00 3C 40 7C 42 42 3C 00 7E 02 04 08 10 10 00 3C 42 3C 42 42;
1E28: 3C 00 3C 42 42 3E 02 3C 00 00 00 10 00 00 10 00 00 10 00 00 10 10 20 00;
1E40: 04 08 10 08 04 00 00 00 3E 00 3E 00 00 00 10 08 04 08 10 00 3C 42 04 08;
1E58: 00 08 3C 4A 56 5E 40 3C 3C 42 42 7E 42 42 7C 42 7C 42 42 7C 3C 42 40 40;
1E70: 42 3C 78 44 42 42 44 78 7E 40 7C 40 40 7E 7E 40 7C 40 40 40 3C 42 40 4E;
1E88: 42 3C 42 42 7E 42 42 42 3E 08 08 08 08 3E 02 02 02 42 42 3C 44 48 70 48;
1EA0: 44 42 40 40 40 40 40 7E 42 66 5A 42 42 42 42 62 52 4A 46 42 3C 42 42 42;
1EB8: 42 3C 7C 42 42 7C 40 40 3C 42 42 52 4A 3C 7C 42 42 7C 44 42 3C 40 3C 02;
1ED0: 42 3C FE 10 10 10 10 10 42 42 42 42 42 3E 42 42 42 42 24 18 42 42 42 42;
1EE8: 5A 24 42 24 18 18 24 42 82 44 28 10 10 10 7E 04 08 10 20 7E 0E 08 08 08;
1F00: 08 0E 00 40 20 10 08 04 70 10 10 10 10 70 10 38 54 10 10 10 00 00 00 00;
1F18: 00 00 FF 1C 22 78 20 20 7E 00 00 38 04 3C 44 3E 00 20 20 3C 22 22 3C 00;
1F30: 00 1C 20 20 20 1C 00 04 04 3C 44 44 3E 00 00 38 44 78 40 3C 00 0C 10 18;
1F48: 10 10 10 00 00 3C 44 44 3C 04 38 40 40 78 44 44 44 00 10 00 30 10 10 38;
1F60: 00 04 00 04 04 04 24 18 20 28 30 30 28 24 00 10 10 10 10 10 0C 00 00 68;
1F78: 54 54 54 54 00 00 78 44 44 44 44 00 00 38 44 44 44 38 00 00 78 44 44 78;
1F90: 40 40 00 3C 44 44 3C 04 06 00 1C 20 20 20 20 00 00 38 40 38 04 78 00 10;
1FA8: 38 10 10 10 0C 00 00 44 44 44 44 3C 00 00 44 44 28 28 10 00 00 44 54 54;
1FC0: 54 28 00 00 44 28 10 28 44 00 00 44 44 44 3C 04 38 00 7C 08 10 20 7C 00;
1FD8: 0E 08 30 30 08 0E 00 08 08 08 08 08 08 00 70 10 0C 0C 10 70 00 32 4C 00;
1FF0: 00 00 00 00 3C 42 99 A1 A1 99 42 3C FF 58 1D 00;
END;

235
Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace_mist.sv
View File

@@ -19,68 +19,44 @@ module ace_mist(
input SPI_SS2,
input SPI_SS3,
input SPI_SS4,
input CONF_DATA0,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
input CONF_DATA0
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"Jupiter ACE;;",
"F,ACE;",
"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
"O67,CPU Speed,Normal,x2,x4;",
"T5,Reset;",
"V,v0.2.",`BUILD_DATE
"V,v0.5.",`BUILD_DATE
};
wire clk_sys;
wire clk_65;
wire clk_cpu;
wire clk_sdram;
wire locked;
wire scandoubler_disable;
wire ypbpr;
wire ps2_kbd_clk, ps2_kbd_data;
wire [10:0] ps2_key;
assign LED = ~ioctl_download;
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire audio;
wire TapeIn;
wire TapeOut;
wire HSync, VSync;
wire HSync, VSync, HBlank, VBlank;
wire blankn = ~(HBlank | VBlank);
wire video;
wire [7:0] kbd_rows;
wire [4:0] kbd_columns;
wire ioctl_download;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
reg ioctl_wait = 0;
pll pll(
.areset(),
.inclk0(CLOCK_27),
.c0(clk_sys),//26.0Mhz
.c1(clk_65),//6.5Mhz
.c2(clk_cpu),//3.25Mhz
.c3(SDRAM_CLK),//100Mhz
.locked(locked)
.c0(clk_sys)
);
reg [7:0] reset_cnt;
always @(posedge clk_sys) begin
if(!locked || buttons[1] || status[0] || status[5])
reset_cnt <= 8'h0;
else if(reset_cnt != 8'd255)
reset_cnt <= reset_cnt + 8'd1;
end
wire reset = (reset_cnt != 8'd255);
mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
(
@@ -96,15 +72,19 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
.scandoubler_disable(scandoubler_disable),
.ypbpr(ypbpr),
.status(status),
.ps2_kbd_clk(ps2_kbd_clk),
.ps2_kbd_data(ps2_kbd_data)
.ps2_key(ps2_key),
.ioctl_download(ioctl_download),
.ioctl_wr(ioctl_wr),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_dout),
.ioctl_wait(ioctl_wait)
);
video_mixer #(.LINE_LENGTH(800), .HALF_DEPTH(1)) video_mixer
video_mixer #(.LINE_LENGTH(280), .HALF_DEPTH(1)) video_mixer
(
.clk_sys(clk_sys),
.ce_pix(clk_65),
.ce_pix_actual(clk_65),
.ce_pix(ce_pix),
.ce_pix_actual(ce_pix),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
@@ -113,12 +93,12 @@ video_mixer #(.LINE_LENGTH(800), .HALF_DEPTH(1)) video_mixer
.hq2x(status[4:3]==1),
.ypbpr(ypbpr),
.ypbpr_full(1),
.R({video,video,1'b0}),
.G({video,video,1'b0}),
.B({video,video,1'b0}),
.mono(1),
.HSync(HSync),
.VSync(VSync),
.R(blankn ? {video,video,video} : "000"),
.G(blankn ? {video,video,video} : "000"),
.B(blankn ? {video,video,video} : "000"),
.mono(0),
.HSync(~HSync),
.VSync(~VSync),
.line_start(0),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
@@ -127,79 +107,118 @@ video_mixer #(.LINE_LENGTH(800), .HALF_DEPTH(1)) video_mixer
.VGA_HS(VGA_HS)
);
wire [14:0]sd_addr;
wire [7:0]sd_dout;
wire [7:0]sd_din;
wire sd_we;
wire sd_rd;
wire sd_ready;
wire [1:0] turbo = status[7:6];
sram sram(
.SDRAM_DQ(SDRAM_DQ),
.SDRAM_A(SDRAM_A),
.SDRAM_DQML(SDRAM_DQML),
.SDRAM_DQMH(SDRAM_DQMH),
.SDRAM_BA(SDRAM_BA),
.SDRAM_nCS(SDRAM_nCS),
.SDRAM_nWE(SDRAM_nWE),
.SDRAM_nRAS(SDRAM_nRAS),
.SDRAM_nCAS(SDRAM_nCAS),
.SDRAM_CKE(SDRAM_CKE),
.init(~locked),
.clk_sdram(SDRAM_CLK),
.addr({10'b0000000000,sd_addr}), // 25 bit address
.dout(sd_dout), // data output to cpu
.din(sd_din), // data input from cpu
.we(sd_we), // cpu requests write
.rd(sd_rd), // cpu requests read
.ready(sd_ready)
);
reg ce_pix;
reg ce_cpu;
always @(negedge clk_sys) begin
reg [2:0] div;
jupiter_ace jupiter_ace
(
.clk_65(clk_65),
.clk_cpu(clk_cpu),
.reset(~reset),
.filas(kbd_rows),
.columnas(kbd_columns),
.video(video),
.hsync(HSync),
div <= div + 1'd1;
ce_pix <= !div[1:0];
ce_cpu <= (!div[2:0] && !turbo) | (!div[1:0] && turbo[0]) | turbo[1];
end
wire reset = ~(buttons[1] || status[0] || status[5]);
wire spk, mic;
jupiter_ace jupiter_ace(
.clk(clk_sys),
.ce_pix(ce_pix),
.ce_cpu(ce_cpu),
.no_wait(|turbo),
.reset(reset|loader_reset),
.kbd_row(kbd_row),
.kbd_col(kbd_col),
.video_out(video),
.hsync(HSync),
.vsync(VSync),
.ear(UART_RX),//Play
.mic(UART_TX),//Record
.spk(audio),
.sd_addr(sd_addr),
.sd_dout(sd_dout),
.sd_din(sd_din),
.sd_we(sd_we),
.sd_rd(sd_rd),
.sd_ready(sd_ready)
.hblank(HBlank),
.vblank(VBlank),
.mic(mic),
.spk(spk),
.loader_en(loader_en),
.loader_addr(loader_addr),
.loader_data(loader_data),
.loader_wr(loader_wr)
);
sigma_delta_dac sigma_delta_dac
(
.DACout(AUDIO_L),
.DACin({audio}),
.CLK(clk_65),
.RESET(0)
.DACin({1'b0, spk, mic, 13'd0}),
.CLK(clk_sys),
.RESET(reset)
);
assign AUDIO_R = AUDIO_L;
keyboard keyboard
(
.clk(clk_65),
.clkps2(ps2_kbd_clk),
.dataps2(ps2_kbd_data),
.rows(kbd_rows),
.columns(kbd_columns),
.kbd_reset(),
.kbd_nmi(),
.kbd_mreset()
wire [7:0] kbd_row;
wire [4:0] kbd_col;
keyboard keyboard(
.reset(reset),
.clk_sys(clk_sys),
.ps2_key(ps2_key),
.kbd_row(kbd_row),
.kbd_col(kbd_col)
);
reg [15:0] loader_addr;
reg [7:0] loader_data;
reg loader_wr;
reg loader_en;
reg loader_reset = 0;
always @(posedge clk_sys) begin
reg [7:0] cnt = 0;
reg [1:0] status = 0;
reg old_download;
integer timeout = 0;
old_download <= ioctl_download;
loader_reset <= 0;
if(~old_download && ioctl_download) begin
loader_addr <= 'h2000;
status <= 0;
loader_reset <=1;
ioctl_wait <= 1;
timeout <= 3000000;
cnt <= 0;
end
loader_wr <= 0;
if(loader_wr) loader_addr <= loader_addr + 1'd1;
if(ioctl_wr) begin
loader_en <= 1;
case(status)
0: if(ioctl_dout == 'hED) status <= 1;
else begin
loader_wr <= 1;
loader_data <= ioctl_dout;
end
1: begin
cnt <= ioctl_dout;
status <= ioctl_dout ? 2'd2 : 2'd3; // cnt = 0 => stop
end
2: begin
loader_data <= ioctl_dout;
ioctl_wait <= 1;
end
endcase
end
if(ioctl_wait && !loader_wr) begin
if(cnt) begin
cnt <= cnt - 1'd1;
loader_wr <= 1;
end
else if(timeout) timeout <= timeout - 1;
else {status,ioctl_wait} <= 0;
end
if(old_download & ~ioctl_download) loader_en <= 0;
if(reset) ioctl_wait <= 0;
end
endmodule

4
Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/build_id.v
View File

@@ -1,2 +1,2 @@
`define BUILD_DATE "180723"
`define BUILD_TIME "190837"
`define BUILD_DATE "181231"
`define BUILD_TIME "044701"

80
Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/dpram.v Normal file
View File

@@ -0,0 +1,80 @@
module dpram #(parameter ADDRWIDTH=8, DATAWIDTH=8, NUMWORDS=1<<ADDRWIDTH, MEM_INIT_FILE="")
(
input clock,
input [ADDRWIDTH-1:0] address_a,
input [DATAWIDTH-1:0] data_a,
input wren_a,
input oe_a_n,
output [DATAWIDTH-1:0] q_a,
input [ADDRWIDTH-1:0] address_b,
input [DATAWIDTH-1:0] data_b,
input wren_b,
input oe_b_n,
output [DATAWIDTH-1:0] q_b
);
wire [DATAWIDTH-1:0] out_a;
wire [DATAWIDTH-1:0] out_b;
assign q_a = oe_a_n ? {DATAWIDTH{1'b1}} : out_a;
assign q_b = oe_b_n ? {DATAWIDTH{1'b1}} : out_b;
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (out_a),
.q_b (out_b),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.numwords_a = NUMWORDS,
altsyncram_component.numwords_b = NUMWORDS,
altsyncram_component.widthad_a = ADDRWIDTH,
altsyncram_component.widthad_b = ADDRWIDTH,
altsyncram_component.width_a = DATAWIDTH,
altsyncram_component.width_b = DATAWIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.init_file = MEM_INIT_FILE,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ";
endmodule

431
Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/jupiter_ace.v
View File

@@ -1,217 +1,230 @@
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:06:40 03/19/2011
// Design Name:
// Module Name: jace_on_fpga
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//============================================================================
// Jupiter Ace main logic
// Copyright (C) 2018 Sorgelig
//
// Dependencies:
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
//////////////////////////////////////////////////////////////////////////////////
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module jupiter_ace (
input wire clk_65,
input wire clk_cpu,
input wire reset,
input wire ear,
output wire [7:0] filas,
input wire [4:0] columnas,
output wire video,
output wire hsync,
output wire vsync,
output wire mic,
output wire spk,
output wire [14:0] sd_addr,
input wire [7:0] sd_dout,
output wire [7:0] sd_din,
output wire sd_we,
output wire sd_rd,
input wire sd_ready
);
module jupiter_ace
(
input clk,
input ce_pix,
input ce_cpu,
input no_wait,
input reset,
wire [7:0] DinZ80;
wire [7:0] DoutZ80;
wire [15:0] AZ80;
output [7:0] kbd_row,
input [4:0] kbd_col,
output video_out,
output hsync,
output vsync,
output hblank,
output vblank,
output reg mic,
output reg spk,
input loader_en,
input [15:0] loader_addr,
input [7:0] loader_data,
input loader_wr
);
assign kbd_row = cpu_addr[15:8];
wire [15:0] addr = loader_en ? loader_addr : cpu_addr;
wire [7:0] data = loader_en ? loader_data : cpu_dout;
wire ram_we = loader_en ? loader_wr : ~wr_n;
wire rom_enable = (~mreq_n | loader_en) && (addr[15:13] == 0); // 0000 - 1FFF 8KB
wire sram_enable = (~mreq_n | loader_en) && (addr[15:11] == 'b00100); // 2000 - 27FF 1KB * 2
wire cram_enable = (~mreq_n | loader_en) && (addr[15:11] == 'b00101); // 2800 - 2FFF 1KB * 2
wire uram_enable = (~mreq_n | loader_en) && (addr[15:12] == 'b0011); // 3000 - 3FFF 1KB * 4
wire xram_enable = (~mreq_n | loader_en) && (addr[15:14] == 'b01); // 4000 - 7FFF 16KB
wire eram_enable = (~mreq_n | loader_en) && (addr[15]); // 8000 - FFFF 32KB
wire wait_n = no_wait | ~(sram_enable | cram_enable) | hblank | vblank | ~addr[10]; // 2400 - 27FF, 2C00 - 2FFF
always @(posedge clk) begin
if (~iorq_n & ~cpu_addr[0]) begin
if (~rd_n) spk <= 0;
if (~wr_n) {spk,mic} <= {1'b1,cpu_dout[3]};
end
end
wire [7:0] io_dout = {8{iorq_n|rd_n}} | (~cpu_addr[0] ? {3'b110, kbd_col} : (sram_data | cram_data));
wire [9:0] sram_addr;
wire [7:0] sram_data;
wire [7:0] sram_dout;
dpram #(10) sram
(
.clock(clk),
.address_a(addr[9:0]),
.data_a(data),
.wren_a(ram_we & sram_enable),
.oe_a_n(~sram_enable),
.q_a(sram_dout),
.address_b(sram_addr),
.q_b(sram_data)
);
wire [9:0] cram_addr;
wire [7:0] cram_data;
dpram #(10) cram
(
.clock(clk),
.address_a(addr[9:0]),
.data_a(data),
.wren_a(ram_we & cram_enable),
.address_b(cram_addr),
.q_b(cram_data)
);
wire [7:0] uram_dout;
dpram #(10) uram
(
.clock(clk),
.address_a(addr[9:0]),
.data_a(data),
.wren_a(ram_we & uram_enable),
.oe_a_n(~uram_enable),
.q_a(uram_dout)
);
wire [7:0] xram_dout;
dpram #(14) xram
(
.clock(clk),
.address_a(addr[13:0]),
.data_a(data),
.wren_a(ram_we & xram_enable),
.oe_a_n(~xram_enable),
.q_a(xram_dout)
);
wire [7:0] eram_dout;
dpram #(14) eram//15
(
.clock(clk),
.address_a(addr[13:0]),
.data_a(data),
.wren_a(ram_we & eram_enable),
.oe_a_n(~eram_enable),
.q_a(eram_dout)
);
wire [7:0] rom_dout;
dpram #(.ADDRWIDTH(13), .MEM_INIT_FILE("ace.mif")) rom
(
.clock(clk),
.address_a(cpu_addr[12:0]),
.oe_a_n(~rom_enable),
.q_a(rom_dout)
);
wire [7:0] cpu_dout;
wire [15:0] cpu_addr;
wire iorq_n, mreq_n, rd_n, wr_n, int_n;
T80pa cpu
(
.RESET_n(~(reset | loader_reset)),
.CLK(clk),
.CEN_p(ce_cpu),
.WAIT_n(wait_n),
.INT_n(vsync),
.MREQ_n(mreq_n),
.IORQ_n(iorq_n),
.RD_n(rd_n),
.WR_n(wr_n),
.A(cpu_addr),
.DI(rom_dout & sram_dout & uram_dout & xram_dout & eram_dout & io_dout),
.DO(cpu_dout),
.DIRSet(|regset),
.DIR(REG)
);
reg [211:0] REG; // IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
reg [1:0] regset = 0;
reg loader_reset;
always @(posedge clk) begin
reg old_loader;
reg old_vsync;
old_vsync <= vsync;
wire iorq_n, mreq_n, rd_n, wr_n, wait_n, int_n;
wire rom_enable, sram_enable, cram_enable, uram_enable, xram_enable, eram_enable, data_from_jace_oe;
wire [7:0] dout_rom, dout_sram, dout_cram, dout_uram, dout_xram, dout_eram, data_from_jace;
wire [7:0] sram_data, cram_data;
wire [9:0] sram_addr, cram_addr;
wire enable_write_to_rom;
wire [7:0] dout_modulo_enable_write;
wire modulo_enable_write_oe;
assign filas = AZ80[15:8];
// Multiplexer
assign DinZ80 = (rom_enable == 1'b1)? dout_rom :
(sram_enable == 1'b1)? dout_sram :
(cram_enable == 1'b1)? dout_cram :
(uram_enable == 1'b1)? dout_uram :
(xram_enable == 1'b1)? dout_xram :
(eram_enable == 1'b1)? dout_eram :
(modulo_enable_write_oe == 1'b1)? dout_modulo_enable_write :
(data_from_jace_oe == 1'b1)? data_from_jace :
sram_data | cram_data; // By default, this is what the data bus sees
ram1k_dualport sram (
.clk(clk_65),
.ce(sram_enable),
.a1(AZ80[9:0]),
.a2(sram_addr),
.din(DoutZ80),
.dout1(dout_sram),
.dout2(sram_data),
.we(~wr_n)
);
ram1k_dualport cram (
.clk(clk_65),
.ce(cram_enable),
.a1(AZ80[9:0]),
.a2(cram_addr),
.din(DoutZ80),
.dout1(dout_cram),
.dout2(cram_data),
.we(~wr_n)
);
ram1k uram(
.clk(clk_65),
.ce(uram_enable),
.a(AZ80[9:0]),
.din(DoutZ80),
.dout(dout_uram),
.we(~wr_n)
);
ram16k xram(
.clk(clk_65),
.ce(xram_enable),
.a(AZ80[13:0]),
.din(DoutZ80),
.dout(dout_xram),
.we(~wr_n)
);
assign sd_addr = AZ80[14:0];
assign dout_eram = sd_dout;
assign sd_din = DoutZ80;
assign sd_we = ~wr_n;
assign sd_rd = eram_enable;
// ram32k eram(//16k for now//todo 32k
// .clk(clk_65),
// .ce(eram_enable),
// .a(AZ80[13:0]),//14
// .din(DoutZ80),
// .dout(dout_eram),
// .we(~wr_n)
// );
// rom the_rom(
// .clk(clk_65),
// .a(AZ80[12:0]),
// .dout(dout_rom)
// );
rom2 the_rom(
.clk(clk_65),
.ce(rom_enable),
.a(AZ80[12:0]),
.din(DoutZ80),
.dout(dout_rom),
.we(~wr_n & enable_write_to_rom)
);
io_write_to_rom modulo_habilitador_escrituras (
.clk(clk_65),
.a(AZ80),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.din(DoutZ80),
.dout(dout_modulo_enable_write),
.dout_oe(modulo_enable_write_oe),
.enable_write_to_rom(enable_write_to_rom)
);
tv80n cpu(
// Outputs
.m1_n(),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.rfsh_n(),
.halt_n(),
.busak_n(),
.A(AZ80),
.dout(DoutZ80),
// Inputs
.di(DinZ80),
.reset_n(reset),
.clk(clk_cpu),
.wait_n(wait_n),
.int_n(int_n),
.nmi_n(1'b1),
.busrq_n(1'b1)
);
glue glogic (
.clk(clk_65),
// CPU interface
.cpu_addr(AZ80),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.data_from_cpu(DoutZ80),
.data_to_cpu(data_from_jace),
.data_to_cpu_oe(data_from_jace_oe),
.wait_n(wait_n),
.int_n(int_n),
// CPU-RAM interface
.rom_enable(rom_enable),
.sram_enable(sram_enable),
.cram_enable(cram_enable),
.uram_enable(uram_enable),
.xram_enable(xram_enable),
.eram_enable(eram_enable),
// Screen RAM and Char RAM interface
.screen_addr(sram_addr),
.screen_data(sram_data),
.char_addr(cram_addr),
.char_data(cram_data),
// Devices
.kbdcols(columnas),
.ear(ear),
.spk(spk),
.mic(mic),
.video(video),
.hsync_pal(hsync),
.vsync_pal(vsync)
);
endmodule
if(loader_en) begin
loader_reset <= 1;
regset <= 2'b11;
if(loader_wr && (loader_addr[15:8] == 8'h21) && !loader_addr[7]) begin
case(loader_addr[6:0])
'h00: REG[15:8] <= loader_data; //f
'h01: REG[7:0] <= loader_data; //a
'h04: REG[87:80] <= loader_data; //c
'h05: REG[95:88] <= loader_data; //b
'h08: REG[103:96] <= loader_data; //e
'h09: REG[111:104] <= loader_data; //d
'h0C: REG[119:112] <= loader_data; //l
'h0D: REG[127:120] <= loader_data; //h
'h10: REG[135:128] <= loader_data; //xl
'h11: REG[143:136] <= loader_data; //xh
'h14: REG[199:192] <= loader_data; //yl
'h15: REG[207:200] <= loader_data; //yh
'h18: REG[55:48] <= loader_data; //spl
'h19: REG[63:56] <= loader_data; //sph
'h1C: REG[71:64] <= loader_data; //pcl
'h1D: REG[79:72] <= loader_data; //pch
'h20: REG[31:24] <= loader_data; //f'
'h21: REG[23:16] <= loader_data; //a'
'h24: REG[151:144] <= loader_data; //c'
'h25: REG[159:152] <= loader_data; //b' //EightyOne wrongly restores it to B register
'h28: REG[167:160] <= loader_data; //e'
'h29: REG[175:168] <= loader_data; //d'
'h2C: REG[183:176] <= loader_data; //l'
'h2D: REG[191:184] <= loader_data; //h'
'h30: REG[209:208] <= loader_data[1:0]; //im
'h34: REG[210] <= loader_data[0]; //iff1
'h38: REG[211] <= loader_data[0]; //iff2
'h3C: REG[39:32] <= loader_data; //i
'h40: REG[47:40] <= loader_data; //r
endcase
end
end
else begin
if(~old_vsync & vsync) loader_reset <= 0;
if(~loader_reset && regset) begin
regset <= regset - 1'd1;
if(REG[63:48] > loader_addr) begin
REG[63:48] <= 16'hFFFE; // bug in dump!
end
end
end
end
video video(
.clk(clk),
.ce_pix(ce_pix),
.sram_addr(sram_addr),
.sram_data(sram_data),
.cram_addr(cram_addr),
.cram_data(cram_data),
.video_out(video_out),
.hsync(hsync),
.vsync(vsync),
.hblank(hblank),
.vblank(vblank)
);
endmodule

843
Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/keyboard.v
View File

@@ -1,632 +1,253 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:36:45 11/07/2015
// Design Name:
// Module Name: keyboard
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//============================================================================
// Jupiter Ace keyboard
// Copyright (C) 2018 Sorgelig
//
// Dependencies:
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
//////////////////////////////////////////////////////////////////////////////////
module keyboard(
input wire clk,
input wire clkps2,
input wire dataps2,
input wire [7:0] rows,
output wire [4:0] columns,
output reg kbd_reset,
output reg kbd_nmi,
output reg kbd_mreset
);
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
initial begin
kbd_reset = 1'b1;
kbd_nmi = 1'b1;
kbd_mreset = 1'b1;
end
module keyboard
(
input reset,
input clk_sys,
// Teclas no extendidas
`define KEY_RELEASED 8'hf0
`define KEY_EXTENDED 8'he0
`define KEY_ESC 8'h76
`define KEY_F1 8'h05
`define KEY_F2 8'h06
`define KEY_F3 8'h04
`define KEY_F4 8'h0C
`define KEY_F5 8'h03
`define KEY_F6 8'h0B
`define KEY_F7 8'h83
`define KEY_F8 8'h0A
`define KEY_F9 8'h01
`define KEY_F10 8'h09
`define KEY_F11 8'h78
`define KEY_F12 8'h07
input [10:0] ps2_key,
`define KEY_BL 8'h0E
`define KEY_1 8'h16
`define KEY_2 8'h1E
`define KEY_3 8'h26
`define KEY_4 8'h25
`define KEY_5 8'h2E
`define KEY_6 8'h36
`define KEY_7 8'h3D
`define KEY_8 8'h3E
`define KEY_9 8'h46
`define KEY_0 8'h45
`define KEY_APOS 8'h4E
`define KEY_AEXC 8'h55
`define KEY_BKSP 8'h66
input [7:0] kbd_row,
output [4:0] kbd_col
);
`define KEY_TAB 8'h0D
`define KEY_Q 8'h15
`define KEY_W 8'h1D
`define KEY_E 8'h24
`define KEY_R 8'h2D
`define KEY_T 8'h2C
`define KEY_Y 8'h35
`define KEY_U 8'h3C
`define KEY_I 8'h43
`define KEY_O 8'h44
`define KEY_P 8'h4D
`define KEY_CORCHA 8'h54
`define KEY_CORCHC 8'h5B
`define KEY_ENTER 8'h5A
reg [4:0] keys[7:0];
wire press_n = ~ps2_key[9];
`define KEY_CPSLK 8'h58
`define KEY_A 8'h1C
`define KEY_S 8'h1B
`define KEY_D 8'h23
`define KEY_F 8'h2B
`define KEY_G 8'h34
`define KEY_H 8'h33
`define KEY_J 8'h3B
`define KEY_K 8'h42
`define KEY_L 8'h4B
`define KEY_NT 8'h4C
`define KEY_LLAVA 8'h52
`define KEY_LLAVC 8'h5D
// Output addressed row to ULA
assign kbd_col = ({5{kbd_row[0]}} | keys[0])
&({5{kbd_row[1]}} | keys[1])
&({5{kbd_row[2]}} | keys[2])
&({5{kbd_row[3]}} | keys[3])
&({5{kbd_row[4]}} | keys[4])
&({5{kbd_row[5]}} | keys[5])
&({5{kbd_row[6]}} | keys[6])
&({5{kbd_row[7]}} | keys[7]);
`define KEY_LSHIFT 8'h12
`define KEY_LT 8'h61
`define KEY_Z 8'h1A
`define KEY_X 8'h22
`define KEY_C 8'h21
`define KEY_V 8'h2A
`define KEY_B 8'h32
`define KEY_N 8'h31
`define KEY_M 8'h3A
`define KEY_COMA 8'h41
`define KEY_PUNTO 8'h49
`define KEY_MENOS 8'h4A
`define KEY_RSHIFT 8'h59
wire shift = ~keys[0][0];
`define KEY_LCTRL 8'h14
`define KEY_LALT 8'h11
`define KEY_SPACE 8'h29
always @(posedge clk_sys) begin
reg old_reset = 0;
reg old_state;
`define KEY_KP0 8'h70
`define KEY_KP1 8'h69
`define KEY_KP2 8'h72
`define KEY_KP3 8'h7A
`define KEY_KP4 8'h6B
`define KEY_KP5 8'h73
`define KEY_KP6 8'h74
`define KEY_KP7 8'h6C
`define KEY_KP8 8'h75
`define KEY_KP9 8'h7D
`define KEY_KPPUNTO 8'h71
`define KEY_KPMAS 8'h79
`define KEY_KPMENOS 8'h7B
`define KEY_KPASTER 8'h7C
old_state <= ps2_key[10];
`define KEY_BLKNUM 8'h77
`define KEY_BLKSCR 8'h7E
old_reset <= reset;
if(~old_reset & reset)begin
keys[0] <= 5'b11111;
keys[1] <= 5'b11111;
keys[2] <= 5'b11111;
keys[3] <= 5'b11111;
keys[4] <= 5'b11111;
keys[5] <= 5'b11111;
keys[6] <= 5'b11111;
keys[7] <= 5'b11111;
end
// Teclas extendidas (E0 + scancode)
`define KEY_WAKEUP 8'h5E
`define KEY_SLEEP 8'h3F
`define KEY_POWER 8'h37
`define KEY_INS 8'h70
`define KEY_SUP 8'h71
`define KEY_HOME 8'h6C
`define KEY_END 8'h69
`define KEY_PGU 8'h7D
`define KEY_PGD 8'h7A
`define KEY_UP 8'h75
`define KEY_DOWN 8'h72
`define KEY_LEFT 8'h6B
`define KEY_RIGHT 8'h74
`define KEY_RCTRL 8'h14
`define KEY_ALTGR 8'h11
`define KEY_KPENTER 8'h5A
`define KEY_KPSLASH 8'h4A
`define KEY_PRTSCR 8'h7C
if(old_state != ps2_key[10]) begin
case(ps2_key[7:0])
8'h12 : keys[0][0] <= press_n; // Left shift (CAPS SHIFT)
8'h59 : keys[0][0] <= press_n; // Right shift (CAPS SHIFT)
8'h14: keys[0][1] <= press_n; // ctrl
8'h1a : keys[0][2] <= press_n; // Z
8'h22 : keys[0][3] <= press_n; // X
8'h21 : keys[0][4] <= press_n; // C
8'h1c : keys[1][0] <= press_n; // A
8'h1b : keys[1][1] <= press_n; // S
8'h23 : keys[1][2] <= press_n; // D
8'h2b : keys[1][3] <= press_n; // F
8'h34 : keys[1][4] <= press_n; // G
wire new_key_aval;
wire [7:0] scancode;
wire is_released;
wire is_extended;
8'h15 : keys[2][0] <= press_n; // Q
8'h1d : keys[2][1] <= press_n; // W
8'h24 : keys[2][2] <= press_n; // E
8'h2d : keys[2][3] <= press_n; // R
8'h2c : keys[2][4] <= press_n; // T
reg shift_pressed = 1'b0;
reg ctrl_pressed = 1'b0;
reg alt_pressed = 1'b0;
8'h16 : keys[3][0] <= press_n; // 1
8'h1e : keys[3][1] <= press_n; // 2
8'h26 : keys[3][2] <= press_n; // 3
8'h25 : keys[3][3] <= press_n; // 4
8'h2e : keys[3][4] <= press_n; // 5
ps2_port ps2_kbd (
.clk(clk), // se recomienda 1 MHz <= clk <= 600 MHz
.enable_rcv(1'b1), // habilitar la maquina de estados de recepcion
.ps2clk_ext(clkps2),
.ps2data_ext(dataps2),
.kb_interrupt(new_key_aval), // a 1 durante 1 clk para indicar nueva tecla recibida
.scancode(scancode), // make o breakcode de la tecla
.released(is_released), // soltada=1, pulsada=0
.extended(is_extended) // extendida=1, no extendida=0
);
8'h45 : keys[4][0] <= press_n; // 0
8'h46 : keys[4][1] <= press_n; // 9
8'h3e : keys[4][2] <= press_n; // 8
8'h3d : keys[4][3] <= press_n; // 7
8'h36 : keys[4][4] <= press_n; // 6
reg [4:0] matrix[0:7]; // 40-key matrix keyboard
initial begin
matrix[0] = 5'b11111; // C X Z SS CS
matrix[1] = 5'b11111; // G F D S A
matrix[2] = 5'b11111; // T R E W Q
matrix[3] = 5'b11111; // 5 4 3 2 1
matrix[4] = 5'b11111; // 6 7 8 9 0
matrix[5] = 5'b11111; // Y U I O P
matrix[6] = 5'b11111; // H J K L ENT
matrix[7] = 5'b11111; // V B N M SP
end
8'h4d : keys[5][0] <= press_n; // P
8'h44 : keys[5][1] <= press_n; // O
8'h43 : keys[5][2] <= press_n; // I
8'h3c : keys[5][3] <= press_n; // U
8'h35 : keys[5][4] <= press_n; // Y
assign columns = (matrix[0] | { {8{rows[0]}} }) &
(matrix[1] | { {8{rows[1]}} }) &
(matrix[2] | { {8{rows[2]}} }) &
(matrix[3] | { {8{rows[3]}} }) &
(matrix[4] | { {8{rows[4]}} }) &
(matrix[5] | { {8{rows[5]}} }) &
(matrix[6] | { {8{rows[6]}} }) &
(matrix[7] | { {8{rows[7]}} });
8'h5a : keys[6][0] <= press_n; // ENTER
8'h4b : keys[6][1] <= press_n; // L
8'h42 : keys[6][2] <= press_n; // K
8'h3b : keys[6][3] <= press_n; // J
8'h33 : keys[6][4] <= press_n; // H
8'h29 : keys[7][0] <= press_n; // SPACE
8'h3a : keys[7][1] <= press_n; // M
8'h31 : keys[7][2] <= press_n; // N
8'h32 : keys[7][3] <= press_n; // B
8'h2a : keys[7][4] <= press_n; // V
8'h6B : begin // Left (CAPS 5)
keys[0][0] <= press_n;
keys[3][4] <= press_n;
end
8'h72 : begin // Up (CAPS 6)
keys[0][0] <= press_n;
keys[4][3] <= press_n;
end
8'h75 : begin // Down (CAPS 7)
keys[0][0] <= press_n;
keys[4][4] <= press_n;
end
8'h74 : begin // Right (CAPS 8)
keys[0][0] <= press_n;
keys[4][2] <= press_n;
end
8'h66 : begin // Backspace (CAPS 0)
keys[0][0] <= press_n;
keys[4][0] <= press_n;
end
8'h76 : begin // Escape (CAPS SPACE)
keys[0][0] <= press_n;
keys[7][0] <= press_n;
end
8'h58 : begin // Caps Lock
keys[0][0] <= press_n;
keys[3][1] <= press_n;
end
8'h0D : begin // TAB
keys[0][0] <= press_n;
keys[3][0] <= press_n;
end
8'h41 : begin // , <
keys[0][1] <= press_n;
if(press_n) begin
keys[7][2] <= 1;
keys[2][3] <= 1;
end
else if(shift) keys[2][3] <= 0;
else keys[7][2] <= 0;
end
8'h49 : begin // . >
keys[0][1] <= press_n;
if(press_n) begin
keys[7][1] <= 1;
keys[2][4] <= 1;
end
else if(shift) keys[2][4] <= 0;
else keys[7][1] <= 0;
end
8'h4C : begin // ; :
keys[0][1] <= press_n;
if(press_n) begin
keys[5][1] <= 1;
keys[0][2] <= 1;
end
else if(shift) keys[0][2] <= 0;
else keys[5][1] <= 0;
end
8'h52 : begin // " '
keys[0][1] <= press_n;
if(press_n) begin
keys[5][0] <= 1;
keys[4][3] <= 1;
end
else if(shift) keys[4][3] <= 0;
else keys[5][0] <= 0;
end
8'h4A : begin // / ?
keys[0][1] <= press_n;
if(press_n) begin
keys[0][4] <= 1;
keys[7][4] <= 1;
end
else if(shift) keys[0][4] <= 0;
else keys[7][4] <= 0;
end
8'h4E : begin // - _
keys[0][1] <= press_n;
if(press_n) begin
keys[6][3] <= 1;
keys[4][0] <= 1;
end
else if(shift) keys[4][0] <= 0;
else keys[6][3] <= 0;
end
8'h55 : begin // = +
keys[0][1] <= press_n;
if(press_n) begin
keys[6][1] <= 1;
keys[6][2] <= 1;
end
else if(shift) keys[6][2] <= 0;
else keys[6][1] <= 0;
end
8'h54 : begin // [ {
keys[0][1] <= press_n;
if(press_n) begin
keys[5][4] <= 1;
keys[1][3] <= 1;
end
else if(shift) keys[1][3] <= 0;
else keys[5][4] <= 0;
end
8'h5B : begin // ] }
keys[0][1] <= press_n;
if(press_n) begin
keys[5][3] <= 1;
keys[1][4] <= 1;
end
else if(shift) keys[1][4] <= 0;
else keys[5][3] <= 0;
end
8'h5D : begin // \ |
keys[0][1] <= press_n;
if(press_n) begin
keys[1][2] <= 1;
keys[1][1] <= 1;
end
else if(shift) keys[1][1] <= 0;
else keys[1][2] <= 0;
end
8'h0E : begin // ~ *
keys[0][1] <= press_n;
if(press_n) begin
keys[1][0] <= 1;
keys[7][3] <= 1;
end
else if(shift) keys[7][3] <= 0;
else keys[1][0] <= 0;
end
default: ;
endcase
end
end
always @(posedge clk) begin
if (new_key_aval == 1'b1) begin
case (scancode)
// Special and control keys
`KEY_LSHIFT,
`KEY_RSHIFT:
shift_pressed <= ~is_released;
`KEY_LCTRL,
`KEY_RCTRL:
begin
ctrl_pressed <= ~is_released;
if (is_extended)
matrix[0][1] <= is_released; // Right control = Symbol shift
else
matrix[0][0] <= is_released; // Left control = Caps shift
end
`KEY_LALT:
alt_pressed <= ~is_released;
`KEY_KPPUNTO:
if (ctrl_pressed && alt_pressed) begin
kbd_reset <= is_released;
if (is_released == 1'b0) begin
matrix[0] <= 5'b11111; // C X Z SS CS
matrix[1] <= 5'b11111; // G F D S A
matrix[2] <= 5'b11111; // T R E W Q
matrix[3] <= 5'b11111; // 5 4 3 2 1
matrix[4] <= 5'b11111; // 6 7 8 9 0
matrix[5] <= 5'b11111; // Y U I O P
matrix[6] <= 5'b11111; // H J K L ENT
matrix[7] <= 5'b11111; // V B N M SP
end
end
`KEY_F5:
if (ctrl_pressed && alt_pressed)
kbd_nmi <= is_released;
`KEY_ENTER:
matrix[6][0] <= is_released;
`KEY_ESC:
begin
matrix[0][0] <= is_released;
matrix[7][0] <= is_released;
end
`KEY_BKSP:
if (ctrl_pressed && alt_pressed) begin
kbd_mreset <= is_released;
end
else begin
matrix[0][0] <= is_released;
matrix[4][0] <= is_released;
end
`KEY_CPSLK:
begin
matrix[0][0] <= is_released;
matrix[3][1] <= is_released; // CAPS LOCK
end
`KEY_F2:
begin
matrix[0][0] <= is_released;
matrix[3][0] <= is_released; // EDIT
end
// Digits and puntuaction marks inside digits
`KEY_1:
begin
if (alt_pressed) begin
matrix[0][1] <= is_released;
matrix[1][1] <= is_released; // |
end
else if (shift_pressed) begin
matrix[0][1] <= is_released;
matrix[3][0] <= is_released; // !
end
else
matrix[3][0] <= is_released;
end
`KEY_2:
begin
if (alt_pressed) begin
matrix[0][1] <= is_released;
matrix[3][1] <= is_released; // @
end
else if (shift_pressed) begin
matrix[0][1] <= is_released;
matrix[5][0] <= is_released; // "
end
else
matrix[3][1] <= is_released;
end
`KEY_3:
begin
if (!shift_pressed)
matrix[3][2] <= is_released;
else begin
matrix[0][1] <= is_released;
matrix[3][2] <= is_released; // #
end
end
`KEY_4:
begin
if (shift_pressed) begin
matrix[0][1] <= is_released;
matrix[3][3] <= is_released; // $
end
else if (ctrl_pressed) begin
matrix[0][0] <= is_released;
matrix[3][3] <= is_released; // INV VIDEO
end
else
matrix[3][3] <= is_released;
end
`KEY_5:
begin
if (!shift_pressed)
matrix[3][4] <= is_released;
else begin
matrix[0][1] <= is_released;
matrix[3][4] <= is_released; // %
end
end
`KEY_6:
begin
if (!shift_pressed)
matrix[4][4] <= is_released;
else begin
matrix[0][1] <= is_released;
matrix[4][4] <= is_released; // &
end
end
`KEY_7:
begin
if (!shift_pressed)
matrix[4][3] <= is_released;
else begin
matrix[0][1] <= is_released;
matrix[7][4] <= is_released; // /
end
end
`KEY_8:
begin
if (!shift_pressed)
matrix[4][2] <= is_released;
else begin
matrix[0][1] <= is_released;
matrix[4][2] <= is_released; // (
end
end
`KEY_9:
begin
if (shift_pressed) begin
matrix[0][1] <= is_released;
matrix[4][1] <= is_released; // )
end
else if (ctrl_pressed) begin
matrix[0][0] <= is_released;
matrix[4][1] <= is_released;
end
else
matrix[4][1] <= is_released;
end
`KEY_0:
begin
if (!shift_pressed)
matrix[4][0] <= is_released;
else begin
matrix[0][1] <= is_released;
matrix[6][1] <= is_released; // =
end
end
// Alphabetic characters
`KEY_Z:
begin
matrix[0][2] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_X:
begin
matrix[0][3] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_C:
begin
matrix[0][4] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_A:
begin
matrix[1][0] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_S:
begin
matrix[1][1] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_D:
begin
matrix[1][2] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_F:
begin
matrix[1][3] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_G:
begin
matrix[1][4] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_Q:
begin
matrix[2][0] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_W:
begin
matrix[2][1] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_E:
begin
matrix[2][2] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_R:
begin
matrix[2][3] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_T:
begin
matrix[2][4] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_P:
begin
matrix[5][0] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_O:
begin
matrix[5][1] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_I:
begin
matrix[5][2] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_U:
begin
matrix[5][3] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_Y:
begin
matrix[5][4] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_L:
begin
matrix[6][1] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_K:
begin
matrix[6][2] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_J:
begin
matrix[6][3] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_H:
begin
matrix[6][4] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_M:
begin
matrix[7][1] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_N:
begin
matrix[7][2] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_B:
begin
matrix[7][3] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
`KEY_V:
begin
matrix[7][4] <= is_released;
if (shift_pressed)
matrix[0][0] <= is_released;
end
// Symbols
`KEY_APOS:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[4][3] <= is_released;
else
matrix[0][4] <= is_released; // ?
end
`KEY_CORCHA:
begin
matrix[0][1] <= is_released;
if (alt_pressed || shift_pressed)
matrix[5][4] <= is_released; // [
else
matrix[6][4] <= is_released; // ^
end
`KEY_CORCHC:
begin
matrix[0][1] <= is_released;
if (shift_pressed)
matrix[7][3] <= is_released; // *
else if (alt_pressed)
matrix[5][3] <= is_released; // ]
else
matrix[6][2] <= is_released; // +
end
`KEY_LLAVA:
begin
matrix[0][1] <= is_released;
if (alt_pressed || shift_pressed)
matrix[1][3] <= is_released; // {
else
matrix[0][3] <= is_released; // pound
end
`KEY_LLAVC:
begin
matrix[0][1] <= is_released;
if (alt_pressed || shift_pressed)
matrix[1][4] <= is_released; // }
else
matrix[5][2] <= is_released; // copyright
end
`KEY_COMA:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[7][2] <= is_released;
else
matrix[5][1] <= is_released; // ;
end
`KEY_PUNTO:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[7][1] <= is_released;
else
matrix[0][2] <= is_released; // :
end
`KEY_MENOS:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[6][3] <= is_released; //
else
matrix[4][0] <= is_released; // _
end
`KEY_LT:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[2][3] <= is_released; // <
else
matrix[2][4] <= is_released; // >
end
`KEY_BL:
begin
matrix[0][1] <= is_released;
matrix[1][2] <= is_released; // \
end
`KEY_SPACE:
matrix[7][0] <= is_released;
// Cursor keys
`KEY_UP:
begin
matrix[0][0] <= is_released;
matrix[4][4] <= is_released;
end
`KEY_DOWN:
begin
matrix[0][0] <= is_released;
matrix[4][3] <= is_released;
end
`KEY_LEFT:
begin
matrix[0][0] <= is_released;
matrix[3][4] <= is_released;
end
`KEY_RIGHT:
begin
matrix[0][0] <= is_released;
matrix[4][2] <= is_released;
end
endcase
end
end
endmodule

385
Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/mist_io.v
View File

@@ -5,6 +5,7 @@
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
// Copyright (c) 2015-2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
@@ -61,13 +62,13 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
// SD config
input sd_conf,
input sd_sdhc,
output img_mounted, // signaling that new image has been mounted
output [1:0] img_mounted, // signaling that new image has been mounted
output reg [31:0] img_size, // size of image in bytes
// SD block level access
input [31:0] sd_lba,
input sd_rd,
input sd_wr,
input [1:0] sd_rd,
input [1:0] sd_wr,
output reg sd_ack,
output reg sd_ack_conf,
@@ -83,25 +84,27 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
output ps2_mouse_clk,
output reg ps2_mouse_data,
// ps2 alternative interface.
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
output reg [10:0] ps2_key = 0,
// [24] - toggles with every event
output reg [24:0] ps2_mouse = 0,
// ARM -> FPGA download
input ioctl_force_erase,
input ioctl_ce,
output reg ioctl_download = 0, // signal indicating an active download
output reg ioctl_erasing = 0, // signal indicating an active erase
output reg [7:0] ioctl_index, // menu index used to upload the file
output reg ioctl_wr = 0,
output reg [24:0] ioctl_addr,
output reg [7:0] ioctl_dout
output reg [7:0] ioctl_dout,
input ioctl_wait
);
reg [7:0] b_data;
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [7:0] byte_cnt; // counts bytes
reg [7:0] but_sw;
reg [2:0] stick_idx;
reg mount_strobe = 0;
reg [1:0] mount_strobe = 0;
assign img_mounted = mount_strobe;
assign buttons = but_sw[1:0];
@@ -109,160 +112,189 @@ assign switches = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
assign ypbpr = but_sw[5];
wire [7:0] spi_dout = { sbuf, SPI_DI};
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
wire drive_sel = sd_rd[1] | sd_wr[1];
wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [9:0] byte_cnt; // counts bytes
reg spi_do;
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
// drive MISO only when transmitting core id
always@(negedge SPI_SCK) begin
if(!CONF_DATA0) begin
// first byte returned is always core type, further bytes are
// command dependent
if(byte_cnt == 0) begin
spi_do <= core_type[~bit_cnt];
reg [7:0] spi_data_out;
end else begin
case(cmd)
// reading config string
8'h14: begin
// returning a byte from string
if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
else spi_do <= 0;
end
// SPI transmitter
always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
// reading sd card status
8'h16: begin
if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
else spi_do <= 0;
end
// reading sd card write data
8'h18:
spi_do <= b_data[~bit_cnt];
default:
spi_do <= 0;
endcase
end
end
end
reg b_wr2,b_wr3;
always @(negedge clk_sys) begin
b_wr3 <= b_wr2;
sd_buff_wr <= b_wr3;
end
reg [7:0] spi_data_in;
reg spi_data_ready = 0;
// SPI receiver
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
reg [6:0] sbuf;
reg [31:0] sd_lba_r;
reg drive_sel_r;
if(CONF_DATA0) begin
b_wr2 <= 0;
bit_cnt <= 0;
byte_cnt <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
end else begin
b_wr2 <= 0;
sbuf <= spi_dout[6:0];
spi_data_out <= core_type;
end
else
begin
bit_cnt <= bit_cnt + 1'd1;
if(bit_cnt == 5) begin
if (byte_cnt == 0) sd_buff_addr <= 0;
if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
end
sbuf <= {sbuf[5:0], SPI_DI};
// finished reading command byte
if(bit_cnt == 7) begin
if(!byte_cnt) cmd <= {sbuf, SPI_DI};
spi_data_in <= {sbuf, SPI_DI};
spi_data_ready <= ~spi_data_ready;
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
if(byte_cnt == 0) begin
cmd <= spi_dout;
if(spi_dout == 8'h19) begin
sd_ack_conf <= 1;
sd_buff_addr <= 0;
end
if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
sd_ack <= 1;
sd_buff_addr <= 0;
end
if(spi_dout == 8'h18) b_data <= sd_buff_din;
mount_strobe <= 0;
end else begin
case(cmd)
// buttons and switches
8'h01: but_sw <= spi_dout;
8'h02: joystick_0 <= spi_dout;
8'h03: joystick_1 <= spi_dout;
spi_data_out <= 0;
case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
// reading config string
8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
// store incoming ps2 mouse bytes
8'h04: begin
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout;
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
end
// reading sd card status
8'h16: if(byte_cnt == 0) begin
spi_data_out <= sd_cmd;
sd_lba_r <= sd_lba;
drive_sel_r <= drive_sel;
end else if (byte_cnt == 1) begin
spi_data_out <= drive_sel_r;
end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
// store incoming ps2 keyboard bytes
8'h05: begin
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout;
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
end
8'h15: status[7:0] <= spi_dout;
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
8'h19,
// send sector IO -> FPGA
// flag that download begins
8'h17: begin
sd_buff_dout <= spi_dout;
b_wr2 <= 1;
end
// reading sd card write data
8'h18: spi_data_out <= sd_buff_din;
endcase
end
end
end
8'h18: b_data <= sd_buff_din;
reg [31:0] ps2_key_raw = 0;
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
// joystick analog
8'h1a: begin
// first byte is joystick index
if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
else if(byte_cnt == 2) begin
// second byte is x axis
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
end else if(byte_cnt == 3) begin
// third byte is y axis
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
end
end
// transfer to clk_sys domain
always@(posedge clk_sys) begin
reg old_ss1, old_ss2;
reg old_ready1, old_ready2;
reg [2:0] b_wr;
reg got_ps2 = 0;
// notify image selection
8'h1c: mount_strobe <= 1;
old_ss1 <= CONF_DATA0;
old_ss2 <= old_ss1;
old_ready1 <= spi_data_ready;
old_ready2 <= old_ready1;
sd_buff_wr <= b_wr[0];
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
b_wr <= (b_wr<<1);
// send image info
8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
// status, 32bit version
8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
default: ;
endcase
if(old_ss2) begin
got_ps2 <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
sd_buff_addr <= 0;
if(got_ps2) begin
if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24];
if(cmd == 5) begin
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
end
end
end
else
if(old_ready2 ^ old_ready1) begin
if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
if(byte_cnt < 2) begin
if (cmd == 8'h19) sd_ack_conf <= 1;
if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
mount_strobe <= 0;
if(cmd == 5) ps2_key_raw <= 0;
end else begin
case(cmd)
// buttons and switches
8'h01: but_sw <= spi_data_in;
8'h02: joystick_0 <= spi_data_in;
8'h03: joystick_1 <= spi_data_in;
// store incoming ps2 mouse bytes
8'h04: begin
got_ps2 <= 1;
case(byte_cnt)
2: ps2_mouse[7:0] <= spi_data_in;
3: ps2_mouse[15:8] <= spi_data_in;
4: ps2_mouse[23:16] <= spi_data_in;
endcase
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in;
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
end
// store incoming ps2 keyboard bytes
8'h05: begin
got_ps2 <= 1;
ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in};
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in;
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
end
8'h15: status[7:0] <= spi_data_in;
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
8'h19,
// send sector IO -> FPGA
// flag that download begins
8'h17: begin
sd_buff_dout <= spi_data_in;
b_wr <= 1;
end
// joystick analog
8'h1a: begin
// first byte is joystick index
if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
else if(byte_cnt == 3) begin
// second byte is x axis
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
end else if(byte_cnt == 4) begin
// third byte is y axis
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
end
end
// notify image selection
8'h1c: mount_strobe[spi_data_in[0]] <= 1;
// send image info
8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
// status, 32bit version
8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
default: ;
endcase
end
end
end
@@ -417,6 +449,8 @@ localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
reg rdownload = 0;
// data_io has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS2) begin
reg [6:0] sbuf;
@@ -426,15 +460,10 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
if(SPI_SS2) cnt <= 0;
else begin
rclk <= 0;
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
// increase target address after write
if(rclk) addr <= addr + 1'd1;
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
@@ -446,18 +475,11 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
case(ioctl_index)
0: addr <= 'h080000; // BOOT ROM
'h01: addr <= 'h000100; // ROM file
'h41: addr <= 'h000100; // COM file
'h81: addr <= 'h000000; // C00 file
'hC1: addr <= 'h010000; // EDD file
default: addr <= 'h100000; // FDD file
endcase
ioctl_download <= 1;
addr <= 25'h080000;
rdownload <= 1;
end else begin
addr_w <= addr;
ioctl_download <= 0;
rdownload <= 0;
end
end
@@ -465,7 +487,8 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
addr_w <= addr;
data_w <= {sbuf, SPI_DI};
rclk <= 1;
addr <= addr + 1'd1;
rclk <= ~rclk;
end
// expose file (menu) index
@@ -473,60 +496,24 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
end
end
reg [24:0] erase_mask;
wire [24:0] next_erase = (ioctl_addr + 1'd1) & erase_mask;
// transfer to ioctl_clk domain.
// ioctl_index is set before ioctl_download, so it's stable already
always@(posedge clk_sys) begin
reg rclkD, rclkD2;
reg old_force = 0;
reg [5:0] erase_clk_div;
reg [24:0] end_addr;
reg erase_trigger = 0;
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wr <= 0;
if(ioctl_ce& ~ioctl_wait) begin
ioctl_download <= rdownload;
if(rclkD & ~rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wr <= 1;
end
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wr <= 0;
if(ioctl_download) begin
old_force <= 0;
ioctl_erasing <= 0;
erase_trigger <= (ioctl_index == 1);
end else begin
old_force <= ioctl_force_erase;
// start erasing
if(erase_trigger) begin
erase_trigger <= 0;
erase_mask <= 'hFFFF;
end_addr <= 'h0100;
erase_clk_div <= 1;
ioctl_erasing <= 1;
end else if((ioctl_force_erase & ~old_force)) begin
erase_trigger <= 0;
ioctl_addr <= 'h1FFFFFF;
erase_mask <= 'h1FFFFFF;
end_addr <= 'h0050000;
erase_clk_div <= 1;
ioctl_erasing <= 1;
end else if(ioctl_erasing) begin
erase_clk_div <= erase_clk_div + 1'd1;
if(!erase_clk_div) begin
if(next_erase == end_addr) ioctl_erasing <= 0;
else begin
ioctl_addr <= next_erase;
ioctl_dout <= 0;
ioctl_wr <= 1;
end
end
if(rclkD != rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wr <= 1;
end
end
end
endmodule
endmodule

2
Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/pll.qip
View File

@@ -1,4 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

120
Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/pll.v
View File

@@ -14,7 +14,7 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
@@ -40,17 +40,11 @@ module pll (
areset,
inclk0,
c0,
c1,
c2,
c3,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output c3;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
@@ -60,26 +54,20 @@ module pll (
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire3;
wire [0:0] sub_wire8 = 1'h0;
wire [2:2] sub_wire5 = sub_wire0[2:2];
wire [0:0] sub_wire4 = sub_wire0[0:0];
wire [3:3] sub_wire2 = sub_wire0[3:3];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c3 = sub_wire2;
wire locked = sub_wire3;
wire c0 = sub_wire4;
wire c2 = sub_wire5;
wire sub_wire6 = inclk0;
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
wire sub_wire0;
wire [4:0] sub_wire1;
wire [0:0] sub_wire5 = 1'h0;
wire locked = sub_wire0;
wire [0:0] sub_wire2 = sub_wire1[0:0];
wire c0 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire7),
.clk (sub_wire0),
.locked (sub_wire3),
.inclk (sub_wire4),
.locked (sub_wire0),
.clk (sub_wire1),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
@@ -119,18 +107,6 @@ module pll (
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 26,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 54,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 13,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 108,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 13,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 27,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 104,
altpll_component.clk3_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
@@ -164,9 +140,9 @@ module pll (
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
@@ -205,17 +181,8 @@ endmodule
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "54"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "108"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "27"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "26.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "3.250000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "104.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -236,42 +203,18 @@ endmodule
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "26"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "13"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "13"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "104"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "26.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "3.25000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "104.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -294,20 +237,11 @@ endmodule
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
@@ -316,18 +250,6 @@ endmodule
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "26"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "54"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "13"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "108"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "13"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "104"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -360,9 +282,9 @@ endmodule
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
@@ -380,18 +302,12 @@ endmodule
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE

0
Computer_MiST/Sharp - MZ-80K_MiST/rtl/sprom.vhd → Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/sprom.vhd
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75
Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/video.sv Normal file
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@@ -0,0 +1,75 @@
//============================================================================
// Jupiter Ace video
// Copyright (C) 2018 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module video
(
input clk,
input ce_pix,
output [9:0] sram_addr,
input [7:0] sram_data,
output [9:0] cram_addr,
input [7:0] cram_data,
output video_out,
output reg hsync,
output reg vsync,
output reg hblank,
output reg vblank
);
assign sram_addr = {vcnt[7:3], hcnt[7:3]};
assign cram_addr = {sram_data[6:0], vcnt[2:0]};
assign video_out = pix[7] ^ inv;
reg [8:0] hcnt;
reg [8:0] vcnt;
reg [7:0] pix;
reg inv;
always @(posedge clk) begin
reg ven,hen;
if(ce_pix) begin
if (hcnt != 415) hcnt <= hcnt + 1'd1;
else begin
hcnt <= 0;
if (vcnt != 311) vcnt <= vcnt + 1'd1;
else vcnt <= 0;
end
if (hcnt == 308) hsync <= 0;
if (hcnt == 340) hsync <= 1;
if (hcnt == 000) hen = 1;
if (hcnt == 256) hen = 0;
if (vcnt == 248) vsync <= 0;
if (vcnt == 256) vsync <= 1;
if (vcnt == 000) ven = 1;
if (vcnt == 192) ven = 0;
hblank <= ~hen;
vblank <= ~ven;
pix <= {pix[6:0], 1'b0};
if (!hcnt[2:0] && ven && hen) pix <= cram_data;
if (!hcnt[2:0]) inv <= ven & hen & sram_data[7];
end
end
endmodule

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@@ -0,0 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
Version_Index = 302049280
Creation_Time = Mon Dec 31 01:30:50 2018

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Computer_MiST/Sharp - MZ-80_MiST_New/rtl/sprom.vhd Normal file
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@@ -0,0 +1,82 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sprom IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END sprom;
ARCHITECTURE SYN OF sprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;

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