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23
Oric Atmos_MiST/Extender.qpf Normal file
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# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
QUARTUS_VERSION = "8.1"
DATE = "20:32:23 January 19, 2009"
# Revisions
PROJECT_REVISION = "Extender"

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Oric Atmos_MiST/Extender.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 00:34:30 May 04, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Extender_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:32:23 JANUARY 19, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name MISC_FILE "C:/_fpga/_cone/C1Extender/SYMB_CPC/Extender.dpf"
set_global_assignment -name VHDL_FILE rtl/oricatmos.vhd
set_global_assignment -name VHDL_FILE rtl/STOP_WATCH.vhd
set_global_assignment -name VHDL_FILE rtl/t65_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/t65.vhd
set_global_assignment -name VHDL_FILE rtl/t65_alu.vhd
set_global_assignment -name VHDL_FILE rtl/pack_t65.vhd
set_global_assignment -name VHDL_FILE rtl/ula.vhd
set_global_assignment -name VHDL_FILE rtl/pack_ula.vhd
set_global_assignment -name VHDL_FILE rtl/m6522.vhd
set_global_assignment -name VHDL_FILE rtl/vag.vhd
set_global_assignment -name VHDL_FILE rtl/video.vhd
set_global_assignment -name VHDL_FILE rtl/keyboard.vhd
set_global_assignment -name VHDL_FILE rtl/iodecode.vhd
set_global_assignment -name VHDL_FILE rtl/addmemux.vhd
set_global_assignment -name VHDL_FILE rtl/memmap.vhd
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name VHDL_FILE rtl/ps2key.vhd
set_global_assignment -name VHDL_FILE rtl/ctrlseq.vhd
set_global_assignment -name VHDL_FILE rtl/ay3819x.vhd
set_global_assignment -name VHDL_FILE rtl/tone_generator.vhd
set_global_assignment -name VHDL_FILE rtl/noise_generator.vhd
set_global_assignment -name VHDL_FILE rtl/GEN_CLK.vhd
set_global_assignment -name VHDL_FILE rtl/MIXER.vhd
set_global_assignment -name VHDL_FILE rtl/gen_env.vhd
set_global_assignment -name VHDL_FILE rtl/manage_amplitude.vhd
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TPD_REQUIREMENT "2 ns"
set_global_assignment -name TSU_REQUIREMENT "2 ns"
set_global_assignment -name TCO_REQUIREMENT "2 ns"
set_global_assignment -name TH_REQUIREMENT "2 ns"
set_global_assignment -name FMAX_REQUIREMENT "96 MHz"
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name TOP_LEVEL_ENTITY oricatmos
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "FAR END"
# start EDA_TOOL_SETTINGS(eda_blast_fpga)
# ---------------------------------------
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
# end EDA_TOOL_SETTINGS(eda_blast_fpga)
# -------------------------------------
# -----------------------
# start ENTITY(oricatmos)
# Fitter Assignments
# ==================
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
# start LOGICLOCK_REGION(Root Region)
# -----------------------------------
# LogicLock Region Assignments
# ============================
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
# end LOGICLOCK_REGION(Root Region)
# ---------------------------------
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(oricatmos)
# ---------------------
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name VHDL_FILE rtl/ram48k.vhd
set_global_assignment -name VHDL_FILE rtl/scan_converter.vhd
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix.vhd
set_global_assignment -name QIP_FILE rtl/RAMB16_S18_S18.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VHDL_FILE rtl/keymap.vhd
set_global_assignment -name VHDL_FILE rtl/keymatrix.vhd
set_global_assignment -name VHDL_FILE rtl/rom.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name QIP_FILE rtl/HC4051.qip
set_global_assignment -name QIP_FILE rtl/rrom.qip
set_global_assignment -name QIP_FILE rtl/RAM16X1D.qip
set_global_assignment -name VHDL_FILE rtl/keyboardX.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Oric Atmos_MiST/Extender.srf Normal file
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{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 13012 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10631 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""}

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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

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Oric Atmos_MiST/rtl/HC4051.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "HC4051.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "HC4051.cmp"]

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-- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: HC4051.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY HC4051 IS
PORT
(
data0 : IN STD_LOGIC ;
data1 : IN STD_LOGIC ;
data2 : IN STD_LOGIC ;
data3 : IN STD_LOGIC ;
data4 : IN STD_LOGIC ;
data5 : IN STD_LOGIC ;
data6 : IN STD_LOGIC ;
data7 : IN STD_LOGIC ;
sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
result : OUT STD_LOGIC
);
END HC4051;
ARCHITECTURE SYN OF hc4051 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_2D (7 DOWNTO 0, 0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC ;
SIGNAL sub_wire9 : STD_LOGIC ;
SIGNAL sub_wire10 : STD_LOGIC ;
BEGIN
sub_wire10 <= data0;
sub_wire9 <= data1;
sub_wire8 <= data2;
sub_wire7 <= data3;
sub_wire6 <= data4;
sub_wire5 <= data5;
sub_wire4 <= data6;
sub_wire1 <= sub_wire0(0);
result <= sub_wire1;
sub_wire2 <= data7;
sub_wire3(7, 0) <= sub_wire2;
sub_wire3(6, 0) <= sub_wire4;
sub_wire3(5, 0) <= sub_wire5;
sub_wire3(4, 0) <= sub_wire6;
sub_wire3(3, 0) <= sub_wire7;
sub_wire3(2, 0) <= sub_wire8;
sub_wire3(1, 0) <= sub_wire9;
sub_wire3(0, 0) <= sub_wire10;
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_size => 8,
lpm_type => "LPM_MUX",
lpm_width => 1,
lpm_widths => 3
)
PORT MAP (
data => sub_wire3,
sel => sel,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0"
-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1"
-- Retrieval info: USED_PORT: data2 0 0 0 0 INPUT NODEFVAL "data2"
-- Retrieval info: USED_PORT: data3 0 0 0 0 INPUT NODEFVAL "data3"
-- Retrieval info: USED_PORT: data4 0 0 0 0 INPUT NODEFVAL "data4"
-- Retrieval info: USED_PORT: data5 0 0 0 0 INPUT NODEFVAL "data5"
-- Retrieval info: USED_PORT: data6 0 0 0 0 INPUT NODEFVAL "data6"
-- Retrieval info: USED_PORT: data7 0 0 0 0 INPUT NODEFVAL "data7"
-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result"
-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
-- Retrieval info: CONNECT: @data 1 2 1 0 data2 0 0 0 0
-- Retrieval info: CONNECT: @data 1 3 1 0 data3 0 0 0 0
-- Retrieval info: CONNECT: @data 1 4 1 0 data4 0 0 0 0
-- Retrieval info: CONNECT: @data 1 5 1 0 data5 0 0 0 0
-- Retrieval info: CONNECT: @data 1 6 1 0 data6 0 0 0 0
-- Retrieval info: CONNECT: @data 1 7 1 0 data7 0 0 0 0
-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

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--
-- fg.vhd
--
-- Generate a random noise.
--
-- Copyright (C)2001 SEILEBOST
-- All rights reserved.
--
-- $Id: fg.vhd, v0.3 2001/11/14 00:00:00 SEILEBOST $
--
-- from XAPP211.pdf & XAPP211.ZIP (XILINX APPLICATION)
--
--The following is example code that implements one LFSR which can be used as part of pn generators.
--The number of taps, tap points, and LFSR width are parameratizable. When targetting Xilinx (Virtex)
--all the latest synthesis vendors (Leonardo, Synplicity, and FPGA Express) will infer the shift
--register LUTS (SRL16) resulting in a very efficient implementation.
--
--Control signals have been provided to allow external circuitry to control such things as filling,
--puncturing, stalling (augmentation), etc.
--
--Mike Gulotta
--11/4/99
--Revised 3/17/00: Fixed "commented" block diagram to match polynomial.
--
--
--###################################################################################################
-- I Polinomials: #
-- I(x) = X**17 + X**2 + 1 #
-- #
-- LFSR implementation format examples: #
--###################################################################################################
-- #
-- I(x) = X**17 + X**2 + 1 #
-- ________ #
-- | |<<......................... #
-- | Parity | | #
-- .................| |<<... | #
-- | |________| | | #
-- | | | #
-- | __________________ | ___ ___ | #
-- |...|\ | | | | | | | | | pn_out_i #
-- ||-->>| 16 | - - - -| 2 |-----| 1 | 0 | >>---------->> #
--DataIn_i.|/ |____|________|____| |___|___| #
-- | srl_i #
-- FillSel..| #
-- ---> shifting -->> #
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i_pn_gen is
generic(NumOfTaps_i : integer := 2; -- # of taps for I channel LFSR, including output tap.
Width : integer := 17); -- LFSR length (ie, total # of storage elements)
port(clk, ShiftEn, FillSel, DataIn_i, RESET : in std_logic;
pn_out_i : out std_logic);
end i_pn_gen ;
architecture rtl of i_pn_gen is
type TapPointArray_i is array (NumOfTaps_i-1 downto 0) of integer;
constant Tap_i : TapPointArray_i := (2, 0);
signal srl_i : std_logic_vector(Width-1 downto 0); -- shift register.
signal par_fdbk_i : std_logic_vector(NumOfTaps_i downto 0); -- Parity feedback.
signal lfsr_in_i : std_logic; -- mux output.
begin
---------------------------------------------------------------------
------------------ I Channel ----------------------------------------
---------------------------------------------------------------------
Shift_i : process (clk, reset)
begin
if (RESET = '1') then
SRL_I <= "00000000000000000";
elsif clk'event and clk = '1' then
if (ShiftEn = '1') then
srl_i <= lfsr_in_i & srl_i(srl_i'high downto 1);
end if;
end if;
end process;
par_fdbk_i(0) <= '0';
fdbk_i : for X in 0 to Tap_i'high generate -- parity generator
par_fdbk_i(X+1) <= par_fdbk_i(X) xor srl_i(Tap_i(X));
end generate fdbk_i;
lfsr_in_i <= DataIn_i when FillSel = '1' else par_fdbk_i(par_fdbk_i'high);
pn_out_i <= srl_i(srl_i'low); -- PN I channel output.
end rtl;

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--
-- MIXER.vhd
--
-- Mix tone generator and noise generator.
--
-- Copyright (C)2001 SEILEBOST
-- All rights reserved.
--
-- $Id: MIXER.vhd, v0.2 2001/11/02 00:00:00 SEILEBOST $
--
-- A lot of work !!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity MIXER is
Port ( CLK : in std_logic;
CS : in std_logic;
RST : in std_logic;
WR : in std_logic;
IN_A : in std_logic;
IN_B : in std_logic;
IN_C : in std_logic;
IN_NOISE : in std_logic;
DATA : in std_logic_vector(5 downto 0);
OUT_A : out std_logic;
OUT_B : out std_logic;
OUT_C : out std_logic );
end MIXER;
architecture Behavioral of MIXER is
begin
PROCESS(CLK, RST, CS, WR, DATA, IN_A, IN_B, IN_C, IN_NOISE)
BEGIN
if (RST = '1') then
OUT_A <= '0';
OUT_B <= '0';
OUT_C <= '0';
elsif ( CLK'event and CLK = '1') then
if not (CS = '1' and WR = '1') then
-- TONE A
if (DATA(0) = '0') then
if (DATA(3) = '0') then
OUT_A <= IN_A xor IN_NOISE;
else
OUT_A <= IN_A;
end if;
else
OUT_A <= '1';
end if;
-- TONE B
if (DATA(1) = '0') then
if (DATA(4) = '0') then
OUT_B <= IN_B xor IN_NOISE;
else
OUT_B <= IN_B;
end if;
else
OUT_B <= '1';
end if;
-- TONE C
if (DATA(2) = '0') then
if (DATA(5) = '0') then
OUT_C <= IN_C xor IN_NOISE;
else
OUT_C <= IN_C;
end if;
else
OUT_C <= '1';
end if;
end if;
end if;
end process;
end Behavioral;

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@@ -0,0 +1,3 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "RAM16X1D.vhd"]

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-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM16X1D.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM16X1D IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END RAM16X1D;
ARCHITECTURE SYN OF ram16x1d IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
q_a <= sub_wire0(0 DOWNTO 0);
q_b <= sub_wire1(0 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 16,
numwords_b => 16,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 4,
widthad_b => 4,
width_a => 1,
width_b => 1,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
clock0 => clock,
wren_a => wren_a,
address_b => address_b,
data_b => data_b,
wren_b => wren_b,
address_a => address_a,
data_a => data_a,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL "address_a[3..0]"
-- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL "address_b[3..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 1 0 INPUT NODEFVAL "data_a[0..0]"
-- Retrieval info: USED_PORT: data_b 0 0 1 0 INPUT NODEFVAL "data_b[0..0]"
-- Retrieval info: USED_PORT: q_a 0 0 1 0 OUTPUT NODEFVAL "q_a[0..0]"
-- Retrieval info: USED_PORT: q_b 0 0 1 0 OUTPUT NODEFVAL "q_b[0..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0
-- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 1 0 data_a 0 0 1 0
-- Retrieval info: CONNECT: @data_b 0 0 1 0 data_b 0 0 1 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 1 0 @q_a 0 0 1 0
-- Retrieval info: CONNECT: q_b 0 0 1 0 @q_b 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM16X1D.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM16X1D.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM16X1D.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM16X1D.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM16X1D_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

0
Oric Atmos_MiST/rtl/RAM16X1Dx.qip Normal file
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3
Oric Atmos_MiST/rtl/RAMB16_S18_S18.qip Normal file
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@@ -0,0 +1,3 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "RAMB16_S18_S18.vhd"]

234
Oric Atmos_MiST/rtl/RAMB16_S18_S18.vhd Normal file
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-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAMB16_S18_S18.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAMB16_S18_S18 IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END RAMB16_S18_S18;
ARCHITECTURE SYN OF ramb16_s18_s18 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
q_a <= sub_wire0(15 DOWNTO 0);
q_b <= sub_wire1(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
widthad_b => 10,
width_a => 16,
width_b => 16,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
clock0 => clock_a,
wren_a => wren_a,
address_b => address_b,
clock1 => clock_b,
data_b => data_b,
rden_a => rden_a,
wren_b => wren_b,
address_a => address_a,
data_a => data_a,
rden_b => rden_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
-- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
-- Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
-- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
-- Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
-- Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
-- Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
-- Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
-- Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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Oric Atmos_MiST/rtl/REG_ADDR.vhd Normal file
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--
-- REG_ADDR.vhd
--
-- DECODER of Registre.
--
-- Copyright (C)2001 SEILEBOST
-- All rights reserved.
--
-- $Id: REG_ADDR.vhd, v0.2 2001/11/02 00:00:00 SEILEBOST $
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity REG_ADRESSE is
Port ( REG_ADDR : in std_logic_vector(3 downto 0);
RST : in std_logic,
SEL_REG : out std_logic_vector(15 downto 0) );
end REG_ADRESSE;
architecture Behavioral of REG_ADRESSE is
-- DECODER 4 -> 16
begin
end Behavioral;

3
Oric Atmos_MiST/rtl/ROM256X1.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ROM256X1.vhd"]

146
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-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ROM256X1.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY ROM256X1 IS
generic (
init_file : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
)
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END ROM256X1;
ARCHITECTURE SYN OF rom256x1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
q <= sub_wire0(0 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 8,
width_a => 1,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "./roms/key1.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "1"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/key1.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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--===================================
-- Listing 4.17
--===================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity stop_watch is
port(
clk: in std_logic;
go, clr: in std_logic;
d2, d1, d0: out std_logic_vector(3 downto 0)
);
end stop_watch;
--===================================
-- Listing 4.18
--===================================
architecture if_arch of stop_watch is
constant DVSR: integer:=5000000;
signal ms_reg, ms_next: unsigned(22 downto 0);
signal d2_reg, d1_reg, d0_reg: unsigned(3 downto 0);
signal d2_next, d1_next, d0_next: unsigned(3 downto 0);
signal ms_tick: std_logic;
begin
-- register
process(clk)
begin
if (clk'event and clk='1') then
ms_reg <= ms_next;
d2_reg <= d2_next;
d1_reg <= d1_next;
d0_reg <= d0_next;
end if;
end process;
-- next-state logic
-- 0.1 sec tick generator: mod-5000000
ms_next <=
(others=>'0') when clr='1' or
(ms_reg=DVSR and go='1') else
ms_reg + 1 when go='1' else
ms_reg;
ms_tick <= '1' when ms_reg=DVSR else '0';
-- 0.1 sec counter
process(d0_reg,d1_reg,d2_reg,ms_tick,clr)
begin
-- defult
d0_next <= d0_reg;
d1_next <= d1_reg;
d2_next <= d2_reg;
if clr='1' then
d0_next <= "0000";
d1_next <= "0000";
d2_next <= "0000";
elsif ms_tick='1' then
if (d0_reg/=9) then
d0_next <= d0_reg + 1;
else -- reach XX9
d0_next <= "0000";
if (d1_reg/=9) then
d1_next <= d1_reg + 1;
else -- reach X99
d1_next <= "0000";
if (d2_reg/=9) then
d2_next <= d2_reg + 1;
else -- reach 999
d2_next <= "0000";
end if;
end if;
end if;
end if;
end process;
-- output logic
d0 <= std_logic_vector(d0_reg);
d1 <= std_logic_vector(d1_reg);
d2 <= std_logic_vector(d2_reg);
end if_arch;

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Oric Atmos_MiST/rtl/TST_ay3819x.vhd Normal file
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-- VHDL Test Bench Created from source file ay3819x.vhd -- 15:33:03 12/26/2001
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
constant CLK_PERIOD : time := 60 nS; -- system clock period
COMPONENT ay3819x
PORT(
RESET : IN std_logic;
CLOCK : IN std_logic;
BDIR : IN std_logic;
BC1 : IN std_logic;
BC2 : IN std_logic;
D : INOUT std_logic_vector(7 downto 0);
IOA : INOUT std_logic_vector(7 downto 0);
IOB : INOUT std_logic_vector(7 downto 0);
AnalogA : OUT std_logic;
AnalogB : OUT std_logic;
AnalogC : OUT std_logic );
END COMPONENT;
SIGNAL D : std_logic_vector(7 downto 0);
SIGNAL RESET : std_logic;
SIGNAL CLOCK : std_logic;
SIGNAL BDIR : std_logic;
SIGNAL BC1 : std_logic;
SIGNAL BC2 : std_logic;
SIGNAL IOA : std_logic_vector(7 downto 0);
SIGNAL IOB : std_logic_vector(7 downto 0);
SIGNAL AnalogA : std_logic;
SIGNAL AnalogB : std_logic;
SIGNAL AnalogC : std_logic;
BEGIN
uut: ay3819x PORT MAP(
D => D,
RESET => RESET,
CLOCK => CLOCK,
BDIR => BDIR,
BC1 => BC1,
BC2 => BC2,
IOA => IOA,
IOB => IOB,
AnalogA => AnalogA,
AnalogB => AnalogB,
AnalogC => AnalogC );
-- *** Test Bench - User Defined Section ***
CREATE_CLK: process
begin
CLOCK <= '0';
wait for CLK_PERIOD/2;
CLOCK <= '1';
wait for CLK_PERIOD/2;
end process;
SIMUL_RESET: process
begin
RESET <= '1';
wait until CLOCK'event and CLOCK = '1';
wait until CLOCK'event and CLOCK = '1';
wait for 15 ns;
RESET <= '0';
wait;
end process;
SIMUL_WR_TO_R0: process
begin
BDIR <= '0';
BC1 <= '0';
BC2 <= '0';
wait for 150 ns;
BDIR <= '1'; -- Latch
BC1 <= '1';
BC2 <= '1';
wait for 15 ns;
BDIR <= '0'; -- HIGH IMPEDANCE
BC1 <= '0';
BC2 <= '0';
wait for 45 ns;
BDIR <= '1'; -- write to register
BC1 <= '0';
BC2 <= '1';
wait for 15 ns;
BDIR <= '0'; -- HIGH IMPEDANCE
BC1 <= '0';
BC2 <= '0';
wait for 45 ns;
BDIR <= '1'; -- latch
BC1 <= '1';
BC2 <= '1';
wait for 15 ns;
BDIR <= '0'; -- High impedance
BC1 <= '0';
BC2 <= '0';
wait for 45 ns;
BDIR <= '1'; -- write to register
BC1 <= '0';
BC2 <= '1';
wait for 15 ns;
BDIR <= '0'; -- High impedance
BC1 <= '0';
BC2 <= '0';
wait for 45 ns;
BDIR <= '1'; -- Latch
BC1 <= '1';
BC2 <= '1';
wait for 15 ns;
BDIR <= '0'; -- High impedance
BC1 <= '0';
BC2 <= '0';
wait for 45 ns;
BDIR <= '0'; -- Read
BC1 <= '1';
BC2 <= '1';
wait for 15 ns;
BDIR <= '0'; -- High impedance
BC1 <= '0';
BC2 <= '0';
wait;
end process;
BUS_D : process
begin
D <= ( others => 'Z');
wait for 150 ns;
D <= "00001110";
wait for 30 ns;
D <= ( others => 'Z');
wait for 30 ns; -- 195 ns
D <= "00010101";
wait for 30 ns; -- 225 ns
D <= ( others => 'Z');
wait for 30 ns; -- 255 ns
D <= "00000001";
wait for 30 ns; -- 285 ns
D <= ( others => 'Z');
wait for 30 ns; -- 315 ns
D <= "10010001";
wait for 30 ns; -- 345 ns
D <= ( others => 'Z');
wait for 30 ns; -- 375 ns
D <= "00001110";
wait for 30 ns; -- 405 ns
D <= ( others => 'Z');
wait;
end process;
tb : PROCESS
BEGIN
wait for 1000 ns; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;

597
Oric Atmos_MiST/rtl/YM2149_linmix.vhd Normal file
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--
-- A simulation model of YM2149 (AY-3-8910 with bells on)
-- Copyright (c) MikeJ - Jan 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email support@fpgaarcade.com
--
-- Revision list
--
-- version 001 initial release
--
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
--
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
-- vol 15 .. 0
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
-- to produced all the required values.
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
--
-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
-- accurate for designs where the outputs are buffered and not simply wired together.
-- The ouput level is more complex in that case and requires a larger table.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity YM2149 is
port (
-- data bus
I_DA : in std_logic_vector(7 downto 0);
O_DA : out std_logic_vector(7 downto 0);
O_DA_OE_L : out std_logic;
-- control
I_A9_L : in std_logic;
I_A8 : in std_logic;
I_BDIR : in std_logic;
I_BC2 : in std_logic;
I_BC1 : in std_logic;
I_SEL_L : in std_logic;
O_AUDIO : out std_logic_vector(7 downto 0) := (others => '0');
-- port a
-- I_IOA : in std_logic_vector(7 downto 0);
-- O_IOA : out std_logic_vector(7 downto 0);
-- O_IOA_OE_L : out std_logic;
-- port b
-- I_IOB : in std_logic_vector(7 downto 0);
-- O_IOB : out std_logic_vector(7 downto 0);
-- O_IOB_OE_L : out std_logic;
ENA : in std_logic; -- clock enable for higher speed operation
RESET_L : in std_logic;
CLK : in std_logic -- note 6 Mhz
);
end;
architecture RTL of YM2149 is
type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0);
type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
signal noise_div : std_logic := '0';
signal ena_div : std_logic := '0';
signal ena_div_noise : std_logic := '0';
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
-- registers
signal addr : std_logic_vector(7 downto 0);
signal busctrl_addr : std_logic;
signal busctrl_we : std_logic;
signal busctrl_re : std_logic;
signal reg : array_16x8 := (others => (others => '0'));
signal env_reset : std_logic := '1';
-- signal ioa_inreg : std_logic_vector(7 downto 0) := (others => '0');
-- signal iob_inreg : std_logic_vector(7 downto 0) := (others => '0');
signal noise_gen_cnt : std_logic_vector(4 downto 0) := (others => '0');
signal noise_gen_op : std_logic;
signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
signal tone_gen_op : std_logic_vector(3 downto 1) := (others => '0');
signal env_gen_cnt : std_logic_vector(15 downto 0) := (others => '0');
signal env_ena : std_logic := '0';
signal env_hold : std_logic := '0';
signal env_inc : std_logic := '0';
signal env_vol : std_logic_vector(4 downto 0) := (others => '0');
signal tone_ena_l : std_logic;
signal tone_src : std_logic;
signal noise_ena_l : std_logic;
signal chan_vol : std_logic_vector(4 downto 0);
signal dac_amp : std_logic_vector(7 downto 0) := (others => '0');
signal audio_mix : std_logic_vector(9 downto 0) := (others => '0');
signal audio_final : std_logic_vector(9 downto 0) := (others => '0');
begin
-- cpu i/f
p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
variable cs : std_logic;
variable sel : std_logic_vector(2 downto 0);
begin
-- BDIR BC2 BC1 MODE
-- 0 0 0 inactive
-- 0 0 1 address
-- 0 1 0 inactive
-- 0 1 1 read
-- 1 0 0 address
-- 1 0 1 inactive
-- 1 1 0 write
-- 1 1 1 read
busctrl_addr <= '0';
busctrl_we <= '0';
busctrl_re <= '0';
cs := '0';
if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
cs := '1';
end if;
sel := (I_BDIR & I_BC2 & I_BC1);
case sel is
when "000" => null;
when "001" => busctrl_addr <= '1';
when "010" => null;
when "011" => busctrl_re <= cs;
when "100" => busctrl_addr <= '1';
when "101" => null;
when "110" => busctrl_we <= cs;
when "111" => busctrl_addr <= '1';
when others => null;
end case;
end process;
p_oe : process(busctrl_re)
begin
-- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
O_DA_OE_L <= not (busctrl_re);
end process;
--
-- CLOCKED
--
p_waddr : process(RESET_L, CLK)
begin
-- looks like registers are latches in real chip, but the address is caught at the end of the address state.
if (RESET_L = '0') then
addr <= (others => '0');
elsif rising_edge(CLK) then
if (ENA = '1') then
if (busctrl_addr = '1') then
addr <= I_DA;
end if;
end if;
end if;
end process;
p_wdata : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
reg <= (others => (others => '0'));
env_reset <= '1';
elsif rising_edge(CLK) then
if (ENA = '1') then
env_reset <= '0';
if (busctrl_we = '1') then
case addr(3 downto 0) is
when x"0" => reg(0) <= I_DA;
when x"1" => reg(1) <= I_DA;
when x"2" => reg(2) <= I_DA;
when x"3" => reg(3) <= I_DA;
when x"4" => reg(4) <= I_DA;
when x"5" => reg(5) <= I_DA;
when x"6" => reg(6) <= I_DA;
when x"7" => reg(7) <= I_DA;
when x"8" => reg(8) <= I_DA;
when x"9" => reg(9) <= I_DA;
when x"A" => reg(10) <= I_DA;
when x"B" => reg(11) <= I_DA;
when x"C" => reg(12) <= I_DA;
when x"D" => reg(13) <= I_DA; env_reset <= '1';
when x"E" => reg(14) <= I_DA;
when x"F" => reg(15) <= I_DA;
when others => null;
end case;
end if;
end if;
end if;
end process;
p_rdata : process(busctrl_re, addr, reg) --, ioa_inreg, iob_inreg)
begin
O_DA <= (others => '0'); -- 'X'
if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
case addr(3 downto 0) is
when x"0" => O_DA <= reg(0) ;
when x"1" => O_DA <= reg(1);
when x"2" => O_DA <= reg(2);
when x"3" => O_DA <= reg(3);
when x"4" => O_DA <= reg(4);
when x"5" => O_DA <= reg(5);
when x"6" => O_DA <= reg(6);
when x"7" => O_DA <= reg(7);
when x"8" => O_DA <= reg(8);
when x"9" => O_DA <= reg(9);
when x"A" => O_DA <= reg(10);
when x"B" => O_DA <= reg(11);
when x"C" => O_DA <= reg(12);
when x"D" => O_DA <= reg(13);
when x"E" =>
if (reg(7)(6) = '0') then -- input
O_DA <= x"00"; --ioa_inreg;
else
O_DA <= reg(14); -- read output reg
end if;
when x"F" =>
if (Reg(7)(7) = '0') then
O_DA <= x"00"; --iob_inreg;
else
O_DA <= reg(15);
end if;
when others => null;
end case;
end if;
end process;
--
p_divider : process
begin
wait until rising_edge(CLK);
-- / 8 when SEL is high and /16 when SEL is low
if (ENA = '1') then
ena_div <= '0';
ena_div_noise <= '0';
if (cnt_div = "0000") then
cnt_div <= (not I_SEL_L) & "111";
ena_div <= '1';
noise_div <= not noise_div;
if (noise_div = '1') then
ena_div_noise <= '1';
end if;
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
p_noise_gen : process
variable noise_gen_comp : std_logic_vector(4 downto 0);
variable poly17_zero : std_logic;
begin
wait until rising_edge(CLK);
if (reg(6)(4 downto 0) = "00000") then
noise_gen_comp := (others => '0');
else
noise_gen_comp := (reg(6)(4 downto 0) - "1");
end if;
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
if (ENA = '1') then
if (ena_div_noise = '1') then -- divider ena
if (noise_gen_cnt >= noise_gen_comp) then
noise_gen_cnt <= (others => '0');
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
else
noise_gen_cnt <= (noise_gen_cnt + "1");
end if;
end if;
end if;
end process;
noise_gen_op <= poly17(0);
p_tone_gens : process
variable tone_gen_freq : array_3x12;
variable tone_gen_comp : array_3x12;
begin
wait until rising_edge(CLK);
-- looks like real chips count up - we need to get the Exact behaviour ..
tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
-- period 0 = period 1
for i in 1 to 3 loop
if (tone_gen_freq(i) = x"000") then
tone_gen_comp(i) := (others => '0');
else
tone_gen_comp(i) := (tone_gen_freq(i) - "1");
end if;
end loop;
if (ENA = '1') then
for i in 1 to 3 loop
if (ena_div = '1') then -- divider ena
if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
tone_gen_cnt(i) <= (others => '0');
tone_gen_op(i) <= not tone_gen_op(i);
else
tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
end if;
end if;
end loop;
end if;
end process;
p_envelope_freq : process
variable env_gen_freq : std_logic_vector(15 downto 0);
variable env_gen_comp : std_logic_vector(15 downto 0);
begin
wait until rising_edge(CLK);
env_gen_freq := reg(12) & reg(11);
-- envelope freqs 1 and 0 are the same.
if (env_gen_freq = x"0000") then
env_gen_comp := (others => '0');
else
env_gen_comp := (env_gen_freq - "1");
end if;
if (ENA = '1') then
env_ena <= '0';
if (ena_div = '1') then -- divider ena
if (env_gen_cnt >= env_gen_comp) then
env_gen_cnt <= (others => '0');
env_ena <= '1';
else
env_gen_cnt <= (env_gen_cnt + "1");
end if;
end if;
end if;
end process;
p_envelope_shape : process
variable is_bot : boolean;
variable is_bot_p1 : boolean;
variable is_top_m1 : boolean;
variable is_top : boolean;
begin
wait until rising_edge(CLK);
-- envelope shapes
-- C AtAlH
-- 0 0 x x \___
--
-- 0 1 x x /___
--
-- 1 0 0 0 \\\\
--
-- 1 0 0 1 \___
--
-- 1 0 1 0 \/\/
-- ___
-- 1 0 1 1 \
--
-- 1 1 0 0 ////
-- ___
-- 1 1 0 1 /
--
-- 1 1 1 0 /\/\
--
-- 1 1 1 1 /___
-- synchronous reset to avoid latch warning
if (env_reset = '1') then
-- load initial state
if (reg(13)(2) = '0') then -- attack
env_vol <= (others => '1');
env_inc <= '0'; -- -1
else
env_vol <= (others => '0');
env_inc <= '1'; -- +1
end if;
env_hold <= '0';
else
is_bot := (env_vol = "00000");
is_bot_p1 := (env_vol = "00001");
is_top_m1 := (env_vol = "11110");
is_top := (env_vol = "11111");
if (ENA = '1') then
if (env_ena = '1') then
if (env_hold = '0') then
if (env_inc = '1') then
env_vol <= (env_vol + "00001");
else
env_vol <= (env_vol + "11111");
end if;
end if;
-- envelope shape control.
if (reg(13)(3) = '0') then
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
else
if is_top then env_hold <= '1'; end if;
end if;
else
if (reg(13)(0) = '1') then -- hold = 1
if (env_inc = '0') then -- down
if (reg(13)(1) = '1') then -- alt
if is_bot then env_hold <= '1'; end if;
else
if is_bot_p1 then env_hold <= '1'; end if;
end if;
else
if (reg(13)(1) = '1') then -- alt
if is_top then env_hold <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
end if;
end if;
elsif (reg(13)(1) = '1') then -- alternate
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
if is_top then env_hold <= '0'; env_inc <= '0'; end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
p_chan_mixer : process(cnt_div, reg, tone_gen_op)
begin
tone_ena_l <= '1';
tone_src <= '1';
noise_ena_l <= '1';
chan_vol <= "00000";
case cnt_div(1 downto 0) is
when "00" =>
tone_ena_l <= reg(7)(0);
tone_src <= tone_gen_op(1);
chan_vol <= reg(8)(4 downto 0);
noise_ena_l <= reg(7)(3);
when "01" =>
tone_ena_l <= reg(7)(1);
tone_src <= tone_gen_op(2);
chan_vol <= reg(9)(4 downto 0);
noise_ena_l <= reg(7)(4);
when "10" =>
tone_ena_l <= reg(7)(2);
tone_src <= tone_gen_op(3);
chan_vol <= reg(10)(4 downto 0);
noise_ena_l <= reg(7)(5);
when "11" => null; -- tone gen outputs become valid on this clock
when others => null;
end case;
end process;
p_op_mixer : process
variable chan_mixed : std_logic;
variable chan_amp : std_logic_vector(4 downto 0);
begin
wait until rising_edge(CLK);
if (ENA = '1') then
chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
chan_amp := (others => '0');
if (chan_mixed = '1') then
if (chan_vol(4) = '0') then
if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
chan_amp := (others => '0');
else
chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
end if;
else
chan_amp := env_vol(4 downto 0);
end if;
end if;
dac_amp <= (others => '0');
case chan_amp is
when "11111" => dac_amp <= x"FF";
when "11110" => dac_amp <= x"D9";
when "11101" => dac_amp <= x"BA";
when "11100" => dac_amp <= x"9F";
when "11011" => dac_amp <= x"88";
when "11010" => dac_amp <= x"74";
when "11001" => dac_amp <= x"63";
when "11000" => dac_amp <= x"54";
when "10111" => dac_amp <= x"48";
when "10110" => dac_amp <= x"3D";
when "10101" => dac_amp <= x"34";
when "10100" => dac_amp <= x"2C";
when "10011" => dac_amp <= x"25";
when "10010" => dac_amp <= x"1F";
when "10001" => dac_amp <= x"1A";
when "10000" => dac_amp <= x"16";
when "01111" => dac_amp <= x"13";
when "01110" => dac_amp <= x"10";
when "01101" => dac_amp <= x"0D";
when "01100" => dac_amp <= x"0B";
when "01011" => dac_amp <= x"09";
when "01010" => dac_amp <= x"08";
when "01001" => dac_amp <= x"07";
when "01000" => dac_amp <= x"06";
when "00111" => dac_amp <= x"05";
when "00110" => dac_amp <= x"04";
when "00101" => dac_amp <= x"03";
when "00100" => dac_amp <= x"03";
when "00011" => dac_amp <= x"02";
when "00010" => dac_amp <= x"02";
when "00001" => dac_amp <= x"01";
when "00000" => dac_amp <= x"00";
when others => null;
end case;
if (cnt_div(1 downto 0) = "10") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & dac_amp);
end if;
end if;
end process;
p_audio_output : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
O_AUDIO <= (others => '0');
elsif rising_edge(CLK) then
if (ENA = '1') then
O_AUDIO <= audio_final(9 downto 2);
end if;
end if;
end process;
-- p_io_ports : process(reg)
-- begin
-- O_IOA <= reg(14);
-- O_IOA_OE_L <= not reg(7)(6);
-- O_IOB <= reg(15);
-- O_IOB_OE_L <= not reg(7)(7);
-- end process;
-- p_io_ports_inreg : process
-- begin
-- wait until rising_edge(CLK);
-- if (ENA = '1') then -- resync
-- ioa_inreg <= I_IOA;
-- iob_inreg <= I_IOB;
-- end if;
-- end process;
end architecture RTL;

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--
-- addmenux.vhd
--
-- Manage bus address multiplexer
--
-- Copyright (C)2001 - 2005 SEILEBOST
-- All rights reserved.
--
-- $Id: addmenux.vhd, v0.10 2009/06/25 00:00:00 SEILEBOST $
-- MODIFICATION :
-- v0.01 : 200X/??/??
-- v0.10 : 2009/06/25 : Intégration de la partie multiplexage de l'accès ram
-- TODO :
--
-- TODO :
-- Remark :
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_STD.all;
--use IEEE.std_logic_unsigned.all;
entity addmemux is
port ( RESETn : in std_logic;
VAP1 : in std_logic_vector(15 downto 0);-- Video address phase 1
VAP2 : in std_logic_vector(15 downto 0);-- Video address phase 2
BAP : in std_logic_vector(15 downto 0);-- Bus address processor (A15-A0)
VA1L : in std_logic; -- Video address phase 1 LATCH
VA1R : in std_logic; -- Video address phase 1 ROW
VA1C : in std_logic; -- Video address phase 1 COLUMN
VA2L : in std_logic; -- Video address phase 2 LATCH
VA2R : in std_logic; -- Video address phase 2 ROW
VA2C : in std_logic; -- Video address phase 2 COLUMN
BAC : in std_logic; -- Bus address COLUMN
BAL : in std_logic; -- Bus address LATCH
AD_DYN : out std_logic_vector(15 downto 0) -- Address Bus dynamic
);
end entity addmemux;
architecture addmemux_arch of addmemux is
signal lVAP1 : std_logic_vector(15 downto 0);
signal lVAP2 : std_logic_vector(15 downto 0);
signal lBAP : std_logic_vector(15 downto 0);
begin
-- Latch VAP1
u_VAP1 : PROCESS ( VAP1, VA1L,resetn )
begin
if (resetn = '0') then
lVAP1 <= (OTHERS => '0');
elsif rising_edge(VA1L) then
lVAP1 <= VAP1;
end if;
end process;
-- Latch VAP2
u_VAP2 : PROCESS ( VAP2, VA2L, resetn )
begin
if (resetn = '0') then
lVAP2 <= (OTHERS => '0');
elsif rising_edge(VA2L) then
lVAP2 <= VAP2;
end if;
end process;
-- Latch BAP
u_BAP: PROCESS ( BAP, BAL, resetn )
begin
if (resetn = '0') then
lBAP<= (OTHERS => '0');
elsif rising_edge(BAL) then
lBAP<= BAP;
end if;
end process;
-- Assignation
AD_DYN <= lVAP1(15 downto 0) when VA1R = '1' else
-- lVAP1(7 downto 0) when VA1C = '1' else
lVAP2(15 downto 0) when VA2R = '1' else
-- lVAP2(7 downto 0) when VA2C = '1' else
-- lBAP when BAL = '1' else
-- (OTHERS => 'Z');
lBAP;
end architecture addmemux_arch;

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--
-- A simulation model of PSG hardware
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: passionoric.free.fr
--
-- Email seilebost@free.fr
--
--
-- Revision list
--
-- v0.42 2002/01/03 : It seems ok
-- v0.43 2009/01/21 : bus bidirectionnel => bus unidirectionnel
-- v0.44 2009/10/11 : Reset asynchrone pour le process U_TRAIT
-- v0.45 2010/01/03 : Ajout d'une horloge pour le DAC
-- v0.46 2010/01/06 : Modification du générateur de fréquence
-- pour ajouter la division par 16 et par 256
-- v0.50 2010/01/19 : Reorganisation du code
--
-- AY3819X.vhd
--
-- Top entity of AY3819X.
--
-- Copyright (C)2001-2010 SEILEBOST
-- All rights reserved.
--
-- $Id: AY3819.vhd, v0.50 2010/01/19 00:00:00 SEILEBOST $
--
-- TODO :
-- Many verification !!
-- Remark :
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use UNISIM.Vcomponents.ALL; -- for IOBUF and OBUF
entity AY3819X is
Port ( DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
O_DATA_OE_L : out std_logic;
RESET : in std_logic;
CLOCK : in std_logic;
CLOCK_DAC : in std_logic; -- 24 MHz pour le DAC
BDIR : in std_logic;
BC1 : in std_logic;
BC2 : in std_logic;
IOA : inout std_logic_vector(7 downto 0);
IOB : inout std_logic_vector(7 downto 0);
AnalogA : out std_logic;
AnalogB : out std_logic;
AnalogC : out std_logic );
end AY3819X;
architecture Behavioral of AY3819X is
SIGNAL BUS_CS : std_logic_vector(15 downto 0); -- Select the different module when Read / Write Register
-- Create register
SIGNAL R0 : std_logic_vector(7 downto 0); -- Tone generator frequency Fine Tune channel A
SIGNAL R1 : std_logic_vector(7 downto 0); -- Tone generator frequency Coarse Tune channel A
SIGNAL R2 : std_logic_vector(7 downto 0); -- Tone generator frequency Fine Tune channel B
SIGNAL R3 : std_logic_vector(7 downto 0); -- Tone generator frequency Coarse Tune channel B
SIGNAL R4 : std_logic_vector(7 downto 0); -- Tone generator frequency Fine Tune channel C
SIGNAL R5 : std_logic_vector(7 downto 0); -- Tone generator frequency Coarse Tune channel B
SIGNAL R6 : std_logic_vector(7 downto 0); -- Noise generator frequency
SIGNAL R7 : std_logic_vector(7 downto 0); -- Mixer Control I/O Enable
SIGNAL R8 : std_logic_vector(7 downto 0); -- Amplitude control channel A
SIGNAL R9 : std_logic_vector(7 downto 0); -- Amplitude control channel B
SIGNAL R10 : std_logic_vector(7 downto 0); -- Amplitude control channel C
SIGNAL R11 : std_logic_vector(7 downto 0); -- Envelope period control fine tune
SIGNAL R12 : std_logic_vector(7 downto 0); -- Envelope period control coarse tune
SIGNAL R13 : std_logic_vector(7 downto 0); -- Envelope shape/cycle control
SIGNAL REG_ADDR : std_logic_vector(3 downto 0); -- Keep the number of register addressed
SIGNAL WR : std_logic; -- WRITE (FLAG)
SIGNAL CLK_A : std_logic; -- CLOCK TONE VOICE A
SIGNAL CLK_B : std_logic; -- CLOCK TONE VOICE B
SIGNAL CLK_C : std_logic; -- CLOCK TONE VOICE C
SIGNAL CLK_TONE_A : std_logic; -- CLOCK TONE VOICE A +/- CLOCK NOISE
SIGNAL CLK_TONE_B : std_logic; -- CLOCK TONE VOICE B +/- CLOCK NOISE
SIGNAL CLK_TONE_C : std_logic; -- CLOCK TONE VOICE C +/- CLOCK NOISE
SIGNAL CLK_E : std_logic; -- CLOCK Envelope Generator
SIGNAL CLK_N : std_logic; -- CLOCK FROM NOISE GENERATOR
SIGNAL CLK_16 : std_logic; -- CLOCK (=1 MHz) / 16 pour le "tone"
SIGNAL CLK_256 : std_logic; -- CLOCK (=1 MHz) / 256 pour l'enveloppe
SIGNAL OUT_AMPL_E : std_logic_vector(3 downto 0); -- Amplitude of signal from Envelope generator
SIGNAL IAnalogA : std_logic; -- FOR IOPAD, exit from DAC VOICE A
SIGNAL IAnalogB : std_logic; -- FOR IOPAD, exit from DAC VOICE B
SIGNAL IAnalogC : std_logic; -- FOR IOPAD, exit from DAC VOICE C
SIGNAL RST_ENV : std_logic; -- FOR RESET THE VALUE OF ENVELOPPE
COMPONENT TONE_GENERATOR PORT ( CLK : in std_logic;
--CLK_TONE : in std_logic;
RST : in std_logic;
WR : in std_logic;
--CS_COARSE : in std_logic;
--CS_FINE : in std_logic;
DATA_COARSE : in std_logic_vector(7 downto 0);
DATA_FINE : in std_logic_vector(7 downto 0);
OUT_TONE : inout std_logic );
END COMPONENT;
COMPONENT NOISE_GENERATOR PORT ( CLK : in std_logic;
RST : in std_logic;
--WR : in std_logic;
--CS : in std_logic;
DATA : in std_logic_vector(4 downto 0);
CLK_N : out std_logic );
END COMPONENT;
COMPONENT GEN_CLK PORT ( CLK : in std_logic;
RST : in std_logic;
CLK_16 : out std_logic;
CLK_256 : out std_logic);
END COMPONENT;
-- COMPONENT MIXER PORT ( CLK : in std_logic;
-- CS : in std_logic;
-- RST : in std_logic;
-- WR : in std_logic;
-- IN_A : in std_logic;
-- IN_B : in std_logic;
-- IN_C : in std_logic;
-- IN_NOISE : in std_logic;
-- DATA : in std_logic_vector(5 downto 0);
-- OUT_A : out std_logic;
-- OUT_B : out std_logic;
-- OUT_C : out std_logic );
--END COMPONENT;
COMPONENT GEN_ENV PORT ( CLK_ENV : in std_logic;
DATA : in std_logic_vector(3 downto 0);
RST_ENV : in std_logic;
WR : in std_logic;
--CS : in std_logic;
OUT_DATA : inout std_logic_vector(3 downto 0));
END COMPONENT;
COMPONENT MANAGE_AMPLITUDE PORT ( CLK : in std_logic;
CLK_DAC : in std_logic;
CLK_TONE : in std_logic;
CLK_NOISE : in std_logic;
RST : in std_logic;
CLK_TONE_ENA : in std_logic;
CLK_NOISE_ENA : in std_logic;
AMPLITUDE : in std_logic_vector(4 downto 0);
AMPLITUDE_E : in std_logic_vector(3 downto 0);
OUT_DAC : out std_logic );
END COMPONENT;
--COMPONENT IOBUF_F_12 port ( O : out std_logic;
-- IO : inout std_logic;
-- I : in std_logic;
-- T : in std_logic );
--END COMPONENT;
--COMPONENT OBUF_F_12 port ( O : out std_logic;
-- IO : inout std_logic;
-- I : in std_logic;
-- T : in std_logic );
--END COMPONENT;
--component OBUF_F_24
--port (
-- I : in std_logic;
-- O : out std_logic );
--end component;
BEGIN
U_TRAIT : PROCESS(CLOCK, RESET, BC1, BC2, BDIR, REG_ADDR, DATA_IN)
BEGIN
if (RESET = '1') then
WR <= '0';
R0 <= "00000000";
R1 <= "00000000";
R2 <= "00000000";
R3 <= "00000000";
R4 <= "00000000";
R5 <= "00000000";
R6 <= "00000000";
R7 <= "00000000";
R8 <= "00000000";
R9 <= "00000000";
R10 <= "00000000";
R11 <= "00000000";
R12 <= "00000000";
R13 <= "00000000";
IOA <= "00000000";
IOB <= "00000000";
DATA_OUT <= "00000000";
RST_ENV <= '1';
else
if rising_edge(CLOCK) then -- edge clock
-- READ FROM REGISTER
RST_ENV <= '0';
if ((BDIR = '0') and (BC2 = '1') and (BC1 = '1')) then
CASE REG_ADDR is
WHEN "0000" => DATA_OUT <= R0;
WHEN "0001" => DATA_OUT <= R1;
WHEN "0010" => DATA_OUT <= R2;
WHEN "0011" => DATA_OUT <= R3;
WHEN "0100" => DATA_OUT <= R4;
WHEN "0101" => DATA_OUT <= R5;
WHEN "0110" => DATA_OUT <= R6;
WHEN "0111" => DATA_OUT <= R7;
WHEN "1000" => DATA_OUT <= R8;
WHEN "1001" => DATA_OUT <= R9;
WHEN "1010" => DATA_OUT <= R10;
WHEN "1011" => DATA_OUT <= R11;
WHEN "1100" => DATA_OUT <= R12;
WHEN "1101" => DATA_OUT <= R13;
WHEN "1110" => DATA_OUT <= IOA;
WHEN "1111" => DATA_OUT <= IOB;
WHEN OTHERS => NULL;
END CASE;
WR <= '0';
else
DATA_OUT <= "00000000";
WR <= '0';
end if;
end if;
end if;
-- LATCH WHAT REGISTER
if ((BDIR = '1') and (BC2 = '1') and (BC1 = '1')) then
REG_ADDR <= DATA_IN(3 downto 0);
WR <= '0';
end if;
-- WRITE TO REGISTER OR IOA/IOB
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0')) then WR <= '1'; end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0000") ) then R0 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0001") ) then R1 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0010") ) then R2 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0011") ) then R3 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0100") ) then R4 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0101") ) then R5 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0110") ) then R6 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0111") ) then R7 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1000") ) then R8 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1001") ) then R9 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1010") ) then R10 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1011") ) then R11 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1100") ) then R12 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1101") ) then R13 <= DATA_IN; RST_ENV <= '1'; end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1110") ) then IOA <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1111") ) then IOB <= DATA_IN;end if;
end PROCESS;
URA: PROCESS(REG_ADDR, RESET)
BEGIN
if (RESET = '1') then
BUS_CS <= "0000000000000000";
else
case REG_ADDR is
when "0000" => BUS_CS <= "0000000000000001";
when "0001" => BUS_CS <= "0000000000000010";
when "0010" => BUS_CS <= "0000000000000100";
when "0011" => BUS_CS <= "0000000000001000";
when "0100" => BUS_CS <= "0000000000010000";
when "0101" => BUS_CS <= "0000000000100000";
when "0110" => BUS_CS <= "0000000001000000";
when "0111" => BUS_CS <= "0000000010000000";
when "1000" => BUS_CS <= "0000000100000000";
when "1001" => BUS_CS <= "0000001000000000";
when "1010" => BUS_CS <= "0000010000000000";
when "1011" => BUS_CS <= "0000100000000000";
when "1100" => BUS_CS <= "0001000000000000";
when "1101" => BUS_CS <= "0010000000000000";
when "1110" => BUS_CS <= "0100000000000000";
when "1111" => BUS_CS <= "1000000000000000";
when others => NULL;
end case;
end if;
END PROCESS;
-- Instantiation of sub_level modules
UCLK : GEN_CLK PORT MAP( CLK => CLOCK,
RST => RESET,
CLK_16 => CLK_16,
CLK_256 => CLK_256
);
UTONE_A : TONE_GENERATOR PORT MAP( CLK => CLOCK,
--CLK_TONE => CLK_16,
RST => RESET,
WR => WR,
--CS_COARSE => BUS_CS(1),
--CS_FINE => BUS_CS(0),
DATA_COARSE => R1,
DATA_FINE => R0,
OUT_TONE => CLK_A);
UTONE_B : TONE_GENERATOR PORT MAP( CLK => CLOCK,
--CLK_TONE => CLK_16,
RST => RESET,
WR => WR,
--CS_COARSE => BUS_CS(3),
--CS_FINE => BUS_CS(2),
DATA_COARSE => R3,
DATA_FINE => R2,
OUT_TONE => CLK_B);
UTONE_C : TONE_GENERATOR PORT MAP( CLK => CLOCK,
--CLK_TONE => CLK_16,
RST => RESET,
WR => WR,
--CS_COARSE => BUS_CS(5),
--CS_FINE => BUS_CS(4),
DATA_COARSE => R5,
DATA_FINE => R4,
OUT_TONE => CLK_C);
UTONE_NOISE : NOISE_GENERATOR PORT MAP( CLK => CLK_16,
RST => RESET,
--WR => WR,
--CS => BUS_CS(6),
DATA => R6(4 downto 0),
CLK_N => CLK_N);
UTONE_ENV : TONE_GENERATOR PORT MAP( CLK => CLK_16,
--CLK => CLOCK,
--CLK_TONE => CLK_256,
RST => RESET,
WR => WR,
--CS_COARSE => BUS_CS(12),
--CS_FINE => BUS_CS(11),
DATA_COARSE => R12,
DATA_FINE => R11,
OUT_TONE => CLK_E);
--UMIXER : MIXER PORT MAP ( CLK => CLOCK,
-- CS => BUS_CS(7),
-- RST => RESET,
-- WR => WR,
-- IN_A => CLK_A,
-- IN_B => CLK_B,
-- IN_C => CLK_C,
-- IN_NOISE => CLK_N,
-- DATA => R7(5 downto 0),
-- OUT_A => CLK_TONE_A,
-- OUT_B => CLK_TONE_B,
-- OUT_C => CLK_TONE_C);
UGenEnv : GEN_ENV PORT MAP( CLK_ENV => CLK_E,
--CS => BUS_CS(13),
DATA => R13(3 downto 0),
RST_ENV => RST_ENV,
WR => WR,
OUT_DATA => OUT_AMPL_E);
UManAmpA : MANAGE_AMPLITUDE PORT MAP ( CLK => CLOCK,
CLK_DAC => CLOCK_DAC,
CLK_TONE => CLK_A, --CLK_TONE_A,
CLK_NOISE => CLK_N,
RST => RESET,
CLK_TONE_ENA => R7(0),
CLK_NOISE_ENA => R7(3),
AMPLITUDE => R8(4 downto 0),
AMPLITUDE_E => OUT_AMPL_E(3 downto 0),
OUT_DAC => IAnalogA );
UManAmpB : MANAGE_AMPLITUDE PORT MAP ( CLK => CLOCK,
CLK_DAC => CLOCK_DAC,
CLK_TONE => CLK_B, --CLK_TONE_B,
CLK_NOISE => CLK_N,
RST => RESET,
CLK_TONE_ENA => R7(1),
CLK_NOISE_ENA => R7(4),
AMPLITUDE => R9(4 downto 0),
AMPLITUDE_E => OUT_AMPL_E(3 downto 0),
OUT_DAC => IAnalogB );
UManAmpC : MANAGE_AMPLITUDE PORT MAP ( CLK => CLOCK,
CLK_DAC => CLOCK_DAC,
CLK_TONE => CLK_C, --CLK_TONE_C,
CLK_NOISE => CLK_N,
RST => RESET,
CLK_TONE_ENA => R7(2),
CLK_NOISE_ENA => R7(5),
AMPLITUDE => R10(4 downto 0),
AMPLITUDE_E => OUT_AMPL_E(3 downto 0),
OUT_DAC => IAnalogC );
--PAD_ANALOGA : OBUF_F_24 port map( I => IAnalogA, O => AnalogA);
--PAD_ANALOGB : OBUF_F_24 port map( I => IAnalogB, O => AnalogB);
--PAD_ANALOGC : OBUF_F_24 port map( I => IAnalogC, O => AnalogC);
AnalogA <= IAnalogA;
AnalogB <= IAnalogB;
AnalogC <= IAnalogC;
end Behavioral;

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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`define BUILD_DATE "180506"
`define BUILD_TIME "191822"

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Oric Atmos_MiST/rtl/ctrlseq.vhd Normal file
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--
-- ctrlseq.vhd
--
-- Manage internal register
--
-- Copyright (C)2001 - 2005 SEILEBOST
-- All rights reserved.
--
-- $Id: ctrlseq.vhd, v0.01 2005/01/01 00:00:00 SEILEBOST $
--
-- TODO :
-- Remark :
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
--use IEEE.std_logic_arith.all;
--use IEEE.numeric_std.all;
entity ctrlseq is
port ( RESETn : in std_logic; -- RESET
CLK_24 : in std_logic; -- 2 x CLOCK SYSTEM
TXTHIR_DEC : in std_logic; -- TeXT HIRes DECode signal
isAttrib : in std_logic; -- Is a attribute byte
iRW : in std_logic; -- Read/Write signal from CPU
CSRAMn : in std_logic; -- SELECT RAM (Active low)
-- OUTPUTS
CLK_1_CPU : out std_logic; -- CLK for CPU
CLK_4 : out std_logic; -- CLK internal for VIA
CLK_6 : out std_logic; -- CLK internal for video generation
VA1L : out std_logic; -- VIDEO ADDRESS PHASE1 LATCH
VA1R : out std_logic; -- VIDEO ADDRESS PHASE1 ROW
VA1C : out std_logic; -- VIDEO ADDRESS PHASE1 COLUMN
VA2L : out std_logic; -- VIDEO ADDRESS PHASE2 LATCH
VA2R : out std_logic; -- VIDEO ADDRESS PHASE2 ROW
VA2C : out std_logic; -- VIDEO ADDRESS PHASE2 COLUMN
BAC : out std_logic; -- BUS ADDRESS COLUMN
BAL : out std_logic; -- BUS ADDRESS LATCH
RAS : out std_logic; -- RAS FOR DYNAMIC RAM
CAS : out std_logic; -- CAS FOR DYNAMIC RAM
MUX : out std_logic; -- MUX
oRW : out std_logic; -- Output Read/Write
ATTRIB_DEC : out std_logic; -- Decode attribute
LD_REG_0 : out std_logic; -- Initialization of video register
LD_REG : out std_logic; -- Load data into video register
LDFROMBUS : out std_logic; -- Load data from data bus
DATABUS_EN : out std_logic; -- Enable data bus
-- ajout du 09/02/09
BAOE : out std_logic; -- Output enable for ram/rom
-- ajout du 03/04/09
SRAM_CE : out std_logic; -- Chip select enable for SRAM
SRAM_OE : out std_logic; -- Ouput enable for SRAM
SRAM_WE : out std_logic; -- Write enable for SRAM =1 for a read cycle
LATCH_SRAM : out std_logic; -- Latch data from SRAM for cpu
-- FOR DEBUG/TESTBENCH
c0_out : out std_logic;
c1_out : out std_logic;
c2_out : out std_logic;
c3_out : out std_logic;
c4_out : out std_logic;
c5_out : out std_logic;
c6_out : out std_logic;
c7_out : out std_logic;
CLK_12 : out std_logic;
TB_CPT : out std_logic_vector(4 downto 0)
);
end entity ctrlseq;
architecture ctrlseq_arch of ctrlseq is
signal lCPT_GEN : std_logic_vector(4 downto 0); -- counter
signal lstate : std_logic_vector(23 downto 0); -- states
signal lreload : std_logic; -- to reload null value to lCPT_GEN
signal lld_reg_p : std_logic; -- to load value into register for VIDEO
signal c_ras : std_logic; -- RAS
signal c_cas : std_logic; -- CAS
signal c_mux : std_logic; -- MUX
signal c_clk_cpu : std_logic; -- CLK_CPU
-- Phase P0
signal c_0 : std_logic; -- state number 0
signal c_1 : std_logic; -- state number 1
signal c_2 : std_logic; -- state number 2
signal c_3 : std_logic; -- state number 3
signal c_4 : std_logic; -- state number 4
signal c_5 : std_logic; -- state number 5
signal c_6 : std_logic; -- state number 6
signal c_7 : std_logic; -- state number 7
-- Phase P1
signal c_8 : std_logic; -- state number 8
signal c_9 : std_logic; -- state number 9
signal c_10 : std_logic; -- state number 10
signal c_11 : std_logic; -- state number 11
signal c_12 : std_logic; -- state number 12
signal c_13 : std_logic; -- state number 13
signal c_14 : std_logic; -- state number 14
signal c_15 : std_logic; -- state number 15
-- Phase P2
signal c_16 : std_logic; -- state number 16
signal c_17 : std_logic; -- state number 17
signal c_18 : std_logic; -- state number 18
signal c_19 : std_logic; -- state number 19
signal c_20 : std_logic; -- state number 20
signal c_21 : std_logic; -- state number 21
signal c_22 : std_logic; -- state number 22
signal c_23 : std_logic; -- state number 23
signal p_0 : std_logic; -- phase number 0
signal p_1 : std_logic; -- phase number 1
signal p_2 : std_logic; -- phase number 2
-- Constants for states
-- Phase P0
constant cd_step_0 : integer :=0;
constant cd_step_1 : integer :=1;
constant cd_step_2 : integer :=2;
constant cd_step_3 : integer :=3;
constant cd_step_4 : integer :=4;
constant cd_step_5 : integer :=5;
constant cd_step_6 : integer :=6;
constant cd_step_7 : integer :=7;
-- Phase P1
constant cd_step_8 : integer :=8;
constant cd_step_9 : integer :=9;
constant cd_step_10: integer :=10;
constant cd_step_11: integer :=11;
constant cd_step_12: integer :=12;
constant cd_step_13: integer :=13;
constant cd_step_14: integer :=14;
constant cd_step_15: integer :=15;
-- Phase P2
constant cd_step_16: integer :=16;
constant cd_step_17: integer :=17;
constant cd_step_18: integer :=18;
constant cd_step_19: integer :=19;
constant cd_step_20: integer :=20;
constant cd_step_21: integer :=21;
constant cd_step_22: integer :=22;
constant cd_step_23: integer :=23;
begin
-- Increment counter
U_TB_CPT: PROCESS (RESETn, CLK_24)
BEGIN
if (RESETn = '0') then
lCPT_GEN <= "00000";
elsif falling_edge(clk_24) then
if (lreload = '1') then
lCPT_GEN <= "00000";
else
lCPT_GEN <= lCPT_GEN + "00001";
end if;
end if;
END PROCESS;
lreload <= '1' when lCPT_GEN = "10111" else '0';
-- Manage states
U_SM_GEST: PROCESS(lCPT_GEN)
BEGIN
lstate <= "000000000000000000000000";
case lCPT_GEN(4 downto 0) is
-- Phase P0
when "00000" => lstate(cd_step_0) <= '1';
when "00001" => lstate(cd_step_1) <= '1';
when "00010" => lstate(cd_step_2) <= '1';
when "00011" => lstate(cd_step_3) <= '1';
when "00100" => lstate(cd_step_4) <= '1';
when "00101" => lstate(cd_step_5) <= '1';
when "00110" => lstate(cd_step_6) <= '1';
when "00111" => lstate(cd_step_7) <= '1';
-- Phase P1
when "01000" => lstate(cd_step_8) <= '1';
when "01001" => lstate(cd_step_9) <= '1';
when "01010" => lstate(cd_step_10) <= '1';
when "01011" => lstate(cd_step_11) <= '1';
when "01100" => lstate(cd_step_12) <= '1';
when "01101" => lstate(cd_step_13) <= '1';
when "01110" => lstate(cd_step_14) <= '1';
when "01111" => lstate(cd_step_15) <= '1';
-- Phase P2
when "10000" => lstate(cd_step_16) <= '1';
when "10001" => lstate(cd_step_17) <= '1';
when "10010" => lstate(cd_step_18) <= '1';
when "10011" => lstate(cd_step_19) <= '1';
when "10100" => lstate(cd_step_20) <= '1';
when "10101" => lstate(cd_step_21) <= '1';
when "10110" => lstate(cd_step_22) <= '1';
when "10111" => lstate(cd_step_23) <= '1';
when others => null;
end case;
END PROCESS;
-- Assign states
-- Phase P0
c_0 <= lstate(cd_step_0);
c_1 <= lstate(cd_step_1);
c_2 <= lstate(cd_step_2);
c_3 <= lstate(cd_step_3);
c_4 <= lstate(cd_step_4);
c_5 <= lstate(cd_step_5);
c_6 <= lstate(cd_step_6);
c_7 <= lstate(cd_step_7);
-- Phase P1
c_8 <= lstate(cd_step_8);
c_9 <= lstate(cd_step_9);
c_10 <= lstate(cd_step_10);
c_11 <= lstate(cd_step_11);
c_12 <= lstate(cd_step_12);
c_13 <= lstate(cd_step_13);
c_14 <= lstate(cd_step_14);
c_15 <= lstate(cd_step_15);
-- Phase P2
c_16 <= lstate(cd_step_16);
c_17 <= lstate(cd_step_17);
c_18 <= lstate(cd_step_18);
c_19 <= lstate(cd_step_19);
c_20 <= lstate(cd_step_20);
c_21 <= lstate(cd_step_21);
c_22 <= lstate(cd_step_22);
c_23 <= lstate(cd_step_23);
-- Three phases
p_0 <= NOT lCPT_GEN(4) and NOT lCPT_GEN(3); -- 00
p_1 <= NOT lCPT_GEN(4) and lCPT_GEN(3); -- 01
p_2 <= lCPT_GEN(4) and NOT lCPT_GEN(3); -- 10
--------------------------------
-- GENERATION DE LA CLOCK CPU --
--------------------------------
CLK_1_CPU <= p_2;
---------------------------------
-- GESTION DE LA RAM DYNAMIQUE --
---------------------------------
ras <= c_2 or c_3 or c_4 or c_5 or c_10 or c_11 or c_12 or c_13 or c_18 or c_19 or c_20 or c_20;
cas <= not (c_2 or c_3) and not (c_10 or c_11) and not (c_18 or c_19);
-- Mux permet de slectionner soit l'adresse haute d'une adresse cpu
-- soit l'adresse haute d'une adresse ula
mux <= '1' when ((c_1 = '1' or c_2 = '1') and p_2 = '1') else '0';
oRW <= iRW and p_2;
---------------------------------
-- GESTION DE LA RAM STATIQUE --
---------------------------------
SRAM_OE <= not (c_2 or c_3) and not (c_10 or c_11) and not iRW ;
SRAM_CE <= not (c_1 or c_2 or c_3 or c_4) and not (c_9 or c_10 or c_11 or c_12) AND (CSRAMn or not (c_19 or c_20));
SRAM_WE <= CSRAMn or not (c_19 or c_20) or irW;
LATCH_SRAM <= not c_4 and not c_12 and not c_20; -- le 19/12/2011 : Ajout not c_4 and c_12 à not c_20
---------------------
-- GESTION INTERNE --
---------------------
--Generation pour la gestion de l'adresse video 1
VA1L <= '1' when (c_1='1') ELSE '0';
--VA1R <= '1' when (c_1='1' or c_2='1') ELSE '0';
VA1R <= '1' when (p_0='1') ELSE '0';
VA1C <= '1' when (c_3='1' or c_4='1' or c_5='1') ELSE '0';
--Generation pour la gestion de l'adresse video 2
VA2L <= '1' when (c_8='1') ELSE '0';
--VA2R <= '1' when (c_8='1' or c_9='1') ELSE '0';
VA2R <= '1' when (p_1='1') ELSE '0';
VA2C <= '1' when (c_10='1' or c_11='1' or c_12='1') ELSE '0';
--Generation pour la gestion de l'adresse CPU
BAL <= '1' when (c_17='1' or c_18='1' or c_19='1' or c_20='1' or c_21='1' or c_22='1' or c_23='1') ELSE '0';
--Modif. du 22/02/09 BAC <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_2='1' and CSRAMn='0') ELSE '0';
BAC <= '1' when (c_19='1' or c_20='1' or c_21='1') ELSE '0';
-- Ajout du 09/02/09 : output enable pour la rom/ram lors de l'adressage par le CPU
BAOE <= '1' when (c_18='1') ELSE '0';
--Pour la partie video
-- 27/07/09 lld_reg_p <= NOT isAttrib and c_7 and NOT TXTHIR_DEC;
-- 27/07/09 c_7 aurait du tre c_15 en ram dynamique
-- 27/07/09 en ram statique :
-- 11/11/09 Modif c_10 en c_11
lld_reg_p <= not isAttrib and c_11 and NOT TXTHIR_DEC; -- Partie texte
-- 04/12/09 ATTRIB_DEC <= '1' when (isAttrib='1' and c_10='1') ELSE '0';
--ATTRIB_DEC <= '1' when (c_4='1') ELSE '0';
-- 04/12/09 LD_REG_0 <= '1' when (isAttrib='1' and c_15='1') ELSE '0';
--LD_REG_0 <= '1' when (isAttrib='1' and c_11='1' and TXTHIR_DEC = '0') ELSE '0';
-- 05/12/09 LD_REG <= '1' when (lld_reg_p='1' or c_4='1') ELSE '0';
--LD_REG <= '1' when (lld_reg_p='1' or (c_4='1' and TXTHIR_DEC = '0')) ELSE '0';
--DATABUS_EN <= '1' when (lld_reg_p='1' or c_3='1') ELSE '0';
--LDFROMBUS <= '1' when (c_16='1') ELSE '0';
-- 15/12/2009 :
ATTRIB_DEC <= '1' when (c_4='1') ELSE '0';
DATABUS_EN <= '1' when (c_11='1' or c_3='1') ELSE '0';
LD_REG_0 <= '1' when (isAttrib='1' and c_5='1') ELSE '0';
LDFROMBUS <= '1' when ( (isAttrib='0' and c_12='1' and TXTHIR_DEC='0')
or (isAttrib='0' and c_5 ='1' and TXTHIR_DEC='1')
) ELSE '0';
LD_REG <= '1' when (c_15='1') ELSE '0';
-- for TEST BENCH
c0_OUT <= lstate(cd_step_0);
c1_OUT <= lstate(cd_step_1);
c2_OUT <= lstate(cd_step_2);
c3_OUT <= lstate(cd_step_3);
c4_OUT <= lstate(cd_step_4);
c5_OUT <= lstate(cd_step_5);
c6_OUT <= lstate(cd_step_6);
c7_OUT <= lstate(cd_step_7);
TB_CPT <= lCPT_GEN;
CLK_12 <= lCPT_GEN(0);
-- for VIA 6522
CLK_4 <= c_0 or c_1 or c_2
or c_6 or c_7 or c_8
or c_12 or c_13 or c_14
or c_18 or c_19 or c_20;
-- for Video Generation
CLK_6 <= c_0 or c_1 or c_4 or c_5 or c_8 or c_9 or c_12 or c_13 or c_16 or c_17 or c_20 or c_21;
end architecture ctrlseq_arch;

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--
-- ctrlseq.vhd
--
-- Manage internal register
--
-- Copyright (C)2001 - 2005 SEILEBOST
-- All rights reserved.
--
-- $Id: ctrlseq.vhd, v0.01 2005/01/01 00:00:00 SEILEBOST $
--
-- TODO :
-- Remark :
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
--use IEEE.std_logic_arith.all;
--use IEEE.numeric_std.all;
entity ctrlseq is
port ( RESETn : in std_logic; -- RESET
CLK_24 : in std_logic; -- 2 x CLOCK SYSTEM
TXTHIR_DEC : in std_logic; -- TeXT HIRes DECode signal
isAttrib : in std_logic; -- Is a attribute byte
iRW : in std_logic; -- Read/Write signal from CPU
CSRAMn : in std_logic; -- SELECT RAM (Active low)
-- OUTPUTS
CLK_1_CPU : out std_logic; -- CLK for CPU
CLK_4 : out std_logic; -- CLK interne for ram statique
VA1L : out std_logic; -- VIDEO ADDRESS PHASE1 LATCH
VA1R : out std_logic; -- VIDEO ADDRESS PHASE1 ROW
VA1C : out std_logic; -- VIDEO ADDRESS PHASE1 COLUMN
VA2L : out std_logic; -- VIDEO ADDRESS PHASE2 LATCH
VA2R : out std_logic; -- VIDEO ADDRESS PHASE2 ROW
VA2C : out std_logic; -- VIDEO ADDRESS PHASE2 COLUMN
BAC : out std_logic; -- BUS ADDRESS COLUMN
BAL : out std_logic; -- BUS ADDRESS LATCH
RAS : out std_logic; -- RAS FOR DYNAMIC RAM
CAS : out std_logic; -- CAS FOR DYNAMIC RAM
MUX : out std_logic; -- MUX
oRW : out std_logic; -- Output Read/Write
ATTRIB_DEC : out std_logic; -- Decode attribute
LD_REG_0 : out std_logic; -- Initialization of video register
LD_REG : out std_logic; -- Load data into video register
LDFROMBUS : out std_logic; -- Load data from data bus
DATABUS_EN : out std_logic; -- Enable data bus
-- ajout du 09/02/09
BAOE : out std_logic; -- Output enable for ram/rom
-- FOR DEBUG/TESTBENCH
c0_out : out std_logic;
c1_out : out std_logic;
c2_out : out std_logic;
c3_out : out std_logic;
c4_out : out std_logic;
c5_out : out std_logic;
c6_out : out std_logic;
c7_out : out std_logic;
CLK_12 : out std_logic;
TB_CPT : out std_logic_vector(4 downto 0)
);
end entity ctrlseq;
architecture ctrlseq_arch of ctrlseq is
signal lCPT_GEN : std_logic_vector(4 downto 0); -- counter
signal lstate : std_logic_vector(7 downto 0); -- states
signal lreload : std_logic; -- to reload null value to lCPT_GEN
signal lld_reg_p : std_logic; -- to load value into register for VIDEO
signal c_ras : std_logic; -- RAS
signal c_cas : std_logic; -- CAS
signal c_mux : std_logic; -- MUX
signal c_clk_cpu : std_logic; -- CLK_CPU
signal c_0 : std_logic; -- state number 0
signal c_1 : std_logic; -- state number 1
signal c_2 : std_logic; -- state number 2
signal c_3 : std_logic; -- state number 3
signal c_4 : std_logic; -- state number 4
signal c_5 : std_logic; -- state number 5
signal c_6 : std_logic; -- state number 6
signal c_7 : std_logic; -- state number 7
signal p_0 : std_logic; -- phase number 0
signal p_1 : std_logic; -- phase number 1
signal p_2 : std_logic; -- phase number 2
-- Constants for states
constant cd_step_0 : integer :=0;
constant cd_step_1 : integer :=1;
constant cd_step_2 : integer :=2;
constant cd_step_3 : integer :=3;
constant cd_step_4 : integer :=4;
constant cd_step_5 : integer :=5;
constant cd_step_6 : integer :=6;
constant cd_step_7 : integer :=7;
begin
-- Increment counter
U_TB_CPT: PROCESS (RESETn, CLK_24)
BEGIN
if (RESETn = '0') then
lCPT_GEN <= "00000";
elsif falling_edge(clk_24) then
if (lreload = '1') then
lCPT_GEN <= "00000";
else
lCPT_GEN <= lCPT_GEN + "00001";
end if;
end if;
END PROCESS;
lreload <= '1' when lCPT_GEN = "10111" else '0';
-- Manage states
U_SM_GEST: PROCESS(lCPT_GEN)
BEGIN
lstate <= "00000000";
case lCPT_GEN(2 downto 0) is
when "000" => lstate(cd_step_0) <= '1';
when "001" => lstate(cd_step_1) <= '1';
when "010" => lstate(cd_step_2) <= '1';
when "011" => lstate(cd_step_3) <= '1';
when "100" => lstate(cd_step_4) <= '1';
when "101" => lstate(cd_step_5) <= '1';
when "110" => lstate(cd_step_6) <= '1';
when "111" => lstate(cd_step_7) <= '1';
when others => null;
end case;
END PROCESS;
-- Assign states
c_0 <= lstate(cd_step_0);
c_1 <= lstate(cd_step_1);
c_2 <= lstate(cd_step_2);
c_3 <= lstate(cd_step_3);
c_4 <= lstate(cd_step_4);
c_5 <= lstate(cd_step_5);
c_6 <= lstate(cd_step_6);
c_7 <= lstate(cd_step_7);
-- Three phases
p_0 <= NOT lCPT_GEN(4) and NOT lCPT_GEN(3); -- 00
p_1 <= NOT lCPT_GEN(4) and lCPT_GEN(3); -- 01
p_2 <= lCPT_GEN(4) and NOT lCPT_GEN(3); -- 10
--------------------------------
-- GENERATION DE LA CLOCK CPU --
--------------------------------
CLK_1_CPU <= p_2;
---------------------------------
-- GESTION DE LA RAM DYNAMIQUE --
---------------------------------
ras <= c_2 or c_3 or c_4 or c_5;
cas <= not (c_2 or c_3) and (not p_2 or CSRAMn);
-- Mux permet de sélectionner soit l'adresse haute d'une adresse cpu
-- soit l'adresse haute d'une adresse ula
mux <= '1' when ((c_1 = '1' or c_2 = '1') and p_2 = '1') else '0';
oRW <= iRW and p_2;
---------------------
-- GESTION INTERNE --
---------------------
--Generation pour la gestion de l'adresse video 1
VA1L <= '1' when (c_1='1' and p_0='1') ELSE '0';
VA1R <= '1' when ((c_1='1' or c_2='1') and p_0='1') ELSE '0';
VA1C <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_0='1') ELSE '0';
--Generation pour la gestion de l'adresse video 2
VA2L <= '1' when (c_1='1' and p_1='1') ELSE '0';
VA2R <= '1' when ((c_1='1' or c_2='1') and p_1='1') ELSE '0';
VA2C <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_1='1') ELSE '0';
--Generation pour la gestion de l'adresse CPU
BAL <= '1' when (c_1='1' and p_2='1') ELSE '0';
--Modif. du 22/02/09 BAC <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_2='1' and CSRAMn='0') ELSE '0';
BAC <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_2='1') ELSE '0';
-- Ajout du 09/02/09 : output enable pour la rom/ram lors de l'adressage par le CPU
BAOE <= '1' when (not(c_0='1' or c_1 ='1') and p_2='1') ELSE '0';
--Pour la partie video
lld_reg_p <= NOT isAttrib and (c_7 and p_1) and NOT TXTHIR_DEC;
ATTRIB_DEC <= '1' when (isAttrib='1' and c_2='1' and p_1='1') ELSE '0';
LD_REG_0 <= '1' when (isAttrib='1' and c_7='1' and p_1='1') ELSE '0';
LD_REG <= '1' when (lld_reg_p='1' or (c_7='1' and p_0='1')) ELSE '0';
DATABUS_EN <= '1' when (lld_reg_p='1' or (c_7='1' and p_0='1')) ELSE '0';
LDFROMBUS <= '1' when (c_0='1' and p_2='1') ELSE '0';
-- for TEST BENCH
c0_OUT <= lstate(cd_step_0);
c1_OUT <= lstate(cd_step_1);
c2_OUT <= lstate(cd_step_2);
c3_OUT <= lstate(cd_step_3);
c4_OUT <= lstate(cd_step_4);
c5_OUT <= lstate(cd_step_5);
c6_OUT <= lstate(cd_step_6);
c7_OUT <= lstate(cd_step_7);
TB_CPT <= lCPT_GEN;
CLK_12 <= lCPT_GEN(0);
-- for ram statique
CLK_4 <= c_6 or c_7;
end architecture ctrlseq_arch;

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--
-- DAC.vhd
--
-- Digital to analog convertor.
--
-- Copyright (C)2001 SEILEBOST
-- All rights reserved.
--
-- $Id: DAC.vhd, v0.2 2001/11/02 00:00:00 SEILEBOST $
--
-- from XAPP154.pdf & XAPP154.ZIP (XILINX APPLICATION)
--
-- DAC 8 Bits ( method : sigma delta)
-- 2^N clock to convert with N = width of input
-- Ex : Bus 8 bits => 256 CLOCK master to convert an value.
-- Theorem Shannon : 2 x Fmax x 256 =< 16 MHz => Fmax = 31250 Hz
-- band of sound : 0 -> 20000 Hz : Ok !!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DAC is
Port ( CLK_DAC : in std_logic;
RST : in std_logic;
IN_DAC : in std_logic_vector(7 downto 0);
OUT_DAC : out std_logic );
end DAC;
architecture Behavioral of DAC is
signal DeltaAdder : std_logic_vector(9 downto 0);
signal SigmaAdder : std_logic_vector(9 downto 0);
signal SigmaLatch : std_logic_vector(9 downto 0);
signal DeltaB : std_logic_vector(9 downto 0);
begin
PROCESS(SigmaLatch, DeltaB)
BEGIN
DeltaB <= TRANSPORT ( SigmaLatch(9) & SigmaLatch(9) & "00000000");
END PROCESS;
PROCESS(IN_DAC, DeltaB, DeltaAdder)
BEGIN
DeltaAdder <= IN_DAC + DeltaB;
END PROCESS;
PROCESS(DeltaAdder, SigmaLatch)
BEGIN
SigmaAdder <= DeltaAdder + SigmaLatch;
END PROCESS;
PROCESS(CLK_DAC, RST)
BEGIN
if (RST = '1') then
SigmaLatch <= "0100000000";
OUT_DAC <= '1';
elsif (CLK_DAC'event and CLK_DAC = '1') then
SigmaLatch <= SigmaAdder;
OUT_DAC <= SigmaLatch(9);
end if;
END PROCESS;
end Behavioral;

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--
-- GEN_CLK.vhd
--
-- GENERATOR of CLOCK.
--
-- Copyright (C)2001 SEILEBOST
-- All rights reserved.
--
-- $Id: GEN_CLK.vhd, v0.42 2002/01/03 00:00:00 SEILEBOST $
--
-- Generate secondary CLK from CLK_MASTER
-- CLK : Clock Master, 16 MHz
-- CLK_16 : for the tone generator,
-- CLK_256 : for the envelope generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity GEN_CLK is
Port ( CLK : in std_logic;
RST : in std_logic;
CLK_16 : out std_logic;
CLK_256 : out std_logic
);
end GEN_CLK;
architecture Behavioral of GEN_CLK is
SIGNAL COUNT : std_logic_vector(7 downto 0);
begin
PROCESS(CLK, RST)
BEGIN
if (RST = '1') then
COUNT <= (OTHERS => '0');
elsif (CLK'event and CLK = '1') then
COUNT <= COUNT + 1;
CLK_16 <= COUNT(3);
CLK_256 <= COUNT(7);
end if;
END PROCESS;
end Behavioral;

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--
-- GEN_ENV.vhd
--
-- GENERATOR of ENVELOPE.
--
-- Copyright (C)2001-2010 SEILEBOST
-- All rights reserved.
--
-- $Id: GEN_ENV.vhd, v0.50 2010/01/19 00:00:00 SEILEBOST $
--
-- NO BUGS
-- NEARLY TESTED
--
-- Revision list
--
-- v0.4 2001/11/21 : Modification
-- v0.46 2010/01/06 : Modification du générateur d'enveloppe
-- et de fréquence
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gen_env is
Port ( CLK_ENV : in std_logic;
DATA : in std_logic_vector(3 downto 0);
RST_ENV : in std_logic;
WR : in std_logic;
--CS : in std_logic;
OUT_DATA : inout std_logic_vector(3 downto 0) );
end gen_env;
architecture Behavioral of gen_env is
SIGNAL DIR : std_logic; -- direction
SIGNAL HOLD : std_logic; -- continue the sound
begin
PROCESS(CLK_ENV, RST_ENV, DATA, WR)
variable isMin : boolean;
variable isNearlyMin : boolean;
variable isNearlyMax : boolean;
variable isMax : boolean;
BEGIN
if (RST_ENV = '1') then -- Reset : to load the good value to generate enveloppe
if (DATA(2) = '0') then -- front initial : 0 = descendant et 1 = montant
OUT_DATA <= "1111";
DIR <= '0';
else
OUT_DATA <= "0000";
DIR <= '1';
end if;
HOLD <= '0';
elsif (CLK_ENV'event and CLK_ENV = '1') then -- edge clock
-- To simply the written code !
isMin := (OUT_DATA = "00000");
isNearlyMin := (OUT_DATA = "00001");
isNearlyMax := (OUT_DATA = "11110");
isMax := (OUT_DATA = "11111");
-- To manage the next value
if (HOLD = '0') then
if (DIR = '0') then
OUT_DATA <= OUT_DATA - 1;
else
OUT_DATA <= OUT_DATA + 1;
end if;
end if;
-- To generate the shape of envelope
if (DATA(3) = '0') then
if (DIR = '0') then
if (isNearlyMin) then
HOLD <= '1';
end if;
else
if (isMax) then
HOLD <= '1'; -- Astuce : il faut que OUT_DATE = "0000" au prochain tick donc comparaison de la sortie sur "1111" car incrementation automatique
end if;
end if;
else
if (DATA(0) = '1') then -- hold = 1
if (DIR = '0') then -- down
if (DATA(1) = '1') then -- alt
if isMin then HOLD <= '1'; end if;
else
if isNearlyMin then HOLD <= '1'; end if;
end if;
else
if (DATA(1) = '1') then -- alt
if isMax then HOLD <= '1'; end if;
else
if isNearlyMax then HOLD <= '1'; end if;
end if;
end if;
elsif (DATA(1) = '1') then -- alternate
if (DIR = '0') then -- down
if isNearlyMin then HOLD <= '1'; end if;
if isMin then HOLD <= '0'; DIR <= '1'; end if;
else
if isNearlyMax then HOLD <= '1'; end if;
if isMax then HOLD <= '0'; DIR <= '0'; end if;
end if;
end if;
end if;
end if; -- fin elsif
END PROCESS;
end Behavioral;

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//
//
// Copyright (c) 2012-2013 Ludvig Strigeus
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <=1024 ? 9 : 10 )
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
wire [DWIDTH:0] out[2];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule
module hq2x_out #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input [1:0] rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input [1:0] wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
wire [DWIDTH:0] out[4];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
endmodule
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
input clock,
input [DWIDTH:0] data,
input [AWIDTH:0] rdaddress,
input [AWIDTH:0] wraddress,
input wren,
output [DWIDTH:0] q
);
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b(q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({(DWIDTH+1){1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = NUMWORDS,
altsyncram_component.numwords_b = NUMWORDS,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = AWIDTH+1,
altsyncram_component.widthad_b = AWIDTH+1,
altsyncram_component.width_a = DWIDTH+1,
altsyncram_component.width_b = DWIDTH+1,
altsyncram_component.width_byteena_a = 1;
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////////
module DiffCheck
(
input [17:0] rgb1,
input [17:0] rgb2,
output result
);
wire [5:0] r = rgb1[5:1] - rgb2[5:1];
wire [5:0] g = rgb1[11:7] - rgb2[11:7];
wire [5:0] b = rgb1[17:13] - rgb2[17:13];
wire [6:0] t = $signed(r) + $signed(b);
wire [6:0] gx = {g[5], g};
wire [7:0] y = $signed(t) + $signed(gx);
wire [6:0] u = $signed(r) - $signed(b);
wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
// if y is inside (-24..24)
wire y_inside = (y < 8'h18 || y >= 8'he8);
// if u is inside (-4, 4)
wire u_inside = (u < 7'h4 || u >= 7'h7c);
// if v is inside (-6, 6)
wire v_inside = (v < 8'h6 || v >= 8'hfA);
assign result = !(y_inside && u_inside && v_inside);
endmodule
module InnerBlend
(
input [8:0] Op,
input [5:0] A,
input [5:0] B,
input [5:0] C,
output [5:0] O
);
function [8:0] mul6x3;
input [5:0] op1;
input [2:0] op2;
begin
mul6x3 = 9'd0;
if(op2[0]) mul6x3 = mul6x3 + op1;
if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
end
endfunction
wire OpOnes = Op[4];
wire [8:0] Amul = mul6x3(A, Op[7:5]);
wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
wire [8:0] At = Amul;
wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
wire [9:0] Res = {At, 1'b0} + Bt + Ct;
assign O = Op[8] ? A : Res[9:4];
endmodule
module Blend
(
input [5:0] rule,
input disable_hq2x,
input [17:0] E,
input [17:0] A,
input [17:0] B,
input [17:0] D,
input [17:0] F,
input [17:0] H,
output [17:0] Result
);
reg [1:0] input_ctrl;
reg [8:0] op;
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
localparam AB = 2'b00;
localparam AD = 2'b01;
localparam DB = 2'b10;
localparam BD = 2'b11;
wire is_diff;
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
always @* begin
case({!is_diff, rule[5:2]})
1,17: {op, input_ctrl} = {BLEND1, AB};
2,18: {op, input_ctrl} = {BLEND1, DB};
3,19: {op, input_ctrl} = {BLEND1, BD};
4,20: {op, input_ctrl} = {BLEND2, DB};
5,21: {op, input_ctrl} = {BLEND2, AB};
6,22: {op, input_ctrl} = {BLEND2, AD};
8: {op, input_ctrl} = {BLEND0, 2'bxx};
9: {op, input_ctrl} = {BLEND0, 2'bxx};
10: {op, input_ctrl} = {BLEND0, 2'bxx};
11: {op, input_ctrl} = {BLEND1, AB};
12: {op, input_ctrl} = {BLEND1, AB};
13: {op, input_ctrl} = {BLEND1, AB};
14: {op, input_ctrl} = {BLEND1, DB};
15: {op, input_ctrl} = {BLEND1, BD};
24: {op, input_ctrl} = {BLEND2, DB};
25: {op, input_ctrl} = {BLEND5, DB};
26: {op, input_ctrl} = {BLEND6, DB};
27: {op, input_ctrl} = {BLEND2, DB};
28: {op, input_ctrl} = {BLEND4, DB};
29: {op, input_ctrl} = {BLEND5, DB};
30: {op, input_ctrl} = {BLEND3, BD};
31: {op, input_ctrl} = {BLEND3, DB};
default: {op, input_ctrl} = 11'bx;
endcase
// Setting op[8] effectively disables HQ2X because blend will always return E.
if (disable_hq2x) op[8] = 1;
end
// Generate inputs to the inner blender. Valid combinations.
// 00: E A B
// 01: E A D
// 10: E D B
// 11: E B D
wire [17:0] Input1 = E;
wire [17:0] Input2 = !input_ctrl[1] ? A :
!input_ctrl[0] ? D : B;
wire [17:0] Input3 = !input_ctrl[0] ? B : D;
InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]);
InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]);
InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
(
input clk,
input ce_x4,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input [1:0] read_y,
input [AWIDTH+1:0] read_x,
output [DWIDTH:0] outpixel
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
localparam DWIDTH = HALF_DEPTH ? 8 : 17;
wire [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
reg [17:0] A, B, D, F, G, H;
reg [7:0] pattern, nextpatt;
reg [1:0] i;
reg [7:0] y;
wire curbuf = y[0];
reg prevbuf = 0;
wire iobuf = !curbuf;
wire diff0, diff1;
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
wire [17:0] blend_result;
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
reg Curr2_addr1;
reg [AWIDTH:0] Curr2_addr2;
wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
wire [DWIDTH:0] Curr2tmp;
reg [AWIDTH:0] wrin_addr2;
reg [DWIDTH:0] wrpix;
reg wrin_en;
function [17:0] h2rgb;
input [8:0] v;
begin
h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
end
endfunction
function [8:0] rgb2h;
input [17:0] v;
begin
rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
end
endfunction
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
(
.clk(clk),
.rdaddr(Curr2_addr2),
.rdbuf(Curr2_addr1),
.q(Curr2tmp),
.wraddr(wrin_addr2),
.wrbuf(iobuf),
.data(wrpix),
.wren(wrin_en)
);
reg [1:0] wrout_addr1;
reg [AWIDTH+1:0] wrout_addr2;
reg wrout_en;
reg [DWIDTH:0] wrdata;
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
(
.clk(clk),
.rdaddr(read_x),
.rdbuf(read_y),
.q(outpixel),
.wraddr(wrout_addr2),
.wrbuf(wrout_addr1),
.data(wrdata),
.wren(wrout_en)
);
always @(posedge clk) begin
reg [AWIDTH:0] offs;
reg old_reset_line;
reg old_reset_frame;
wrout_en <= 0;
wrin_en <= 0;
if(ce_x4) begin
pattern <= new_pattern;
if(~&offs) begin
if (i == 0) begin
Curr2_addr1 <= prevbuf;
Curr2_addr2 <= offs;
end
if (i == 1) begin
Prev2 <= Curr2;
Curr2_addr1 <= curbuf;
Curr2_addr2 <= offs;
end
if (i == 2) begin
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
wrpix <= inputpixel;
wrin_addr2 <= offs;
wrin_en <= 1;
end
if (i == 3) begin
offs <= offs + 1'd1;
end
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
else wrdata <= blend_result;
wrout_addr1 <= {curbuf, i[1]};
wrout_addr2 <= {offs, i[1]^i[0]};
wrout_en <= 1;
end
if(i==3) begin
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
{A, G} <= {Prev0, Next0};
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
{Prev0, Prev1} <= {Prev1, Prev2};
{Curr0, Curr1} <= {Curr1, Curr2};
{Next0, Next1} <= {Next1, Next2};
end else begin
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
{B, F, H, D} <= {F, H, D, B};
end
i <= i + 1'b1;
if(old_reset_line && ~reset_line) begin
old_reset_frame <= reset_frame;
offs <= 0;
i <= 0;
y <= y + 1'd1;
prevbuf <= curbuf;
if(old_reset_frame & ~reset_frame) begin
y <= 0;
prevbuf <= 0;
end
end
old_reset_line <= reset_line;
end
end
endmodule // Hq2x

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--
-- iodecode.vhd
--
-- Manage access for I/O, Ram and Rom
--
-- Copyright (C)2001 - 2005 SEILEBOST
-- All rights reserved.
--
-- $Id: iodecode.vhd, v0.10 2009/06/25 00:00:00 SEILEBOST $
--
-- TODO :
-- Remark :
-- 08/03/09 : Retour en arrière
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_STD.all;
--use IEEE.std_logic_unsigned.all;
entity iodecode is
port ( RESETn : in std_logic;
CLK_1 : in std_logic;
ADDR : in std_logic_vector(15 downto 0);
ADDR_LE : in std_logic;
MAPn : in std_logic;
CSROMn : out std_logic;
CSRAMn : out std_logic;
CSIOn : out std_logic
);
end entity iodecode;
architecture iodecode_arch of iodecode is
signal lCSROMn : std_logic;
signal lCSRAMn : std_logic;
signal lCSIOn : std_logic;
signal lADDR : std_logic_vector(15 downto 0);
begin
-- Latch BAP
u_laddr: PROCESS ( ADDR_LE, resetn )
begin
if (resetn = '0') then
lADDR<= (OTHERS => '0');
elsif rising_edge(ADDR_LE) then
lAddr<= Addr;
end if;
end process;
-- PAGE I/O : 0x300-0x3FF
-- lCSIOn <= '0' WHEN (lADDR(7 downto 0) = "00000011") AND (CLK_1 = '1') ELSE '1';
lCSIOn <= '0' WHEN (ADDR(15 downto 8) = "00000011") AND (ADDR_LE = '1') ELSE '1';
--p_CSION : process(CLK_1)
--begin
-- lCSIOn <= '1';
-- if (rising_edge(CLK_1)) then
-- if (lADDR(7 downto 0) = "00000011") then
-- lCSION <= '0';
-- end if;
-- end if;
--end process;
-- PAGE ROM : 0xC000-0xFFFF
-- lCSROMn <= '0' WHEN (lADDR(7 downto 6) = "11" AND MAPn = '1' AND CLK_1 = '1') ELSE '1'; p_CSION : process(CLK_1)
lCSROMn <= '0' WHEN (ADDR(15 downto 14) = "11" AND MAPn = '1' AND ADDR_LE = '1') ELSE '1';
--p_CSROMN : process(CLK_1)
--begin
-- lCSROMn <= '1';
-- if (rising_edge(CLK_1)) then
-- if (lADDR(7 downto 6) = "11" AND MAPn = '1') then
-- lCSROMn <= '0';
-- end if;
-- end if;
-- end process;
-- PAGR RAM : le reste ...
-- lCSRAMn <= '0' WHEN -- Partie Ram shadow
-- (lADDR(7 downto 6) = "11" AND MAPn = '0' AND CLK_1 = '1')
-- OR
-- -- Partie Ram normale
-- ( (lADDR(7 downto 0) /= "00000011" and lADDR(7 downto 6) /= "11")
-- AND MAPn = '1' AND CLK_1 = '1')
-- ELSE '1';
lCSRAMn <= '0' WHEN -- Partie Ram shadow
(ADDR(15 downto 14) = "11" AND MAPn = '0' AND ADDR_LE = '1')
OR
-- Partie Ram normale
(((ADDR(15 downto 8) /= "00000011") AND (ADDR(15 downto 14) /= "11")) AND MAPn = '1' AND ADDR_LE = '1')
ELSE '1';
--p_CSRAMN : process(CLK_1)
--begin
-- lCSRAMn <= '1';
-- if (rising_edge(CLK_1)) then
-- if ((lADDR(7 downto 6) = "11" AND MAPn = '0')
-- OR ((lADDR(7 downto 0) /= "00000011" and lADDR(7 downto 6) /= "11")
-- AND MAPn = '1')) then
-- lCSRAMn <= '0';
-- end if;
-- end if;
--end process;
-- Assign output signal
CSROMn <= lCSROMn;
CSRAMn <= lCSRAMn;
CSIOn <= lCSIOn;
end architecture iodecode_arch;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keyboard is
port(
CLK : in std_logic;
RESET : in std_logic;
PS2CLK : in std_logic;
PS2DATA : in std_logic;
COL : in std_logic_vector(2 downto 0);
ROWbit : out std_logic_vector(7 downto 0)
);
end keyboard;
architecture arch of keyboard is
-- Gestion du protocole sur PS/2
component ps2key is
generic (
FREQ : integer := 24
);
port(
CLK : in std_logic;
RESET : in std_logic;
PS2CLK : in std_logic;
PS2DATA : in std_logic;
BREAK : out std_logic;
EXTENDED : out std_logic;
CODE : out std_logic_vector(6 downto 0);
LATCH : out std_logic
);
end component;
-- La matrice du clavier
component keymatrix is
port(
CLK : in std_logic;
wROW : in std_logic_vector(2 downto 0);
wCOL : in std_logic_vector(2 downto 0);
wVAL : in std_logic;
wEN : in std_logic;
WE : in std_logic;
rCOL : in std_logic_vector(2 downto 0);
rROWbit : out std_logic_vector(7 downto 0)
);
end component;
signal MAT_wROW : std_logic_vector(2 downto 0);
signal MAT_wCOL : std_logic_vector(2 downto 0);
signal MAT_wVAL : std_logic;
signal MAT_WE : std_logic;
signal MAT_wEN : std_logic;
signal ROM_A : std_logic_vector(7 downto 0);
signal DISPLAY : std_logic_vector(15 downto 0);
begin
PS2 : ps2key port map(
CLK => CLK,
RESET => RESET,
PS2CLK => PS2CLK,
PS2DATA => PS2DATA,
BREAK => MAT_wVAL,
EXTENDED => ROM_A(7),
CODE(0) => ROM_A(0),
CODE(1) => ROM_A(1),
CODE(2) => ROM_A(2),
CODE(3) => ROM_A(3),
CODE(4) => ROM_A(4),
CODE(5) => ROM_A(5),
CODE(6) => ROM_A(6),
LATCH => MAT_WE
);
ROM : entity work.keymap port map(
A => ROM_A,
ROW => MAT_wROW,
COL => MAT_wCOL,
clk_sys => CLK,
EN => MAT_wEN
);
MAT : keymatrix port map(
CLK => CLK,
wROW => MAT_wROW,
wCOL => MAT_wCOL,
wVAL => MAT_wVAL,
wEN => MAT_wEN,
WE => MAT_WE,
rCOL => COL,
rROWbit => ROWbit
);
end arch;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity keyboardX is
port (
CLK : in std_logic;
RESET : in std_logic;
PS2CLK : in std_logic;
PS2DATA : in std_logic_vector( 7 downto 0);
COL : in std_logic_vector(2 downto 0);
ROWbit : out std_logic_vector( 7 downto 0)
);
end;
architecture RTL of keyboardX is
begin
CLKp: PROCESS ( CLK )
begin
if (RESET = '0') then
COL<= (OTHERS => '0');
ROWbit<= (OTHERS => '0');
elsif rising_edge(CLK) then
---
end if;
end process;
end RTL;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keymap is
port(
A : in std_logic_vector(7 downto 0);
clk_sys: in std_logic;
ROW : out std_logic_vector(2 downto 0);
COL : out std_logic_vector(2 downto 0);
EN : out std_logic
);
end keymap;
architecture arch of keymap is
begin
ROM256X1_ROW2 : entity work.sprom
generic map
(
init_file => "roms/key1.hex",
widthad_a => 8,
width_a => 1
)
port map
(
clock => clk_sys,
address => A,
q(0) => ROW(2)
);
-- ROWS
-- ROM256X1_ROW2 : ROM256X1
-- generic map (
-- INIT => X"00140800000000000000000000000000004000402E3400000000004E7C760000")
-- port map (
-- q => ROW(2), -- ROM output
-- address => A
-- );
ROM256X1_ROW1 : entity work.sprom
generic map
(
init_file => "roms/key2.hex",
widthad_a => 8,
width_a => 1
)
port map
(
clock => clk_sys,
address => A,
q(0) => ROW(1)
);
-- ROM256X1_ROW1 : ROM256X1
-- generic map (
-- INIT => X"00340000000000000000000000000000000000002834763000146C7E68200000")
-- port map (
-- q => ROW(1), -- ROM output
-- address => A
-- );
ROM256X1_ROW0 : entity work.sprom
generic map
(
init_file => "roms/key3.hex",
widthad_a => 8,
width_a => 1
)
port map
(
clock => clk_sys,
address => A,
q(0) => ROW(0)
);
-- ROM256X1_ROW0 : ROM256X1
-- generic map (
-- INIT => X"003008000000000000000000000000000040004004346C4A004A1C7A34400000")
-- port map (
-- q => ROW(0), -- ROM output
-- address => A -- ROM address
-- );
-- COLUMNS
ROM256X1_COL2 : entity work.sprom
generic map
(
init_file => "roms/key4.hex",
widthad_a => 8,
width_a => 1
)
port map
(
clock => clk_sys,
address => A,
q(0) => COL(2)
);
-- ROM256X1_COL2 : ROM256X1
-- generic map (
-- INIT => X"00340800000000000000000000000000000000400E302E3A5038021038060000")
-- port map (
-- q => COL(2), -- ROM output
-- address => A -- ROM address[7]
-- );
ROM256X1_COL1 : entity work.sprom
generic map
(
init_file => "roms/key5.hex",
widthad_a => 8,
width_a => 1
)
port map
(
clock => clk_sys,
address => A,
q(0) => COL(1)
);
-- ROM256X1_COL1 : ROM256X1
-- generic map (
-- INIT => X"000000000000000000000000000000000000000026245C64447C00327C100000")
-- port map (
-- q => COL(1), -- ROM output
-- address => A -- ROM address[7]
-- );
ROM256X1_COL0 : entity work.sprom
generic map
(
init_file => "roms/key6.hex",
widthad_a => 8,
width_a => 1
)
port map
(
clock => clk_sys,
address => A,
q(0) => COL(0)
);
-- ROM256X1_COL0 : ROM256X1
-- generic map (
-- INIT => X"00000000000000000000000000000000004000402E347C7C5800380800220000")
-- port map (
-- q => COL(0), -- ROM output
-- address => A -- ROM address[7]
-- );
-- ENABLE
ROM256X1_EN : entity work.sprom
generic map
(
init_file => "roms/key7.hex",
widthad_a => 8,
width_a => 1
)
port map
(
clock => clk_sys,
address => A,
q(0) => EN
);
-- ROM256X1_EN : ROM256X1
-- generic map (
-- INIT => X"00340800000000000000000000000000004000402E347E7E7C7E7E7E7C760000")
-- port map (
-- q => EN, -- ROM output
-- address => A -- ROM address[7]
-- );
end arch;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keymatrix is
port(
CLK : in std_logic;
wROW : in std_logic_vector(2 downto 0);
wCOL : in std_logic_vector(2 downto 0);
wVAL : in std_logic;
wEN : in std_logic;
WE : in std_logic;
rCOL : in std_logic_vector(2 downto 0);
rROWbit : out std_logic_vector(7 downto 0)
);
end keymatrix;
architecture arch of keymatrix is
signal WEi : std_logic_vector(7 downto 0);
-- inutilise
signal SPOi : std_logic_vector(7 downto 0);
begin
WEi(0) <= WE when wEN = '1' and wROW = "000" else '0';
WEi(1) <= WE when wEN = '1' and wROW = "001" else '0';
WEi(2) <= WE when wEN = '1' and wROW = "010" else '0';
WEi(3) <= WE when wEN = '1' and wROW = "011" else '0';
WEi(4) <= WE when wEN = '1' and wROW = "100" else '0';
WEi(5) <= WE when wEN = '1' and wROW = "101" else '0';
WEi(6) <= WE when wEN = '1' and wROW = "110" else '0';
WEi(7) <= WE when wEN = '1' and wROW = "111" else '0';
--ROWBit : for i in 0 to 7 generate
-- RAM16X1D_ROWBit : RAM16X1D
-- generic map (
-- INIT => X"FFFF")
-- port map (
-- D => wVAL, -- Write 1-bit data input
-- SPO => SPOi(i), -- R/W 1-bit data output for A0-A3
-- A0 => wCOL(0), -- R/W address[0] input bit
-- A1 => wCOL(1), -- R/W address[1] input bit
-- A2 => wCOL(2), -- R/W address[2] input bit
-- A3 => '0', -- R/W ddress[3] input bit
-- DPO => rROWBit(i), -- Read-only 1-bit data output for DPRA
-- DPRA0 => rCOL(0), -- Read-only address[0] input bit
-- DPRA1 => rCOL(1), -- Read-only address[1] input bit
-- DPRA2 => rCOL(2), -- Read-only address[2] input bit
-- DPRA3 => '0', -- Read-only address[3] input bit
-- WCLK => CLK, -- Write clock input
-- WE => WEi(i) -- Write enable input
-- );
--end generate;
end arch;

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--
-- A simulation model of VIC20 hardware
-- Copyright (c) MikeJ - March 2003
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email vic20@fpgaarcade.com
--
--
-- Revision list
--
-- version 002 fix from Mark McDougall, untested
-- version 001 initial release
-- not very sure about the shift register, documentation is a bit light.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity M6522 is
port (
I_RS : in std_logic_vector(3 downto 0);
I_DATA : in std_logic_vector(7 downto 0);
O_DATA : out std_logic_vector(7 downto 0);
O_DATA_OE_L : out std_logic;
I_RW_L : in std_logic;
I_CS1 : in std_logic;
I_CS2_L : in std_logic;
O_IRQ_L : out std_logic; -- note, not open drain
-- port a
I_CA1 : in std_logic;
I_CA2 : in std_logic;
O_CA2 : out std_logic;
O_CA2_OE_L : out std_logic;
I_PA : in std_logic_vector(7 downto 0);
O_PA : out std_logic_vector(7 downto 0);
O_PA_OE_L : out std_logic_vector(7 downto 0);
-- port b
I_CB1 : in std_logic;
O_CB1 : out std_logic;
O_CB1_OE_L : out std_logic;
I_CB2 : in std_logic;
O_CB2 : out std_logic;
O_CB2_OE_L : out std_logic;
I_PB : in std_logic_vector(7 downto 0);
O_PB : out std_logic_vector(7 downto 0);
O_PB_OE_L : out std_logic_vector(7 downto 0);
I_P2_H : in std_logic; -- high for phase 2 clock ____----__
RESET_L : in std_logic;
ENA_4 : in std_logic; -- clk enable
CLK : in std_logic
);
end;
architecture RTL of M6522 is
signal phase : std_logic_vector(1 downto 0);
signal p2_h_t1 : std_logic;
signal cs : std_logic;
-- registers
signal r_ddra : std_logic_vector(7 downto 0);
signal r_ora : std_logic_vector(7 downto 0);
signal r_ira : std_logic_vector(7 downto 0);
signal r_ddrb : std_logic_vector(7 downto 0);
signal r_orb : std_logic_vector(7 downto 0);
signal r_irb : std_logic_vector(7 downto 0);
signal r_t1l_l : std_logic_vector(7 downto 0);
signal r_t1l_h : std_logic_vector(7 downto 0);
signal r_t2l_l : std_logic_vector(7 downto 0);
signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip
signal r_sr : std_logic_vector(7 downto 0);
signal r_acr : std_logic_vector(7 downto 0);
signal r_pcr : std_logic_vector(7 downto 0);
signal r_ifr : std_logic_vector(7 downto 0);
signal r_ier : std_logic_vector(6 downto 0);
signal sr_write_ena : boolean;
signal sr_read_ena : boolean;
signal ifr_write_ena : boolean;
signal ier_write_ena : boolean;
signal clear_irq : std_logic_vector(7 downto 0);
signal load_data : std_logic_vector(7 downto 0);
-- timer 1
signal t1c : std_logic_vector(15 downto 0);
signal t1c_active : boolean;
signal t1c_done : boolean;
signal t1_w_reset_int : boolean;
signal t1_r_reset_int : boolean;
signal t1_load_counter : boolean;
signal t1_reload_counter : boolean;
signal t1_toggle : std_logic;
signal t1_irq : std_logic := '0';
-- timer 2
signal t2c : std_logic_vector(15 downto 0);
signal t2c_active : boolean;
signal t2c_done : boolean;
signal t2_pb6 : std_logic;
signal t2_pb6_t1 : std_logic;
signal t2_w_reset_int : boolean;
signal t2_r_reset_int : boolean;
signal t2_load_counter : boolean;
signal t2_reload_counter : boolean;
signal t2_irq : std_logic := '0';
signal t2_sr_ena : boolean;
-- shift reg
signal sr_cnt : std_logic_vector(3 downto 0);
signal sr_cb1_oe_l : std_logic;
signal sr_cb1_out : std_logic;
signal sr_drive_cb2 : std_logic;
signal sr_strobe : std_logic;
signal sr_strobe_t1 : std_logic;
signal sr_strobe_falling : boolean;
signal sr_strobe_rising : boolean;
signal sr_irq : std_logic;
signal sr_out : std_logic;
signal sr_off_delay : std_logic;
-- io
signal w_orb_hs : std_logic;
signal w_ora_hs : std_logic;
signal r_irb_hs : std_logic;
signal r_ira_hs : std_logic;
signal ca_hs_sr : std_logic;
signal ca_hs_pulse : std_logic;
signal cb_hs_sr : std_logic;
signal cb_hs_pulse : std_logic;
signal cb1_in_mux : std_logic;
signal ca1_ip_reg : std_logic;
signal cb1_ip_reg : std_logic;
signal ca1_int : boolean;
signal cb1_int : boolean;
signal ca1_irq : std_logic;
signal cb1_irq : std_logic;
signal ca2_ip_reg : std_logic;
signal cb2_ip_reg : std_logic;
signal ca2_int : boolean;
signal cb2_int : boolean;
signal ca2_irq : std_logic;
signal cb2_irq : std_logic;
signal final_irq : std_logic;
begin
p_phase : process
begin
-- internal clock phase
wait until rising_edge(CLK);
if (ENA_4 = '1') then
p2_h_t1 <= I_P2_H;
if (p2_h_t1 = '0') and (I_P2_H = '1') then
phase <= "11";
else
phase <= phase + "1";
end if;
end if;
end process;
p_cs : process(I_CS1, I_CS2_L, I_P2_H)
begin
cs <= '0';
if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then
cs <= '1';
end if;
end process;
-- peripheral control reg (pcr)
-- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge)
-- 3..1 ca2 operation
-- 000 input -ve edge
-- 001 independend interrupt input -ve edge
-- 010 input +ve edge
-- 011 independend interrupt input +ve edge
-- 100 handshake output
-- 101 pulse output
-- 110 low output
-- 111 high output
-- 7..4 as 3..0 for cb1,cb2
-- auxiliary control reg (acr)
-- 0 input latch PA (0 disable, 1 enable)
-- 1 input latch PB (0 disable, 1 enable)
-- 4..2 shift reg control
-- 000 disable
-- 001 shift in using t2
-- 010 shift in using o2
-- 011 shift in using ext clk
-- 100 shift out free running t2 rate
-- 101 shift out using t2
-- 101 shift out using o2
-- 101 shift out using ext clk
-- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6)
-- 7..6 t1 timer control
-- 00 timed interrupt each time t1 is loaded pb7 disable
-- 01 continuous interrupts pb7 disable
-- 00 timed interrupt each time t1 is loaded pb7 one shot output
-- 01 continuous interrupts pb7 square wave output
--
p_write_reg_reset : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
r_ora <= x"00"; r_orb <= x"00";
r_ddra <= x"00"; r_ddrb <= x"00";
r_acr <= x"00"; r_pcr <= x"00";
w_orb_hs <= '0';
w_ora_hs <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
w_orb_hs <= '0';
w_ora_hs <= '0';
if (cs = '1') and (I_RW_L = '0') then
case I_RS is
when x"0" => r_orb <= I_DATA; w_orb_hs <= '1';
when x"1" => r_ora <= I_DATA; w_ora_hs <= '1';
when x"2" => r_ddrb <= I_DATA;
when x"3" => r_ddra <= I_DATA;
when x"B" => r_acr <= I_DATA;
when x"C" => r_pcr <= I_DATA;
when x"F" => r_ora <= I_DATA;
when others => null;
end case;
end if;
if (r_acr(7) = '1') and (t1_toggle = '1') then
r_orb(7) <= not r_orb(7); -- toggle
end if;
end if;
end if;
end process;
p_write_reg : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
t1_w_reset_int <= false;
t1_load_counter <= false;
t2_w_reset_int <= false;
t2_load_counter <= false;
load_data <= x"00";
sr_write_ena <= false;
ifr_write_ena <= false;
ier_write_ena <= false;
if (cs = '1') and (I_RW_L = '0') then
load_data <= I_DATA;
case I_RS is
when x"4" => r_t1l_l <= I_DATA;
when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
t1_load_counter <= true;
when x"6" => r_t1l_l <= I_DATA;
when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
when x"8" => r_t2l_l <= I_DATA;
when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true;
t2_load_counter <= true;
when x"A" => sr_write_ena <= true;
when x"D" => ifr_write_ena <= true;
when x"E" => ier_write_ena <= true;
when others => null;
end case;
end if;
end if;
end process;
p_oe : process(cs, I_RW_L)
begin
O_DATA_OE_L <= '1';
if (cs = '1') and (I_RW_L = '1') then
O_DATA_OE_L <= '0';
end if;
end process;
p_read : process(cs, I_RW_L, I_RS, r_irb, r_ira, r_ddrb, r_ddra, t1c, r_t1l_l,
r_t1l_h, t2c, r_sr, r_acr, r_pcr, r_ifr, r_ier, r_orb)
begin
t1_r_reset_int <= false;
t2_r_reset_int <= false;
sr_read_ena <= false;
r_irb_hs <= '0';
r_ira_hs <= '0';
O_DATA <= x"00"; -- default
if (cs = '1') and (I_RW_L = '1') then
case I_RS is
--when x"0" => O_DATA <= r_irb; r_irb_hs <= '1';
-- fix from Mark McDougall, untested
when x"0" => O_DATA <= (r_irb and not r_ddrb) or (r_orb and r_ddrb); r_irb_hs <= '1';
when x"1" => O_DATA <= r_ira; r_ira_hs <= '1';
when x"2" => O_DATA <= r_ddrb;
when x"3" => O_DATA <= r_ddra;
when x"4" => O_DATA <= t1c( 7 downto 0); t1_r_reset_int <= true;
when x"5" => O_DATA <= t1c(15 downto 8);
when x"6" => O_DATA <= r_t1l_l;
when x"7" => O_DATA <= r_t1l_h;
when x"8" => O_DATA <= t2c( 7 downto 0); t2_r_reset_int <= true;
when x"9" => O_DATA <= t2c(15 downto 8);
when x"A" => O_DATA <= r_sr; sr_read_ena <= true;
when x"B" => O_DATA <= r_acr;
when x"C" => O_DATA <= r_pcr;
when x"D" => O_DATA <= r_ifr;
when x"E" => O_DATA <= ('0' & r_ier);
when x"F" => O_DATA <= r_ira;
when others => null;
end case;
end if;
end process;
--
-- IO
--
p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1)
begin
-- if the shift register is enabled, cb1 may be an output
-- in this case, we should listen to the CB1_OUT for the interrupt
if (sr_cb1_oe_l = '1') then
cb1_in_mux <= I_CB1;
else
cb1_in_mux <= sr_cb1_out;
end if;
end process;
p_ca1_cb1_int : process(r_pcr, ca1_ip_reg, I_CA1, cb1_ip_reg, cb1_in_mux)
begin
if (r_pcr(0) = '0') then -- ca1 control
-- negative edge
ca1_int <= (ca1_ip_reg = '1') and (I_CA1 = '0');
else
-- positive edge
ca1_int <= (ca1_ip_reg = '0') and (I_CA1 = '1');
end if;
if (r_pcr(4) = '0') then -- cb1 control
-- negative edge
cb1_int <= (cb1_ip_reg = '1') and (cb1_in_mux = '0');
else
-- positive edge
cb1_int <= (cb1_ip_reg = '0') and (cb1_in_mux = '1');
end if;
end process;
p_ca2_cb2_int : process(r_pcr, ca2_ip_reg, I_CA2, cb2_ip_reg, I_CB2)
begin
ca2_int <= false;
if (r_pcr(3) = '0') then -- ca2 input
if (r_pcr(2) = '0') then -- ca2 edge
-- negative edge
ca2_int <= (ca2_ip_reg = '1') and (I_CA2 = '0');
else
-- positive edge
ca2_int <= (ca2_ip_reg = '0') and (I_CA2 = '1');
end if;
end if;
cb2_int <= false;
if (r_pcr(7) = '0') then -- cb2 input
if (r_pcr(6) = '0') then -- cb2 edge
-- negative edge
cb2_int <= (cb2_ip_reg = '1') and (I_CB2 = '0');
else
-- positive edge
cb2_int <= (cb2_ip_reg = '0') and (I_CB2 = '1');
end if;
end if;
end process;
p_ca2_cb2 : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
O_CA2 <= '0';
O_CA2_OE_L <= '1';
O_CB2 <= '0';
O_CB2_OE_L <= '1';
ca_hs_sr <= '0';
ca_hs_pulse <= '0';
cb_hs_sr <= '0';
cb_hs_pulse <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- ca
if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then
ca_hs_sr <= '1';
elsif ca1_int then
ca_hs_sr <= '0';
end if;
if (phase = "00") then
ca_hs_pulse <= w_ora_hs or r_ira_hs;
end if;
O_CA2_OE_L <= not r_pcr(3); -- ca2 output
case r_pcr(3 downto 1) is
when "000" => O_CA2 <= '0'; -- input
when "001" => O_CA2 <= '0'; -- input
when "010" => O_CA2 <= '0'; -- input
when "011" => O_CA2 <= '0'; -- input
when "100" => O_CA2 <= not (ca_hs_sr); -- handshake
when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse
when "110" => O_CA2 <= '0'; -- low
when "111" => O_CA2 <= '1'; -- high
when others => null;
end case;
-- cb
if (phase = "00") and (w_orb_hs = '1') then
cb_hs_sr <= '1';
elsif cb1_int then
cb_hs_sr <= '0';
end if;
if (phase = "00") then
cb_hs_pulse <= w_orb_hs;
end if;
O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial
if (sr_drive_cb2 = '1') then -- serial output
O_CB2 <= sr_out;
else
case r_pcr(7 downto 5) is
when "000" => O_CB2 <= '0'; -- input
when "001" => O_CB2 <= '0'; -- input
when "010" => O_CB2 <= '0'; -- input
when "011" => O_CB2 <= '0'; -- input
when "100" => O_CB2 <= not (cb_hs_sr); -- handshake
when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse
when "110" => O_CB2 <= '0'; -- low
when "111" => O_CB2 <= '1'; -- high
when others => null;
end case;
end if;
end if;
end if;
end process;
O_CB1 <= sr_cb1_out;
O_CB1_OE_L <= sr_cb1_oe_l;
p_ca_cb_irq : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
ca1_irq <= '0';
ca2_irq <= '0';
cb1_irq <= '0';
cb2_irq <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- not pretty
if ca1_int then
ca1_irq <= '1';
elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then
ca1_irq <= '0';
end if;
if ca2_int then
ca2_irq <= '1';
else
if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or
(clear_irq(0) = '1') then
ca2_irq <= '0';
end if;
end if;
if cb1_int then
cb1_irq <= '1';
elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then
cb1_irq <= '0';
end if;
if cb2_int then
cb2_irq <= '1';
else
if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or
(clear_irq(3) = '1') then
cb2_irq <= '0';
end if;
end if;
end if;
end if;
end process;
p_input_reg : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
ca1_ip_reg <= '0';
cb1_ip_reg <= '0';
ca2_ip_reg <= '0';
cb2_ip_reg <= '0';
r_ira <= x"00";
r_irb <= x"00";
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- we have a fast clock, so we can have input registers
ca1_ip_reg <= I_CA1;
cb1_ip_reg <= cb1_in_mux;
ca2_ip_reg <= I_CA2;
cb2_ip_reg <= I_CB2;
if (r_acr(0) = '0') then
r_ira <= I_PA;
else -- enable latching
if ca1_int then
r_ira <= I_PA;
end if;
end if;
if (r_acr(1) = '0') then
r_irb <= I_PB;
else -- enable latching
if cb1_int then
r_irb <= I_PB;
end if;
end if;
end if;
end if;
end process;
p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb)
begin
-- data direction reg (ddr) 0 = input, 1 = output
O_PA <= r_ora;
O_PA_OE_L <= not r_ddra;
if (r_acr(7) = '1') then -- not clear if r_ddrb(7) must be 1 as well
O_PB_OE_L(7) <= '0'; -- an output if under t1 control
else
O_PB_OE_L(7) <= not (r_ddrb(7));
end if;
O_PB_OE_L(6 downto 0) <= not r_ddrb(6 downto 0);
O_PB <= r_orb;
end process;
--
-- Timer 1
--
p_timer1_done : process
variable done : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
done := (t1c = x"0000");
t1c_done <= done and (phase = "11");
if (phase = "11") then
t1_reload_counter <= done and (r_acr(6) = '1');
end if;
end if;
end process;
p_timer1 : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if t1_load_counter or (t1_reload_counter and phase = "11") then
t1c( 7 downto 0) <= r_t1l_l;
t1c(15 downto 8) <= r_t1l_h;
elsif (phase="11") then
t1c <= t1c - "1";
end if;
if t1_load_counter or t1_reload_counter then
t1c_active <= true;
elsif t1c_done then
t1c_active <= false;
end if;
t1_toggle <= '0';
if t1c_active and t1c_done then
t1_toggle <= '1';
t1_irq <= '1';
elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then
t1_irq <= '0';
end if;
end if;
end process;
--
-- Timer2
--
p_timer2_pb6_input : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if (phase = "01") then -- leading edge p2_h
t2_pb6 <= I_PB(6);
t2_pb6_t1 <= t2_pb6;
end if;
end if;
end process;
p_timer2_done : process
variable done : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
done := (t2c = x"0000");
t2c_done <= done and (phase = "11");
if (phase = "11") then
t2_reload_counter <= done;
end if;
end if;
end process;
p_timer2 : process
variable ena : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if (r_acr(5) = '0') then
ena := true;
else
ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge
end if;
if t2_load_counter or (t2_reload_counter and phase = "11") then
-- not sure if t2c_reload should be here. Does timer2 just continue to
-- count down, or is it reloaded ? Reloaded makes more sense if using
-- it to generate a clock for the shift register.
t2c( 7 downto 0) <= r_t2l_l;
t2c(15 downto 8) <= r_t2l_h;
else
if (phase="11") and ena then -- or count mode
t2c <= t2c - "1";
end if;
end if;
t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11");
if t2_load_counter then
t2c_active <= true;
elsif t2c_done then
t2c_active <= false;
end if;
if t2c_active and t2c_done then
t2_irq <= '1';
elsif t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then
t2_irq <= '0';
end if;
end if;
end process;
--
-- Shift Register
--
p_sr : process(RESET_L, CLK)
variable dir_out : std_logic;
variable ena : std_logic;
variable cb1_op : std_logic;
variable cb1_ip : std_logic;
variable use_t2 : std_logic;
variable free_run : std_logic;
variable sr_count_ena : boolean;
begin
if (RESET_L = '0') then
r_sr <= x"00";
sr_drive_cb2 <= '0';
sr_cb1_oe_l <= '1';
sr_cb1_out <= '0';
sr_strobe <= '1';
sr_cnt <= "0000";
sr_irq <= '0';
sr_out <= '1';
sr_off_delay <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- decode mode
dir_out := r_acr(4); -- output on cb2
cb1_op := '0';
cb1_ip := '0';
use_t2 := '0';
free_run := '0';
case r_acr(4 downto 2) is
when "000" => ena := '0';
when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1';
when "010" => ena := '1'; cb1_op := '1';
when "011" => ena := '1'; cb1_ip := '1';
when "100" => ena := '1'; use_t2 := '1'; free_run := '1';
when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1';
when "110" => ena := '1';
when "111" => ena := '1'; cb1_ip := '1';
when others => null;
end case;
-- clock select
if (ena = '0') then
sr_strobe <= '1';
else
if (cb1_ip = '1') then
sr_strobe <= I_CB1;
else
if (sr_cnt(3) = '0') and (free_run = '0') then
sr_strobe <= '1';
else
if ((use_t2 = '1') and t2_sr_ena) or
((use_t2 = '0') and (phase = "00")) then
sr_strobe <= not sr_strobe;
end if;
end if;
end if;
end if;
-- latch on rising edge, shift on falling edge
if sr_write_ena then
r_sr <= load_data;
elsif (ena = '1') then -- use shift reg
if (dir_out = '0') then
-- input
if (sr_cnt(3) = '1') or (cb1_ip = '1') then
if sr_strobe_rising then
r_sr(0) <= I_CB2;
elsif sr_strobe_falling then
r_sr(7 downto 1) <= r_sr(6 downto 0);
end if;
end if;
sr_out <= '1';
else
-- output
if (sr_cnt(3) = '1') or (sr_off_delay = '1') or (cb1_ip = '1') or (free_run = '1') then
if sr_strobe_falling then
r_sr(7 downto 1) <= r_sr(6 downto 0);
r_sr(0) <= r_sr(7);
sr_out <= r_sr(7);
end if;
else
sr_out <= '1';
end if;
end if;
end if;
sr_count_ena := sr_strobe_rising;
if sr_write_ena or sr_read_ena then
-- some documentation says sr bit in IFR must be set as well ?
sr_cnt <= "1000";
elsif sr_count_ena and (sr_cnt(3) = '1') then
sr_cnt <= sr_cnt + "1";
end if;
if (phase = "00") then
sr_off_delay <= sr_cnt(3); -- give some hold time when shifting out
end if;
if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then
sr_irq <= '1';
elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then
sr_irq <= '0';
end if;
-- assign ops
sr_drive_cb2 <= dir_out;
sr_cb1_oe_l <= not cb1_op;
sr_cb1_out <= sr_strobe;
end if;
end if;
end process;
p_sr_strobe_rise_fall : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
sr_strobe_t1 <= sr_strobe;
sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1');
sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0');
end if;
end process;
--
-- Interrupts
--
p_ier : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
r_ier <= "0000000";
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
if ier_write_ena then
if (load_data(7) = '1') then
-- set
r_ier <= r_ier or load_data(6 downto 0);
else
-- clear
r_ier <= r_ier and not load_data(6 downto 0);
end if;
end if;
end if;
end if;
end process;
p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq,
cb1_irq, cb2_irq)
begin
r_ifr(7) <= final_irq;
r_ifr(6) <= t1_irq;
r_ifr(5) <= t2_irq;
r_ifr(4) <= cb1_irq;
r_ifr(3) <= cb2_irq;
r_ifr(2) <= sr_irq;
r_ifr(1) <= ca1_irq;
r_ifr(0) <= ca2_irq;
O_IRQ_L <= not final_irq;
end process;
p_irq : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
final_irq <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then
final_irq <= '0'; -- no interrupts
else
final_irq <= '1';
end if;
end if;
end if;
end process;
p_clear_irq : process(ifr_write_ena, load_data)
begin
clear_irq <= x"00";
if ifr_write_ena then
clear_irq <= load_data;
end if;
end process;
end architecture RTL;

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--
-- MANAGE_AMPLITUDE.vhd
--
-- Manage the amplitude for each tone.
--
-- Copyright (C)2001-2010 SEILEBOST
-- All rights reserved.
--
-- $Id: MANAGE_AMPLITUDE.vhd, v0.50 2010/01/19 00:00:00 SEILEBOST $
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MANAGE_AMPLITUDE is
Port ( CLK : in std_logic; -- the system clock
CLK_DAC : in std_logic; -- the clok of DAC
CLK_TONE : in std_logic; -- the frequency of sound
CLK_NOISE : in std_logic; -- the noise
RST : in std_logic; -- reset
CLK_TONE_ENA : in std_logic; -- enable tone
CLK_NOISE_ENA : in std_logic; -- enable noise
AMPLITUDE : in std_logic_vector(4 downto 0); -- value from register
AMPLITUDE_E : in std_logic_vector(3 downto 0); -- value from envelope
OUT_DAC : out std_logic );
end MANAGE_AMPLITUDE;
architecture Behavioral of MANAGE_AMPLITUDE is
signal AMPLITUDE_TMP : std_logic_vector(3 downto 0);
signal IN_DATA : std_logic_vector(7 downto 0);
COMPONENT DAC is Port ( CLK_DAC : in std_logic;
RST : in std_logic;
IN_DAC : in std_logic_vector(7 downto 0);
OUT_DAC : out std_logic );
END COMPONENT;
begin
-- Convertisseur numérique analogique : méthode sigma delta
U_DAC : DAC PORT MAP ( CLK_DAC => CLK_DAC,
RST => RST,
IN_DAC => IN_DATA,
OUT_DAC => OUT_DAC);
-- Calcule de l'amplitude à générer par le DAC
PROCESS(CLK, RST, AMPLITUDE_TMP, AMPLITUDE_E)
variable mix_tone_noise : std_logic;
BEGIN
if (RST = '1') then -- reset
AMPLITUDE_TMP <= "0000";
IN_DATA <= "00000000";
elsif (CLK'event and CLK = '1') then -- edge clock
-- Note that this means that if both tone and noise are disabled, the output */
-- is 1, not 0, and can be modulated changing the volume. */
mix_tone_noise := (CLK_TONE or CLK_TONE_ENA) AND (CLK_NOISE or CLK_NOISE_ENA);
if (mix_tone_noise = '1') then
if (AMPLITUDE(4) = '0') then -- Utilisation de la valeur du registre
AMPLITUDE_TMP <= AMPLITUDE(3 downto 0);
else -- Utilisation de la valeur de l'enveloppe
AMPLITUDE_TMP <= AMPLITUDE_E;
end if;
else
AMPLITUDE_TMP <= "0000";
end if;
-- Each amplitude has an 1.5 db step from previous amplitude
CASE AMPLITUDE_TMP IS
when "0000" => IN_DATA <= "00000000"; -- 0
when "0001" => IN_DATA <= "00010110"; -- 22
when "0010" => IN_DATA <= "00011010"; -- 26
when "0011" => IN_DATA <= "00011111"; -- 31
when "0100" => IN_DATA <= "00100101"; -- 37
when "0101" => IN_DATA <= "00101100"; -- 44
when "0110" => IN_DATA <= "00110100"; -- 52
when "0111" => IN_DATA <= "00111110"; -- 62
when "1000" => IN_DATA <= "01001010"; -- 74
when "1001" => IN_DATA <= "01011000"; -- 88
when "1010" => IN_DATA <= "01101001"; -- 105
when "1011" => IN_DATA <= "01110101"; -- 125
when "1100" => IN_DATA <= "10011001"; -- 149
when "1101" => IN_DATA <= "10110001"; -- 177
when "1110" => IN_DATA <= "11010010"; -- 210
when "1111" => IN_DATA <= "11111111"; -- 255
when OTHERS => NULL;
END CASE;
end if;
END PROCESS;
end Behavioral;

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--
-- memmap.vhd
--
-- Manage offset for read ula
--
-- Copyright (C)2001 - 2005 SEILEBOST
-- All rights reserved.
--
-- $Id: memmap.vhd, v0.02 2005/01/01 00:00:00 SEILEBOST $
--
-- TODO :
-- Remark :
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
--use IEEE.std_logic_arith.all;
--use IEEE.numeric_std.all;
entity memmap is
port ( TXTHIR_SEL : in std_logic;
DBLHGT_SEL : in std_logic;
FORCETXT : in std_logic;
CPT_H : in std_logic_vector(6 downto 0);
CPT_V : in std_logic_vector(8 downto 0);
VAP1 : out std_logic_vector(15 downto 0);
CHROWCNT : out std_logic_vector(2 downto 0);
TXTHIR_DEC : out std_logic
);
end entity memmap;
architecture memmap_arch of memmap is
signal lDBLHGT_EN : std_logic; -- ENABLE DOUBLE HEIGT
signal lTXTHIR_DEC : std_logic; -- MODE TEXT / HIRES
signal lCPT_V_TMP : std_logic_vector(8 downto 0); -- VERTICAL COUNTER
signal lCPT_V_8_TMP : std_logic_vector(8 downto 0); -- VERTICAL COUNTER DIVIDE OR NOT BY 8
signal lVAP1 : std_logic_vector(12 downto 0); -- VIDEO ADDRESS PHASE 1
signal lOFFSCR : std_logic_vector(15 downto 0); -- OFFSET SCREEN
signal ltmpBy10 : std_logic_vector(12 downto 0); -- Using to mult by 10
begin
-- local signal
lTXTHIR_DEC <= (TXTHIR_SEL and FORCETXT);
lDBLHGT_EN <= (DBLHGT_SEL and lTXTHIR_DEC);
-- Compute video adress phase 1
lCPT_V_TMP <= '0'&CPT_V(8 downto 1) when lDBLHGT_EN = '1' else CPT_V(8 downto 0);
-- divide by 8 if necessary : erreur sur la manière de diviser par 8? 03/02/2010
--lCPT_V_8_TMP <= lCPT_V_TMP when lTXTHIR_DEC = '1' else lCPT_V_TMP(8 downto 3) & "000";
lCPT_V_8_TMP <= lCPT_V_TMP when lTXTHIR_DEC = '1' else "000" & lCPT_V_TMP(8 downto 3) ;
-- 03/02/2010 : Le bonne blague : après la phase de synthese, le 'bench' ne
-- fonctionnait plus. Le synthetiseur de XILINX avait utilisé un multiplieur 18x18
-- pour générer la multiplication par 10 et la simulation a repris cela. Or le
-- multiplier a une latence de 1 µs (latence de l'horloge PHI2) d'où les problèmes
-- durant les simulations (génération de 2 fois de suite de l'adresse vidéo)
-- On revient à la bonne vieille méthode Bx10 = Bx8 + Bx2 !!
--lVAP1 <= ("0000000" & CPT_H) + (lCPT_V_8_TMP * "1010");
ltmpBy10 <= ("0" & lCPT_V_8_TMP & "000") + ("000" & lCPT_V_8_TMP & "0");
-- le décalage en Y : il faut multiplier par 40 donc 4 * ltmpBy10
lVAP1 <= ("00000" & CPT_H) + (ltmpBy10(10 downto 0) & "00");
lOFFSCR <= X"A000" when lTXTHIR_DEC = '1' else X"BB80";
VAP1 <= ("000" & lVAP1) + lOFFSCR;
-- Compute character row counter
CHROWCNT <= CPT_V(2 downto 0) when lDBLHGT_EN = '1' else CPT_V(3 downto 1);
-- Output signal for texte/hires mode decode
TXTHIR_DEC <= lTXTHIR_DEC;
end architecture memmap_arch;

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//
// mist_io.v
//
// mist_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
//
// Use buffer to access SD card. It's time-critical part.
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
// (Sorgelig)
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = clk_sys/(PS2DIV*2)
//
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
(
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
// Global clock. It should be around 100MHz (higher is better).
input clk_sys,
// Global SPI clock from ARM. 24MHz
input SPI_SCK,
input CONF_DATA0,
input SPI_SS2,
output SPI_DO,
input SPI_DI,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output ypbpr,
output reg [31:0] status,
// SD config
input sd_conf,
input sd_sdhc,
output img_mounted, // signaling that new image has been mounted
output reg [31:0] img_size, // size of image in bytes
// SD block level access
input [31:0] sd_lba,
input sd_rd,
input sd_wr,
output reg sd_ack,
output reg sd_ack_conf,
// SD byte level access. Signals for 2-PORT altsyncram.
output reg [8:0] sd_buff_addr,
output reg [7:0] sd_buff_dout,
input [7:0] sd_buff_din,
output reg sd_buff_wr,
// ps2 keyboard emulation
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
input ps2_caps_led,
// ARM -> FPGA download
output reg ioctl_download = 0, // signal indicating an active download
output reg [7:0] ioctl_index, // menu index used to upload the file
output ioctl_wr,
output reg [24:0] ioctl_addr,
output reg [7:0] ioctl_dout
);
reg [7:0] b_data;
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [9:0] byte_cnt; // counts bytes
reg [7:0] but_sw;
reg [2:0] stick_idx;
reg mount_strobe = 0;
assign img_mounted = mount_strobe;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
assign ypbpr = but_sw[5];
wire [7:0] spi_dout = { sbuf, SPI_DI};
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
reg spi_do;
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1};
// drive MISO only when transmitting core id
always@(negedge SPI_SCK) begin
if(!CONF_DATA0) begin
// first byte returned is always core type, further bytes are
// command dependent
if(byte_cnt == 0) begin
spi_do <= core_type[~bit_cnt];
end else begin
case(cmd)
// reading config string
8'h14: begin
// returning a byte from string
if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
else spi_do <= 0;
end
// reading sd card status
8'h16: begin
if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
else spi_do <= 0;
end
// reading sd card write data
8'h18:
spi_do <= b_data[~bit_cnt];
// reading keyboard LED status
8'h1f:
spi_do <= kbd_led[~bit_cnt];
default:
spi_do <= 0;
endcase
end
end
end
reg b_wr2,b_wr3;
always @(negedge clk_sys) begin
b_wr3 <= b_wr2;
sd_buff_wr <= b_wr3;
end
// SPI receiver
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
if(CONF_DATA0) begin
b_wr2 <= 0;
bit_cnt <= 0;
byte_cnt <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
end else begin
b_wr2 <= 0;
sbuf <= spi_dout[6:0];
bit_cnt <= bit_cnt + 1'd1;
if(bit_cnt == 5) begin
if (byte_cnt == 0) sd_buff_addr <= 0;
if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
end
// finished reading command byte
if(bit_cnt == 7) begin
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
if(byte_cnt == 0) begin
cmd <= spi_dout;
if(spi_dout == 8'h19) begin
sd_ack_conf <= 1;
sd_buff_addr <= 0;
end
if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
sd_ack <= 1;
sd_buff_addr <= 0;
end
if(spi_dout == 8'h18) b_data <= sd_buff_din;
mount_strobe <= 0;
end else begin
case(cmd)
// buttons and switches
8'h01: but_sw <= spi_dout;
8'h02: joystick_0 <= spi_dout;
8'h03: joystick_1 <= spi_dout;
// store incoming ps2 mouse bytes
8'h04: begin
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout;
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
end
// store incoming ps2 keyboard bytes
8'h05: begin
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout;
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
end
8'h15: status[7:0] <= spi_dout;
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
8'h19,
// send sector IO -> FPGA
// flag that download begins
8'h17: begin
sd_buff_dout <= spi_dout;
b_wr2 <= 1;
end
8'h18: b_data <= sd_buff_din;
// joystick analog
8'h1a: begin
// first byte is joystick index
if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
else if(byte_cnt == 2) begin
// second byte is x axis
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
end else if(byte_cnt == 3) begin
// third byte is y axis
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
end
end
// notify image selection
8'h1c: mount_strobe <= 1;
// send image info
8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
// status, 32bit version
8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
default: ;
endcase
end
end
end
end
/////////////////////////////// PS2 ///////////////////////////////
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
reg clk_ps2;
always @(negedge clk_sys) begin
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
clk_ps2 <= ~clk_ps2;
cnt <= 0;
end
end
// keyboard
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_kbd_tx_state;
reg [7:0] ps2_kbd_tx_byte;
reg ps2_kbd_parity;
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_kbd_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_kbd_r_inc <= 0;
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
// transmitter is idle?
if(ps2_kbd_tx_state == 0) begin
// data in fifo present?
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
// load tx register from fifo
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
ps2_kbd_r_inc <= 1;
// reset parity
ps2_kbd_parity <= 1;
// start transmitter
ps2_kbd_tx_state <= 1;
// put start bit on data line
ps2_kbd_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
if(ps2_kbd_tx_byte[0])
ps2_kbd_parity <= !ps2_kbd_parity;
end
// transmission of parity
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
// transmission of stop bit
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
// advance state machine
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
else ps2_kbd_tx_state <= 0;
end
end
end
// mouse
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_mouse_tx_state;
reg [7:0] ps2_mouse_tx_byte;
reg ps2_mouse_parity;
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_mouse_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_mouse_r_inc <= 0;
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
// transmitter is idle?
if(ps2_mouse_tx_state == 0) begin
// data in fifo present?
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
// load tx register from fifo
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
ps2_mouse_r_inc <= 1;
// reset parity
ps2_mouse_parity <= 1;
// start transmitter
ps2_mouse_tx_state <= 1;
// put start bit on data line
ps2_mouse_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
if(ps2_mouse_tx_byte[0])
ps2_mouse_parity <= !ps2_mouse_parity;
end
// transmission of parity
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
// transmission of stop bit
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
// advance state machine
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
else ps2_mouse_tx_state <= 0;
end
end
end
/////////////////////////////// DOWNLOADING ///////////////////////////////
reg [7:0] data_w;
reg [24:0] addr_w;
reg rclk = 0;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
// data_io has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS2) begin
reg [6:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [24:0] addr;
if(SPI_SS2) cnt <= 0;
else begin
rclk <= 0;
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
// increase target address after write
if(rclk) addr <= addr + 1'd1;
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
// finished command byte
if(cnt == 7) cmd <= {sbuf, SPI_DI};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
addr <= 0;
ioctl_download <= 1;
end else begin
addr_w <= addr;
ioctl_download <= 0;
end
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
addr_w <= addr;
data_w <= {sbuf, SPI_DI};
rclk <= 1;
end
// expose file (menu) index
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
end
end
assign ioctl_wr = |ioctl_wrd;
reg [1:0] ioctl_wrd;
always@(negedge clk_sys) begin
reg rclkD, rclkD2;
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wrd<= {ioctl_wrd[0],1'b0};
if(rclkD & ~rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wrd <= 2'b11;
end
end
endmodule

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--
-- NOISE_GENERATOR.vhd
--
-- Generator a noise tone.
--
-- Copyright (C)2001 SEILEBOST
-- All rights reserved.
--
-- $Id: NOISE_GENERATOR.vhd, v0.41 2002/01/03 00:00:00 SEILEBOST $
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity noise_generator is
Port ( CLK : in std_logic;
RST : in std_logic;
--WR : in std_logic;
--CS : in std_logic;
DATA : in std_logic_vector(4 downto 0);
CLK_N : out std_logic -- pseudo clock
);
end noise_generator;
architecture Behavioral of noise_generator is
SIGNAL COUNT : std_logic_vector(4 downto 0);
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
--SIGNAL ShiftEn : std_logic;
--SIGNAL FillSel : std_logic;
--SIGNAL DataIn : std_logic;
--SIGNAL lData : std_logic_vector(4 downto 0);
--COMPONENT i_pn_gen port (clk, ShiftEn, FillSel, DataIn_i, RESET : in std_logic;
-- pn_out_i : out std_logic);
--END COMPONENT;
begin
--U_IPNG : I_PN_GEN PORT MAP ( CLK => CLK,
-- ShiftEn => ShiftEn,
-- FillSel => FillSel,
-- RESET => RST,
-- DataIn_i => DataIn,
-- pn_out_i => CLK_N);
-- The noise generator
PROCESS(CLK,RST)
variable COUNT_MAX : std_logic_vector(4 downto 0);
variable poly17_zero : std_logic;
BEGIN
if (RST = '1') then
poly17 <= (others => '0');
elsif ( CLK'event and CLK = '1') then
if (DATA = "00000") then
COUNT_MAX := "00000";
else
COUNT_MAX := (DATA - "1");
end if;
-- Manage the polynome = 0 to regenerate another sequence
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
if (COUNT >= COUNT_MAX) then
COUNT <= "00000";
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero)
& poly17(16 downto 1);
else
COUNT <= (COUNT + "1");
end if;
end if;
END PROCESS;
CLK_N <= poly17(0);
end Behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
entity oricatmos is
port (
CLOCK_27 : in std_logic;
LED : out std_logic;
VGA_R : out std_logic_vector(5 downto 0);
VGA_G : out std_logic_vector(5 downto 0);
VGA_B : out std_logic_vector(5 downto 0);
VGA_HS : out std_logic;
VGA_VS : out std_logic;
SPI_SCK : in std_logic;
SPI_DI : in std_logic;
SPI_DO : out std_logic;
SPI_SS3 : in std_logic;
CONF_DATA0 : in std_logic;
AUDIO_L : out std_logic;
AUDIO_R : out std_logic
);
end;
architecture RTL of oricatmos is
signal VGA_R_O : std_logic_vector(3 downto 0);
signal VGA_G_O : std_logic_vector(3 downto 0);
signal VGA_B_O : std_logic_vector(3 downto 0);
signal hsync : std_logic;
signal vsync : std_logic;
signal hq2x : std_logic;
signal buttons : std_logic_vector(1 downto 0);
signal switches : std_logic_vector(1 downto 0);
signal status : std_logic_vector(31 downto 0);
signal scandoubler_disable : std_logic;
signal scanlines : std_logic_vector(1 downto 0);
signal ypbpr : std_logic;
signal ps2Clk : std_logic;
signal ps2Data : std_logic;
signal loc_reset_n : std_logic; --active low
signal reset : std_logic := '1';
signal clk24 : std_logic := '0';
signal clk12 : std_logic := '0';
signal clk6 : std_logic := '0';
signal pll_locked : std_logic := '0';
signal CPU_ADDR : std_logic_vector(23 downto 0);
signal CPU_DI : std_logic_vector( 7 downto 0);
signal CPU_DO : std_logic_vector( 7 downto 0);
signal cpu_rw : std_logic;
signal cpu_irq : std_logic;
signal ad : std_logic_vector(15 downto 0);
signal via_pa_out_oe : std_logic_vector( 7 downto 0);
signal via_pa_in : std_logic_vector( 7 downto 0);
signal via_pa_out : std_logic_vector( 7 downto 0);
signal via_cb1_out : std_logic;
signal via_cb1_oe_l : std_logic;
signal via_cb2_out : std_logic;
signal via_cb2_oe_l : std_logic;
signal via_in : std_logic_vector( 7 downto 0);
signal via_out : std_logic_vector( 7 downto 0);
signal via_oe_l : std_logic_vector( 7 downto 0);
signal VIA_DO : std_logic_vector( 7 downto 0);
signal KEY_ROW : std_logic_vector( 7 downto 0);
signal psg_bdir : std_logic;
signal PSG_OUT : std_logic_vector( 7 downto 0);
signal ula_phi2 : std_logic;
signal ula_CSIOn : std_logic;
signal ula_CSIO : std_logic;
signal ula_CSROMn : std_logic;
signal SRAM_DO : std_logic_vector( 7 downto 0);
signal ula_AD_SRAM : std_logic_vector(15 downto 0);
signal ula_CE_SRAM : std_logic;
signal ula_OE_SRAM : std_logic;
signal ula_WE_SRAM : std_logic;
signal ula_LE_SRAM : std_logic;
signal ula_CLK_4 : std_logic;
signal ula_IOCONTROL : std_logic;
signal ula_VIDEO_R : std_logic;
signal ula_VIDEO_G : std_logic;
signal ula_VIDEO_B : std_logic;
signal ula_SYNC : std_logic;
signal ROM_DO : std_logic_vector( 7 downto 0);
signal hs_int : std_logic;
signal vs_int : std_logic;
signal dummy : std_logic_vector( 3 downto 0) := (others => '0');
signal s_cmpblk_n_out : std_logic;
constant CONF_STR : string :=
"ORIC;;O89,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;T6,Reset;";
function to_slv(s: string) return std_logic_vector is
constant ss: string(1 to s'length) := s;
variable rval: std_logic_vector(1 to 8 * s'length);
variable p: integer;
variable c: integer;
begin
for i in ss'range loop
p := 8 * i;
c := character'pos(ss(i));
rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8));
end loop;
return rval;
end function;
component mist_io
generic ( STRLEN : integer := 0 );
port (
clk_sys :in std_logic;
SPI_SCK, CONF_DATA0, SPI_DI :in std_logic;
SPI_DO : out std_logic;
conf_str : in std_logic_vector(8*STRLEN-1 downto 0);
buttons : out std_logic_vector(1 downto 0);
switches : out std_logic_vector(1 downto 0);
joystick_0 : out std_logic_vector(7 downto 0);
joystick_1 : out std_logic_vector(7 downto 0);
status : out std_logic_vector(31 downto 0);
scandoubler_disable, ypbpr : out std_logic;
ps2_kbd_clk : out std_logic;
ps2_kbd_data : out std_logic
);
end component mist_io;
component video_mixer
generic ( LINE_LENGTH : integer := 384; HALF_DEPTH : integer := 1 );
port (
clk_sys, ce_pix, ce_pix_actual : in std_logic;
SPI_SCK, SPI_SS3, SPI_DI : in std_logic;
scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic;
scanlines : in std_logic_vector(1 downto 0);
R, G, B : in std_logic_vector(2 downto 0);
HSync, VSync, line_start, mono : in std_logic;
VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0);
VGA_VS, VGA_HS : out std_logic
);
end component video_mixer;
begin
inst_pll : entity work.pll
port map (
areset => open,
inclk0 => CLOCK_27,
c0 => clk24,
c1 => clk12,
c2 => clk6,
locked => pll_locked
);
loc_reset_n <= pll_locked;
--reset <= not status(0) or status(6) or buttons(1);
inst_cpu : entity work.T65
port map (
Mode => "00",
Res_n => loc_reset_n,
Enable => '1',
Clk => ula_phi2,
Rdy => '1',
Abort_n => '1',
IRQ_n => cpu_irq,
NMI_n => '1',
SO_n => '1',
R_W_n => cpu_rw,
Sync => open,
EF => open,
MF => open,
XF => open,
ML_n => open,
VP_n => open,
VDA => open,
VPA => open,
A => CPU_ADDR,
DI => CPU_DI,
DO => CPU_DO
);
-- place Rom in LE and we can use 48kb Memory
-- inst_rom : entity work.rom
-- port map (
-- clk => clk24,
-- ADDR => CPU_ADDR(13 downto 0),
-- DATA => ROM_DO
-- );
-- place in BRAM and reduce Memory to 16kb see file ram48k
inst_rom : entity work.rrom
port map (
clock => clk24,
address => CPU_ADDR(13 downto 0),
q => ROM_DO
);
ad(15 downto 0) <= ula_AD_SRAM when ula_phi2 = '0' else CPU_ADDR(15 downto 0);
inst_ram : entity work.ram48k
port map(
clk => clk24,
cs => ula_CE_SRAM,
oe => ula_OE_SRAM,
we => ula_WE_SRAM,
addr => ad,
di => CPU_DO,
do => SRAM_DO
);
inst_ula : entity work.ULA
port map (
RESETn => loc_reset_n,
CLK => clk24,
CLK_4 => ula_CLK_4,
RW => cpu_rw,
ADDR => CPU_ADDR(15 downto 0),
MAPn => '1',
DB => SRAM_DO,
CSROMn => ula_CSROMn,
CSIOn => ula_CSIOn,
SRAM_AD => ula_AD_SRAM,
SRAM_OE => ula_OE_SRAM,
SRAM_CE => ula_CE_SRAM,
SRAM_WE => ula_WE_SRAM,
LATCH_SRAM => ula_LE_SRAM,
PHI2 => ula_PHI2,
R => ULA_VIDEO_R,
G => ULA_VIDEO_G,
B => ULA_VIDEO_B,
SYNC => ULA_SYNC,
HSYNC => hs_int,
VSYNC => vs_int
);
vmixer : video_mixer
generic map(
HALF_DEPTH => 1,
LINE_LENGTH => 480
)
port map (
clk_sys => clk24,
ce_pix => clk6,
ce_pix_actual => clk6,
SPI_SCK => SPI_SCK,
SPI_SS3 => SPI_SS3,
SPI_DI => SPI_DI,
hq2x => hq2x,
ypbpr => ypbpr,
ypbpr_full => '1',
scanlines => scanlines,
scandoubler_disable => scandoubler_disable,
R => ULA_VIDEO_R & ULA_VIDEO_R & ULA_VIDEO_R,
G => ULA_VIDEO_G & ULA_VIDEO_G & ULA_VIDEO_G,
B => ULA_VIDEO_B & ULA_VIDEO_B & ULA_VIDEO_B,
HSync => hs_int,
VSync => vs_int,
line_start => '0',
mono => '0',
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_VS => VGA_VS,
VGA_HS => VGA_HS
);
scanlines(1) <= '1' when status(9 downto 8) = "11" and scandoubler_disable = '0' else '0';
scanlines(0) <= '1' when status(9 downto 8) = "10" and scandoubler_disable = '0' else '0';
hq2x <= '1' when status(9 downto 8) = "01" else '0';
mist_io_inst : mist_io
generic map (STRLEN => CONF_STR'length)
port map (
clk_sys => clk24,
SPI_SCK => SPI_SCK,
CONF_DATA0 => CONF_DATA0,
SPI_DI => SPI_DI,
SPI_DO => SPI_DO,
conf_str => to_slv(CONF_STR),
buttons => buttons,
switches => switches,
scandoubler_disable => scandoubler_disable,
ypbpr => ypbpr,
status => status,
ps2_kbd_clk => ps2Clk,
ps2_kbd_data => ps2Data
);
ula_CSIO <= not ula_CSIOn;
inst_via : entity work.M6522
port map (
I_RS => CPU_ADDR(3 downto 0),
I_DATA => CPU_DO(7 downto 0),
O_DATA => VIA_DO,
O_DATA_OE_L => open,
I_RW_L => cpu_rw,
I_CS1 => ula_CSIO,
I_CS2_L => ula_IOCONTROL,
O_IRQ_L => cpu_irq, -- note, not open drain
I_CA1 => '1', -- PRT_ACK
I_CA2 => '1', -- psg_bdir
O_CA2 => psg_bdir, -- via_ca2_out
O_CA2_OE_L => open,
I_PA => via_pa_in,
O_PA => via_pa_out,
O_PA_OE_L => via_pa_out_oe,
-- I_CB1 => K7_TAPEIN,
I_CB1 => '0',
O_CB1 => via_cb1_out,
O_CB1_OE_L => via_cb1_oe_l,
I_CB2 => '1',
O_CB2 => via_cb2_out,
O_CB2_OE_L => via_cb2_oe_l,
I_PB => via_in,
O_PB => via_out,
O_PB_OE_L => via_oe_l,
RESET_L => loc_reset_n,
I_P2_H => ula_phi2,
ENA_4 => '1',
CLK => ula_CLK_4
);
inst_key : entity work.keyboard
port map(
CLK => clk24,
RESET => '0', -- active high reset
PS2CLK => ps2Clk,
PS2DATA => ps2Data,
COL => via_out(2 downto 0),
ROWbit => KEY_ROW
);
via_in <= x"F7" when (KEY_ROW or VIA_PA_OUT) = x"FF" else x"FF";
inst_psg : entity work.YM2149
port map (
I_DA => via_pa_out,
O_DA => via_pa_in,
O_DA_OE_L => open,
I_A9_L => '0',
I_A8 => '1',
I_BDIR => via_cb2_out,
I_BC2 => '1',
I_BC1 => psg_bdir,
I_SEL_L => '1',
O_AUDIO => PSG_OUT,
RESET_L => loc_reset_n,
ENA => '1',
CLK => ula_PHI2
);
inst_dacl : entity work.DAC
port map (
CLK_DAC => clk24,
RST => loc_reset_n,
IN_DAC => PSG_OUT,
OUT_DAC => AUDIO_L
);
inst_dacr : entity work.DAC
port map (
CLK_DAC => clk24,
RST => loc_reset_n,
IN_DAC => PSG_OUT,
OUT_DAC => AUDIO_R
);
ula_IOCONTROL <= '0';
process
begin
wait until rising_edge(clk24);
-- expansion port
if cpu_rw = '1' and ula_IOCONTROL = '1' and ula_CSIOn = '0' then
CPU_DI <= SRAM_DO;
-- Via
elsif cpu_rw = '1' and ula_IOCONTROL = '0' and ula_CSIOn = '0' and ula_LE_SRAM = '0' then
CPU_DI <= VIA_DO;
-- ROM
elsif cpu_rw = '1' and ula_IOCONTROL = '0' and ula_CSROMn = '0' then
CPU_DI <= ROM_DO;
-- Read data
elsif cpu_rw = '1' and ula_IOCONTROL = '0' and ula_phi2 = '1' and ula_LE_SRAM = '0' then
cpu_di <= SRAM_DO;
end if;
end process;
------------------------------------------------------------
-- K7 PORT
------------------------------------------------------------
-- K7_TAPEOUT <= via_out(7);
-- K7_REMOTE <= via_out(6);
-- K7_AUDIOOUT <= AUDIO_OUT;
------------------------------------------------------------
-- PRINTER PORT
------------------------------------------------------------
-- PRT_DATA <= via_pa_out;
-- PRT_STR <= via_out(4);
LED <= '1';
end RTL;

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// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input clk_sys,
// SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
// VGA signals coming from core
input [5:0] R_in,
input [5:0] G_in,
input [5:0] B_in,
input HSync,
input VSync,
// VGA signals going to video connector
output [5:0] R_out,
output [5:0] G_out,
output [5:0] B_out
);
parameter OSD_X_OFFSET = 10'd0;
parameter OSD_Y_OFFSET = 10'd0;
parameter OSD_COLOR = 3'd0;
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS3) begin
reg [4:0] cnt;
reg [10:0] bcnt;
reg [7:0] sbuf;
reg [7:0] cmd;
if(SPI_SS3) begin
cnt <= 0;
bcnt <= 0;
end else begin
sbuf <= {sbuf[6:0], SPI_DI};
// 0:7 is command, rest payload
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], SPI_DI};
// lower three command bits are line address
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
bcnt <= bcnt + 1'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [9:0] h_cnt;
reg [9:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
// vertical counter
reg [9:0] v_cnt;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
wire doublescan = (dsp_height>350);
reg ce_pix;
always @(negedge clk_sys) begin
integer cnt = 0;
integer pixsz, pixcnt;
reg hs;
cnt <= cnt + 1;
hs <= HSync;
pixcnt <= pixcnt + 1;
if(pixcnt == pixsz) pixcnt <= 0;
ce_pix <= !pixcnt;
if(hs && ~HSync) begin
cnt <= 0;
pixsz <= (cnt >> 9) - 1;
pixcnt <= 0;
ce_pix <= 1;
end
end
always @(posedge clk_sys) begin
reg hsD, hsD2;
reg vsD, vsD2;
if(ce_pix) begin
// bring hsync into local clock domain
hsD <= HSync;
hsD2 <= hsD;
// falling edge of HSync
if(!hsD && hsD2) begin
h_cnt <= 0;
hs_high <= h_cnt;
end
// rising edge of HSync
else if(hsD && !hsD2) begin
h_cnt <= 0;
hs_low <= h_cnt;
v_cnt <= v_cnt + 1'd1;
end else begin
h_cnt <= h_cnt + 1'd1;
end
vsD <= VSync;
vsD2 <= vsD;
// falling edge of VSync
if(!vsD && vsD2) begin
v_cnt <= 0;
vs_high <= v_cnt;
end
// rising edge of VSync
else if(vsD && !vsD2) begin
v_cnt <= 0;
vs_low <= v_cnt;
end
end
end
// area in which OSD is being displayed
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
wire [9:0] osd_hcnt = h_cnt - h_osd_start + 1'd1; // one pixel offset for osd_byte register
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
wire osd_de = osd_enable &&
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
reg [7:0] osd_byte;
always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
endmodule

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--
-- A simulation model of ORIC hardware
-- Copyright (c) seilebost - January 2009
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email seilebost@free.fr
--
--
-- Revision list
--
-- version 001 initial release
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package pkg_oric is
component T65
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end component;
component ULA
port (
CLK : in std_logic;
PHI2 : out std_logic;
CLK_4 : out std_logic;
RW : in std_logic;
RESETn : in std_logic;
MAPn : in std_logic;
DB : in std_logic_vector(7 downto 0);
AD : in std_logic_vector(15 downto 0);
AD_RAM : out std_logic_vector(7 downto 0);
AD_SRAM : out std_logic_vector(15 downto 0);
OE_SRAM : out std_logic;
CE_SRAM : out std_logic;
WE_SRAM : out std_logic;
LATCH_SRAM : out std_logic;
RASn : out std_logic;
CASn : out std_logic;
MUX : out std_logic;
RW_RAM : out std_logic;
CSIOn : out std_logic;
CSROMn : out std_logic;
CSRAMn : out std_logic;
R : out std_logic;
G : out std_logic;
B : out std_logic;
SYNC : out std_logic
);
end component;
component M6522 is
port (
RS : in std_logic_vector(3 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_OE_L : out std_logic;
RW_L : in std_logic;
CS1 : in std_logic;
CS2_L : in std_logic;
IRQ_L : out std_logic; -- note, not open drain
CA1_IN : in std_logic;
CA2_IN : in std_logic;
CA2_OUT : out std_logic;
CA2_OUT_OE_L : out std_logic;
PA_IN : in std_logic_vector(7 downto 0);
PA_OUT : out std_logic_vector(7 downto 0);
PA_OUT_OE_L : out std_logic_vector(7 downto 0);
-- port b
CB1_IN : in std_logic;
CB1_OUT : out std_logic;
CB1_OUT_OE_L : out std_logic;
CB2_IN : in std_logic;
CB2_OUT : out std_logic;
CB2_OUT_OE_L : out std_logic;
PB_IN : in std_logic_vector(7 downto 0);
PB_OUT : out std_logic_vector(7 downto 0);
PB_OUT_OE_L : out std_logic_vector(7 downto 0);
RESET_L : in std_logic;
P2_H : in std_logic; -- high for phase 2 clock ____----__
CLK_4 : in std_logic -- 4x system clock (4HZ) _-_-_-_-_-
);
end component;
component AY3819X
port (
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
O_DATA_OE_L : out std_logic;
RESET : in std_logic;
CLOCK : in std_logic;
CLOCK_DAC : in std_logic;
BDIR : in std_logic;
BC1 : in std_logic;
BC2 : in std_logic;
IOA : inout std_logic_vector(7 downto 0);
IOB : inout std_logic_vector(7 downto 0);
AnalogA : out std_logic;
AnalogB : out std_logic;
AnalogC : out std_logic
);
end component;
component ORIC_PS2_IF
port (
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
COL_IN : in std_logic_vector(7 downto 0);
ROW_IN : in std_logic_vector(7 downto 0);
RESTORE : out std_logic;
RESET_L : in std_logic;
ENA_1MHZ : in std_logic;
P2_H : in std_logic; -- high for phase 2 clock ____----__
CLK_4 : in std_logic -- 4x system clock (4HZ) _-_-_-_-_-
);
end component;
component ORIC_CHAR_ROM
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end component;
component ORIC_BASIC_ROM
port (
CLK : in std_logic;
ADDR : in std_logic_vector(12 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end component;
component ORIC_KERNAL_ROM
port (
CLK : in std_logic;
ADDR : in std_logic_vector(12 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end component;
component ORIC_RAMS
port (
V_ADDR : in std_logic_vector(9 downto 0);
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0);
V_RW_L : in std_logic;
CS_L : in std_logic; -- used for write enable gate only
CLK : in std_logic
);
end component;
component keyboard
port (
CLK : in std_logic;
RESET : in std_logic;
PS2CLK : in std_logic;
PS2DATA : in std_logic;
COL : in std_logic_vector(2 downto 0);
ROWbit : out std_logic_vector(7 downto 0)
);
end component;
component file_log
generic (
log_file: string := "res.log"
);
port(
CLK : in std_logic;
RST : in std_logic;
x1 : in std_logic_vector(7 downto 0);
x2 : in std_logic_vector(7 downto 0);
x3 : in std_logic_vector(15 downto 0);
x4 : in std_logic_vector(2 downto 0);
x5 : in std_logic
);
end component;
component psg_log
generic (
log_psg: string := "psg.log"
);
port(
CLK : in std_logic;
RST : in std_logic;
x1 : in std_logic
);
end component;
component ula_log
generic (
log_ula: string := "ula.log"
);
port(
CLK : in std_logic;
RST : in std_logic;
x1 : in std_logic_vector(7 downto 0);
x2 : in std_logic_vector(15 downto 0);
x3 : in std_logic
);
end component;
end pkg_oric;
package body pkg_ORIC is
end pkg_oric;

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-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package pack_t65 is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
component T65_MCode
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out std_logic_vector(3 downto 0);
Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end component;
component T65_ALU
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end component;
end;

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--
-- ula_pkg.vhd
--
-- Package of ULA
--
-- Copyright (C)2001 - 2005 SEILEBOST
-- All rights reserved.
--
-- $Id: ula_pkg.vhd, v0.02 2005/01/01 00:00:00 SEILEBOST $
--
-- TODO :
-- Remark :
library ieee;
use ieee.std_logic_1164.all;
package pack_ula is
component video port (
RESETn : in std_logic;
CLK_PIXEL : in std_logic;
CLK_FLASH : in std_logic;
-- delete 17/11/2009 FLASH_SEL : in std_logic;
BLANKINGn : in std_logic;
RELOAD_SEL : in std_logic;
DATABUS : in std_logic_vector(7 downto 0);
ATTRIB_DEC : in std_logic;
DATABUS_EN : in std_logic;
LDFROMBUS : in std_logic;
LD_REG_0 : in std_logic;
RELD_REG : in std_logic;
CHROWCNT : in std_logic_vector(2 downto 0);
RGB : out std_logic_vector(2 downto 0);
FREQ_SEL : out std_logic;
TXTHIR_SEL : out std_logic;
isAttrib : out std_logic;
DBLSTD_SEL : out std_logic;
VAP2 : out std_logic_vector(15 downto 0) );
end component;
component iodecode port (
RESETn : in std_logic;
CLK_1 : in std_logic;
ADDR : in std_logic_vector(15 downto 0);
ADDR_LE : in std_logic;
MAPn : in std_logic;
CSROMn : out std_logic;
CSRAMn : out std_logic;
CSIOn : out std_logic);
end component;
component memmap port (
TXTHIR_SEL : in std_logic;
DBLHGT_SEL : in std_logic;
FORCETXT : in std_logic;
CPT_H : in std_logic_vector(6 downto 0);
CPT_V : in std_logic_vector(8 downto 0);
VAP1 : out std_logic_vector(15 downto 0);
CHROWCNT : out std_logic_vector(2 downto 0);
TXTHIR_DEC : out std_logic );
end component;
component vag port (
CLK_1 : in std_logic;
RESETn : in std_logic;
FREQ_SEL : in std_logic;
CPT_H : out std_logic_vector(6 downto 0);
CPT_V : out std_logic_vector(8 downto 0);
RELOAD_SEL : out std_logic;
FORCETXT : out std_logic;
CLK_FLASH : out std_logic;
COMPSYNC : out std_logic;
BLANKINGn : out std_logic);
end component;
component ctrlseq port (
RESETn : in std_logic;
CLK_24 : in std_logic;
TXTHIR_DEC : in std_logic;
isAttrib : in std_logic;
iRW : in std_logic;
CSRAMn : in std_logic;
CLK_1_CPU : out std_logic;
CLK_4 : out std_logic;
CLK_6 : out std_logic;
VA1L : out std_logic;
VA1R : out std_logic;
VA1C : out std_logic;
VA2L : out std_logic;
VA2R : out std_logic;
VA2C : out std_logic;
BAC : out std_logic;
BAL : out std_logic;
RAS : out std_logic;
CAS : out std_logic;
MUX : out std_logic;
oRW : out std_logic;
ATTRIB_DEC : out std_logic;
LD_REG_0 : out std_logic;
LD_REG : out std_logic;
LDFROMBUS : out std_logic;
DATABUS_EN : out std_logic;
-- ajout du 09/02/09
BAOE : out std_logic;
-- ajout du 03/04/09
SRAM_CE : out std_logic;
SRAM_OE : out std_logic;
SRAM_WE : out std_logic;
LATCH_SRAM : out std_logic
);
end component;
component addmemux port (
RESETn : in std_logic;
VAP1 : in std_logic_vector(15 downto 0);
VAP2 : in std_logic_vector(15 downto 0);
BAP : in std_logic_vector(15 downto 0);
VA1L : in std_logic;
VA1R : in std_logic;
VA1C : in std_logic;
VA2L : in std_logic;
VA2R : in std_logic;
VA2C : in std_logic;
BAC : in std_logic;
BAL : in std_logic;
AD_DYN : out std_logic_vector(15 downto 0) );
end component;
component gen_clock port (
RESETn : in std_logic;
CLK_12 : in std_logic;
CLK_24 : out std_logic;
CLK_12_INT : out std_logic;
CLK_PIXEL_INT : out std_logic );
end component;
end pack_ula;

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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

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-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 9,
clk0_duty_cycle => 50,
clk0_multiply_by => 8,
clk0_phase_shift => "0",
clk1_divide_by => 9,
clk1_duty_cycle => 50,
clk1_multiply_by => 4,
clk1_phase_shift => "0",
clk2_divide_by => 9,
clk2_duty_cycle => 50,
clk2_multiply_by => 2,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

120
Oric Atmos_MiST/rtl/ps2key.vhd Normal file
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-- base sur les infos des pages suivantes :
-- http://www.computer-engineering.org/ps2protocol/
-- http://www.computer-engineering.org/ps2keyboard/
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ps2key is
generic (
FREQ : integer := 24
);
port(
CLK : in std_logic;
RESET : in std_logic;
PS2CLK : in std_logic;
PS2DATA : in std_logic;
BREAK : out std_logic;
EXTENDED : out std_logic;
CODE : out std_logic_vector(6 downto 0);
LATCH : out std_logic
);
end ps2key;
architecture rtl of ps2key is
constant CLKCNT_SAMPLE : integer := FREQ * 20; -- 20us apres transition de l'horloge
-- Sampling
signal clkcnt : std_logic_vector(15 downto 0);
signal shift : std_logic;
signal idlcnt : std_logic_vector(15 downto 0);
-- Shifting
signal bitcnt : std_logic_vector(3 downto 0);
signal cready : std_logic;
signal char : std_logic_vector(10 downto 0);
-- Decodage
signal brkcode : std_logic;
signal extcode : std_logic;
-- Signal de controle
signal kready : std_logic;
begin
process(RESET, CLK, PS2CLK, PS2DATA)
begin
if RESET = '1' then
clkcnt <= (others => '0');
shift <= '0';
bitcnt <= x"0";
cready <= '0';
char <= (others => '0');
brkcode <= '0';
extcode <= '0';
kready <= '0';
elsif rising_edge(CLK) then
-- Sampling des bits
if PS2CLK = '1' then
shift <= '0';
clkcnt <= (others => '0');
else
clkcnt <= clkcnt + 1;
if clkcnt = CLKCNT_SAMPLE then
shift <= '1';
else
shift <= '0';
end if;
end if;
-- Bit-shifting
if shift = '1' then
char <= PS2DATA & char(10 downto 1);
if bitcnt = x"A" then
bitcnt <= x"0";
cready <= '1';
else
bitcnt <= bitcnt + 1;
end if;
end if;
-- Decodage sequence
if cready = '1' then
cready <= '0';
if char(8 downto 1) = x"E0" then
extcode <= '1';
kready <= '0';
elsif char(8 downto 1) = x"F0" then
brkcode <= '1';
kready <= '0';
elsif char(8) = '1' then -- les codes > 0x7F sont reserves apparemment
kready <= '0';
else
kready <= '1';
end if;
else
if kready = '1' then
brkcode <= '0';
extcode <= '0';
kready <= '0';
end if;
end if;
end if;
end process;
BREAK <= brkcode;
EXTENDED <= extcode;
CODE <= char(7 downto 1);
LATCH <= kready;
end rtl;

3
Oric Atmos_MiST/rtl/ram16k.qip Normal file
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@@ -0,0 +1,3 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ram16k.vhd"]

160
Oric Atmos_MiST/rtl/ram16k.vhd Normal file
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@@ -0,0 +1,160 @@
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram16k.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY ram16k IS
PORT
(
address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rden : IN STD_LOGIC := '1';
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram16k;
ARCHITECTURE SYN OF ram16k IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 16384,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 14,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
rden_a => rden,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram16k.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram16k.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram16k.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram16k.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram16k_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ram32k.vhd"]

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-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram32k.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY ram32k IS
PORT
(
address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram32k;
ARCHITECTURE SYN OF ram32k IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "NORMAL",
clock_enable_output_a => "NORMAL",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 32768,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 15,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
clocken0 => clken,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: Clken NUMERIC "1"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram32k.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram32k.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram32k.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram32k.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram32k_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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--
-- 48K RAM comprised of three smaller 16K RAMs
--
-- (c) 2012 d18c7db(a)hotmail
--
-- This program is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License version 3 or, at your option,
-- any later version as published by the Free Software Foundation.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--
-- For full details, see the GNU General Public License at www.gnu.org/licenses
-- Changed for Mist FPGA Gehstock(2018)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ram48k is
port (
clk : in std_logic;
cs : in std_logic;
oe : in std_logic;
we : in std_logic;
addr : in std_logic_vector(15 downto 0);
di : in std_logic_vector( 7 downto 0);
do : out std_logic_vector( 7 downto 0)
);
end;
architecture RTL of ram48k is
signal ro0, ro1, ro2, ro3 : std_logic_vector(7 downto 0);
signal cs0, cs1, cs2, cs3 : std_logic := '0';
begin
cs0 <= '1';
-- cs0 <= '1' when cs='1' and addr(15 downto 14)="00" else '0';
-- cs1 <= '1' when cs='1' and addr(15 downto 14)="01" else '0';
-- cs2 <= '1' when cs='1' and addr(15 downto 14)="10" else '0';
-- cs3 <= '1' when cs='1' and addr(15 downto 14)="11" else '0';
do <= ro0;
-- ro0 when oe='1' and cs0='1' else
-- ro1 when oe='1' and cs1='1' else
-- ro2 when oe='1' and cs2='1' else
-- ro3 when oe='1' and cs3='1' else
-- (others=>'0');
--16kb
RAM_0000_3FFF : entity work.spram
port map (
clk_i => clk,
we_i => cs0 and we,
addr_i => addr(13 downto 0),
data_i => di,
data_o => ro0
);
--32kb
-- RAM_4000_7FFF : entity work.spram
-- port map (
-- clk_i => clk,
-- we_i => cs1 and we,
-- addr_i => addr(13 downto 0),
-- data_i => di,
-- data_o => ro1
-- );
--48kb
-- RAM_8000_BFFF : entity work.spram
-- port map (
-- clk_i => clk,
-- we_i => cs2 and we,
-- addr_i => addr(13 downto 0),
-- data_i => di,
-- data_o => ro2
-- );
--64kb
-- RAM_C000_FFFF : entity work.spram
-- port map (
-- clk_i => clk,
-- we_i => cs3 and we,
-- addr_i => addr(13 downto 0),
-- data_i => di,
-- data_o => ro3
-- );
end RTL;

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@echo off
cls
echo Generating intermediate file from : basic11b : rom.vhd
romgen.exe basic11b.rom rom 14 a \n e > rom.vhd
pause

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Oric Atmos_MiST/rtl/roms/basic11b.rom Normal file
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Oric Atmos_MiST/rtl/roms/key1.hex Normal file
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@@ -0,0 +1,3 @@
:020000040000FA
:2000000000140800000000000000000000000000004000402E3400000000004E7C760000A2
:00000001FF

3
Oric Atmos_MiST/rtl/roms/key2.hex Normal file
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@@ -0,0 +1,3 @@
:020000040000FA
:2000000000340000000000000000000000000000000000002834763000146C7E6820000024
:00000001FF

3
Oric Atmos_MiST/rtl/roms/key3.hex Normal file
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@@ -0,0 +1,3 @@
:020000040000FA
:20000000003008000000000000000000000000000040004004346C4A004A1C7A34400000E6
:00000001FF

3
Oric Atmos_MiST/rtl/roms/key4.hex Normal file
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@@ -0,0 +1,3 @@
:020000040000FA
:2000000000340800000000000000000000000000000000400E302E3A5038021038060000E6
:00000001FF

3
Oric Atmos_MiST/rtl/roms/key5.hex Normal file
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@@ -0,0 +1,3 @@
:020000040000FA
:20000000000000000000000000000000000000000000000026245C64447C00327C10000058
:00000001FF

3
Oric Atmos_MiST/rtl/roms/key6.hex Normal file
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@@ -0,0 +1,3 @@
:020000040000FA
:2000000000000000000000000000000000000000004000402E347C7C58003808002200004C
:00000001FF

3
Oric Atmos_MiST/rtl/roms/key7.hex Normal file
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@@ -0,0 +1,3 @@
:020000040000FA
:2000000000000000000000000000000000000000004000402E347C7C58003808002200004C
:00000001FF

BIN
Oric Atmos_MiST/rtl/roms/romgen.exe Normal file
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3
Oric Atmos_MiST/rtl/rrom.qip Normal file
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@@ -0,0 +1,3 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rrom.vhd"]

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Oric Atmos_MiST/rtl/rrom.vhd Normal file
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-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: rrom.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY rrom IS
PORT
(
address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END rrom;
ARCHITECTURE SYN OF rrom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "./roms/basic11b.hex",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 16384,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 14,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "./roms/basic11b.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/basic11b.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL rrom.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rrom.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rrom.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rrom.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rrom_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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Oric Atmos_MiST/rtl/scan_converter.vhd Normal file
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-- (c) 2012 d18c7db(a)hotmail
--
-- This program is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License version 3 or, at your option,
-- any later version as published by the Free Software Foundation.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--
-- For full details, see the GNU General Public License at www.gnu.org/licenses
--------------------------------------------------------------------------------
-- Video scan converter
--
-- Horizonal Timing
-- _____________ ______________________ _____________________
-- VIDEO (last) |____________| VIDEO |____________| VIDEO (next)
-- -hD----------|-hA-|hB|-hC-|----------hD----------|-hA-|hB|-hC-|----------hD---------
-- __________________| |________________________________| |__________________________
-- HSYNC |__| HSYNC |__| HSYNC
-- Vertical Timing
-- _____________ ______________________ _____________________
-- VIDEO (last)||____________||||||||||VIDEO|||||||||____________||||||||||VIDEO (next)
-- -vD----------|-vA-|vB|-vC-|----------vD----------|-vA-|vB|-vC-|----------vD---------
-- __________________| |________________________________| |__________________________
-- VSYNC |__| VSYNC |__| VSYNC
-- Scan converter input and output timings compared to standard VGA
-- Resolution - Frame | Pixel | Front | HSYNC | Back | Active | HSYNC | Front | VSYNC | Back | Active | VSYNC
-- - Rate | Clock | Porch hA | Pulse hB | Porch hC | Video hD | Polarity | Porch vA | Pulse vB | Porch vC | Video vD | Polarity
-------------------------------------------------------------------------------------------------------------------------------------------------------------
-- In 256x224 - 59.18Hz | 6.000 MHz | 38 pixels | 32 pixels | 58 pixels | 256 pixels | negative | 16 lines | 8 lines | 16 lines | 224 lines | negative
-- Out 640x480 - 59.18Hz | 24.000 MHz | 2 pixels | 92 pixels | 34 pixels | 640 pixels | negative | 17 lines | 2 lines | 29 lines | 480 lines | negative
-- VGA 640x480 - 59.94Hz | 25.175 MHz | 16 pixels | 96 pixels | 48 pixels | 640 pixels | negative | 10 lines | 2 lines | 33 lines | 480 lines | negative
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--pragma translate_off
use ieee.std_logic_textio.all;
use std.textio.all;
--pragma translate_on
entity VGA_SCANCONV is
generic (
cstart : integer range 0 to 1023 := 144; -- composite sync start
clength : integer range 0 to 1023 := 640; -- composite sync length
hA : integer range 0 to 1023 := 16; -- h front porch
hB : integer range 0 to 1023 := 96; -- h sync
hC : integer range 0 to 1023 := 48; -- h back porch
hD : integer range 0 to 1023 := 640; -- visible video
-- vA : integer range 0 to 1023 := 16; -- v front porch
vB : integer range 0 to 1023 := 2; -- v sync
vC : integer range 0 to 1023 := 33; -- v back porch
vD : integer range 0 to 1023 := 480; -- visible video
hpad : integer range 0 to 1023 := 0; -- H black border
vpad : integer range 0 to 1023 := 0 -- V black border
);
port (
I_VIDEO : in std_logic_vector(15 downto 0);
I_HSYNC : in std_logic;
I_VSYNC : in std_logic;
--
O_VIDEO : out std_logic_vector(15 downto 0);
O_HSYNC : out std_logic;
O_VSYNC : out std_logic;
O_CMPBLK_N : out std_logic;
--
CLK : in std_logic;
CLK_x2 : in std_logic
);
end;
architecture RTL of VGA_SCANCONV is
--
-- input timing
--
signal ivsync_last_x2 : std_logic := '1';
signal ihsync_last : std_logic := '1';
signal hpos_i : std_logic_vector( 9 downto 0) := (others => '0');
--
-- output timing
--
signal hpos_o : std_logic_vector(9 downto 0) := (others => '0');
signal vcnt : integer range 0 to 1023 := 0;
signal hcnt : integer range 0 to 1023 := 0;
signal hcnti : integer range 0 to 1023 := 0;
signal CLK_x2_n : std_logic := '1';
begin
-- dual port line buffer, max line of 1024 pixels
u_ram : entity work.RAMB16_S18_S18
-- generic map (INIT_A => X"00000", INIT_B => X"00000", SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
port map (
-- input
q_a => open,
data_a => I_VIDEO,
address_a => hpos_i,
wren_a => '1',
rden_a => CLK,
clock_a => CLK_x2,
-- output
q_b => O_VIDEO,
data_b => x"0000",
address_b => hpos_o,
wren_b => '0',
rden_b => '1',
clock_b => CLK_x2_n
);
CLK_x2_n <= not CLK_x2;
-- horizontal counter for input video
p_hcounter : process
begin
wait until rising_edge(CLK_x2);
if CLK = '0' then
ihsync_last <= I_HSYNC;
-- trigger off rising hsync
if I_HSYNC = '1' and ihsync_last = '0' then
hcnti <= 0;
else
hcnti <= hcnti + 1;
end if;
end if;
end process;
-- increment write position during active video
p_ram_in : process
begin
wait until rising_edge(CLK_x2);
if CLK = '0' then
if (hcnti < cstart) or (hcnti >= (cstart + clength)) then
hpos_i <= (others => '0');
else
hpos_i <= hpos_i + 1;
end if;
end if;
end process;
-- VGA H and V counters, synchronized to input frame V sync, then H sync
p_out_ctrs : process
variable trigger : boolean;
begin
wait until rising_edge(CLK_x2);
ivsync_last_x2 <= I_VSYNC;
if (I_VSYNC = '0') and (ivsync_last_x2 = '1') then
trigger := true;
elsif trigger and I_HSYNC = '0' then
trigger := false;
hcnt <= 0;
vcnt <= 0;
else
hcnt <= hcnt + 1;
if hcnt = (hA+hB+hC+hD+hpad+hpad-1) then
hcnt <= 0;
vcnt <= vcnt + 1;
end if;
end if;
end process;
-- generate hsync
p_gen_hsync : process
begin
wait until rising_edge(CLK_x2);
-- H sync timing
if (hcnt < hB) then
O_HSYNC <= '0';
else
O_HSYNC <= '1';
end if;
end process;
-- generate vsync
p_gen_vsync : process
begin
wait until rising_edge(CLK_x2);
-- V sync timing
if (vcnt < vB) then
O_VSYNC <= '0';
else
O_VSYNC <= '1';
end if;
end process;
-- generate active output video
p_gen_active_vid : process
begin
wait until rising_edge(CLK_x2);
-- visible video area doubled from the original game
if ((hcnt >= (hB + hC + hpad)) and (hcnt < (hB + hC + hD + hpad))) and ((vcnt > 2*(vB + vC + vpad)) and (vcnt <= 2*(vB + vC + vD + vpad))) then
hpos_o <= hpos_o + 1;
else
hpos_o <= (others => '0');
end if;
end process;
-- generate blanking signal including additional borders to pad the input signal to standard VGA resolution
p_gen_blank : process
begin
wait until rising_edge(CLK_X2);
-- active video area 640x480 (VGA) after padding with blank borders
if ((hcnt >= (hB + hC)) and (hcnt < (hB + hC + hD + 2*hpad))) and ((vcnt > 2*(vB + vC)) and (vcnt <= 2*(vB + vC + vD + 2*vpad))) then
O_CMPBLK_N <= '1';
else
O_CMPBLK_N <= '0';
end if;
end process;
end architecture RTL;

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//
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
// TODO: Delay vsync one line
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
(
// system interface
input clk_sys,
input ce_pix,
input ce_pix_actual,
input hq2x,
// shifter video interface
input hs_in,
input vs_in,
input line_start,
input [DWIDTH:0] r_in,
input [DWIDTH:0] g_in,
input [DWIDTH:0] b_in,
input mono,
// output interface
output reg hs_out,
output vs_out,
output [DWIDTH:0] r_out,
output [DWIDTH:0] g_out,
output [DWIDTH:0] b_out
);
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
assign vs_out = vs_in;
reg [2:0] phase;
reg [2:0] ce_div;
reg [7:0] pix_len = 0;
wire [7:0] pl = pix_len + 1'b1;
reg ce_x1, ce_x4;
reg req_line_reset;
wire ls_in = hs_in | line_start;
always @(negedge clk_sys) begin
reg old_ce;
reg [2:0] ce_cnt;
reg [7:0] pixsz2, pixsz4 = 0;
old_ce <= ce_pix;
if(~&pix_len) pix_len <= pix_len + 1'd1;
ce_x4 <= 0;
ce_x1 <= 0;
// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
phase <= phase + 1'd1;
ce_x4 <= 1;
end
if(~old_ce & ce_pix) begin
pixsz2 <= {1'b0, pl[7:1]};
pixsz4 <= {2'b00, pl[7:2]};
ce_x1 <= 1;
ce_x4 <= 1;
pix_len <= 0;
phase <= phase + 1'd1;
ce_cnt <= ce_cnt + 1'd1;
if(ce_pix_actual) begin
phase <= 0;
ce_div <= ce_cnt + 1'd1;
ce_cnt <= 0;
req_line_reset <= 0;
end
if(ls_in) req_line_reset <= 1;
end
end
reg ce_sd;
always @(*) begin
case(ce_div)
2: ce_sd = !phase[0];
4: ce_sd = !phase[1:0];
default: ce_sd <= 1;
endcase
end
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <=1024 ? 9 : 10 )
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
.ce_x4(ce_x4 & ce_sd),
.inputpixel({b_in,g_in,r_in}),
.mono(mono),
.disable_hq2x(~hq2x),
.reset_frame(vs_in),
.reset_line(req_line_reset),
.read_y(sd_line),
.read_x(sd_h_actual),
.outpixel({b_out,g_out,r_out})
);
reg [10:0] sd_h_actual;
always @(*) begin
case(ce_div)
2: sd_h_actual = sd_h[10:1];
4: sd_h_actual = sd_h[10:2];
default: sd_h_actual = sd_h;
endcase
end
reg [10:0] sd_h;
reg [1:0] sd_line;
always @(posedge clk_sys) begin
reg [11:0] hs_max,hs_rise,hs_ls;
reg [10:0] hcnt;
reg [11:0] sd_hcnt;
reg hs, hs2, vs, ls;
if(ce_x1) begin
hs <= hs_in;
ls <= ls_in;
if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
// falling edge of hsync indicates start of line
if(hs && !hs_in) begin
hs_max <= {hcnt,1'b1};
hcnt <= 0;
if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
end else begin
hcnt <= hcnt + 1'd1;
end
// save position of rising edge
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
vs <= vs_in;
if(vs && ~vs_in) sd_line <= 0;
end
if(ce_x4) begin
hs2 <= hs_in;
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1'd1;
sd_h <= sd_h + 1'd1;
if(hs2 && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 0;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_out <= 0;
if(sd_hcnt == hs_rise) hs_out <= 1;
if(sd_hcnt == hs_ls) sd_h <= 0;
if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1;
end
end
endmodule

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-------------------------------------------------------------------------------
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
--
-- Generic single port RAM.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity spram is
generic (
addr_width_g : integer := 14;
data_width_g : integer := 8
);
port (
clk_i : in std_logic;
we_i : in std_logic;
addr_i : in std_logic_vector(addr_width_g-1 downto 0);
data_i : in std_logic_vector(data_width_g-1 downto 0);
data_o : out std_logic_vector(data_width_g-1 downto 0)
);
end spram;
library ieee;
use ieee.numeric_std.all;
architecture rtl of spram is
type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0);
signal ram_q : ram_t
-- pragma translate_off
:= (others => (others => '0'))
-- pragma translate_on
;
signal read_addr_q : unsigned(addr_width_g-1 downto 0);
begin
process (clk_i)
begin
if rising_edge(clk_i) then
if we_i = '1' then
ram_q(to_integer(unsigned(addr_i))) <= data_i;
end if;
read_addr_q <= unsigned(addr_i);
end if;
end process;
data_o <= ram_q(to_integer(read_addr_q));
end rtl;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sprom IS
GENERIC
(
init_file : string := "";
numwords_a : natural := 0; -- not used any more
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END sprom;
ARCHITECTURE SYN OF sprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;

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-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 more merging
-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02 and 65C816 modes are incomplete
-- Undocumented instructions are not supported
-- Some interface signals behaves incorrect
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_t65.all;
-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
-- the ready signal to limit the CPU.
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Write_Data_r : std_logic_vector(2 downto 0);
signal Set_Addr_To_r : std_logic_vector(1 downto 0);
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal B_o : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(2 downto 0);
signal Set_Addr_To : std_logic_vector(1 downto 0);
signal Write_Data : std_logic_vector(2 downto 0);
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal really_rdy : std_logic;
signal R_W_n_i : std_logic;
begin
-- ehenciak : gate Rdy with read/write to make an "OK, it's
-- really OK to stop the processor now if Rdy is
-- deasserted" signal
really_rdy <= Rdy or not(R_W_n_i);
-- ehenciak : Drive R_W_n_i off chip.
R_W_n <= R_W_n_i;
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= "000" else '0'; -- Incorrect !!!!!!!!!!!!
VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
mcode : T65_MCode
port map(
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
Write => Write
);
alu : T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
process (Res_n, Clk)
begin
if Res_n = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= "1100";
Write_Data_r <= "000";
Set_Addr_To_r <= "00";
R_W_n_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
R_W_n_i <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= "00";
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if LDS = '1' then
S(7 downto 0) <= unsigned(ALU_Q);
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Clk)
begin
if Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
-- assert false report "Chargement A" severity warning;
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
P <= P_Out;
end if;
end if;
if SaveP = '1' then
P <= P_Out;
end if;
if LDP = '1' then
P <= ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>
P(Flag_C) <= '0';
when "001" =>
P(Flag_C) <= '1';
when "010" =>
P(Flag_I) <= '0';
when "011" =>
P(Flag_I) <= '1';
when "101" =>
P(Flag_V) <= '0';
when "110" =>
P(Flag_D) <= '0';
when "111" =>
P(Flag_D) <= '1';
when others =>
end case;
end if;
if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
P(Flag_B) <= '1';
end if;
if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
P(Flag_I) <= '1';
P(Flag_B) <= B_o;
end if;
if SO_n_o = '1' and SO_n = '0' then
P(Flag_V) <= '1';
end if;
if RstCycle = '1' and Mode_r /= "00" then
P(Flag_1) <= '1';
P(Flag_D) <= '0';
P(Flag_I) <= '1';
end if;
P(Flag_1) <= '1';
B_o <= P(Flag_B);
SO_n_o <= SO_n;
IRQ_n_o <= IRQ_n;
NMI_n_o <= NMI_n;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (Rdy = '1') then
BusA_r <= BusA;
BusB <= DI;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- ehenciak : modified to use Y register as well (bugfix)
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' then
BAL(2 downto 0) <= "010";
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = "11" then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <= DI when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
(others => '-') when others;
with Set_Addr_To_r select
A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
DBR & "00000000" & AD when "10",
"00000000" & BAH & BAL(7 downto 0) when "11",
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
with Write_Data_r select
DO <= DL when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
std_logic_vector(PC(7 downto 0)) when "110",
std_logic_vector(PC(15 downto 8)) when others;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' then
NMICycle <= '1';
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
if NMICycle = '1' then
NMIAct <= '0';
end if;
if NMI_n_o = '1' and NMI_n = '0' then
NMIAct <= '1';
end if;
end if;
end if;
end if;
end process;
end;

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-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 6502 compatible microprocessor core
--
-- Version : 0245
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
-- 0245 : First version
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_t65.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end T65_ALU;
architecture rtl of T65_ALU is
-- AddSub variables (temporary signals)
signal ADC_Z : std_logic;
signal ADC_C : std_logic;
signal ADC_V : std_logic;
signal ADC_N : std_logic;
signal ADC_Q : std_logic_vector(7 downto 0);
signal SBC_Z : std_logic;
signal SBC_C : std_logic;
signal SBC_V : std_logic;
signal SBC_N : std_logic;
signal SBC_Q : std_logic_vector(7 downto 0);
begin
process (P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
begin
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
ADC_Z <= '1';
else
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
C := AL(6) or AL(5);
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
ADC_N <= AH(4);
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-- pragma translate_off
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
ADC_C <= AH(6) or AH(5);
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
begin
C := P_In(Flag_C) or not Op(0);
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
SBC_Z <= '1';
else
SBC_Z <= '0';
end if;
SBC_C <= not AH(5);
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
SBC_N <= AH(4);
if P_In(Flag_D) = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
if AH(5) = '1' then
AH(5 downto 1) := AH(5 downto 1) - 6;
end if;
end if;
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
variable Q_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
case Op(3 downto 0) is
when "0000" =>
-- ORA
Q_t := BusA or BusB;
when "0001" =>
-- AND
Q_t := BusA and BusB;
when "0010" =>
-- EOR
Q_t := BusA xor BusB;
when "0011" =>
-- ADC
P_Out(Flag_V) <= ADC_V;
P_Out(Flag_C) <= ADC_C;
Q_t := ADC_Q;
when "0101" | "1101" =>
-- LDA
when "0110" =>
-- CMP
P_Out(Flag_C) <= SBC_C;
when "0111" =>
-- SBC
P_Out(Flag_V) <= SBC_V;
P_Out(Flag_C) <= SBC_C;
Q_t := SBC_Q;
when "1000" =>
-- ASL
Q_t := BusA(6 downto 0) & "0";
P_Out(Flag_C) <= BusA(7);
when "1001" =>
-- ROL
Q_t := BusA(6 downto 0) & P_In(Flag_C);
P_Out(Flag_C) <= BusA(7);
when "1010" =>
-- LSR
Q_t := "0" & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1011" =>
-- ROR
Q_t := P_In(Flag_C) & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1100" =>
-- BIT
P_Out(Flag_V) <= BusB(6);
when "1110" =>
-- DEC
Q_t := std_logic_vector(unsigned(BusA) - 1);
when "1111" =>
-- INC
Q_t := std_logic_vector(unsigned(BusA) + 1);
when others =>
end case;
case Op(3 downto 0) is
when "0011" =>
P_Out(Flag_N) <= ADC_N;
P_Out(Flag_Z) <= ADC_Z;
when "0110" | "0111" =>
P_Out(Flag_N) <= SBC_N;
P_Out(Flag_Z) <= SBC_Z;
when "0100" =>
when "1100" =>
P_Out(Flag_N) <= BusB(7);
if (BusA and BusB) = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when others =>
P_Out(Flag_N) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
end case;
Q <= Q_t;
end process;
end;

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--
-- TONE_GENERATOR.vhd
--
-- Generator a tone.
--
-- Copyright (C)2001 SEILEBOST
-- All rights reserved.
--
-- $Id: TONE_GENERATOR.vhd, v0.2 2001/11/02 00:00:00 SEILEBOST $
--
-- Question : if WR is set To add one to count ?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TONE_GENERATOR is
Port ( CLK : in std_logic;
RST : in std_logic;
WR : in std_logic;
CS_COARSE : in std_logic;
CS_FINE : in std_logic;
DATA_COARSE : in std_logic_vector(7 downto 0);
DATA_FINE : in std_logic_vector(7 downto 0);
OUT_TONE : inout std_logic );
end TONE_GENERATOR;
architecture Behavioral of TONE_GENERATOR is
SIGNAL COUNT : std_logic_vector(15 downto 0);
begin
PROCESS(CLK, RST,CS_COARSE, CS_FINE)
BEGIN
if (RST = '1') then
COUNT <= "0000000000000000";
OUT_TONE <= '0';
elsif (CLK'event and CLK = '1') then
if (WR = '1') then
if (CS_FINE = '1') then
COUNT(7 downto 0) <= DATA_FINE;
elsif (CS_COARSE = '1') then
COUNT(15 downto 8) <= DATA_COARSE;
end if;
else
if (COUNT = "0000000000000000") then
COUNT(15 downto 8) <= DATA_COARSE;
COUNT(7 downto 0) <= DATA_FINE;
OUT_TONE <= NOT OUT_TONE;
else
COUNT <= COUNT - 1;
end if;
end if;
end if;
end process;
end Behavioral;

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--
-- A simulation model of ULA
-- Copyright (c) seilebost - 2001 - 2009
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email seilebost@free.fr
--
--
--
--
-- 2013 Significant rewrite by d18c7db(a)hotmail
--
-- Combined all ULA submodules into one file
-- Elliminated gated clocks
-- Overall simplified and streamlined RTL
-- Reduced number of synthesis warnings
-- Fixed attribute decoding
-- Fixed phase1/phase2 address generation
-- Changes in timing signal generation
-- Fixed attributes not alligned to characters on screen
-- Implemented 50/60Hz attribute
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- ULA pinout
-- 1 MUX U RAM_D1 40
-- 2 RAM_D2 RAM_D0 39
-- 3 RAM_D3 RAM_D7 38
-- 4 RAM_D4 RAM_D5 37
-- 5 D5 RAM_D6 36
-- 6 GND A12 35
-- 7 CLK D6 34
-- 8 D0 A09 33
-- 9 CAS A08 32
-- 10 RAS A10 31
-- 11 D2 A15 30
-- 12 D3 A14 29
-- 13 D4 RAM_R/W 28
-- 14 PHI R/W 27
-- 15 A11 MAP 26
-- 16 SYNC I/O 25
-- 17 D1 Vcc 24
-- 18 D7 ROM_CS 23
-- 19 BLU A13 22
-- 20 GRN RED 21
entity ula is
port (
RESETn : in std_logic; -- RESET master
CLK_4 : out std_logic; -- 4 MHz internal
CLK : in std_logic; -- 24 MHz -- pin 07
PHI2 : out std_logic; -- 1 MHz CPU & system -- pin 14
RW : in std_logic; -- R/W from CPU -- pin 27
MAPn : in std_logic; -- MAP -- pin 26
DB : in std_logic_vector( 7 downto 0); -- DATA BUS -- pin 18,34,5,13,12,11,17,8
ADDR : in std_logic_vector(15 downto 0); -- ADDRESS BUS -- pin 30,29,22,35,15,31,33,32, A7,A6,A5,A4,A3,A2,A1,A0
-- SRAM
CSRAMn : out std_logic;
SRAM_AD : out std_logic_vector(15 downto 0);
SRAM_OE : out std_logic;
SRAM_CE : out std_logic;
SRAM_WE : out std_logic;
LATCH_SRAM : out std_logic;
-- DRAM
-- AD_RAM : out std_logic_vector( 7 downto 0); -- ADDRESS BUS for dynamic ram -- pin 38,36,37,4,3,2,40,39
-- RASn : out std_logic; -- RAS for dynamic ram -- pin 10
-- CASn : out std_logic; -- CAS for dynamic ram -- pin 09
-- MUX : out std_logic; -- MUX selector -- pin 01
-- RW_RAM : out std_logic; -- Read/Write for dynamic ram -- pin 28
CSIOn : out std_logic; -- Chip select IO (VIA) -- pin 25
CSROMn : out std_logic; -- ROM select -- pin 23
R : out std_logic; -- Red -- pin 21
G : out std_logic; -- Green -- pin 20
B : out std_logic; -- Blue -- pin 19
SYNC : out std_logic; -- Synchronisation -- pin 16
-- VCC -- pin 24
-- GND -- pin 06
HSYNC : out std_logic;
VSYNC : out std_logic
);
end;
architecture RTL of ula is
-- Signal CLOCK
signal CLK_24 : std_logic; -- CLOCK 24 MHz internal
signal CLK_4_INT : std_logic; -- CLOCK 4 MHz internal
signal CLK_1_INT : std_logic; -- CLOCK 1 MHz internal
signal CLK_PIXEL_INT : std_logic; -- CLOCK PIXEL internal
signal CLK_FLASH : std_logic; -- CLOCK FLASH external
-- Data Bus Internal
signal DB_INT : std_logic_vector( 7 downto 0);
-- Manage memory access
signal VAP1 : std_logic_vector(15 downto 0); -- VIDEO ADDRESS PHASE 1
signal VAP2 : std_logic_vector(15 downto 0); -- VIDEO ADDRESS PHASE 2
signal lADDR : std_logic_vector(15 downto 0); -- BUS ADDRESS PROCESSOR
signal RW_INT : std_logic; -- Read/Write INTERNAL FROM CPU
-- local signal
signal lHIRES_SEL : std_logic; -- TXT/HIRES SELECT
signal HIRES_DEC : std_logic; -- TXT/HIRES DECODE
signal lDBLHGT_SEL : std_logic; -- Double Height SELECT
signal lALT_SEL : std_logic; -- Character set select
signal lFORCETXT : std_logic; -- Force text mode
signal isAttrib : std_logic; -- Attrib
signal ATTRIB_DEC : std_logic; -- Attrib decode
-- signal LD_REG_0 : std_logic; -- Load zero into video register
signal RELD_REG : std_logic; -- Reload from register to shift
signal DATABUS_EN : std_logic; -- Data bus enable
signal lCOMPSYNC : std_logic; -- Composite Synchronization for video
signal lHSYNCn : std_logic; -- Horizontal Synchronization for video
signal lVSYNC50n : std_logic; -- Vertical Synchronization for 50Hz video
signal lVSYNC60n : std_logic; -- Vertical Synchronization for 60Hz video
signal lVSYNCn : std_logic; -- Vertical Synchronization for video
signal BLANKINGn : std_logic; -- Blanking signal
signal lRELOAD_SEL : std_logic; -- reload register SELECT
signal lFREQ_SEL : std_logic; -- Frequency video SELECT (50 or 60 Hz)
signal LDFROMBUS : std_logic; -- Load from Bus Data
signal CHROWCNT : std_logic_vector( 2 downto 0); -- ch?? row count
signal lCTR_H : std_logic_vector( 6 downto 0); -- Horizontal counter
signal lCTR_V : std_logic_vector( 8 downto 0); -- Vertical counter
signal rgb_int : std_logic_vector( 2 downto 0); -- Red Green Blue video signal
-- local select RAM, IO & ROM
signal CSRAMn_INT : std_logic; -- RAM Chip Select
signal CSIOn_INT : std_logic; -- Input/Output Chip Select
signal CSROMn_INT : std_logic; -- ROM Chip select
-- Bus Address internal
signal AD_RAM_INT : std_logic_vector(15 downto 0); -- RAM ADDRESS BUS
-- RESET internal
signal RESET_INT : std_logic;
-- MAP internal
signal lMAPn : std_logic;
signal DBLHGT_EN : std_logic; -- ENABLE DOUBLE HEIGHT
signal CTR_V_DIV8 : std_logic_vector( 8 downto 0); -- VERTICAL COUNTER DIVIDE OR NOT BY 8
signal voffset : std_logic_vector(15 downto 0); -- OFFSET SCREEN
signal mulBy40 : std_logic_vector(14 downto 0); -- Used to mult by 40
signal c : std_logic_vector(23 downto 0); -- states
signal ph : std_logic_vector( 2 downto 0); -- phases
signal lCTR_FLASH : std_logic_vector( 4 downto 0);
signal lVBLANKn : std_logic;
signal lHBLANKn : std_logic;
signal lDATABUS : std_logic_vector( 7 downto 0);
signal lSHFREG : std_logic_vector( 5 downto 0);
signal lREGHOLD : std_logic_vector( 6 downto 0);
signal lRGB : std_logic_vector( 2 downto 0);
signal lREG_INK : std_logic_vector( 2 downto 0);
signal lREG_STYLE : std_logic_vector( 2 downto 0);
signal lREG_PAPER : std_logic_vector( 2 downto 0);
signal lREG_MODE : std_logic_vector( 2 downto 0);
signal ModeStyle : std_logic_vector( 1 downto 0);
signal lADD : std_logic_vector( 5 downto 0);
signal lInv : std_logic; -- inverse signal
signal lInv_hold : std_logic; -- inverse signal hold
signal lBGFG_SEL : std_logic;
signal lFLASH_SEL : std_logic;
begin
-- input assignments
lADDR <= ADDR;
DB_INT <= DB;
CLK_24 <= CLK;
RESET_INT <= not RESETn;
lMAPn <= MAPn;
RW_INT <= RW;
-- output assignments
PHI2 <= CLK_1_INT;
-- AD_RAM <= AD_RAM_INT(15 downto 8);
CSIOn <= CSIOn_INT;
CSROMn <= CSROMn_INT;
CSRAMn <= CSRAMn_INT;
CLK_4 <= CLK_4_INT;
------------------
-- SRAM signals --
------------------
SRAM_AD <= AD_RAM_INT;
LATCH_SRAM <= not c(4) and not c(12) and not c(20);
-- phase 1 phase 2 phase 3
SRAM_OE <= ph(0) or ph(1) or RW_INT ;
SRAM_CE <= ph(0) or ph(1) or (ph(2) and (not CSRAMn_INT) );
SRAM_WE <= (not CSRAMn_INT) and (not RW_INT) and c(17) ;
-- VIDEO OUT
R <= RGB_INT(0);
G <= RGB_INT(1);
B <= RGB_INT(2);
SYNC <= lCOMPSYNC;
HSYNC <= lHSYNCn;
VSYNC <= lVSYNCn;
----------------------
----------------------
-- Address Decoding --
----------------------
----------------------
-- PAGE 3 I/O decoder : 0x300-0x3FF
CSIOn_INT <= '0' when (lADDR(15 downto 8) = x"03") and (CLK_1_INT = '1') else '1';
-- PAGE ROM : 0xC000-0xFFFF
CSROMn_INT <= '0' when (lADDR(15 downto 14) = "11" and lMAPn = '1' and CLK_1_INT = '1') else '1';
CSRAMn_INT <= '0' when -- shadow RAM section
(lADDR(15 downto 14) = "11" and lMAPn = '0' and CLK_1_INT = '1')
or
-- normal RAM section
(((lADDR(15 downto 8) /= x"03") and (lADDR(15 downto 14) /= "11")) and lMAPn = '1' and CLK_1_INT = '1')
else '1';
----------------------------------------------
----------------------------------------------
-- Control signal generation and sequencing --
----------------------------------------------
----------------------------------------------
-- state and phase shifter
U_TB_CPT: process (CLK_24, RESET_INT)
begin
if (RESET_INT = '1') then
c <= "000000000000000000000001";
ph <= "001";
elsif falling_edge(CLK_24) then
-- advance states
c <= c(22 downto 0) & c(23);
if (c(7) or c(15) or c(23)) = '1' then
-- advance phases
ph <= ph(1 downto 0) & ph(2);
end if;
end if;
end process;
----------------------
-- Clock generation --
----------------------
-- CPU clock --
CLK_1_INT <= ph(2);
-- VIA 6522 clock
CLK_4_INT <= c(0) or c(1) or c(2) or c(6) or c(7) or c(8) or c(12) or c(13) or c(14) or c(18) or c(19) or c(20);
-- LD_REG_0 <= isAttrib and c(5);
CLK_PIXEL_INT <= c(1) or c(5) or c(9) or c(13) or c(17) or c(21);
ATTRIB_DEC <= c(3);
RELD_REG <= c(17);
DATABUS_EN <= c(2) or c(10);
LDFROMBUS <= ((not isAttrib) and c(12) and (not HIRES_DEC)) or ((not isAttrib) and c(5) and HIRES_DEC) or (isAttrib and c(9));
-------------------------------------
-------------------------------------
-- Video timing signals generation --
-------------------------------------
-------------------------------------
-- Horizontal Counter
u_CPT_H: process(CLK_1_INT, RESET_INT)
begin
if (RESET_INT = '1') then
lCTR_H <= (others => '0');
elsif rising_edge(CLK_1_INT) then
if lCTR_H < 63 then
lCTR_H <= lCTR_H + 1;
else
lCTR_H <= (others => '0');
end if;
end if;
end process;
-- Vertical Counter
u_CPT_V: process(CLK_1_INT, RESET_INT)
begin
if (RESET_INT = '1') then
lCTR_V <= (others => '0');
lCTR_FLASH <= (others => '0');
elsif rising_edge(CLK_1_INT) then
if (lCTR_H = 63) then
-- 50Hz = 312 lines, 60Hz = 260 lines
if ((lCTR_V < 312) and lFREQ_SEL='1') or
((lCTR_V < 260) and lFREQ_SEL='0') then
lCTR_V <= lCTR_V + 1;
else
lCTR_V <= (others => '0');
-- increment flash counter every frame
lCTR_FLASH <= lCTR_FLASH + 1;
end if;
end if;
end if;
end process;
-- Horizontal Synchronisation
lHSYNCn <= '0' when (lCTR_H >= 49) and (lCTR_H <= 53) else '1';
-- Horizontal Blank
lHBLANKn <= '1' when (lCTR_H >= 1) and (lCTR_H <= 40) else '0';
-- Signal to Reload Register to reset attributes
lRELOAD_SEL <= '1' when (lCTR_H >= 49) else '0';
-- Vertical Synchronisation
lVSYNC50n <= '0' when (lCTR_V >= 258) and (lCTR_V <= 259) else '1'; -- 50Hz
lVSYNC60n <= '0' when (lCTR_V >= 241) and (lCTR_V <= 242) else '1'; -- 60Hz
lVSYNCn <= lVSYNC50n when lFREQ_SEL='1' else lVSYNC60n;
-- Vertical Blank
lVBLANKn <= '0' when (lCTR_V >= 224) else '1';
-- Signal To Force TEXT MODE
lFORCETXT <= '1' when (lCTR_V > 199) else '0';
-- Assign output signals
CLK_FLASH <= lCTR_FLASH(4); -- Flash clock toggles every 16 video frames
lCOMPSYNC <= not (lHSYNCn xor lVSYNCn);
BLANKINGn <= lVBLANKn and lHBLANKn;
-----------------------------
-----------------------------
-- Video attribute decoder --
-----------------------------
-----------------------------
-- Latch data from Data Bus
u_data_bus: process
begin
wait until rising_edge(CLK_24);
if (DATABUS_EN = '1') then
lDATABUS <= DB_INT;
end if;
end process;
u_isattrib : process(CLK_24, RESET_INT)
begin
if (RESET_INT = '1') then
IsATTRIB <= '0';
lInv_hold <= '0';
elsif rising_edge(CLK_24) then
if ATTRIB_DEC = '1' then
IsATTRIB <= not (DB_INT(6) or DB_INT(5)); -- 1 = attribute, 0 = not an attribute
lInv_hold <= DB_INT(7);
end if;
end if;
end process;
u_lInv_hold : process
begin
wait until rising_edge(CLK_24);
if (CLK_PIXEL_INT = '1' and RELD_REG = '1') then
lInv <= lInv_hold;
end if;
end process;
-- hold data bus value
u_hold_reg: process(CLK_24, RESET_INT)
begin
if (RESET_INT = '1') then
lREGHOLD <= (others => '0');
elsif rising_edge(CLK_24) then
if LDFROMBUS = '1' then
lREGHOLD <= lDATABUS(6 downto 0);
end if;
end if;
end process;
u_ld_reg: process(CLK_24, lRELOAD_SEL, RESET_INT)
begin
if (RESET_INT = '1') then
lREG_INK <= (others=>'1');
lREG_STYLE <= (others=>'0');
lREG_PAPER <= (others=>'0');
lREG_MODE <= (others=>'0');
elsif (lRELOAD_SEL = '1') then
lREG_INK <= (others=>'1');
lREG_STYLE <= (others=>'0');
lREG_PAPER <= (others=>'0');
elsif rising_edge(CLK_24) then
if (RELD_REG = '1' and isAttrib = '1') then
case lREGHOLD(6 downto 3) is
when "0000" => lREG_INK <= lREGHOLD(2 downto 0);
when "0001" => lREG_STYLE <= lREGHOLD(2 downto 0);
when "0010" => lREG_PAPER <= lREGHOLD(2 downto 0);
when "0011" => lREG_MODE <= lREGHOLD(2 downto 0);
when others => null;
end case;
end if;
end if;
end process;
-- selector bits in mode/style registers
lALT_SEL <= lREG_STYLE(0); -- Character set select : 0=Standard 1=Alternate
lDBLHGT_SEL <= lREG_STYLE(1); -- Character type select: 0=Standard 1=Double
lFLASH_SEL <= lREG_STYLE(2); -- Flash select : 0=Steady 1=Flashing
lFREQ_SEL <= lREG_MODE(1); -- Frequency select : 0=60Hz 1=50Hz
lHIRES_SEL <= lREG_MODE(2); -- Mode Select : 0=Text 1=Hires
-- Output signal for text/hires mode decode
HIRES_DEC <= (lHIRES_SEL and (not lFORCETXT));
DBLHGT_EN <= (lDBLHGT_SEL and (not HIRES_DEC));
-- shift video data
u_shf_reg: process
begin
wait until rising_edge(CLK_24);
if CLK_PIXEL_INT = '1' then
-- Load shifter before the rising edge of PHI2
if (RELD_REG = '1' and isAttrib = '0') then
lSHFREG <= lREGHOLD(5 downto 0);
else
-- send 6 bits
lSHFREG <= lSHFREG(4 downto 0) & '0';
end if;
end if;
end process;
lBGFG_SEL <= '0' when ( (CLK_FLASH = '1') and (lFLASH_SEL = '1') ) else lSHFREG(5);
-- local assign for R(ed)G(reen)B(lue) signal
lRGB <= lREG_INK when lBGFG_SEL = '1' else lREG_PAPER;
-- Assign out signal
RGB_INT <= lRGB when (lInv = '0' and BLANKINGn = '1') else
not(lRGB) when (lInv = '1' and BLANKINGn = '1') else
(others=>'0');
-- Compute offset
ModeStyle <= lHIRES_SEL & lALT_SEL;
with ModeStyle select
lADD <= "100111" when "11", -- HIRES & ALT x9Cxx
"100110" when "10", -- HIRES & STD x98xx
"101110" when "01", -- TEXT & ALT xB8xx
"101101" when others; -- TEXT & STD xB4xx
-----------------------------
-----------------------------
-- Video address generator --
-----------------------------
-----------------------------
-- divide by 8 in LORES
CTR_V_DIV8 <= lCTR_V when (HIRES_DEC = '1') else "000" & lCTR_V(8 downto 3) ;
-- to multiply by 40 without using a multiplier we just sum the results of the operations of
-- multiply by 32 by shifting 5 bits and multiply by 8 by shifting 3 bits
mulBy40 <= ("0" & CTR_V_DIV8 & "00000") + ("000" & CTR_V_DIV8 & "000");
voffset <= X"A000" when (HIRES_DEC = '1') else X"BB80";
-- Generate Address Phase 1
VAP1 <= (voffset + mulBy40) + lCTR_H;
-- Compute character row counter
CHROWCNT <= lCTR_V(3 downto 1) when (DBLHGT_EN = '1') else lCTR_V(2 downto 0);
-- Generate Address Phase 2
VAP2 <= lADD & lDATABUS(6 downto 0) & CHROWCNT;
-- multiplex addresses at rising edge of each phase
addr_latch: process
begin
wait until rising_edge(CLK_24);
if c(0) = '1' then
-- Generate video phase 1 address
AD_RAM_INT <= VAP1;
elsif c(8) = '1' then
-- Generate video phase 2 address
AD_RAM_INT <= VAP2;
elsif c(16) = '1' then
-- Generate CPU phase 3 address
AD_RAM_INT <= lADDR;
end if;
end process;
end architecture RTL;

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--
-- vag.vhd
--
-- Generate video signals
--
-- Copyright (C)2001 - 2005 SEILEBOST
-- All rights reserved.
--
-- $Id: vag.vhd, v0.01 2005/01/01 00:00:00 SEILEBOST $
--
-- TODO :
-- Remark :
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
--use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity vag is
port ( CLK_1 : in std_logic;
RESETn : in std_logic;
FREQ_SEL : in std_logic; -- Select 50/60 Hz frequency
CPT_H : out std_logic_vector(6 downto 0); -- Horizontal Counter
CPT_V : out std_logic_vector(8 downto 0); -- Vertical Counter
RELOAD_SEL : out std_logic; -- Reload registe SEL
FORCETXT : out std_logic; -- Force Mode Text
CLK_FLASH : out std_logic; -- Flash Clock
COMPSYNC : out std_logic; -- Composite Synchro signal
BLANKINGn : out std_logic -- Blanking signal
);
end entity vag;
architecture vag_arch of vag is
signal lCPT_H : std_logic_vector(6 downto 0);
signal lCPT_V : std_logic_vector(8 downto 0);
signal lCPT_FLASH : std_logic_vector(5 downto 0);
signal lVSYNCn : std_logic;
signal lVBLANKn : std_logic;
signal lVFRAME : std_logic;
signal lFORCETXT : std_logic;
signal lHSYNCn : std_logic;
signal lHBLANKn : std_logic;
signal lRELOAD_SEL : std_logic;
signal lCLK_V : std_logic;
begin
-- Horizontal Counter
u_CPT_H: PROCESS(CLK_1, RESETn)
BEGIN
IF (RESETn = '0') THEN
lCPT_H <= (OTHERS => '0');
ELSIF rising_edge(CLK_1) THEN
IF lCPT_H < 63 then
lCPT_H <= lCPT_H + "0000001";
ELSE
lCPT_H <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Horizontal Synchronisation
lHSYNCn <= '0' when (lCPT_H >= 49) AND (lCPT_H <= 53) ELSE '1';
-- Horizontal Blank
lHBLANKn <= '0' when (lCPT_H >= 40) AND (lCPT_H <= 63) ELSE '1';
-- Signal to Reload Register to reset attribut
lRELOAD_SEL <= '1' WHEN (lCPT_H >= 56) AND (lCPT_H <= 63) ELSE '0';
-- Clock for Vertical counter
lCLK_V <= '1' WHEN (lCPT_H = 63) ELSE '0';
-- Vertical Counter
u_CPT_V: PROCESS(lCLK_V, RESETn)
BEGIN
IF (RESETn = '0') THEN
lCPT_V <= (OTHERS => '0');
ELSIF rising_edge(lCLK_V) THEN
IF (lCPT_V < 311) THEN
lCPT_V <= lCPT_V + "000000001";
ELSE
lCPT_V <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Vertical Synchronisation
lVSYNCn <= '0' when(lCPT_V >= 258) AND (lCPT_V <= 259) ELSE '1';
-- Vertical Blank
lVBLANKn <= '0' when(lCPT_V >= 224) AND (lCPT_V <= 311) ELSE '1';
-- Clock to Flash Counter
lVFRAME <= '1' WHEN (lCPT_V = 311) ELSE '0';
-- Signal To Force TEXT MODE
lFORCETXT <= '1' WHEN (lCPT_V > 199) ELSE '0';
-- Flash Counter
u_FLASH : PROCESS( lVSYNCn, RESETn )
BEGIN
IF (RESETn = '0') THEN
lCPT_FLASH <= (OTHERS => '0');
ELSIF rising_edge(lVSYNCn) THEN
lCPT_FLASH <= lCPT_FLASH + "000001";
END IF;
END PROCESS;
-- Assign signals
FORCETXT <= '1' WHEN ((lFORCETXT = '1') OR (lVFRAME = '1') ) ELSE '0';
CLK_FLASH <= lCPT_FLASH(5);
RELOAD_SEL <= lRELOAD_SEL;
COMPSYNC <= NOT(lHSYNCn XOR lVSYNCn);
-- Assign counters
CPT_H <= lCPT_H;
CPT_V <= lCPT_V;
-- Assign blanking signal
BLANKINGn <= lVBLANKn AND lHBLANKn;
end architecture vag_arch;

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--
-- video.vhd
--
-- Manage video attribute
--
-- Copyright (C)2001 - 2005 SEILEBOST
-- All rights reserved.
--
-- $Id: video.vhd, v0.01 2005/01/01 00:00:00 SEILEBOST $
--
-- TODO :
-- Remark :
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_STD.all;
entity video is
port ( RESETn : in std_logic;
CLK_PIXEL : in std_logic;
CLK_FLASH : in std_logic;
-- delete 17/11/2009 FLASH_SEL : in std_logic;
BLANKINGn : in std_logic;
RELOAD_SEL : in std_logic;
DATABUS : in std_logic_vector(7 downto 0);
ATTRIB_DEC : in std_logic;
DATABUS_EN : in std_logic;
LDFROMBUS : in std_logic;
LD_REG_0 : in std_logic;
RELD_REG : in std_logic;
CHROWCNT : in std_logic_vector(2 downto 0);
RGB : out std_logic_vector(2 downto 0);
FREQ_SEL : out std_logic;
TXTHIR_SEL : out std_logic;
isAttrib : out std_logic;
DBLSTD_SEL : out std_logic;
VAP2 : out std_logic_vector(15 downto 0)
);
end entity video;
architecture video_arch of video is
-- locals signals
signal lDATABUS : std_logic_vector(7 downto 0);
signal lSHFREG : std_logic_vector(5 downto 0);
signal lREGHOLD : std_logic_vector(5 downto 0);
signal lRGB : std_logic_vector(2 downto 0);
signal lCLK_REG : std_logic_vector(3 downto 0);
signal lREG_0 : std_logic_vector(2 downto 0);
signal lREG_1 : std_logic_vector(2 downto 0);
signal lREG_2 : std_logic_vector(2 downto 0);
signal lREG_3 : std_logic_vector(2 downto 0);
signal tmp : std_logic_vector(1 downto 0);
signal lADD : std_logic_vector(1 downto 0);
signal lDIN : std_logic; -- SET INVERSE SIGNAL
signal lSHFVIDEO : std_logic;
signal lBGFG_SEL : std_logic;
signal lFLASH_SEL : std_logic;
signal lIsATTRIB : std_logic;
begin
-- Latch data from Data Bus
u_data_bus: PROCESS( DATABUS, DATABUS_EN)
BEGIN
-- Correctif 03/02/09 if (DATABUS_EN = '1') then
if (rising_edge(DATABUS_EN)) then
lDATABUS <= DATABUS;
end if;
END PROCESS;
-- Ajout du 04/02/09 / Commentaire le 05/12/09
--isAttrib <= not lDATABUS(6); -- =1 is an attribut, = 0 is not an attribut
-- Decode register
-- Modification multiple le 03/02/2010
--u_attr_dec: PROCESS(lDATABUS, ATTRIB_DEC)
--BEGIN
--lCLK_REG <= "0000"; -- Ajout 11/11/09 Suppression 03/02/2010
-- if rising_edge(ATTRIB_DEC) then
-- le 03/02/2010 : commentaire de 9 lignes
-- if (lDATABUS(6 downto 5) = "00") then
-- case lDATABUS(4 downto 3) is
-- when "00" => lCLK_REG <= "0001";
-- when "01" => lCLK_REG <= "0010";
-- when "10" => lCLK_REG <= "0100";
-- when "11" => lCLK_REG <= "1000";
-- when others => null; --lCLK_REG <= "1111"; -- 11/11/09 null;
-- end case;
--end if;
-- case lDATABUS(6 downto 3) is
-- when "0000" => lCLK_REG <= "0001";
-- when "0001" => lCLK_REG <= "0010";
-- when "0010" => lCLK_REG <= "0100";
-- when "0011" => lCLK_REG <= "1000";
-- when others => lCLK_REG <= "0000";
-- end case;
-- end if;
--END PROCESS;
lCLK_REG(0) <= '1' when (lDATABUS(6 downto 3) = "0000") and (ATTRIB_DEC = '1') else '0';
lCLK_REG(1) <= '1' when (lDATABUS(6 downto 3) = "0010") and (ATTRIB_DEC = '1') else '0';
lCLK_REG(2) <= '1' when (lDATABUS(6 downto 3) = "0100") and (ATTRIB_DEC = '1') else '0';
lCLK_REG(3) <= '1' when (lDATABUS(6 downto 3) = "1000") and (ATTRIB_DEC = '1') else '0';
-- ajout le 05/12/09
u_isattrib : PROCESS(DATABUS_EN, ATTRIB_DEC, RESETn)
BEGIN
if (RESETn = '0') then
lIsATTRIB <= '0';
elsif rising_edge(ATTRIB_DEC) then
lIsATTRIB <= not (DATABUS(6) or DATABUS(5)); -- =1 is an attribut, = 0 is not an attribut
end if;
END PROCESS;
-- Assignation
isAttrib <= lIsATTRIB;
-- get value for register number 0 : INK
u_ld_reg0: PROCESS(lCLK_REG, RELOAD_SEL, lDATABUS, RESETn)
BEGIN
-- Ajout du 17/11/2009
if (RESETn = '0') then
lREG_0 <= "000";
elsif (RELOAD_SEL = '1') then
lREG_0 <= "000";
-- le 17/11/2009 elsif (lCLK_REG(0) = '1') then
elsif rising_edge(lCLK_REG(0)) then
lREG_0 <= lDATABUS(2 downto 0);
end if;
END PROCESS;
-- get value for register number 1 : STYLE : Alt/std, Dbl/std, Flash sel
u_ld_reg1: PROCESS(lCLK_REG, RELOAD_SEL, lDATABUS, RESETN)
BEGIN
-- Ajout du 17/11/2009
if (RESETn = '0') then
lREG_1 <= "000";
elsif (RELOAD_SEL = '1') then
lREG_1 <= "000";
-- le 17/11/2009 elsif (lCLK_REG(1) = '1') then
elsif rising_edge(lCLK_REG(1)) then
lREG_1 <= lDATABUS(2 downto 0);
end if;
END PROCESS;
-- get value for register number 2 : PAPER
u_ld_reg2: PROCESS(lCLK_REG, RELOAD_SEL, lDATABUS, RESETN)
BEGIN
-- Ajout du 17/11/2009
if (RESETn = '0') then
lREG_2 <= "111";
elsif (RELOAD_SEL = '1') then
lREG_2 <= "111";
-- le 17/11/2009 elsif (lCLK_REG(2) = '1') then
elsif rising_edge(lCLK_REG(2)) then
lREG_2 <= lDATABUS(2 downto 0);
end if;
END PROCESS;
-- get value for register number 3 : Mode
u_ld_reg3: PROCESS(lCLK_REG, lDATABUS, RESETn)
BEGIN
if (RESETn = '0') then
lREG_3 <= "000";
-- modif 04/02/09 elsif (lCLK_REG(3) = '1') then
elsif rising_edge(lCLK_REG(3)) then
lREG_3 <= lDATABUS(2 downto 0);
end if;
END PROCESS;
-- hold data value
u_hold_reg: PROCESS( LD_REG_0, LDFROMBUS, lDATABUS)
BEGIN
-- Chargement si attribut
if (LD_REG_0 = '1') then
lREGHOLD <= (OTHERS => '0');
elsif (rising_edge(LDFROMBUS)) then
lREGHOLD <= lDATABUS(5 downto 0);
lDIN <= lDATABUS(7); -- Ajout du 15/12/2009
end if;
---mise en commentaire 15/12/2009 lDIN <= lDATABUS(7);
END PROCESS;
-- shift data for video
u_shf_reg: PROCESS(RELD_REG, CLK_PIXEL, lREGHOLD)
BEGIN
-- Chargement du shifter avant le front montant de PHI2
if (RELD_REG = '1') then
lSHFREG <= lREGHOLD;
-- 6 bits à envoyer
elsif (rising_edge(CLK_PIXEL)) then
lSHFVIDEO <= lSHFREG(5);
lSHFREG <= lSHFREG(4 downto 0) & '0';
end if;
END PROCESS;
lFLASH_SEL <= lREG_1(2);
lBGFG_SEL <= NOT(lSHFVIDEO) when ( (CLK_FLASH = '1') AND (lFLASH_SEL = '1') ) else lSHFVIDEO;
-- le 17/11/2009 : lBGFG_SEL <= NOT(lSHFVIDEO) when ( (CLK_FLASH = '1') AND (FLASH_SEL = '1') ) else lSHFVIDEO;
-- lBGFG_SEL <= lSHFVIDEO and not ( CLK_FLASH AND FLASH_SEL );
-- local assign for R(ed)G(reen)B(lue) signal
lRGB <= lREG_0 when lBGFG_SEL = '0' else lREG_2;
-- Assign out signal
RGB <= lRGB when (lDIN = '0' and BLANKINGn = '1') else
not(lRGB) when (lDIN = '1' and BLANKINGn = '1') else
"000";
DBLSTD_SEL <= lREG_1(1); -- Double/Standard height character select
FREQ_SEL <= lREG_3(1); -- Frenquecy video (50/60Hz) select
TXTHIR_SEL <= lREG_3(2); -- Texte/Hires mode select
-- Compute offset
tmp <= lREG_3(2) & lREG_1(0);
with tmp select
lADD <= "01" when "00", -- TXT & STD
"10" when "01", -- TXT & ALT
"10" when "10", -- HIRES & STD
"11" when "11", -- HIRES & ALT
"01" when others; -- Du fait que le design original de l'ULA
-- n'a pas de reset, nous supposerons que
-- l'ULA est en mode text et standard
-- Generate Address Phase 2
VAP2 <= "10" & not lREG_3(2) & '1' & lADD & lDATABUS(6 downto 0) & CHROWCNT;
end architecture video_arch;

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Oric Atmos_MiST/rtl/video_mixer.sv Normal file
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//
//
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//
// LINE_LENGTH: Length of display line in pixels
// Usually it's length from HSync to HSync.
// May be less if line_start is used.
//
// HALF_DEPTH: If =1 then color dept is 3 bits per component
// For half depth 6 bits monochrome is available with
// mono signal enabled and color = {G, R}
module video_mixer
#(
parameter LINE_LENGTH = 768,
parameter HALF_DEPTH = 0,
parameter OSD_COLOR = 3'd4,
parameter OSD_X_OFFSET = 10'd0,
parameter OSD_Y_OFFSET = 10'd0
)
(
// master clock
// it should be multiple by (ce_pix*4).
input clk_sys,
// Pixel clock or clock_enable (both are accepted).
input ce_pix,
// Some systems have multiple resolutions.
// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
input ce_pix_actual,
// OSD SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// 0 = HVSync 31KHz, 1 = CSync 15KHz
input scandoubler_disable,
// High quality 2x scaling
input hq2x,
// YPbPr always uses composite sync
input ypbpr,
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
input ypbpr_full,
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
input [DWIDTH:0] B,
// Monochrome mode (for HALF_DEPTH only)
input mono,
// interlace sync. Positive pulses.
input HSync,
input VSync,
// Falling of this signal means start of informative part of line.
// It can be horizontal blank signal.
// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel
// before first informative pixel.
input line_start,
// MiST video output signals
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_VS,
output VGA_HS
);
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
wire [DWIDTH:0] R_sd;
wire [DWIDTH:0] G_sd;
wire [DWIDTH:0] B_sd;
wire hs_sd, vs_sd;
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
(
.*,
.hs_in(HSync),
.vs_in(VSync),
.r_in(R),
.g_in(G),
.b_in(B),
.hs_out(hs_sd),
.vs_out(vs_sd),
.r_out(R_sd),
.g_out(G_sd),
.b_out(B_sd)
);
wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd);
wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd);
wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd);
generate
if(HALF_DEPTH) begin
wire [5:0] r = mono ? {gt,rt} : {rt,rt};
wire [5:0] g = mono ? {gt,rt} : {gt,gt};
wire [5:0] b = mono ? {gt,rt} : {bt,bt};
end else begin
wire [5:0] r = rt;
wire [5:0] g = gt;
wire [5:0] b = bt;
end
endgenerate
wire hs = (scandoubler_disable ? HSync : hs_sd);
wire vs = (scandoubler_disable ? VSync : vs_sd);
reg scanline = 0;
always @(posedge clk_sys) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) scanline <= ~scanline;
if(old_vs && ~vs) scanline <= 0;
end
wire [5:0] r_out, g_out, b_out;
always @(*) begin
case(scanlines & {scanline, scanline})
1: begin // reduce 25% = 1/2 + 1/4
r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
end
2: begin // reduce 50% = 1/2
r_out = {1'b0, r[5:1]};
g_out = {1'b0, g[5:1]};
b_out = {1'b0, b[5:1]};
end
3: begin // reduce 75% = 1/4
r_out = {2'b00, r[5:2]};
g_out = {2'b00, g[5:2]};
b_out = {2'b00, b[5:2]};
end
default: begin
r_out = r;
g_out = g;
b_out = b;
end
endcase
end
wire [5:0] red, green, blue;
osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
(
.*,
.R_in(r_out),
.G_in(g_out),
.B_in(b_out),
.HSync(hs),
.VSync(vs),
.R_out(red),
.G_out(green),
.B_out(blue)
);
wire [5:0] yuv_full[225] = '{
6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
6'd63
};
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
endmodule

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Oric Atmos_MiST/storage/BRAIN_RAM.txt Normal file
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Ram dynamique :
RAS
CAS
R/W
RAM STATIQUE
CS
R/W
clk
cs = Page 0-2 + Page 4-BF
CLK = CAS

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Oric Atmos_MiST/storage/ORIC_pad.txt Normal file
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Release 11.1 - par L.33 (lin)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Thu Apr 8 22:11:19 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
INPUT FILE: ORIC_map.ncd
OUTPUT FILE: ORIC_pad.txt
PART TYPE: xa3s1000
SPEED GRADE: -4
PACKAGE: ftg256
Pinout by Pin Number:
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|A1 | | |GND | | | | | | | | | | | |
|A2 | | |TDI | | | | | | | | | | | |
|A3 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | |
|A4 | |DIFFM |IO_L01P_0/VRN_0 |UNUSED | |0 | | | | | | | | |
|A5 | |IOB |IO |UNUSED | |0 | | | | | | | | |
|A6 | | |VCCAUX | | | | | | | |2.5 | | | |
|A7 | |IOB |IO |UNUSED | |0 | | | | | | | | |
|A8 | |DIFFM |IO_L32P_0/GCLK6 |UNUSED | |0 | | | | | | | | |
|A9 | |IOB |IO |UNUSED | |1 | | | | | | | | |
|A10 | |DIFFS |IO_L31N_1/VREF_1 |UNUSED | |1 | | | | | | | | |
|A11 | | |VCCAUX | | | | | | | |2.5 | | | |
|A12 | |IOB |IO |UNUSED | |1 | | | | | | | | |
|A13 | |DIFFS |IO_L10N_1/VREF_1 |UNUSED | |1 | | | | | | | | |
|A14 | |DIFFS |IO_L01N_1/VRP_1 |UNUSED | |1 | | | | | | | | |
|A15 | | |TDO | | | | | | | | | | | |
|A16 | | |GND | | | | | | | | | | | |
|B1 |D<7> |IOB |IO_L01P_7/VRN_7 |BIDIR |LVCMOS25* |7 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|B2 | | |GND | | | | | | | | | | | |
|B3 | | |PROG_B | | | | | | | | | | | |
|B4 | |DIFFS |IO_L01N_0/VRP_0 |UNUSED | |0 | | | | | | | | |
|B5 | |DIFFM |IO_L25P_0 |UNUSED | |0 | | | | | | | | |
|B6 | |DIFFM |IO_L28P_0 |UNUSED | |0 | | | | | | | | |
|B7 | |DIFFM |IO_L30P_0 |UNUSED | |0 | | | | | | | | |
|B8 | |DIFFS |IO_L32N_0/GCLK7 |UNUSED | |0 | | | | | | | | |
|B9 | | |GND | | | | | | | | | | | |
|B10 | |DIFFM |IO_L31P_1 |UNUSED | |1 | | | | | | | | |
|B11 | |DIFFS |IO_L29N_1 |UNUSED | |1 | | | | | | | | |
|B12 | |DIFFS |IO_L27N_1 |UNUSED | |1 | | | | | | | | |
|B13 | |DIFFM |IO_L10P_1 |UNUSED | |1 | | | | | | | | |
|B14 | |DIFFM |IO_L01P_1/VRN_1 |UNUSED | |1 | | | | | | | | |
|B15 | | |GND | | | | | | | | | | | |
|B16 | |DIFFS |IO_L01N_2/VRP_2 |UNUSED | |2 | | | | | | | | |
|C1 |D<6> |IOB |IO_L01N_7/VRP_7 |BIDIR |LVCMOS25* |7 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|C2 |D<5> |IOB |IO_L16N_7 |BIDIR |LVCMOS25* |7 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|C3 | |DIFFM |IO_L16P_7/VREF_7 |UNUSED | |7 | | | | | | | | |
|C4 | | |HSWAP_EN | | | | | | | | | | | |
|C5 | |DIFFS |IO_L25N_0 |UNUSED | |0 | | | | | | | | |
|C6 | |DIFFS |IO_L28N_0 |UNUSED | |0 | | | | | | | | |
|C7 | |DIFFS |IO_L30N_0 |UNUSED | |0 | | | | | | | | |
|C8 | |DIFFM |IO_L31P_0/VREF_0 |UNUSED | |0 | | | | | | | | |
|C9 | |DIFFS |IO_L32N_1/GCLK5 |UNUSED | |1 | | | | | | | | |
|C10 | |IOB |IO |UNUSED | |1 | | | | | | | | |
|C11 | |DIFFM |IO_L29P_1 |UNUSED | |1 | | | | | | | | |
|C12 | |DIFFM |IO_L27P_1 |UNUSED | |1 | | | | | | | | |
|C13 | | |TMS | | | | | | | | | | | |
|C14 | | |TCK | | | | | | | | | | | |
|C15 | |DIFFS |IO_L16N_2 |UNUSED | |2 | | | | | | | | |
|C16 | |DIFFM |IO_L01P_2/VRN_2 |UNUSED | |2 | | | | | | | | |
|D1 | |DIFFS |IO_L17N_7 |UNUSED | |7 | | | | | | | | |
|D2 | |DIFFM |IO_L17P_7 |UNUSED | |7 | | | | | | | | |
|D3 | |DIFFM |IO_L19P_7 |UNUSED | |7 | | | | | | | | |
|D4 | | |VCCINT | | | | | | | |1.2 | | | |
|D5 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | |
|D6 | |DIFFM |IO_L27P_0 |UNUSED | |0 | | | | | | | | |
|D7 | |DIFFM |IO_L29P_0 |UNUSED | |0 | | | | | | | | |
|D8 | |DIFFS |IO_L31N_0 |UNUSED | |0 | | | | | | | | |
|D9 | |DIFFM |IO_L32P_1/GCLK4 |UNUSED | |1 | | | | | | | | |
|D10 | |DIFFS |IO_L30N_1 |UNUSED | |1 | | | | | | | | |
|D11 | |DIFFS |IO_L28N_1 |UNUSED | |1 | | | | | | | | |
|D12 | |IOB |IO/VREF_1 |UNUSED | |1 | | | | | | | | |
|D13 | | |VCCINT | | | | | | | |1.2 | | | |
|D14 |an<0> |IOB |IO_L16P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|D15 | |DIFFS |IO_L17N_2 |UNUSED | |2 | | | | | | | | |
|D16 | |DIFFM |IO_L17P_2/VREF_2 |UNUSED | |2 | | | | | | | | |
|E1 | |DIFFS |IO_L20N_7 |UNUSED | |7 | | | | | | | | |
|E2 | |DIFFM |IO_L20P_7 |UNUSED | |7 | | | | | | | | |
|E3 |AD<8> |IOB |IO_L19N_7/VREF_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|E4 |AD<9> |IOB |IO_L21P_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|E5 | | |VCCINT | | | | | | | |1.2 | | | |
|E6 | |DIFFS |IO_L27N_0 |UNUSED | |0 | | | | | | | | |
|E7 | |DIFFS |IO_L29N_0 |UNUSED | |0 | | | | | | | | |
|E8 | | |VCCO_0 | | |0 | | | | |any******| | | |
|E9 | | |VCCO_1 | | |1 | | | | |any******| | | |
|E10 | |DIFFM |IO_L30P_1 |UNUSED | |1 | | | | | | | | |
|E11 | |DIFFM |IO_L28P_1 |UNUSED | |1 | | | | | | | | |
|E12 | | |VCCINT | | | | | | | |1.2 | | | |
|E13 |an<3> |IOB |IO_L19N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|E14 |sseg<6> |IOB |IO_L19P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|E15 | |DIFFS |IO_L20N_2 |UNUSED | |2 | | | | | | | | |
|E16 | |DIFFM |IO_L20P_2 |UNUSED | |2 | | | | | | | | |
|F1 | | |VCCAUX | | | | | | | |2.5 | | | |
|F2 | |DIFFS |IO_L22N_7 |UNUSED | |7 | | | | | | | | |
|F3 |AD<6> |IOB |IO_L22P_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|F4 |AD<7> |IOB |IO_L21N_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|F5 | |DIFFM |IO_L23P_7 |UNUSED | |7 | | | | | | | | |
|F6 | | |GND | | | | | | | | | | | |
|F7 | | |VCCO_0 | | |0 | | | | |any******| | | |
|F8 | | |VCCO_0 | | |0 | | | | |any******| | | |
|F9 | | |VCCO_1 | | |1 | | | | |any******| | | |
|F10 | | |VCCO_1 | | |1 | | | | |any******| | | |
|F11 | | |GND | | | | | | | | | | | |
|F12 | |DIFFS |IO_L21N_2 |UNUSED | |2 | | | | | | | | |
|F13 |sseg<1> |IOB |IO_L21P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|F14 |an<2> |IOB |IO_L22N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|F15 | |DIFFM |IO_L22P_2 |UNUSED | |2 | | | | | | | | |
|F16 | | |VCCAUX | | | | | | | |2.5 | | | |
|G1 | |DIFFM |IO_L40P_7 |UNUSED | |7 | | | | | | | | |
|G2 | |DIFFS |IO |UNUSED | |7 | | | | | | | | |
|G3 |WE_SRAMn |IOB |IO_L24N_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|G4 |AD<5> |IOB |IO_L24P_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|G5 |AD<10> |IOB |IO_L23N_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|G6 | | |VCCO_7 | | |7 | | | | |2.50 | | | |
|G7 | | |GND | | | | | | | | | | | |
|G8 | | |GND | | | | | | | | | | | |
|G9 | | |GND | | | | | | | | | | | |
|G10 | | |GND | | | | | | | | | | | |
|G11 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|G12 | |DIFFS |IO_L23N_2/VREF_2 |UNUSED | |2 | | | | | | | | |
|G13 |sseg<5> |IOB |IO_L23P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|G14 |an<1> |IOB |IO_L24N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|G15 | |DIFFM |IO_L24P_2 |UNUSED | |2 | | | | | | | | |
|G16 | |DIFFM |IO |UNUSED | |2 | | | | | | | | |
|H1 | |DIFFS |IO_L40N_7/VREF_7 |UNUSED | |7 | | | | | | | | |
|H2 | | |GND | | | | | | | | | | | |
|H3 |AD<11> |IOB |IO_L39N_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|H4 |AD<12> |IOB |IO_L39P_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|H5 | | |VCCO_7 | | |7 | | | | |2.50 | | | |
|H6 | | |VCCO_7 | | |7 | | | | |2.50 | | | |
|H7 | | |GND | | | | | | | | | | | |
|H8 | | |GND | | | | | | | | | | | |
|H9 | | |GND | | | | | | | | | | | |
|H10 | | |GND | | | | | | | | | | | |
|H11 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|H12 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|H13 | |DIFFS |IO_L39N_2 |UNUSED | |2 | | | | | | | | |
|H14 | |DIFFM |IO_L39P_2 |UNUSED | |2 | | | | | | | | |
|H15 | |DIFFS |IO_L40N_2 |UNUSED | |2 | | | | | | | | |
|H16 | |DIFFM |IO_L40P_2/VREF_2 |UNUSED | |2 | | | | | | | | |
|J1 |VIDEO_R |IOB |IO_L40P_6/VREF_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|J2 |VIDEO_G |IOB |IO_L40N_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|J3 |AD<14> |IOB |IO_L39P_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|J4 |AD<13> |IOB |IO_L39N_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|J5 | | |VCCO_6 | | |6 | | | | |2.50 | | | |
|J6 | | |VCCO_6 | | |6 | | | | |2.50 | | | |
|J7 | | |GND | | | | | | | | | | | |
|J8 | | |GND | | | | | | | | | | | |
|J9 | | |GND | | | | | | | | | | | |
|J10 | | |GND | | | | | | | | | | | |
|J11 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|J12 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|J13 | |DIFFM |IO_L39P_3 |UNUSED | |3 | | | | | | | | |
|J14 | |DIFFS |IO_L39N_3 |UNUSED | |3 | | | | | | | | |
|J15 | | |GND | | | | | | | | | | | |
|J16 | |DIFFS |IO_L40N_3/VREF_3 |UNUSED | |3 | | | | | | | | |
|K1 |VIDEO_B |IOB |IO |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|K2 | |DIFFM |IO_L24P_6 |UNUSED | |6 | | | | | | | | |
|K3 |AD<15> |IOB |IO_L24N_6/VREF_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|K4 |OE_SRAMn |IOB |IO_L23P_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|K5 |AD<16> |IOB |IO_L23N_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|K6 | | |VCCO_6 | | |6 | | | | |2.50 | | | |
|K7 | | |GND | | | | | | | | | | | |
|K8 | | |GND | | | | | | | | | | | |
|K9 | | |GND | | | | | | | | | | | |
|K10 | | |GND | | | | | | | | | | | |
|K11 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|K12 | |DIFFS |IO_L23N_3 |UNUSED | |3 | | | | | | | | |
|K13 | |DIFFM |IO_L24P_3 |UNUSED | |3 | | | | | | | | |
|K14 | |DIFFS |IO_L24N_3 |UNUSED | |3 | | | | | | | | |
|K15 | |DIFFS |IO |UNUSED | |3 | | | | | | | | |
|K16 | |DIFFM |IO_L40P_3 |UNUSED | |3 | | | | | | | | |
|L1 | | |VCCAUX | | | | | | | |2.5 | | | |
|L2 |VIDEO_SYNC |IOB |IO_L22P_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|L3 |AD<17> |IOB |IO_L22N_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|L4 |AD<4> |IOB |IO_L21P_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|L5 |AD<0> |IOB |IO_L21N_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|L6 | | |GND | | | | | | | | | | | |
|L7 | | |VCCO_5 | | |5 | | | | |2.50 | | | |
|L8 | | |VCCO_5 | | |5 | | | | |2.50 | | | |
|L9 | | |VCCO_4 | | |4 | | | | |2.50 | | | |
|L10 | | |VCCO_4 | | |4 | | | | |2.50 | | | |
|L11 | | |GND | | | | | | | | | | | |
|L12 | |DIFFM |IO_L23P_3/VREF_3 |UNUSED | |3 | | | | | | | | |
|L13 |btn<2> |IOB |IO_L21N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|L14 |RESETn |IOB |IO_L22P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|L15 | |DIFFS |IO_L22N_3 |UNUSED | |3 | | | | | | | | |
|L16 | | |VCCAUX | | | | | | | |2.5 | | | |
|M1 | |DIFFM |IO_L20P_6 |UNUSED | |6 | | | | | | | | |
|M2 | |DIFFS |IO_L20N_6 |UNUSED | |6 | | | | | | | | |
|M3 |AD<3> |IOB |IO_L19P_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|M4 |AD<2> |IOB |IO_L19N_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|M5 | | |VCCINT | | | | | | | |1.2 | | | |
|M6 | |DIFFM |IO_L28P_5/D7 |UNUSED | |5 | | | | | | | | |
|M7 | |DIFFM |IO_L30P_5 |UNUSED | |5 | | | | | | | | |
|M8 | | |VCCO_5 | | |5 | | | | |2.50 | | | |
|M9 | | |VCCO_4 | | |4 | | | | |2.50 | | | |
|M10 | |DIFFS |IO_L29N_4 |UNUSED | |4 | | | | | | | | |
|M11 | |DIFFS |IO_L27N_4/DIN/D0 |UNUSED | |4 | | | | | | | | |
|M12 | | |VCCINT | | | | | | | |1.2 | | | |
|M13 |btn<0> |IOB |IO_L21P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|M14 |btn<1> |IOB |IO_L19N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|M15 |PS2_DATA |IOB |IO_L20P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|M16 |PS2_CLK |IOB |IO_L20N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|N1 | |DIFFM |IO_L17P_6/VREF_6 |UNUSED | |6 | | | | | | | | |
|N2 | |DIFFS |IO_L17N_6 |UNUSED | |6 | | | | | | | | |
|N3 |AD<1> |IOB |IO_L16P_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|N4 | | |VCCINT | | | | | | | |1.2 | | | |
|N5 | |IOB |IO |UNUSED | |5 | | | | | | | | |
|N6 | |DIFFS |IO_L28N_5/D6 |UNUSED | |5 | | | | | | | | |
|N7 |D<0> |IOB |IO_L30N_5 |BIDIR |LVCMOS25* |5 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|N8 | |DIFFM |IO_L32P_5/GCLK2 |UNUSED | |5 | | | | | | | | |
|N9 | |DIFFS |IO_L31N_4/INIT_B |UNUSED | |4 | | | | | | | | |
|N10 | |DIFFM |IO_L29P_4 |UNUSED | |4 | | | | | | | | |
|N11 | |DIFFM |IO_L27P_4/D1 |UNUSED | |4 | | | | | | | | |
|N12 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | |
|N13 | | |VCCINT | | | | | | | |1.2 | | | |
|N14 | |DIFFM |IO_L19P_3 |UNUSED | |3 | | | | | | | | |
|N15 |sseg<4> |IOB |IO_L17P_3/VREF_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|N16 |sseg<0> |IOB |IO_L17N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P1 | |DIFFM |IO_L01P_6/VRN_6 |UNUSED | |6 | | | | | | | | |
|P2 | |DIFFS |IO_L16N_6 |UNUSED | |6 | | | | | | | | |
|P3 | | |M0 | | | | | | | | | | | |
|P4 | | |M2 | | | | | | | | | | | |
|P5 | |DIFFM |IO_L27P_5 |UNUSED | |5 | | | | | | | | |
|P6 |LB_SRAMn |IOB |IO_L29P_5/VREF_5 |OUTPUT |LVCMOS25* |5 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P7 |CE_SRAMn |IOB |IO |OUTPUT |LVCMOS25* |5 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P8 | |DIFFS |IO_L32N_5/GCLK3 |UNUSED | |5 | | | | | | | | |
|P9 | |DIFFM |IO_L31P_4/DOUT/BUSY|UNUSED | |4 | | | | | | | | |
|P10 | |DIFFS |IO_L30N_4/D2 |UNUSED | |4 | | | | | | | | |
|P11 | |DIFFS |IO_L28N_4 |UNUSED | |4 | | | | | | | | |
|P12 | |DIFFS |IO_L25N_4 |UNUSED | |4 | | | | | | | | |
|P13 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | |
|P14 | |DIFFM |IO_L16P_3 |UNUSED | |3 | | | | | | | | |
|P15 |sseg<3> |IOB |IO_L16N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P16 |sseg<7> |IOB |IO_L01N_3/VRP_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|R1 | |DIFFS |IO_L01N_6/VRP_6 |UNUSED | |6 | | | | | | | | |
|R2 | | |GND | | | | | | | | | | | |
|R3 | |DIFFM |IO_L01P_5/CS_B |UNUSED | |5 | | | | | | | | |
|R4 | |DIFFM |IO_L10P_5/VRN_5 |UNUSED | |5 | | | | | | | | |
|R5 |D<4> |IOB |IO_L27N_5/VREF_5 |BIDIR |LVCMOS25* |5 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|R6 |D<2> |IOB |IO_L29N_5 |BIDIR |LVCMOS25* |5 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|R7 | |DIFFM |IO_L31P_5/D5 |UNUSED | |5 | | | | | | | | |
|R8 | | |GND | | | | | | | | | | | |
|R9 |RW |IOB |IO_L32N_4/GCLK1 |OUTPUT |LVCMOS25* |4 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|R10 | |DIFFM |IO_L30P_4/D3 |UNUSED | |4 | | | | | | | | |
|R11 | |DIFFM |IO_L28P_4 |UNUSED | |4 | | | | | | | | |
|R12 | |DIFFM |IO_L25P_4 |UNUSED | |4 | | | | | | | | |
|R13 | |DIFFS |IO_L01N_4/VRP_4 |UNUSED | |4 | | | | | | | | |
|R14 | | |DONE | | | | | | | | | | | |
|R15 | | |GND | | | | | | | | | | | |
|R16 |sseg<2> |IOB |IO_L01P_3/VRN_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|T1 | | |GND | | | | | | | | | | | |
|T2 | | |M1 | | | | | | | | | | | |
|T3 | |DIFFS |IO_L01N_5/RDWR_B |UNUSED | |5 | | | | | | | | |
|T4 |UB_SRAMn |IOB |IO_L10N_5/VRP_5 |OUTPUT |LVCMOS25* |5 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|T5 |D<3> |IOB |IO |BIDIR |LVCMOS25* |5 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|T6 | | |VCCAUX | | | | | | | |2.5 | | | |
|T7 | |DIFFS |IO_L31N_5/D4 |UNUSED | |5 | | | | | | | | |
|T8 |D<1> |IOB |IO/VREF_5 |BIDIR |LVCMOS25* |5 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|T9 |CLK_50 |IOB |IO_L32P_4/GCLK0 |INPUT |LVCMOS25* |4 | | | |NONE | |LOCATED |NO |NONE |
|T10 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | |
|T11 | | |VCCAUX | | | | | | | |2.5 | | | |
|T12 | |IOB |IO |UNUSED | |4 | | | | | | | | |
|T13 | |DIFFM |IO_L01P_4/VRN_4 |UNUSED | |4 | | | | | | | | |
|T14 | |DIFFS |IO |UNUSED | |4 | | | | | | | | |
|T15 | | |CCLK | | | | | | | | | | | |
|T16 | | |GND | | | | | | | | | | | |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.

BIN
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@@ -0,0 +1,170 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="OricinFPGA.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_LSO" xil_pn:name=".lso"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="FILE_LOG_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="FILE_LOG_stx_beh.prj"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ORIC.prj"/>
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="ORIC.stx"/>
<file xil_pn:fileType="FILE_XST" xil_pn:name="ORIC.xst"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="ORIC_isim_beh.exe"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="memmap_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="simul_test_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="simul_test_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="simul_test_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="simul_test_stx_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="ula_log_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1324894412" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1324894412">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1324894412" xil_pn:in_ck="6316734020865723497" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1324894412">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="DISP_HEX.vhd"/>
<outfile xil_pn:name="DISP_UNIT.vhd"/>
<outfile xil_pn:name="SRAM.vhd"/>
<outfile xil_pn:name="STOP_WATCH.vhd"/>
<outfile xil_pn:name="ULA_LOG.vhd"/>
<outfile xil_pn:name="addmemux.vhd"/>
<outfile xil_pn:name="ay3819x.vhd"/>
<outfile xil_pn:name="ctrlseq.vhd"/>
<outfile xil_pn:name="dac.vhd"/>
<outfile xil_pn:name="file_log.vhd"/>
<outfile xil_pn:name="gen_clk.vhd"/>
<outfile xil_pn:name="gen_env.vhd"/>
<outfile xil_pn:name="iodecode.vhd"/>
<outfile xil_pn:name="keyboard.vhd"/>
<outfile xil_pn:name="keymap.vhd"/>
<outfile xil_pn:name="keymatrix.vhd"/>
<outfile xil_pn:name="m6522.vhd"/>
<outfile xil_pn:name="manage_amplitude.vhd"/>
<outfile xil_pn:name="memmap.vhd"/>
<outfile xil_pn:name="noise_generator.vhd"/>
<outfile xil_pn:name="oa_test.vhd"/>
<outfile xil_pn:name="oricatmos.vhd"/>
<outfile xil_pn:name="pack_oric_xilinx_prims.vhd"/>
<outfile xil_pn:name="pack_oricatmos.vhd"/>
<outfile xil_pn:name="pack_t65.vhd"/>
<outfile xil_pn:name="pack_ula.vhd"/>
<outfile xil_pn:name="ps2key.vhd"/>
<outfile xil_pn:name="psg_log.vhd"/>
<outfile xil_pn:name="rom_oa.vhd"/>
<outfile xil_pn:name="simul_test.vhd"/>
<outfile xil_pn:name="t65.vhd"/>
<outfile xil_pn:name="t65_MCode.vhd"/>
<outfile xil_pn:name="t65_alu.vhd"/>
<outfile xil_pn:name="tone_generator.vhd"/>
<outfile xil_pn:name="txt_util.vhd"/>
<outfile xil_pn:name="ula.vhd"/>
<outfile xil_pn:name="vag.vhd"/>
<outfile xil_pn:name="video.vhd"/>
</transform>
<transform xil_pn:end_ts="1324894412" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-623724164505690369" xil_pn:start_ts="1324894412">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1324894412" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5541081177768733925" xil_pn:start_ts="1324894412">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1324894412" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-3832308785315811670" xil_pn:start_ts="1324894412">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1324894412" xil_pn:in_ck="6316734020865723497" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1324894412">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="DISP_HEX.vhd"/>
<outfile xil_pn:name="DISP_UNIT.vhd"/>
<outfile xil_pn:name="SRAM.vhd"/>
<outfile xil_pn:name="STOP_WATCH.vhd"/>
<outfile xil_pn:name="ULA_LOG.vhd"/>
<outfile xil_pn:name="addmemux.vhd"/>
<outfile xil_pn:name="ay3819x.vhd"/>
<outfile xil_pn:name="ctrlseq.vhd"/>
<outfile xil_pn:name="dac.vhd"/>
<outfile xil_pn:name="file_log.vhd"/>
<outfile xil_pn:name="gen_clk.vhd"/>
<outfile xil_pn:name="gen_env.vhd"/>
<outfile xil_pn:name="iodecode.vhd"/>
<outfile xil_pn:name="keyboard.vhd"/>
<outfile xil_pn:name="keymap.vhd"/>
<outfile xil_pn:name="keymatrix.vhd"/>
<outfile xil_pn:name="m6522.vhd"/>
<outfile xil_pn:name="manage_amplitude.vhd"/>
<outfile xil_pn:name="memmap.vhd"/>
<outfile xil_pn:name="noise_generator.vhd"/>
<outfile xil_pn:name="oa_test.vhd"/>
<outfile xil_pn:name="oricatmos.vhd"/>
<outfile xil_pn:name="pack_oric_xilinx_prims.vhd"/>
<outfile xil_pn:name="pack_oricatmos.vhd"/>
<outfile xil_pn:name="pack_t65.vhd"/>
<outfile xil_pn:name="pack_ula.vhd"/>
<outfile xil_pn:name="ps2key.vhd"/>
<outfile xil_pn:name="psg_log.vhd"/>
<outfile xil_pn:name="rom_oa.vhd"/>
<outfile xil_pn:name="simul_test.vhd"/>
<outfile xil_pn:name="t65.vhd"/>
<outfile xil_pn:name="t65_MCode.vhd"/>
<outfile xil_pn:name="t65_alu.vhd"/>
<outfile xil_pn:name="tone_generator.vhd"/>
<outfile xil_pn:name="txt_util.vhd"/>
<outfile xil_pn:name="ula.vhd"/>
<outfile xil_pn:name="vag.vhd"/>
<outfile xil_pn:name="video.vhd"/>
</transform>
<transform xil_pn:end_ts="1324894417" xil_pn:in_ck="6316734020865723497" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="589917253963545191" xil_pn:start_ts="1324894412">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="simul_test_beh.prj"/>
<outfile xil_pn:name="simul_test_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1324894418" xil_pn:in_ck="-280243908413541662" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-6660432983106578295" xil_pn:start_ts="1324894417">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="simul_test_isim_beh.wdb"/>
</transform>
</transforms>
</generated_project>

497
Oric Atmos_MiST/storage/OricinFPGA.xise Normal file
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@@ -0,0 +1,497 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="addmemux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="ay3819x.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="ctrlseq.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="gen_clk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="gen_env.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="iodecode.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="keyboard.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="keymap.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="keymatrix.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="m6522.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="manage_amplitude.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="memmap.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="noise_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="oricatmos.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="pack_oric_xilinx_prims.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="pack_oricatmos.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="pack_t65.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="pack_ula.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="ps2key.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="rom_oa.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="t65.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="t65_MCode.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="t65_alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="tone_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="ula.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="vag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="video.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="oa_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="DISP_HEX.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="STOP_WATCH.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="DISP_UNIT.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="SRAM.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="txt_util.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="file_log.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="simul_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="ORIC.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="psg_log.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="ULA_LOG.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
</files>
<properties>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Port" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Simulation Command File" xil_pn:value="test.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xa3s1000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ORIC|RTL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="oricatmos.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ORIC" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instance Name for Simulation in Hardware" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="ORIC" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="ftg256" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="ORIC_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="ORIC_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="ORIC_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="ORIC_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Re-Use Last Bitstream File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="ORIC" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/simul_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.simul_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="100000 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.simul_test" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Board for Hardware Co-Simulation" xil_pn:value="N/A" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="ORIC.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|simul_test|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="OricinFPGA" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-09-06T21:54:43" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="794468EA9878FB0D13152CBF9D6D35B9" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
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</autoManagedFiles>
</project>

5
Oric Atmos_MiST/storage/PLLJ_PLLSPE_INFO.txt Normal file
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PLL_Name pll:inst_pll|altpll:altpll_component|pll_altpll:auto_generated|pll1
PLLJITTER 31
PLLSPEmax 84
PLLSPEmin -53

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Oric Atmos_MiST/storage/oric_PS2_IF_pad.txt Normal file
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Release 11.1 - par L.33 (lin)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Thu Jan 28 22:35:29 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
INPUT FILE: oric_PS2_IF_map.ncd
OUTPUT FILE: oric_PS2_IF_pad.txt
PART TYPE: xa3s1000
SPEED GRADE: -4
PACKAGE: ftg256
Pinout by Pin Number:
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|A1 | | |GND | | | | | | | | | | | |
|A2 | | |TDI | | | | | | | | | | | |
|A3 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | |
|A4 | |DIFFM |IO_L01P_0/VRN_0 |UNUSED | |0 | | | | | | | | |
|A5 | |IOB |IO |UNUSED | |0 | | | | | | | | |
|A6 | | |VCCAUX | | | | | | | |2.5 | | | |
|A7 | |IOB |IO |UNUSED | |0 | | | | | | | | |
|A8 |RESTORE |IOB |IO_L32P_0/GCLK6 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|A9 | |IOB |IO |UNUSED | |1 | | | | | | | | |
|A10 | |DIFFS |IO_L31N_1/VREF_1 |UNUSED | |1 | | | | | | | | |
|A11 | | |VCCAUX | | | | | | | |2.5 | | | |
|A12 | |IOB |IO |UNUSED | |1 | | | | | | | | |
|A13 | |DIFFS |IO_L10N_1/VREF_1 |UNUSED | |1 | | | | | | | | |
|A14 | |DIFFS |IO_L01N_1/VRP_1 |UNUSED | |1 | | | | | | | | |
|A15 | | |TDO | | | | | | | | | | | |
|A16 | | |GND | | | | | | | | | | | |
|B1 | |DIFFM |IO_L01P_7/VRN_7 |UNUSED | |7 | | | | | | | | |
|B2 | | |GND | | | | | | | | | | | |
|B3 | | |PROG_B | | | | | | | | | | | |
|B4 | |DIFFS |IO_L01N_0/VRP_0 |UNUSED | |0 | | | | | | | | |
|B5 | |DIFFM |IO_L25P_0 |UNUSED | |0 | | | | | | | | |
|B6 | |DIFFM |IO_L28P_0 |UNUSED | |0 | | | | | | | | |
|B7 | |DIFFM |IO_L30P_0 |UNUSED | |0 | | | | | | | | |
|B8 | |DIFFS |IO_L32N_0/GCLK7 |UNUSED | |0 | | | | | | | | |
|B9 | | |GND | | | | | | | | | | | |
|B10 | |DIFFM |IO_L31P_1 |UNUSED | |1 | | | | | | | | |
|B11 | |DIFFS |IO_L29N_1 |UNUSED | |1 | | | | | | | | |
|B12 | |DIFFS |IO_L27N_1 |UNUSED | |1 | | | | | | | | |
|B13 | |DIFFM |IO_L10P_1 |UNUSED | |1 | | | | | | | | |
|B14 | |DIFFM |IO_L01P_1/VRN_1 |UNUSED | |1 | | | | | | | | |
|B15 | | |GND | | | | | | | | | | | |
|B16 | |DIFFS |IO_L01N_2/VRP_2 |UNUSED | |2 | | | | | | | | |
|C1 | |DIFFS |IO_L01N_7/VRP_7 |UNUSED | |7 | | | | | | | | |
|C2 | |DIFFS |IO_L16N_7 |UNUSED | |7 | | | | | | | | |
|C3 | |DIFFM |IO_L16P_7/VREF_7 |UNUSED | |7 | | | | | | | | |
|C4 | | |HSWAP_EN | | | | | | | | | | | |
|C5 | |DIFFS |IO_L25N_0 |UNUSED | |0 | | | | | | | | |
|C6 | |DIFFS |IO_L28N_0 |UNUSED | |0 | | | | | | | | |
|C7 | |DIFFS |IO_L30N_0 |UNUSED | |0 | | | | | | | | |
|C8 | |DIFFM |IO_L31P_0/VREF_0 |UNUSED | |0 | | | | | | | | |
|C9 | |DIFFS |IO_L32N_1/GCLK5 |UNUSED | |1 | | | | | | | | |
|C10 | |IOB |IO |UNUSED | |1 | | | | | | | | |
|C11 | |DIFFM |IO_L29P_1 |UNUSED | |1 | | | | | | | | |
|C12 | |DIFFM |IO_L27P_1 |UNUSED | |1 | | | | | | | | |
|C13 | | |TMS | | | | | | | | | | | |
|C14 | | |TCK | | | | | | | | | | | |
|C15 | |DIFFS |IO_L16N_2 |UNUSED | |2 | | | | | | | | |
|C16 | |DIFFM |IO_L01P_2/VRN_2 |UNUSED | |2 | | | | | | | | |
|D1 | |DIFFS |IO_L17N_7 |UNUSED | |7 | | | | | | | | |
|D2 | |DIFFM |IO_L17P_7 |UNUSED | |7 | | | | | | | | |
|D3 | |DIFFM |IO_L19P_7 |UNUSED | |7 | | | | | | | | |
|D4 | | |VCCINT | | | | | | | |1.2 | | | |
|D5 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | |
|D6 | |DIFFM |IO_L27P_0 |UNUSED | |0 | | | | | | | | |
|D7 | |DIFFM |IO_L29P_0 |UNUSED | |0 | | | | | | | | |
|D8 | |DIFFS |IO_L31N_0 |UNUSED | |0 | | | | | | | | |
|D9 | |DIFFM |IO_L32P_1/GCLK4 |UNUSED | |1 | | | | | | | | |
|D10 | |DIFFS |IO_L30N_1 |UNUSED | |1 | | | | | | | | |
|D11 | |DIFFS |IO_L28N_1 |UNUSED | |1 | | | | | | | | |
|D12 | |IOB |IO/VREF_1 |UNUSED | |1 | | | | | | | | |
|D13 | | |VCCINT | | | | | | | |1.2 | | | |
|D14 | |DIFFM |IO_L16P_2 |UNUSED | |2 | | | | | | | | |
|D15 | |DIFFS |IO_L17N_2 |UNUSED | |2 | | | | | | | | |
|D16 | |DIFFM |IO_L17P_2/VREF_2 |UNUSED | |2 | | | | | | | | |
|E1 | |DIFFS |IO_L20N_7 |UNUSED | |7 | | | | | | | | |
|E2 | |DIFFM |IO_L20P_7 |UNUSED | |7 | | | | | | | | |
|E3 | |DIFFS |IO_L19N_7/VREF_7 |UNUSED | |7 | | | | | | | | |
|E4 | |DIFFM |IO_L21P_7 |UNUSED | |7 | | | | | | | | |
|E5 | | |VCCINT | | | | | | | |1.2 | | | |
|E6 | |DIFFS |IO_L27N_0 |UNUSED | |0 | | | | | | | | |
|E7 | |DIFFS |IO_L29N_0 |UNUSED | |0 | | | | | | | | |
|E8 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|E9 | | |VCCO_1 | | |1 | | | | |any******| | | |
|E10 | |DIFFM |IO_L30P_1 |UNUSED | |1 | | | | | | | | |
|E11 | |DIFFM |IO_L28P_1 |UNUSED | |1 | | | | | | | | |
|E12 | | |VCCINT | | | | | | | |1.2 | | | |
|E13 | |DIFFS |IO_L19N_2 |UNUSED | |2 | | | | | | | | |
|E14 | |DIFFM |IO_L19P_2 |UNUSED | |2 | | | | | | | | |
|E15 | |DIFFS |IO_L20N_2 |UNUSED | |2 | | | | | | | | |
|E16 | |DIFFM |IO_L20P_2 |UNUSED | |2 | | | | | | | | |
|F1 | | |VCCAUX | | | | | | | |2.5 | | | |
|F2 | |DIFFS |IO_L22N_7 |UNUSED | |7 | | | | | | | | |
|F3 | |DIFFM |IO_L22P_7 |UNUSED | |7 | | | | | | | | |
|F4 | |DIFFS |IO_L21N_7 |UNUSED | |7 | | | | | | | | |
|F5 | |DIFFM |IO_L23P_7 |UNUSED | |7 | | | | | | | | |
|F6 | | |GND | | | | | | | | | | | |
|F7 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|F8 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|F9 | | |VCCO_1 | | |1 | | | | |any******| | | |
|F10 | | |VCCO_1 | | |1 | | | | |any******| | | |
|F11 | | |GND | | | | | | | | | | | |
|F12 | |DIFFS |IO_L21N_2 |UNUSED | |2 | | | | | | | | |
|F13 | |DIFFM |IO_L21P_2 |UNUSED | |2 | | | | | | | | |
|F14 | |DIFFS |IO_L22N_2 |UNUSED | |2 | | | | | | | | |
|F15 | |DIFFM |IO_L22P_2 |UNUSED | |2 | | | | | | | | |
|F16 | | |VCCAUX | | | | | | | |2.5 | | | |
|G1 | |DIFFM |IO_L40P_7 |UNUSED | |7 | | | | | | | | |
|G2 | |DIFFS |IO |UNUSED | |7 | | | | | | | | |
|G3 | |DIFFS |IO_L24N_7 |UNUSED | |7 | | | | | | | | |
|G4 | |DIFFM |IO_L24P_7 |UNUSED | |7 | | | | | | | | |
|G5 | |DIFFS |IO_L23N_7 |UNUSED | |7 | | | | | | | | |
|G6 | | |VCCO_7 | | |7 | | | | |any******| | | |
|G7 | | |GND | | | | | | | | | | | |
|G8 | | |GND | | | | | | | | | | | |
|G9 | | |GND | | | | | | | | | | | |
|G10 | | |GND | | | | | | | | | | | |
|G11 | | |VCCO_2 | | |2 | | | | |any******| | | |
|G12 | |DIFFS |IO_L23N_2/VREF_2 |UNUSED | |2 | | | | | | | | |
|G13 | |DIFFM |IO_L23P_2 |UNUSED | |2 | | | | | | | | |
|G14 | |DIFFS |IO_L24N_2 |UNUSED | |2 | | | | | | | | |
|G15 | |DIFFM |IO_L24P_2 |UNUSED | |2 | | | | | | | | |
|G16 | |DIFFM |IO |UNUSED | |2 | | | | | | | | |
|H1 | |DIFFS |IO_L40N_7/VREF_7 |UNUSED | |7 | | | | | | | | |
|H2 | | |GND | | | | | | | | | | | |
|H3 | |DIFFS |IO_L39N_7 |UNUSED | |7 | | | | | | | | |
|H4 | |DIFFM |IO_L39P_7 |UNUSED | |7 | | | | | | | | |
|H5 | | |VCCO_7 | | |7 | | | | |any******| | | |
|H6 | | |VCCO_7 | | |7 | | | | |any******| | | |
|H7 | | |GND | | | | | | | | | | | |
|H8 | | |GND | | | | | | | | | | | |
|H9 | | |GND | | | | | | | | | | | |
|H10 | | |GND | | | | | | | | | | | |
|H11 | | |VCCO_2 | | |2 | | | | |any******| | | |
|H12 | | |VCCO_2 | | |2 | | | | |any******| | | |
|H13 | |DIFFS |IO_L39N_2 |UNUSED | |2 | | | | | | | | |
|H14 | |DIFFM |IO_L39P_2 |UNUSED | |2 | | | | | | | | |
|H15 | |DIFFS |IO_L40N_2 |UNUSED | |2 | | | | | | | | |
|H16 | |DIFFM |IO_L40P_2/VREF_2 |UNUSED | |2 | | | | | | | | |
|J1 | |DIFFM |IO_L40P_6/VREF_6 |UNUSED | |6 | | | | | | | | |
|J2 | |DIFFS |IO_L40N_6 |UNUSED | |6 | | | | | | | | |
|J3 | |DIFFM |IO_L39P_6 |UNUSED | |6 | | | | | | | | |
|J4 | |DIFFS |IO_L39N_6 |UNUSED | |6 | | | | | | | | |
|J5 | | |VCCO_6 | | |6 | | | | |any******| | | |
|J6 | | |VCCO_6 | | |6 | | | | |any******| | | |
|J7 | | |GND | | | | | | | | | | | |
|J8 | | |GND | | | | | | | | | | | |
|J9 | | |GND | | | | | | | | | | | |
|J10 | | |GND | | | | | | | | | | | |
|J11 | | |VCCO_3 | | |3 | | | | |any******| | | |
|J12 | | |VCCO_3 | | |3 | | | | |any******| | | |
|J13 | |DIFFM |IO_L39P_3 |UNUSED | |3 | | | | | | | | |
|J14 | |DIFFS |IO_L39N_3 |UNUSED | |3 | | | | | | | | |
|J15 | | |GND | | | | | | | | | | | |
|J16 | |DIFFS |IO_L40N_3/VREF_3 |UNUSED | |3 | | | | | | | | |
|K1 | |DIFFM |IO |UNUSED | |6 | | | | | | | | |
|K2 | |DIFFM |IO_L24P_6 |UNUSED | |6 | | | | | | | | |
|K3 | |DIFFS |IO_L24N_6/VREF_6 |UNUSED | |6 | | | | | | | | |
|K4 | |DIFFM |IO_L23P_6 |UNUSED | |6 | | | | | | | | |
|K5 | |DIFFS |IO_L23N_6 |UNUSED | |6 | | | | | | | | |
|K6 | | |VCCO_6 | | |6 | | | | |any******| | | |
|K7 | | |GND | | | | | | | | | | | |
|K8 | | |GND | | | | | | | | | | | |
|K9 | | |GND | | | | | | | | | | | |
|K10 | | |GND | | | | | | | | | | | |
|K11 | | |VCCO_3 | | |3 | | | | |any******| | | |
|K12 | |DIFFS |IO_L23N_3 |UNUSED | |3 | | | | | | | | |
|K13 | |DIFFM |IO_L24P_3 |UNUSED | |3 | | | | | | | | |
|K14 | |DIFFS |IO_L24N_3 |UNUSED | |3 | | | | | | | | |
|K15 | |DIFFS |IO |UNUSED | |3 | | | | | | | | |
|K16 | |DIFFM |IO_L40P_3 |UNUSED | |3 | | | | | | | | |
|L1 | | |VCCAUX | | | | | | | |2.5 | | | |
|L2 | |DIFFM |IO_L22P_6 |UNUSED | |6 | | | | | | | | |
|L3 | |DIFFS |IO_L22N_6 |UNUSED | |6 | | | | | | | | |
|L4 | |DIFFM |IO_L21P_6 |UNUSED | |6 | | | | | | | | |
|L5 | |DIFFS |IO_L21N_6 |UNUSED | |6 | | | | | | | | |
|L6 | | |GND | | | | | | | | | | | |
|L7 | | |VCCO_5 | | |5 | | | | |any******| | | |
|L8 | | |VCCO_5 | | |5 | | | | |any******| | | |
|L9 | | |VCCO_4 | | |4 | | | | |any******| | | |
|L10 | | |VCCO_4 | | |4 | | | | |any******| | | |
|L11 | | |GND | | | | | | | | | | | |
|L12 | |DIFFM |IO_L23P_3/VREF_3 |UNUSED | |3 | | | | | | | | |
|L13 | |DIFFS |IO_L21N_3 |UNUSED | |3 | | | | | | | | |
|L14 | |DIFFM |IO_L22P_3 |UNUSED | |3 | | | | | | | | |
|L15 | |DIFFS |IO_L22N_3 |UNUSED | |3 | | | | | | | | |
|L16 | | |VCCAUX | | | | | | | |2.5 | | | |
|M1 | |DIFFM |IO_L20P_6 |UNUSED | |6 | | | | | | | | |
|M2 | |DIFFS |IO_L20N_6 |UNUSED | |6 | | | | | | | | |
|M3 | |DIFFM |IO_L19P_6 |UNUSED | |6 | | | | | | | | |
|M4 | |DIFFS |IO_L19N_6 |UNUSED | |6 | | | | | | | | |
|M5 | | |VCCINT | | | | | | | |1.2 | | | |
|M6 | |DIFFM |IO_L28P_5/D7 |UNUSED | |5 | | | | | | | | |
|M7 | |DIFFM |IO_L30P_5 |UNUSED | |5 | | | | | | | | |
|M8 | | |VCCO_5 | | |5 | | | | |any******| | | |
|M9 | | |VCCO_4 | | |4 | | | | |any******| | | |
|M10 | |DIFFS |IO_L29N_4 |UNUSED | |4 | | | | | | | | |
|M11 | |DIFFS |IO_L27N_4/DIN/D0 |UNUSED | |4 | | | | | | | | |
|M12 | | |VCCINT | | | | | | | |1.2 | | | |
|M13 | |DIFFM |IO_L21P_3 |UNUSED | |3 | | | | | | | | |
|M14 | |DIFFS |IO_L19N_3 |UNUSED | |3 | | | | | | | | |
|M15 | |DIFFM |IO_L20P_3 |UNUSED | |3 | | | | | | | | |
|M16 | |DIFFS |IO_L20N_3 |UNUSED | |3 | | | | | | | | |
|N1 | |DIFFM |IO_L17P_6/VREF_6 |UNUSED | |6 | | | | | | | | |
|N2 | |DIFFS |IO_L17N_6 |UNUSED | |6 | | | | | | | | |
|N3 | |DIFFM |IO_L16P_6 |UNUSED | |6 | | | | | | | | |
|N4 | | |VCCINT | | | | | | | |1.2 | | | |
|N5 | |IOB |IO |UNUSED | |5 | | | | | | | | |
|N6 | |DIFFS |IO_L28N_5/D6 |UNUSED | |5 | | | | | | | | |
|N7 | |DIFFS |IO_L30N_5 |UNUSED | |5 | | | | | | | | |
|N8 | |DIFFM |IO_L32P_5/GCLK2 |UNUSED | |5 | | | | | | | | |
|N9 | |DIFFS |IO_L31N_4/INIT_B |UNUSED | |4 | | | | | | | | |
|N10 | |DIFFM |IO_L29P_4 |UNUSED | |4 | | | | | | | | |
|N11 | |DIFFM |IO_L27P_4/D1 |UNUSED | |4 | | | | | | | | |
|N12 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | |
|N13 | | |VCCINT | | | | | | | |1.2 | | | |
|N14 | |DIFFM |IO_L19P_3 |UNUSED | |3 | | | | | | | | |
|N15 | |DIFFM |IO_L17P_3/VREF_3 |UNUSED | |3 | | | | | | | | |
|N16 | |DIFFS |IO_L17N_3 |UNUSED | |3 | | | | | | | | |
|P1 | |DIFFM |IO_L01P_6/VRN_6 |UNUSED | |6 | | | | | | | | |
|P2 | |DIFFS |IO_L16N_6 |UNUSED | |6 | | | | | | | | |
|P3 | | |M0 | | | | | | | | | | | |
|P4 | | |M2 | | | | | | | | | | | |
|P5 | |DIFFM |IO_L27P_5 |UNUSED | |5 | | | | | | | | |
|P6 | |DIFFM |IO_L29P_5/VREF_5 |UNUSED | |5 | | | | | | | | |
|P7 | |IOB |IO |UNUSED | |5 | | | | | | | | |
|P8 | |DIFFS |IO_L32N_5/GCLK3 |UNUSED | |5 | | | | | | | | |
|P9 | |DIFFM |IO_L31P_4/DOUT/BUSY|UNUSED | |4 | | | | | | | | |
|P10 | |DIFFS |IO_L30N_4/D2 |UNUSED | |4 | | | | | | | | |
|P11 | |DIFFS |IO_L28N_4 |UNUSED | |4 | | | | | | | | |
|P12 | |DIFFS |IO_L25N_4 |UNUSED | |4 | | | | | | | | |
|P13 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | |
|P14 | |DIFFM |IO_L16P_3 |UNUSED | |3 | | | | | | | | |
|P15 | |DIFFS |IO_L16N_3 |UNUSED | |3 | | | | | | | | |
|P16 | |DIFFS |IO_L01N_3/VRP_3 |UNUSED | |3 | | | | | | | | |
|R1 | |DIFFS |IO_L01N_6/VRP_6 |UNUSED | |6 | | | | | | | | |
|R2 | | |GND | | | | | | | | | | | |
|R3 | |DIFFM |IO_L01P_5/CS_B |UNUSED | |5 | | | | | | | | |
|R4 | |DIFFM |IO_L10P_5/VRN_5 |UNUSED | |5 | | | | | | | | |
|R5 | |DIFFS |IO_L27N_5/VREF_5 |UNUSED | |5 | | | | | | | | |
|R6 | |DIFFS |IO_L29N_5 |UNUSED | |5 | | | | | | | | |
|R7 | |DIFFM |IO_L31P_5/D5 |UNUSED | |5 | | | | | | | | |
|R8 | | |GND | | | | | | | | | | | |
|R9 | |DIFFS |IO_L32N_4/GCLK1 |UNUSED | |4 | | | | | | | | |
|R10 | |DIFFM |IO_L30P_4/D3 |UNUSED | |4 | | | | | | | | |
|R11 | |DIFFM |IO_L28P_4 |UNUSED | |4 | | | | | | | | |
|R12 | |DIFFM |IO_L25P_4 |UNUSED | |4 | | | | | | | | |
|R13 | |DIFFS |IO_L01N_4/VRP_4 |UNUSED | |4 | | | | | | | | |
|R14 | | |DONE | | | | | | | | | | | |
|R15 | | |GND | | | | | | | | | | | |
|R16 | |DIFFM |IO_L01P_3/VRN_3 |UNUSED | |3 | | | | | | | | |
|T1 | | |GND | | | | | | | | | | | |
|T2 | | |M1 | | | | | | | | | | | |
|T3 | |DIFFS |IO_L01N_5/RDWR_B |UNUSED | |5 | | | | | | | | |
|T4 | |DIFFS |IO_L10N_5/VRP_5 |UNUSED | |5 | | | | | | | | |
|T5 | |IOB |IO |UNUSED | |5 | | | | | | | | |
|T6 | | |VCCAUX | | | | | | | |2.5 | | | |
|T7 | |DIFFS |IO_L31N_5/D4 |UNUSED | |5 | | | | | | | | |
|T8 | |IOB |IO/VREF_5 |UNUSED | |5 | | | | | | | | |
|T9 | |DIFFM |IO_L32P_4/GCLK0 |UNUSED | |4 | | | | | | | | |
|T10 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | |
|T11 | | |VCCAUX | | | | | | | |2.5 | | | |
|T12 | |IOB |IO |UNUSED | |4 | | | | | | | | |
|T13 | |DIFFM |IO_L01P_4/VRN_4 |UNUSED | |4 | | | | | | | | |
|T14 | |DIFFS |IO |UNUSED | |4 | | | | | | | | |
|T15 | | |CCLK | | | | | | | | | | | |
|T16 | | |GND | | | | | | | | | | | |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.

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22/01/2012 : Version 0.91 de travail / release working
FR :
Des mises à jour pour debugger
Correction de bugs.
GB
Many upadates to debug
Bugs fixes
01/02/2010 : Version 0.9 de travail / release working
Ce n'est pas encore un version fonctionnelle
mais c'est pour bientôt.
It's not running but perhaps tomorrow ? ;-)
======================================================
======================================================
Merci à / Thanks to :
+ MikeJ de www.fpgaarcade.com pour avoir mis à disposition une
version de AY-3-8192 qui a permis de corriger la mienne et pour
le source du VIA 6522,
+ Gregory Estrade de www.torlus.com (pour son aide et son libre accès
à son code vhdl)
+ Daniel Wallner pour le T65 (www.opencores.org)

0
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:49:44 12/03/2009
-- Design Name:
-- Module Name: BMP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BMP is
end BMP;
architecture Behavioral of BMP is
begin
-- Header
-- MAGIC NUMBER : 2 octets 'BM'
-- Size of bitmap : 4 octets
-- Reserved : 2 octets
-- Reserved : 2 octets
-- Offset : 4 octets
end Behavioral;

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-- Listing 4.15
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity disp_hex_mux is
port(
clk, reset: in std_logic;
hex3, hex2, hex1, hex0: in std_logic_vector(3 downto 0);
dp_in: in std_logic_vector(3 downto 0);
an: out std_logic_vector(3 downto 0);
sseg: out std_logic_vector(7 downto 0)
);
end disp_hex_mux ;
architecture arch of disp_hex_mux is
-- each 7-seg led enabled (2^18/4)*25 ns (40 ms)
constant N: integer:=18;
signal q_reg, q_next: unsigned(N-1 downto 0);
signal sel: std_logic_vector(1 downto 0);
signal hex: std_logic_vector(3 downto 0);
signal dp: std_logic;
begin
-- register
process(clk,reset)
begin
if reset='1' then
q_reg <= (others=>'0');
elsif (clk'event and clk='1') then
q_reg <= q_next;
end if;
end process;
-- next-state logic for the counter
q_next <= q_reg + 1;
-- 2 MSBs of counter to control 4-to-1 multiplexing
sel <= std_logic_vector(q_reg(N-1 downto N-2));
process(sel,hex0,hex1,hex2,hex3,dp_in)
begin
case sel is
when "00" =>
an <= "1110";
hex <= hex0;
dp <= dp_in(0);
when "01" =>
an <= "1101";
hex <= hex1;
dp <= dp_in(1);
when "10" =>
an <= "1011";
hex <= hex2;
dp <= dp_in(2);
when others =>
an <= "0111";
hex <= hex3;
dp <= dp_in(3);
end case;
end process;
-- hex-to-7-segment led decoding
with hex select
sseg(6 downto 0) <=
"0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010", --a
"1100000" when "1011", --b
"0110001" when "1100", --c
"1000010" when "1101", --d
"0110000" when "1110", --e
"0111000" when others; --f
-- decimal point
sseg(7) <= dp;
end arch;

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-- Listing 4.15
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity disp_hex_mux is
port(
clk, reset: in std_logic;
hex3, hex2, hex1, hex0: in std_logic_vector(3 downto 0);
dp_in: in std_logic_vector(3 downto 0);
an: out std_logic_vector(3 downto 0);
sseg: out std_logic_vector(7 downto 0)
);
end disp_hex_mux ;
architecture arch of disp_hex_mux is
-- each 7-seg led enabled (2^18/4)*25 ns (40 ms)
constant N: integer:=18;
signal q_reg, q_next: unsigned(N-1 downto 0);
signal sel: std_logic_vector(1 downto 0);
signal hex: std_logic_vector(3 downto 0);
signal dp: std_logic;
begin
-- register
process(clk,reset)
begin
if reset='1' then
q_reg <= (others=>'0');
elsif (clk'event and clk='1') then
q_reg <= q_next;
end if;
end process;
-- next-state logic for the counter
q_next <= q_reg + 1;
-- 2 MSBs of counter to control 4-to-1 multiplexing
sel <= std_logic_vector(q_reg(N-1 downto N-2));
process(sel,hex0,hex1,hex2,hex3,dp_in)
begin
case sel is
when "00" =>
an <= "1110";
hex <= hex0;
dp <= dp_in(0);
when "01" =>
an <= "1101";
hex <= hex1;
dp <= dp_in(1);
when "10" =>
an <= "1011";
hex <= hex2;
dp <= dp_in(2);
when others =>
an <= "0111";
hex <= hex3;
dp <= dp_in(3);
end case;
end process;
-- hex-to-7-segment led decoding
with hex select
sseg(6 downto 0) <=
"0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010", --a
"1100000" when "1011", --b
"0110001" when "1100", --c
"1000010" when "1101", --d
"0110000" when "1110", --e
"0111000" when others; --f
-- decimal point
sseg(7) <= dp;
end arch;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:13:33 02/03/2009
-- Design Name:
-- Module Name: RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
--
-- gen_ram.vhd
--
-- -----------------------------------------------------------------------
--
-- Simple dual port ram: One read and one write port
--
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- -----------------------------------------------------------------------
entity ram is
generic (
dWidth : integer := 8;
aWidth : integer := 16
);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector((aWidth-1) downto 0);
d : in std_logic_vector((dWidth-1) downto 0);
q : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of ram is
type RAM_ARRAY is array(0 to 65535) of std_logic_vector(7 downto 0);
signal RAM : RAM_ARRAY := ((others=> (others=>'0')));
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
signal qReg : std_logic_vector((dWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
-- Memory write
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if we = '0' then
RAM(to_integer(unsigned(addr))) <= d;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Memory read
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
rAddrReg <= addr;
end if;
end process;
q <= RAM(to_integer(unsigned(rAddrReg)));
end rtl;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM is
port(
A : in std_logic_vector(15 downto 0);
nOE : in std_logic;
nWE : in std_logic;
nCE1 : in std_logic;
nUB1 : in std_logic;
nLB1 : in std_logic;
D : inout std_logic_vector(7 downto 0)
);
end SRAM;
architecture sim of SRAM is
-- write timings :
constant Thzwe : time := 6 ns; -- nWE LOW to High-Z Output
-- read timings :
constant Taa : time := 12 ns; -- address access time
constant numWords : integer := 65536; -- 262144 max;
type memType is array (numWords-1 downto 0) of std_logic_vector( 7 downto 0);
signal memory : memType := (others => (others => '0'));
begin
rdMem: process (nCE1, nWE, nOE, nUB1, nLB1, A)
begin
D <= (others => 'Z'); -- defaults to hi-Z
if nCE1 = '0' then
if nOE = '0' then
if nWE = '1' then
if nUB1 = '1' and nLB1 = '0' then
D <= memory(conv_integer(to_x01(A))) after Taa;
else
assert false report "%W : nUB1 and nLB1 are both deasserted during ram read" severity warning;
end if;
else
assert false report "%W : signal assertion violation : nOE and nWE asserted" severity warning;
end if;
end if;
end if;
end process;
wrMem: process (nCE1, nWE, nOE, A, D)
begin
if nCE1 = '0' then
if nWE= '0' then
if nOE = '1' then
memory(conv_integer(to_x01(A))) <= D(7 downto 0) after Thzwe;
else
assert false report "%W : ubL and lbL are both deasserted during ram write" severity warning;
end if;
-- else
-- assert false report "%W : signal assertion violation : oeL and weL asserted" severity warning;
end if;
end if;
end process;
end sim;

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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:44:36 03/10/2011
-- Design Name:
-- Module Name: /home/will/Documents/VHDL/PROJET/OricinFPGA/T1.vhd
-- Project Name: OricinFPGA
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ORIC
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY T1 IS
END T1;
ARCHITECTURE behavior OF T1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ORIC
PORT(
AD : INOUT std_logic_vector(17 downto 0);
OE_SRAMn : OUT std_logic;
WE_SRAMn : OUT std_logic;
CE_SRAMn : OUT std_logic;
UB_SRAMn : OUT std_logic;
LB_SRAMn : OUT std_logic;
RW : OUT std_logic;
D : INOUT std_logic_vector(7 downto 0);
RESETn : IN std_logic;
PS2_CLK : IN std_logic;
PS2_DATA : IN std_logic;
VIDEO_R : OUT std_logic;
VIDEO_G : OUT std_logic;
VIDEO_B : OUT std_logic;
VIDEO_SYNC : OUT std_logic;
CLK_50 : IN std_logic;
btn : IN std_logic_vector(3 downto 0);
an : OUT std_logic_vector(3 downto 0);
sseg : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal RESETn : std_logic := '0';
signal PS2_CLK : std_logic := '0';
signal PS2_DATA : std_logic := '0';
signal CLK_50 : std_logic := '0';
signal btn : std_logic_vector(3 downto 0) := (others => '0');
--BiDirs
signal AD : std_logic_vector(17 downto 0);
signal D : std_logic_vector(7 downto 0);
--Outputs
signal OE_SRAMn : std_logic;
signal WE_SRAMn : std_logic;
signal CE_SRAMn : std_logic;
signal UB_SRAMn : std_logic;
signal LB_SRAMn : std_logic;
signal RW : std_logic;
signal VIDEO_R : std_logic;
signal VIDEO_G : std_logic;
signal VIDEO_B : std_logic;
signal VIDEO_SYNC : std_logic;
signal an : std_logic_vector(3 downto 0);
signal sseg : std_logic_vector(7 downto 0);
-- Clock period definitions
constant PS2_CLK_period : time := 10 ns;
constant CLK_50_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ORIC PORT MAP (
AD => AD,
OE_SRAMn => OE_SRAMn,
WE_SRAMn => WE_SRAMn,
CE_SRAMn => CE_SRAMn,
UB_SRAMn => UB_SRAMn,
LB_SRAMn => LB_SRAMn,
RW => RW,
D => D,
RESETn => RESETn,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
VIDEO_R => VIDEO_R,
VIDEO_G => VIDEO_G,
VIDEO_B => VIDEO_B,
VIDEO_SYNC => VIDEO_SYNC,
CLK_50 => CLK_50,
btn => btn,
an => an,
sseg => sseg
);
-- Clock process definitions
PS2_CLK_process :process
begin
PS2_CLK <= '0';
wait for PS2_CLK_period/2;
PS2_CLK <= '1';
wait for PS2_CLK_period/2;
end process;
CLK_50_process :process
begin
CLK_50 <= '0';
wait for CLK_50_period/2;
CLK_50 <= '1';
wait for CLK_50_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for PS2_CLK_period*10;
-- insert stimulus here
wait;
end process;
END;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:12:00 08/14/2011
-- Design Name:
-- Module Name: ula_log - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.txt_util.all;
entity ula_log is
generic (
log_ula: string := "ula.log"
);
port(
CLK : in std_logic;
RST : in std_logic;
x1 : in std_logic_vector(7 downto 0);
x2 : in std_logic_vector(15 downto 0);
x3 : in std_logic
);
end ula_log;
architecture log_to_file of ula_log is
file l_file_ula: TEXT open write_mode is log_ula;
begin
-- write data and control information to a file
receive_data: process (CLK,RST)
variable l: line;
variable cnt : integer:=0;
begin
if (RST = '0') then
print(l_file_ula, "---- 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23");
elsif (clk'event and clk='0') then
-- Low period of PHI2
if (x3 ='0') then
if (cnt = 0) then
write (l, hstr(x2) & " " & hstr(x1) & " ");
else
-- Je récupére que le code ASCII
if (cnt mod 2 = 0) then
write(l, hstr(x1) & " ");
end if;
end if;
cnt:=cnt+1;
-- Il y a 64 pixels dont 40 utiles par ligne et deux accès à la mémoire donc 64 X 2 = 128
if (cnt = 128) then
writeline(l_file_ula, l);
cnt:=0;
end if;
end if;
end if;
end process receive_data;
end log_to_file;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:21:17 12/18/2011
-- Design Name:
-- Module Name: U_ULA_LGO - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity U_ULA_LGO is
end U_ULA_LGO;
architecture Behavioral of U_ULA_LGO is
begin
end Behavioral;

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