mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-03-09 20:18:22 +00:00
New Core - Birdiy
This commit is contained in:
Marcel
@@ -1,2 +1,2 @@
|
||||
`define BUILD_DATE "190410"
|
||||
`define BUILD_TIME "234817"
|
||||
`define BUILD_DATE "190513"
|
||||
`define BUILD_TIME "152214"
|
||||
|
||||
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@@ -1,12 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
@@ -1,12 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="Clock" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="c3" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
@@ -1,13 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
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31
Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.qpf
Normal file
31
Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.qpf
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@@ -0,0 +1,31 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel MegaCore Function License Agreement, or other
|
||||
# applicable license agreement, including, without limitation,
|
||||
# that your use is for the sole purpose of programming logic
|
||||
# devices manufactured by Intel and sold by Intel or its
|
||||
# authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
|
||||
# Date created = 04:04:47 October 16, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "17.0"
|
||||
DATE = "04:04:47 October 16, 2017"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "Birdiy"
|
||||
176
Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.qsf
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176
Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.qsf
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@@ -0,0 +1,176 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
# Date created = 12:33:31 March 10, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# Birdiy_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Birdiy.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/pacman.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/pacman_vram_addr.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
|
||||
set_global_assignment -name VERILOG_FILE rtl/osd.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/dac.vhd
|
||||
set_global_assignment -name QIP_FILE rtl/pll.qip
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
|
||||
set_location_assignment PIN_54 -to CLOCK_27
|
||||
set_location_assignment PIN_144 -to VGA_R[5]
|
||||
set_location_assignment PIN_143 -to VGA_R[4]
|
||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
||||
set_location_assignment PIN_137 -to VGA_R[1]
|
||||
set_location_assignment PIN_135 -to VGA_R[0]
|
||||
set_location_assignment PIN_133 -to VGA_B[5]
|
||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY Birdiy
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name ENABLE_NCE_PIN OFF
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
# --------------------
|
||||
# start ENTITY(Birdiy)
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(Birdiy)
|
||||
# ------------------
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
51
Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.srf
Normal file
51
Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.srf
Normal file
@@ -0,0 +1,51 @@
|
||||
{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
23
Arcade_MiST/Pacman Hardware/Birdiy_MiST/README.txt
Normal file
23
Arcade_MiST/Pacman Hardware/Birdiy_MiST/README.txt
Normal file
@@ -0,0 +1,23 @@
|
||||
---------------------------------------------------------------------------------
|
||||
--
|
||||
-- Arcade: Birdiy port to MiST by Gehstock
|
||||
-- 17 May 2019
|
||||
--
|
||||
---------------------------------------------------------------------------------
|
||||
-- A simulation model of Pacman hardware
|
||||
-- Copyright (c) MikeJ - January 2006
|
||||
---------------------------------------------------------------------------------
|
||||
--
|
||||
-- Only controls and OSD are rotated on Video output.
|
||||
--
|
||||
--
|
||||
-- Keyboard inputs :
|
||||
--
|
||||
-- ESC : Coin
|
||||
-- F2 : Start 2 players
|
||||
-- F1 : Start 1 player
|
||||
-- UP,DOWN,LEFT,RIGHT arrows : Movements
|
||||
--
|
||||
-- Joystick support.
|
||||
--
|
||||
---------------------------------------------------------------------------------
|
||||
BIN
Arcade_MiST/Pacman Hardware/Birdiy_MiST/Release/Birdiy.rbf
Normal file
BIN
Arcade_MiST/Pacman Hardware/Birdiy_MiST/Release/Birdiy.rbf
Normal file
Binary file not shown.
37
Arcade_MiST/Pacman Hardware/Birdiy_MiST/clean.bat
Normal file
37
Arcade_MiST/Pacman Hardware/Birdiy_MiST/clean.bat
Normal file
@@ -0,0 +1,37 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
del /s *~
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
rmdir /s /q hc_output
|
||||
rmdir /s /q .qsys_edit
|
||||
rmdir /s /q hps_isw_handoff
|
||||
rmdir /s /q sys\.qsys_edit
|
||||
rmdir /s /q sys\vip
|
||||
cd sys
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
cd ..
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
del build_id.v
|
||||
del c5_pin_model_dump.txt
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del /s *.qws
|
||||
del /s *.ppf
|
||||
del /s *.ddb
|
||||
del /s *.csv
|
||||
del /s *.cmp
|
||||
del /s *.sip
|
||||
del /s *.spd
|
||||
del /s *.bsf
|
||||
del /s *.f
|
||||
del /s *.sopcinfo
|
||||
del /s *.xml
|
||||
del /s new_rtl_netlist
|
||||
del /s old_rtl_netlist
|
||||
|
||||
pause
|
||||
192
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/Birdiy.sv
Normal file
192
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/Birdiy.sv
Normal file
@@ -0,0 +1,192 @@
|
||||
//============================================================================
|
||||
// Arcade: Birdiy
|
||||
//
|
||||
// Version for MiSTer
|
||||
// Copyright (C) 2017 Sorgelig
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//============================================================================
|
||||
|
||||
module Birdiy(
|
||||
output LED,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input CONF_DATA0,
|
||||
input CLOCK_27
|
||||
);
|
||||
|
||||
`include "rtl\build_id.v"
|
||||
|
||||
localparam CONF_STR = {
|
||||
"Birdiy;;",
|
||||
"O2,Rotate Controls,Off,On;",
|
||||
"O34,Scanlines,Off,25%,50%,75%;",
|
||||
"T6,Reset;",
|
||||
"V,v1.20.",`BUILD_DATE
|
||||
};
|
||||
|
||||
assign LED = 1;
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
|
||||
wire clk_sys, clk_snd;
|
||||
wire pll_locked;
|
||||
pll pll(
|
||||
.inclk0(CLOCK_27),
|
||||
.areset(0),
|
||||
.c0(clk_sys),
|
||||
.locked(pll_locked)
|
||||
);
|
||||
|
||||
reg ce_6m;
|
||||
always @(posedge clk_sys) begin
|
||||
reg [1:0] div;
|
||||
div <= div + 1'd1;
|
||||
ce_6m <= !div;
|
||||
end
|
||||
|
||||
wire [31:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [7:0] joystick_0;
|
||||
wire [7:0] joystick_1;
|
||||
wire scandoublerD;
|
||||
wire ypbpr;
|
||||
wire [10:0] ps2_key;
|
||||
wire [7:0] audio;
|
||||
wire hs, vs;
|
||||
wire hb, vb;
|
||||
wire blankn = ~(hb | vb);
|
||||
wire [2:0] r,g;
|
||||
wire [1:0] b;
|
||||
|
||||
pacmant pacmant(
|
||||
.O_VIDEO_R(r),
|
||||
.O_VIDEO_G(g),
|
||||
.O_VIDEO_B(b),
|
||||
.O_HSYNC(hs),
|
||||
.O_VSYNC(vs),
|
||||
.O_HBLANK(hb),
|
||||
.O_VBLANK(vb),
|
||||
.O_AUDIO(audio),
|
||||
.I_JOYSTICK_A(~{m_fire,m_right,m_left,m_down,m_up}),
|
||||
.I_JOYSTICK_B(5'b11111),
|
||||
.I_SW({btn_two_players, btn_coin, 1'b0, btn_one_player}),
|
||||
.RESET(status[0] | status[6] | buttons[1]),
|
||||
.CLK(clk_sys),
|
||||
.ENA_6(ce_6m)
|
||||
);
|
||||
|
||||
video_mixer video_mixer(
|
||||
.clk_sys(clk_sys),
|
||||
.ce_pix(ce_6m),
|
||||
.ce_pix_actual(ce_6m),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_SS3(SPI_SS3),
|
||||
.SPI_DI(SPI_DI),
|
||||
.R(blankn ? {r} : "000"),
|
||||
.G(blankn ? {g} : "000"),
|
||||
.B(blankn ? {b,b[1]} : "000"),
|
||||
.HSync(hs),
|
||||
.VSync(vs),
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_HS(VGA_HS),
|
||||
.rotate({1'b1,status[2]}),
|
||||
.scandoublerD(scandoublerD),
|
||||
.scanlines(scandoublerD ? 2'b00 : status[4:3]),
|
||||
.ypbpr(ypbpr),
|
||||
.ypbpr_full(1),
|
||||
.line_start(0),
|
||||
.mono(0)
|
||||
);
|
||||
|
||||
mist_io #(
|
||||
.STRLEN(($size(CONF_STR)>>3)))
|
||||
mist_io(
|
||||
.clk_sys (clk_sys ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_SCK (SPI_SCK ),
|
||||
.CONF_DATA0 (CONF_DATA0 ),
|
||||
.SPI_SS2 (SPI_SS2 ),
|
||||
.SPI_DO (SPI_DO ),
|
||||
.SPI_DI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoublerD (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.ps2_key (ps2_key ),
|
||||
.joystick_0 (joystick_0 ),
|
||||
.joystick_1 (joystick_1 ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
dac #(
|
||||
.C_bits(15))
|
||||
dac(
|
||||
.clk_i(clk_sys),
|
||||
.res_n_i(1),
|
||||
.dac_i({audio,audio}),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
|
||||
// Rotated Normal
|
||||
wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
|
||||
wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
|
||||
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
|
||||
wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
|
||||
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
|
||||
|
||||
reg btn_one_player = 0;
|
||||
reg btn_two_players = 0;
|
||||
reg btn_left = 0;
|
||||
reg btn_right = 0;
|
||||
reg btn_down = 0;
|
||||
reg btn_up = 0;
|
||||
reg btn_fire1 = 0;
|
||||
|
||||
reg btn_coin = 0;
|
||||
wire pressed = ps2_key[9];
|
||||
wire [7:0] code = ps2_key[7:0];
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
reg old_state;
|
||||
old_state <= ps2_key[10];
|
||||
if(old_state != ps2_key[10]) begin
|
||||
case(code)
|
||||
'h75: btn_up <= pressed; // up
|
||||
'h72: btn_down <= pressed; // down
|
||||
'h6B: btn_left <= pressed; // left
|
||||
'h74: btn_right <= pressed; // right
|
||||
'h76: btn_coin <= pressed; // ESC
|
||||
'h05: btn_one_player <= pressed; // F1
|
||||
'h06: btn_two_players <= pressed; // F2
|
||||
'h29: btn_fire1 <= pressed; // Space
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
534
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/GFX1.vhd
Normal file
534
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/GFX1.vhd
Normal file
@@ -0,0 +1,534 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity GFX1 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(12 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of GFX1 is
|
||||
type rom is array(0 to 8191) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"00",X"00",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"00",X"00",X"00",X"00",X"EE",X"FF",X"FF",X"FF",
|
||||
X"CC",X"EE",X"EE",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"77",X"22",X"88",X"CC",X"FF",X"FF",X"77",X"11",X"CC",X"FF",X"FF",X"FF",
|
||||
X"88",X"CC",X"EE",X"EE",X"EE",X"EE",X"CC",X"88",X"33",X"77",X"DF",X"BF",X"BF",X"FF",X"77",X"33",
|
||||
X"FF",X"BF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"33",X"67",X"CF",X"9F",X"FF",X"FF",X"77",X"33",
|
||||
X"22",X"88",X"CC",X"CC",X"EE",X"EE",X"FF",X"FF",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"77",X"33",X"11",X"11",X"00",X"00",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"CC",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",
|
||||
X"3F",X"7F",X"FF",X"FF",X"EE",X"FF",X"FF",X"FF",X"33",X"33",X"33",X"77",X"77",X"77",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"EE",X"CC",X"00",X"CC",X"FF",X"FF",X"FF",X"FF",X"77",X"00",X"EE",X"FF",
|
||||
X"00",X"00",X"00",X"00",X"88",X"FF",X"9F",X"3F",X"00",X"00",X"00",X"00",X"11",X"11",X"11",X"11",
|
||||
X"00",X"88",X"CC",X"EE",X"EE",X"FF",X"FF",X"FF",X"00",X"FF",X"33",X"11",X"11",X"FF",X"3F",X"FF",
|
||||
X"CC",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"BF",X"BF",X"FF",X"77",X"77",X"33",X"11",X"00",
|
||||
X"FF",X"FF",X"FF",X"EE",X"EE",X"CC",X"88",X"00",X"33",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"EE",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"CC",X"CC",X"FF",X"FF",X"FF",X"FF",X"77",X"77",X"DF",X"DF",
|
||||
X"88",X"EE",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"33",
|
||||
X"FF",X"FF",X"FF",X"FF",X"EE",X"EE",X"CC",X"00",X"FF",X"FF",X"FF",X"FF",X"77",X"77",X"33",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"23",X"47",X"57",X"57",X"9F",X"BF",X"BF",X"FF",
|
||||
X"00",X"00",X"00",X"00",X"33",X"FF",X"9F",X"BF",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"33",
|
||||
X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"33",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"77",X"77",X"33",X"BB",X"99",X"DD",X"CC",X"EE",X"FF",
|
||||
X"00",X"00",X"00",X"00",X"00",X"88",X"FF",X"FF",X"00",X"00",X"88",X"88",X"CC",X"DD",X"CC",X"EE",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",
|
||||
X"11",X"33",X"77",X"77",X"77",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"FF",
|
||||
X"FF",X"FF",X"FF",X"33",X"11",X"11",X"11",X"00",X"FF",X"FF",X"FF",X"CC",X"88",X"88",X"88",X"00",
|
||||
X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"FF",X"BF",X"7F",X"FF",X"FF",
|
||||
X"FF",X"FF",X"77",X"00",X"00",X"00",X"00",X"00",X"FF",X"33",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"FF",X"33",X"88",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"00",X"00",X"88",X"88",X"CC",X"CC",X"EE",X"EE",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"77",
|
||||
X"00",X"00",X"00",X"00",X"33",X"67",X"47",X"DF",X"00",X"00",X"00",X"00",X"CC",X"EE",X"EE",X"EE",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"33",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"11",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"BB",X"BB",X"00",X"00",X"00",X"00",X"00",X"66",X"FF",X"FF",X"66",X"00",X"00",
|
||||
X"FF",X"FF",X"FF",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"33",X"CC",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"EE",X"FF",X"FF",X"FF",X"FF",
|
||||
X"99",X"55",X"55",X"33",X"88",X"44",X"22",X"11",X"88",X"55",X"33",X"11",X"00",X"FF",X"88",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"33",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"CC",X"FF",X"FF",X"FF",
|
||||
X"FF",X"CC",X"77",X"FF",X"CC",X"77",X"FF",X"FF",X"FF",X"FF",X"EE",X"BB",X"FF",X"EE",X"DD",X"FF",
|
||||
X"FF",X"FF",X"44",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"33",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"BB",X"FF",X"EE",X"EE",X"77",X"BB",X"FF",X"FF",X"FF",X"FF",X"33",X"CC",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"11",X"FF",X"FF",
|
||||
X"00",X"00",X"EE",X"DD",X"DD",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"8D",X"8A",X"8D",X"8A",X"8D",X"8A",X"8D",X"8A",
|
||||
X"00",X"00",X"00",X"66",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"DD",X"DD",X"00",X"00",X"00",
|
||||
X"88",X"CC",X"22",X"22",X"66",X"CC",X"88",X"00",X"33",X"77",X"CC",X"88",X"88",X"77",X"33",X"00",
|
||||
X"22",X"22",X"EE",X"EE",X"22",X"22",X"00",X"00",X"00",X"00",X"FF",X"FF",X"44",X"00",X"00",X"00",
|
||||
X"22",X"22",X"AA",X"AA",X"EE",X"EE",X"66",X"00",X"66",X"FF",X"BB",X"99",X"99",X"CC",X"44",X"00",
|
||||
X"CC",X"EE",X"22",X"22",X"22",X"66",X"44",X"00",X"88",X"DD",X"FF",X"BB",X"99",X"88",X"00",X"00",
|
||||
X"88",X"EE",X"EE",X"88",X"88",X"88",X"88",X"00",X"00",X"FF",X"FF",X"CC",X"66",X"33",X"11",X"00",
|
||||
X"CC",X"EE",X"22",X"22",X"22",X"66",X"44",X"00",X"11",X"BB",X"AA",X"AA",X"AA",X"EE",X"EE",X"00",
|
||||
X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"00",X"99",X"99",X"99",X"DD",X"77",X"33",X"00",
|
||||
X"00",X"00",X"00",X"EE",X"EE",X"00",X"00",X"00",X"CC",X"EE",X"BB",X"99",X"88",X"CC",X"CC",X"00",
|
||||
X"CC",X"EE",X"AA",X"AA",X"22",X"22",X"CC",X"00",X"00",X"66",X"99",X"99",X"BB",X"FF",X"66",X"00",
|
||||
X"88",X"CC",X"66",X"22",X"22",X"22",X"00",X"00",X"77",X"FF",X"99",X"99",X"99",X"FF",X"66",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DD",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"33",X"FF",
|
||||
X"77",X"99",X"EE",X"FF",X"77",X"FF",X"FF",X"FF",X"FF",X"77",X"BB",X"CC",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"66",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",
|
||||
X"C0",X"C8",X"D5",X"FF",X"FF",X"D9",X"C0",X"80",X"30",X"71",X"F0",X"F3",X"F4",X"F0",X"71",X"30",
|
||||
X"CC",X"22",X"11",X"55",X"55",X"99",X"22",X"CC",X"33",X"44",X"88",X"AA",X"AA",X"99",X"44",X"33",
|
||||
X"EE",X"EE",X"88",X"88",X"88",X"EE",X"EE",X"00",X"33",X"77",X"CC",X"88",X"CC",X"77",X"33",X"00",
|
||||
X"CC",X"EE",X"22",X"22",X"22",X"EE",X"EE",X"00",X"66",X"FF",X"99",X"99",X"99",X"FF",X"FF",X"00",
|
||||
X"44",X"66",X"22",X"22",X"66",X"CC",X"88",X"00",X"44",X"CC",X"88",X"88",X"CC",X"77",X"33",X"00",
|
||||
X"88",X"CC",X"66",X"22",X"22",X"EE",X"EE",X"00",X"33",X"77",X"CC",X"88",X"88",X"FF",X"FF",X"00",
|
||||
X"22",X"22",X"22",X"22",X"EE",X"EE",X"00",X"00",X"88",X"99",X"99",X"99",X"FF",X"FF",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"EE",X"EE",X"00",X"88",X"99",X"99",X"99",X"99",X"FF",X"FF",X"00",
|
||||
X"EE",X"EE",X"22",X"22",X"66",X"CC",X"88",X"00",X"99",X"99",X"99",X"88",X"CC",X"77",X"33",X"00",
|
||||
X"EE",X"EE",X"00",X"00",X"00",X"EE",X"EE",X"00",X"FF",X"FF",X"11",X"11",X"11",X"FF",X"FF",X"00",
|
||||
X"22",X"22",X"EE",X"EE",X"22",X"22",X"00",X"00",X"88",X"88",X"FF",X"FF",X"88",X"88",X"00",X"00",
|
||||
X"CC",X"EE",X"22",X"22",X"22",X"66",X"44",X"00",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"22",X"66",X"EE",X"CC",X"88",X"EE",X"EE",X"00",X"88",X"CC",X"66",X"33",X"11",X"FF",X"FF",X"00",
|
||||
X"22",X"22",X"22",X"22",X"EE",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",
|
||||
X"EE",X"EE",X"00",X"88",X"00",X"EE",X"EE",X"00",X"FF",X"FF",X"77",X"33",X"77",X"FF",X"FF",X"00",
|
||||
X"EE",X"EE",X"CC",X"88",X"00",X"EE",X"EE",X"00",X"FF",X"FF",X"11",X"33",X"77",X"FF",X"FF",X"00",
|
||||
X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"77",X"FF",X"88",X"88",X"88",X"FF",X"77",X"00",
|
||||
X"00",X"88",X"88",X"88",X"88",X"EE",X"EE",X"00",X"77",X"FF",X"88",X"88",X"88",X"FF",X"FF",X"00",
|
||||
X"AA",X"CC",X"EE",X"AA",X"22",X"EE",X"CC",X"00",X"77",X"FF",X"88",X"88",X"88",X"FF",X"77",X"00",
|
||||
X"22",X"66",X"EE",X"CC",X"88",X"EE",X"EE",X"00",X"77",X"FF",X"99",X"88",X"88",X"FF",X"FF",X"00",
|
||||
X"CC",X"EE",X"22",X"22",X"22",X"66",X"44",X"00",X"00",X"55",X"DD",X"99",X"99",X"FF",X"66",X"00",
|
||||
X"00",X"00",X"EE",X"EE",X"00",X"00",X"00",X"00",X"88",X"88",X"FF",X"FF",X"88",X"88",X"00",X"00",
|
||||
X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"FF",X"FF",X"00",X"00",X"00",X"FF",X"FF",X"00",
|
||||
X"00",X"88",X"CC",X"EE",X"CC",X"88",X"00",X"00",X"FF",X"FF",X"11",X"00",X"11",X"FF",X"FF",X"00",
|
||||
X"EE",X"EE",X"CC",X"88",X"CC",X"EE",X"EE",X"00",X"FF",X"FF",X"11",X"33",X"11",X"FF",X"FF",X"00",
|
||||
X"66",X"EE",X"CC",X"88",X"CC",X"EE",X"66",X"00",X"CC",X"EE",X"77",X"33",X"77",X"EE",X"CC",X"00",
|
||||
X"00",X"00",X"EE",X"EE",X"00",X"00",X"00",X"00",X"EE",X"FF",X"11",X"11",X"FF",X"EE",X"00",X"00",
|
||||
X"22",X"22",X"22",X"AA",X"EE",X"EE",X"66",X"00",X"CC",X"EE",X"FF",X"BB",X"99",X"88",X"88",X"00",
|
||||
X"77",X"DD",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"88",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"CC",X"FF",X"00",X"FF",X"FF",X"FF",
|
||||
X"EE",X"11",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"88",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"DD",X"BB",X"FF",X"FF",X"FF",X"FF",X"77",X"FF",X"FF",X"FF",X"CC",X"FF",X"FF",X"FF",
|
||||
X"01",X"03",X"05",X"0E",X"05",X"0A",X"05",X"0A",X"88",X"88",X"88",X"88",X"89",X"8B",X"8D",X"8E",
|
||||
X"00",X"00",X"00",X"0C",X"1F",X"3F",X"7F",X"FF",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"1F",X"3F",X"7F",X"FF",X"00",X"00",X"00",X"00",X"03",X"01",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"CC",X"CC",X"EE",X"6E",X"04",X"04",X"06",X"3F",X"FF",X"FF",X"FF",X"CF",
|
||||
X"00",X"00",X"00",X"00",X"CC",X"CC",X"EE",X"6E",X"01",X"03",X"06",X"3F",X"FF",X"FF",X"FF",X"CF",
|
||||
X"6E",X"EE",X"EE",X"EE",X"EE",X"CC",X"88",X"08",X"8F",X"0F",X"0F",X"0F",X"8F",X"8F",X"CF",X"01",
|
||||
X"6E",X"EE",X"EE",X"EE",X"EE",X"CC",X"88",X"00",X"8F",X"0F",X"0F",X"0F",X"1F",X"3F",X"7F",X"00",
|
||||
X"DD",X"FF",X"FF",X"77",X"33",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"DD",X"FF",X"EF",X"67",X"23",X"01",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"11",X"33",X"77",X"FF",X"FF",X"DD",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"01",X"01",X"01",X"23",X"67",X"EF",X"FF",X"DD",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"08",X"88",X"CC",X"EE",X"EE",X"EE",X"EE",X"6E",X"01",X"CF",X"8F",X"8F",X"0F",X"0F",X"0F",X"8F",
|
||||
X"00",X"88",X"CC",X"EE",X"EE",X"EE",X"EE",X"6E",X"00",X"7F",X"3F",X"1F",X"0F",X"0F",X"0F",X"8F",
|
||||
X"6E",X"EE",X"CC",X"CC",X"00",X"00",X"00",X"00",X"CF",X"FF",X"FF",X"FF",X"3F",X"06",X"04",X"04",
|
||||
X"6E",X"EE",X"CC",X"CC",X"00",X"00",X"00",X"00",X"CF",X"FF",X"FF",X"FF",X"3F",X"06",X"03",X"01",
|
||||
X"FF",X"7F",X"3F",X"1F",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",
|
||||
X"FF",X"7F",X"3F",X"1F",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"00",X"00",X"00",X"00",
|
||||
X"80",X"C0",X"C0",X"C0",X"C0",X"80",X"A6",X"84",X"76",X"54",X"F0",X"F0",X"D4",X"F6",X"F0",X"78",
|
||||
X"C0",X"E0",X"E0",X"E0",X"E0",X"C0",X"D3",X"86",X"00",X"30",X"76",X"54",X"70",X"70",X"54",X"76",
|
||||
X"1F",X"0E",X"0E",X"0E",X"0F",X"0F",X"0F",X"06",X"0F",X"07",X"07",X"07",X"03",X"03",X"01",X"00",
|
||||
X"1F",X"0F",X"0F",X"0E",X"0E",X"0E",X"0C",X"08",X"01",X"01",X"01",X"03",X"07",X"0F",X"0F",X"07",
|
||||
X"06",X"0F",X"0F",X"0F",X"0E",X"0E",X"0E",X"1F",X"00",X"01",X"03",X"03",X"07",X"07",X"07",X"0F",
|
||||
X"08",X"0C",X"0E",X"0E",X"0E",X"0F",X"0F",X"1F",X"07",X"0F",X"0F",X"07",X"03",X"01",X"01",X"01",
|
||||
X"84",X"A6",X"80",X"C0",X"C0",X"C0",X"C0",X"80",X"78",X"F0",X"F6",X"D4",X"F0",X"F0",X"54",X"76",
|
||||
X"86",X"D3",X"C0",X"E0",X"E0",X"E0",X"E0",X"C0",X"76",X"54",X"70",X"70",X"54",X"76",X"30",X"00",
|
||||
X"F0",X"98",X"AE",X"8E",X"9F",X"8E",X"8E",X"06",X"31",X"22",X"EE",X"E2",X"22",X"22",X"EE",X"F1",
|
||||
X"F0",X"98",X"AE",X"8E",X"9F",X"8E",X"8E",X"06",X"F1",X"EE",X"22",X"22",X"E2",X"EE",X"22",X"31",
|
||||
X"06",X"06",X"1F",X"0E",X"3A",X"F8",X"70",X"F0",X"F0",X"F0",X"E0",X"C1",X"83",X"83",X"83",X"C0",
|
||||
X"06",X"06",X"06",X"0E",X"0E",X"1C",X"7C",X"70",X"F0",X"F0",X"90",X"06",X"07",X"8F",X"07",X"A2",
|
||||
X"F0",X"70",X"F8",X"3A",X"0E",X"1F",X"06",X"06",X"C0",X"83",X"83",X"83",X"C1",X"E0",X"F0",X"F0",
|
||||
X"70",X"7C",X"1C",X"0E",X"0E",X"06",X"06",X"06",X"A2",X"07",X"8F",X"07",X"06",X"90",X"F0",X"F0",
|
||||
X"06",X"8E",X"8E",X"9F",X"8E",X"AE",X"98",X"F0",X"F1",X"EE",X"22",X"22",X"E2",X"EE",X"22",X"31",
|
||||
X"06",X"8E",X"8E",X"9F",X"8E",X"AE",X"98",X"F0",X"31",X"22",X"EE",X"E2",X"22",X"22",X"EE",X"F1",
|
||||
X"10",X"0E",X"0F",X"0F",X"8F",X"A2",X"F0",X"F0",X"C0",X"83",X"07",X"07",X"06",X"32",X"F0",X"F0",
|
||||
X"F0",X"F0",X"A2",X"8F",X"0F",X"0F",X"0E",X"10",X"F0",X"F0",X"32",X"06",X"07",X"07",X"83",X"C0",
|
||||
X"72",X"55",X"DD",X"D5",X"55",X"55",X"DD",X"72",X"E0",X"E0",X"75",X"1C",X"0E",X"0E",X"17",X"80",
|
||||
X"72",X"DD",X"55",X"55",X"D5",X"DD",X"55",X"72",X"80",X"17",X"0E",X"0E",X"1C",X"75",X"E0",X"E0",
|
||||
X"22",X"88",X"44",X"88",X"22",X"88",X"44",X"88",X"DD",X"EE",X"BB",X"EE",X"DD",X"EE",X"BB",X"EE",
|
||||
X"00",X"00",X"00",X"00",X"08",X"0C",X"06",X"0B",X"08",X"0C",X"06",X"0B",X"05",X"0A",X"05",X"0A",
|
||||
X"07",X"0A",X"0C",X"08",X"00",X"00",X"00",X"00",X"05",X"0A",X"05",X"0A",X"07",X"0A",X"0C",X"08",
|
||||
X"07",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"0A",X"07",X"0C",X"08",X"0C",X"06",X"0B",
|
||||
X"00",X"00",X"00",X"00",X"01",X"13",X"37",X"36",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"03",X"1F",X"93",X"93",X"D3",X"80",X"00",X"00",X"00",X"00",X"03",X"17",X"9B",X"9B",X"CA",X"80",
|
||||
X"80",X"C4",X"0A",X"D6",X"32",X"FC",X"B6",X"7C",X"93",X"82",X"93",X"C7",X"39",X"57",X"33",X"03",
|
||||
X"B4",X"B2",X"54",X"BE",X"7A",X"54",X"FA",X"BA",X"37",X"13",X"56",X"36",X"33",X"57",X"32",X"32",
|
||||
X"7C",X"B6",X"FC",X"32",X"D6",X"0A",X"C4",X"80",X"03",X"33",X"57",X"39",X"C7",X"93",X"82",X"93",
|
||||
X"00",X"00",X"80",X"D3",X"93",X"93",X"1F",X"03",X"80",X"CA",X"9B",X"9B",X"17",X"03",X"00",X"00",
|
||||
X"36",X"37",X"13",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"DD",X"EA",X"55",X"6A",X"BE",X"5C",X"3A",X"37",X"01",X"01",X"01",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"01",X"03",X"17",X"3F",X"3F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"08",X"0C",X"8E",X"CE",X"CE",X"CE",X"00",X"00",X"07",X"3F",X"FF",X"FF",X"FF",X"FF",
|
||||
X"CE",X"CE",X"CE",X"8E",X"0C",X"08",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"3F",X"07",X"00",X"00",
|
||||
X"3F",X"3F",X"17",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"05",X"0A",X"05",X"0A",X"85",X"C2",X"E1",X"F0",X"05",X"0A",X"05",X"0A",X"14",X"38",X"70",X"F0",
|
||||
X"F0",X"E0",X"C1",X"82",X"05",X"0A",X"05",X"0A",X"F0",X"78",X"34",X"1A",X"05",X"0A",X"05",X"0A",
|
||||
X"14",X"1A",X"34",X"38",X"34",X"78",X"70",X"78",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",
|
||||
X"70",X"78",X"70",X"38",X"34",X"38",X"14",X"1A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",
|
||||
X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"85",X"82",X"C1",X"C2",X"C1",X"E0",X"E1",X"E0",
|
||||
X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"E1",X"E0",X"E1",X"C2",X"C1",X"C2",X"85",X"82",
|
||||
X"14",X"38",X"70",X"F0",X"F0",X"78",X"34",X"1A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",
|
||||
X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"85",X"C2",X"E1",X"F0",X"F0",X"E0",X"C1",X"82",
|
||||
X"05",X"0A",X"05",X"0A",X"05",X"78",X"F0",X"F0",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"34",X"F0",
|
||||
X"05",X"0A",X"05",X"0A",X"05",X"0A",X"C1",X"F0",X"05",X"0A",X"05",X"0A",X"05",X"E0",X"F0",X"F0",
|
||||
X"F0",X"F0",X"70",X"0A",X"05",X"0A",X"05",X"0A",X"F0",X"38",X"05",X"0A",X"05",X"0A",X"05",X"0A",
|
||||
X"F0",X"C2",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"F0",X"F0",X"E1",X"0A",X"05",X"0A",X"05",X"0A",
|
||||
X"05",X"1B",X"37",X"7F",X"77",X"FF",X"FF",X"FF",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"37",X"7F",
|
||||
X"FF",X"CC",X"33",X"FF",X"EF",X"8A",X"05",X"0A",X"FF",X"FF",X"FF",X"DD",X"BB",X"FF",X"EF",X"8A",
|
||||
X"EF",X"8A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"11",X"FF",X"EF",X"8A",X"05",X"0A",X"05",X"0A",
|
||||
X"15",X"1B",X"37",X"B3",X"F7",X"7F",X"FF",X"FF",X"85",X"C2",X"F0",X"F0",X"F0",X"F0",X"C1",X"82",
|
||||
X"EF",X"CE",X"8D",X"82",X"C1",X"C2",X"E1",X"F0",X"FF",X"FF",X"DD",X"BB",X"76",X"FC",X"F8",X"F0",
|
||||
X"FE",X"DC",X"BC",X"38",X"34",X"78",X"70",X"78",X"15",X"1B",X"37",X"3B",X"67",X"4E",X"8D",X"0A",
|
||||
X"05",X"0A",X"8D",X"EE",X"77",X"99",X"EE",X"FF",X"8D",X"EE",X"BB",X"DD",X"EE",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"77",X"F7",X"B7",X"3B",X"15",X"1B",X"85",X"C2",X"F0",X"F0",X"F0",X"F0",X"C1",X"82",
|
||||
X"F0",X"E0",X"C1",X"C2",X"85",X"8A",X"CD",X"EE",X"F0",X"F8",X"FC",X"76",X"BB",X"DD",X"FF",X"FF",
|
||||
X"77",X"BB",X"FF",X"EE",X"77",X"3B",X"15",X"0A",X"77",X"3B",X"15",X"0A",X"05",X"0A",X"05",X"0A",
|
||||
X"05",X"0A",X"05",X"0A",X"05",X"0A",X"8D",X"EE",X"05",X"0A",X"05",X"0A",X"8D",X"EE",X"77",X"11",
|
||||
X"05",X"0A",X"05",X"0A",X"0D",X"06",X"03",X"01",X"0D",X"06",X"03",X"01",X"00",X"00",X"00",X"00",
|
||||
X"C7",X"1F",X"93",X"93",X"13",X"00",X"00",X"00",X"CF",X"E4",X"E7",X"97",X"0A",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"13",X"93",X"93",X"1F",X"C7",X"00",X"00",X"00",X"0A",X"97",X"E7",X"E4",X"CF",
|
||||
X"93",X"82",X"93",X"82",X"D9",X"E8",X"D9",X"E8",X"11",X"11",X"11",X"11",X"01",X"01",X"01",X"01",
|
||||
X"37",X"3A",X"5C",X"BE",X"6A",X"55",X"EA",X"DD",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"01",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"15",X"1B",X"37",X"3B",X"77",X"7F",X"FF",X"FF",
|
||||
X"FE",X"DC",X"BC",X"38",X"34",X"78",X"70",X"78",X"FF",X"FF",X"FF",X"FF",X"EF",X"CE",X"8D",X"0A",
|
||||
X"15",X"1B",X"37",X"3B",X"77",X"7F",X"FF",X"FF",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",
|
||||
X"FE",X"FE",X"FC",X"FC",X"BC",X"F8",X"70",X"78",X"15",X"1B",X"37",X"3B",X"77",X"7F",X"FF",X"FF",
|
||||
X"70",X"78",X"70",X"38",X"34",X"38",X"14",X"1A",X"EF",X"EE",X"CD",X"CE",X"8D",X"8A",X"05",X"0A",
|
||||
X"EF",X"EE",X"CD",X"CE",X"8D",X"8A",X"05",X"0A",X"15",X"1B",X"37",X"3B",X"77",X"7F",X"FF",X"FF",
|
||||
X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"EF",X"EE",X"CD",X"CE",X"8D",X"8A",X"05",X"0A",
|
||||
X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"8D",X"8A",X"CD",X"CE",X"EF",X"EE",
|
||||
X"05",X"0A",X"8D",X"8A",X"CD",X"CE",X"EF",X"EE",X"FF",X"FF",X"77",X"7F",X"37",X"3B",X"15",X"1B",
|
||||
X"FF",X"FF",X"77",X"7F",X"37",X"3B",X"15",X"1B",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",
|
||||
X"05",X"0A",X"05",X"0A",X"05",X"8A",X"CD",X"EE",X"05",X"8A",X"CD",X"EE",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"7F",X"37",X"3B",X"15",X"1B",
|
||||
X"70",X"78",X"70",X"38",X"34",X"B8",X"DC",X"FE",X"05",X"8A",X"CD",X"66",X"BB",X"DD",X"FF",X"FF",
|
||||
X"14",X"1A",X"34",X"38",X"34",X"78",X"70",X"78",X"05",X"0A",X"8D",X"8A",X"CD",X"CE",X"EF",X"EE",
|
||||
X"70",X"78",X"F8",X"B8",X"FC",X"FC",X"FE",X"FE",X"FF",X"FF",X"77",X"7F",X"37",X"3B",X"15",X"1B",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
|
||||
X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"F0",X"00",X"00",X"00",X"00",X"10",X"30",X"70",X"F0",
|
||||
X"F0",X"E0",X"C0",X"80",X"00",X"00",X"00",X"00",X"F0",X"70",X"30",X"10",X"00",X"00",X"00",X"00",
|
||||
X"10",X"10",X"30",X"30",X"30",X"70",X"70",X"70",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"70",X"70",X"70",X"30",X"30",X"30",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"C0",X"C0",X"C0",X"E0",X"E0",X"E0",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"E0",X"E0",X"E0",X"C0",X"C0",X"C0",X"80",X"80",
|
||||
X"10",X"30",X"70",X"F0",X"F0",X"70",X"30",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"01",X"03",X"07",X"0F",X"0F",X"07",X"03",X"01",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
|
||||
X"00",X"00",X"00",X"00",X"00",X"70",X"F0",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"F0",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"F0",X"00",X"00",X"00",X"00",X"00",X"E0",X"F0",X"F0",
|
||||
X"F0",X"F0",X"70",X"00",X"00",X"00",X"00",X"00",X"F0",X"30",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"F0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"F0",X"E0",X"00",X"00",X"00",X"00",X"00",
|
||||
X"0F",X"0F",X"0F",X"0F",X"0F",X"8F",X"CF",X"EF",X"0F",X"8F",X"CF",X"EF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"11",X"33",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"11",X"33",X"77",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"33",X"11",X"FF",X"77",X"33",X"11",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"11",X"00",X"00",X"00",X"00",X"00",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"33",X"11",X"FF",X"FF",X"FF",X"77",X"11",X"00",X"00",X"00",
|
||||
X"CC",X"EE",X"FF",X"FF",X"FF",X"66",X"33",X"11",X"FF",X"77",X"33",X"11",X"00",X"00",X"00",X"00",
|
||||
X"77",X"DD",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"88",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"00",X"00",X"00",X"00",X"00",X"11",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"77",
|
||||
X"11",X"33",X"77",X"EE",X"DD",X"BB",X"FF",X"FF",X"00",X"00",X"00",X"11",X"77",X"FF",X"FF",X"FF",
|
||||
X"11",X"33",X"77",X"FF",X"FF",X"FF",X"BB",X"77",X"00",X"00",X"00",X"00",X"11",X"33",X"77",X"FF",
|
||||
X"FF",X"FF",X"77",X"CC",X"FF",X"77",X"CC",X"FF",X"FF",X"DD",X"EE",X"FF",X"BB",X"EE",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"44",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"EE",X"33",X"FF",
|
||||
X"FF",X"BB",X"77",X"EE",X"EE",X"FF",X"BB",X"FF",X"FF",X"FF",X"FF",X"CC",X"33",X"FF",X"FF",X"FF",
|
||||
X"14",X"38",X"F0",X"F0",X"F0",X"F0",X"34",X"1A",X"8D",X"8A",X"CD",X"56",X"76",X"66",X"77",X"33",
|
||||
X"05",X"8A",X"8D",X"CE",X"CD",X"66",X"67",X"BB",X"BB",X"DD",X"DD",X"EE",X"66",X"BB",X"FF",X"FF",
|
||||
X"FF",X"FF",X"EE",X"FF",X"F7",X"F3",X"F1",X"F0",X"77",X"3B",X"15",X"1A",X"34",X"38",X"70",X"F0",
|
||||
X"14",X"38",X"F0",X"F0",X"F0",X"F8",X"FC",X"FE",X"05",X"8A",X"CD",X"76",X"BB",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"3B",X"05",X"0A",X"05",X"0A",X"F7",X"B3",X"C1",X"C2",X"C1",X"E0",X"E1",X"E0",
|
||||
X"F0",X"F0",X"70",X"0A",X"05",X"8A",X"CD",X"2A",X"F0",X"B8",X"CD",X"EE",X"FF",X"3B",X"05",X"0A",
|
||||
X"EE",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"FF",X"EE",X"88",X"00",X"00",X"00",X"00",
|
||||
X"FF",X"CC",X"33",X"FF",X"EE",X"88",X"00",X"00",X"FF",X"FF",X"FF",X"DD",X"BB",X"FF",X"EE",X"88",
|
||||
X"11",X"33",X"77",X"FF",X"77",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"11",X"22",X"77",X"FF",
|
||||
X"EE",X"CC",X"88",X"80",X"C0",X"C0",X"E0",X"F0",X"FF",X"FF",X"DD",X"BB",X"76",X"FC",X"F8",X"F0",
|
||||
X"11",X"11",X"33",X"B3",X"F7",X"77",X"FF",X"FF",X"80",X"C0",X"F0",X"F0",X"F0",X"F0",X"C0",X"80",
|
||||
X"FE",X"DC",X"B8",X"30",X"30",X"70",X"70",X"70",X"11",X"11",X"33",X"33",X"66",X"44",X"88",X"00",
|
||||
X"70",X"70",X"70",X"30",X"30",X"B8",X"DC",X"FE",X"00",X"88",X"44",X"66",X"33",X"33",X"11",X"11",
|
||||
X"FF",X"FF",X"77",X"F7",X"B3",X"33",X"11",X"11",X"80",X"C0",X"F0",X"F0",X"F0",X"F0",X"C0",X"80",
|
||||
X"F0",X"E0",X"C0",X"C0",X"80",X"88",X"CC",X"EE",X"F0",X"F8",X"FC",X"76",X"BB",X"DD",X"FF",X"FF",
|
||||
X"77",X"BB",X"FF",X"EE",X"FF",X"77",X"33",X"11",X"FF",X"77",X"33",X"11",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"88",X"EE",X"77",X"99",X"EE",X"FF",X"88",X"EE",X"BB",X"DD",X"EE",X"FF",X"FF",X"FF",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"EE",X"00",X"00",X"00",X"00",X"88",X"EE",X"77",X"11",
|
||||
X"00",X"00",X"00",X"00",X"88",X"EE",X"FF",X"FF",X"88",X"88",X"CC",X"66",X"77",X"33",X"99",X"CC",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"CC",X"FF",
|
||||
X"99",X"77",X"FF",X"CC",X"00",X"00",X"00",X"00",X"FF",X"FF",X"AA",X"77",X"77",X"EE",X"CC",X"88",
|
||||
X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"88",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"88",X"FF",X"BF",X"FF",X"FF",X"FF",X"00",X"00",X"33",X"77",X"CF",X"9F",X"BF",X"BF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"EE",X"CC",X"00",X"FF",X"77",X"11",X"11",X"77",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"EE",X"CC",X"00",X"CC",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"77",X"77",X"00",
|
||||
X"CC",X"EE",X"FF",X"FF",X"FF",X"FF",X"77",X"11",X"77",X"77",X"33",X"33",X"11",X"00",X"00",X"00",
|
||||
X"33",X"33",X"99",X"DD",X"CC",X"EE",X"EE",X"FF",X"FF",X"00",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"77",X"77",X"33",X"BB",X"99",X"88",X"CC",X"EE",X"EE",X"FF",X"FF",X"FF",X"FF",X"77",X"77",
|
||||
X"07",X"0A",X"0C",X"08",X"00",X"00",X"00",X"00",X"8D",X"8A",X"8D",X"8A",X"8F",X"8A",X"8C",X"88",
|
||||
X"00",X"00",X"00",X"00",X"08",X"0C",X"06",X"0B",X"88",X"8C",X"8E",X"8B",X"8D",X"8A",X"8D",X"8A",
|
||||
X"00",X"00",X"00",X"00",X"80",X"C0",X"60",X"B0",X"80",X"C0",X"60",X"B0",X"50",X"A0",X"50",X"A0",
|
||||
X"70",X"A0",X"C0",X"80",X"00",X"00",X"00",X"00",X"50",X"A0",X"50",X"A0",X"70",X"A0",X"C0",X"80",
|
||||
X"01",X"03",X"05",X"0E",X"05",X"0A",X"05",X"0A",X"00",X"00",X"00",X"00",X"01",X"03",X"05",X"0E",
|
||||
X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
|
||||
X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"08",X"0C",X"0E",X"0E",X"0E",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"01",X"03",X"07",X"0F",X"0F",X"00",X"00",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",
|
||||
X"0E",X"0E",X"0E",X"0E",X"0C",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"0F",X"0F",X"07",X"03",X"01",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"0F",X"07",X"00",X"00",
|
||||
X"00",X"00",X"08",X"0C",X"0E",X"0E",X"0E",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"01",X"03",X"07",X"0F",X"05",X"00",X"00",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",
|
||||
X"0E",X"0E",X"0E",X"0E",X"0C",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"0A",X"0F",X"07",X"03",X"01",X"00",X"00",X"00",X"0F",X"07",X"0F",X"0F",X"0F",X"07",X"00",X"00",
|
||||
X"00",X"00",X"08",X"0C",X"06",X"0E",X"0E",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"01",X"03",X"07",X"0F",X"05",X"00",X"00",X"07",X"0F",X"0F",X"0C",X"0B",X"05",
|
||||
X"0E",X"0E",X"06",X"0E",X"0C",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"0A",X"0F",X"07",X"03",X"01",X"00",X"00",X"00",X"0E",X"06",X"0F",X"0F",X"0F",X"07",X"00",X"00",
|
||||
X"00",X"00",X"08",X"0C",X"06",X"0E",X"0E",X"0E",X"00",X"01",X"00",X"08",X"00",X"04",X"00",X"02",
|
||||
X"0A",X"08",X"04",X"01",X"E0",X"F0",X"70",X"70",X"00",X"00",X"07",X"0F",X"87",X"C0",X"C3",X"C1",
|
||||
X"0E",X"0E",X"06",X"0E",X"0C",X"08",X"00",X"00",X"04",X"02",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"5A",X"0F",X"06",X"03",X"01",X"00",X"00",X"00",X"0E",X"06",X"0F",X"0F",X"0F",X"07",X"00",X"00",
|
||||
X"02",X"06",X"0A",X"0D",X"07",X"0E",X"0E",X"06",X"00",X"00",X"00",X"70",X"30",X"10",X"10",X"00",
|
||||
X"01",X"02",X"01",X"F0",X"F0",X"F0",X"F1",X"F3",X"08",X"00",X"07",X"0F",X"CF",X"BF",X"FF",X"FF",
|
||||
X"0A",X"0E",X"06",X"0E",X"0C",X"08",X"00",X"00",X"00",X"01",X"00",X"00",X"02",X"00",X"00",X"00",
|
||||
X"F7",X"5D",X"3F",X"03",X"14",X"10",X"34",X"08",X"FF",X"DF",X"E9",X"E1",X"C3",X"87",X"04",X"0D",
|
||||
X"0D",X"0B",X"01",X"84",X"0F",X"8E",X"8E",X"8F",X"00",X"00",X"00",X"78",X"34",X"03",X"01",X"00",
|
||||
X"09",X"00",X"03",X"F0",X"F0",X"F0",X"78",X"1E",X"09",X"0C",X"0C",X"F0",X"F0",X"E1",X"C3",X"97",
|
||||
X"8E",X"8B",X"CD",X"00",X"CD",X"0B",X"07",X"0A",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",
|
||||
X"CF",X"EF",X"BB",X"77",X"33",X"08",X"01",X"03",X"7F",X"FF",X"FF",X"FF",X"FF",X"0E",X"0E",X"0C",
|
||||
X"00",X"08",X"0C",X"4A",X"FD",X"F0",X"FD",X"FB",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"70",
|
||||
X"00",X"00",X"11",X"22",X"75",X"F8",X"F0",X"F0",X"00",X"03",X"89",X"EE",X"FF",X"FF",X"F3",X"F0",
|
||||
X"F7",X"FB",X"FD",X"F0",X"FD",X"4A",X"0C",X"08",X"F0",X"70",X"10",X"00",X"00",X"00",X"00",X"00",
|
||||
X"F0",X"F0",X"F0",X"F8",X"75",X"22",X"11",X"00",X"F0",X"F0",X"F3",X"FF",X"FF",X"EE",X"89",X"03",
|
||||
X"00",X"07",X"0E",X"0C",X"FE",X"FC",X"FE",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",
|
||||
X"00",X"00",X"11",X"22",X"77",X"DE",X"DE",X"9E",X"00",X"00",X"CC",X"EF",X"FF",X"FF",X"7F",X"7F",
|
||||
X"FF",X"FF",X"FE",X"FC",X"FE",X"0C",X"0E",X"07",X"11",X"11",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"9E",X"9E",X"DE",X"DE",X"77",X"22",X"11",X"00",X"7F",X"7F",X"7F",X"FF",X"FF",X"EF",X"CC",X"00",
|
||||
X"00",X"88",X"CC",X"EE",X"2E",X"0E",X"0E",X"0E",X"60",X"10",X"70",X"10",X"60",X"00",X"00",X"03",
|
||||
X"00",X"32",X"F1",X"33",X"76",X"77",X"3F",X"1F",X"FF",X"FC",X"F3",X"F5",X"FD",X"CF",X"EF",X"FD",
|
||||
X"8E",X"8B",X"03",X"01",X"01",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"06",X"0F",X"0F",X"06",
|
||||
X"1F",X"01",X"05",X"01",X"09",X"09",X"01",X"01",X"F8",X"FD",X"7F",X"0E",X"0C",X"08",X"08",X"00",
|
||||
X"40",X"40",X"E0",X"80",X"FE",X"FE",X"F9",X"FD",X"00",X"00",X"03",X"01",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"0E",X"0F",X"03",X"01",X"01",X"20",X"10",X"00",X"77",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FA",X"FF",X"7F",X"2E",X"0C",X"0C",X"0E",X"0E",X"0F",X"03",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"0F",X"1F",X"3F",X"11",X"00",X"00",X"00",X"00",X"EF",X"EB",X"E1",X"EB",X"CF",X"03",X"01",X"00",
|
||||
X"40",X"50",X"20",X"B8",X"E6",X"FB",X"F1",X"FB",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"08",X"0C",X"0E",X"07",X"07",X"13",X"17",X"00",X"00",X"00",X"77",X"FF",X"FF",X"FC",X"FF",
|
||||
X"F5",X"FF",X"7F",X"2E",X"4C",X"00",X"00",X"00",X"01",X"07",X"0F",X"00",X"00",X"00",X"00",X"00",
|
||||
X"3F",X"7E",X"FC",X"76",X"33",X"00",X"01",X"07",X"BE",X"8F",X"87",X"8F",X"0F",X"0F",X"0E",X"0C",
|
||||
X"00",X"00",X"00",X"00",X"88",X"CC",X"EE",X"EE",X"00",X"07",X"00",X"80",X"40",X"F0",X"73",X"B3",
|
||||
X"00",X"0E",X"0F",X"33",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"0C",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"EE",X"EE",X"CC",X"88",X"00",X"00",X"00",X"00",X"B3",X"73",X"F0",X"40",X"80",X"00",X"07",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"33",X"0F",X"0E",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"0C",X"00",X"00",
|
||||
X"0E",X"4A",X"2C",X"F0",X"AC",X"C8",X"88",X"88",X"33",X"33",X"33",X"11",X"00",X"00",X"00",X"00",
|
||||
X"BC",X"BC",X"DA",X"69",X"1F",X"27",X"01",X"00",X"A7",X"A7",X"7F",X"FF",X"FF",X"FF",X"7F",X"37",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3F",X"6E",X"4C",X"08",X"00",X"00",X"00",X"00",
|
||||
X"0C",X"0C",X"0C",X"48",X"B8",X"20",X"50",X"00",X"77",X"77",X"77",X"23",X"01",X"00",X"00",X"00",
|
||||
X"AD",X"AD",X"A5",X"D3",X"3F",X"5F",X"13",X"01",X"CF",X"CF",X"EF",X"FF",X"FB",X"FD",X"EE",X"EE",
|
||||
X"00",X"00",X"00",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"6E",X"7F",X"17",X"01",X"00",X"00",X"00",X"00",
|
||||
X"0E",X"0E",X"1E",X"AC",X"BC",X"A8",X"98",X"00",X"33",X"33",X"33",X"11",X"00",X"00",X"00",X"00",
|
||||
X"BC",X"BC",X"DA",X"69",X"1F",X"27",X"01",X"13",X"A7",X"A7",X"7F",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",
|
||||
X"13",X"13",X"37",X"3F",X"6E",X"00",X"00",X"00",X"FF",X"FF",X"CC",X"00",X"00",X"00",X"00",X"00",
|
||||
X"08",X"08",X"08",X"80",X"60",X"40",X"A0",X"00",X"FF",X"FF",X"FE",X"56",X"03",X"01",X"00",X"00",
|
||||
X"5B",X"5B",X"5B",X"B7",X"7F",X"BF",X"37",X"37",X"8F",X"8F",X"CF",X"EF",X"F7",X"EA",X"CC",X"CC",
|
||||
X"00",X"00",X"00",X"00",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"13",X"13",X"01",X"00",X"00",X"00",X"00",X"00",X"CC",X"EE",X"7F",X"17",X"01",X"00",X"00",X"00",
|
||||
X"00",X"88",X"88",X"CC",X"CC",X"EE",X"EE",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"11",
|
||||
X"01",X"03",X"56",X"76",X"EF",X"CF",X"DE",X"FE",X"08",X"3E",X"B6",X"F6",X"7E",X"3E",X"B6",X"F6",
|
||||
X"EE",X"EE",X"EE",X"CE",X"CE",X"8E",X"0E",X"0C",X"11",X"11",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"77",X"33",X"11",X"00",X"FE",X"FE",X"FF",X"FF",X"FF",X"FF",X"FF",X"01",
|
||||
X"00",X"00",X"10",X"10",X"F0",X"1C",X"1C",X"0C",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01",
|
||||
X"0F",X"77",X"33",X"11",X"33",X"37",X"3F",X"3F",X"00",X"88",X"CC",X"FF",X"CF",X"8F",X"0F",X"0F",
|
||||
X"0C",X"0C",X"0C",X"80",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01",
|
||||
X"3F",X"3F",X"37",X"32",X"11",X"33",X"77",X"0F",X"87",X"4B",X"AD",X"F0",X"EC",X"C8",X"80",X"00",
|
||||
X"0C",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"10",X"00",X"00",X"30",X"00",X"00",X"10",
|
||||
X"01",X"00",X"80",X"40",X"F0",X"40",X"80",X"00",X"0F",X"13",X"17",X"1F",X"3F",X"3F",X"37",X"37",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"EE",X"0C",X"10",X"00",X"00",X"30",X"00",X"00",X"10",X"00",
|
||||
X"00",X"80",X"40",X"F0",X"40",X"80",X"00",X"00",X"37",X"37",X"3F",X"3F",X"1F",X"17",X"13",X"0F",
|
||||
X"22",X"26",X"B7",X"3F",X"5F",X"5F",X"CE",X"8C",X"00",X"00",X"00",X"00",X"00",X"13",X"17",X"3F",
|
||||
X"00",X"00",X"00",X"11",X"11",X"99",X"BA",X"BB",X"30",X"27",X"4F",X"5A",X"D2",X"5E",X"C7",X"EF",
|
||||
X"8C",X"8E",X"CE",X"DF",X"DF",X"5F",X"5F",X"14",X"3F",X"3F",X"1F",X"1F",X"07",X"03",X"00",X"00",
|
||||
X"CC",X"CC",X"CC",X"EE",X"FF",X"7F",X"0F",X"07",X"6F",X"EF",X"67",X"75",X"FC",X"DE",X"0C",X"00",
|
||||
X"00",X"00",X"00",X"08",X"4C",X"4E",X"2E",X"C3",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"01",X"32",X"23",X"23",X"74",X"77",X"60",X"4E",X"9F",X"A7",X"A7",X"BF",X"9F",X"DF",
|
||||
X"8C",X"C2",X"2E",X"CE",X"8C",X"88",X"00",X"00",X"33",X"77",X"EF",X"DF",X"8F",X"CF",X"77",X"33",
|
||||
X"89",X"EE",X"3F",X"CF",X"4C",X"6E",X"EE",X"CC",X"CF",X"EF",X"EF",X"EF",X"7F",X"37",X"00",X"00",
|
||||
X"C1",X"DB",X"5B",X"B7",X"5E",X"4E",X"9E",X"BC",X"00",X"00",X"00",X"03",X"07",X"0F",X"1F",X"1F",
|
||||
X"00",X"00",X"00",X"4C",X"EE",X"EE",X"EE",X"EE",X"00",X"01",X"13",X"74",X"56",X"57",X"F9",X"FF",
|
||||
X"2D",X"D3",X"3F",X"CE",X"0C",X"00",X"00",X"00",X"3F",X"3F",X"1F",X"17",X"17",X"03",X"01",X"00",
|
||||
X"DF",X"9F",X"9F",X"DF",X"FF",X"7F",X"0F",X"00",X"1E",X"CF",X"EF",X"9F",X"CF",X"7F",X"0E",X"00",
|
||||
X"00",X"00",X"08",X"0C",X"0C",X"0C",X"86",X"4A",X"00",X"00",X"01",X"03",X"12",X"01",X"07",X"07",
|
||||
X"00",X"0C",X"0E",X"87",X"4B",X"0F",X"0F",X"0F",X"04",X"04",X"0D",X"4B",X"87",X"0F",X"0F",X"C3",
|
||||
X"0C",X"0E",X"0E",X"86",X"0E",X"0C",X"08",X"00",X"07",X"07",X"16",X"03",X"03",X"01",X"00",X"00",
|
||||
X"1E",X"2D",X"1E",X"87",X"4B",X"09",X"01",X"00",X"2D",X"1E",X"1E",X"0F",X"1E",X"2D",X"0D",X"00",
|
||||
X"00",X"0C",X"C0",X"C0",X"00",X"0C",X"C0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"11",X"33",X"77",X"7F",X"7F",X"7F",X"02",X"25",X"AD",X"AD",X"AD",X"2D",X"2D",X"0A",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"7F",X"7F",X"7F",X"77",X"77",X"33",X"11",X"00",X"08",X"08",X"08",X"FF",X"FF",X"EE",X"EE",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"11",X"11",X"11",X"11",X"11",X"11",X"77",X"FF",X"EE",X"CC",X"CC",X"CC",X"88",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"61",X"07",X"01",X"61",X"61",X"07",X"00",
|
||||
X"19",X"95",X"B7",X"B7",X"B7",X"A6",X"84",X"08",X"00",X"88",X"CC",X"88",X"88",X"00",X"00",X"00",
|
||||
X"00",X"0C",X"C0",X"C0",X"00",X"0C",X"C0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"11",X"33",X"33",X"77",X"77",X"77",X"02",X"25",X"AD",X"AD",X"AD",X"AD",X"25",X"EE",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"7F",X"7F",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"77",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"7F",X"7F",X"00",X"00",X"00",X"00",X"00",X"77",X"FF",X"FF",
|
||||
X"C0",X"C0",X"0C",X"00",X"C0",X"C0",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"77",X"77",X"77",X"33",X"33",X"11",X"00",X"00",X"CE",X"25",X"AD",X"AD",X"AD",X"AD",X"25",X"02",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"76",X"76",X"F0",X"F0",X"F6",X"FE",X"F8",X"BC",X"80",X"C0",X"C0",X"C0",X"C0",X"88",X"88",X"88",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"8F",X"8F",X"8F",X"0F",X"0F",X"07",X"07",X"03",X"88",X"88",X"88",X"08",X"0C",X"0C",X"0C",X"0C",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"01",X"03",X"03",X"07",X"07",X"07",X"07",X"0E",X"0E",X"0E",X"0C",X"0C",X"0C",X"08",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"34",X"70",X"76",X"F6",X"F0",X"F0",X"73",X"33",X"00",X"80",X"C0",X"C0",X"C0",X"C0",X"80",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"30",X"43",X"07",X"07",X"00",X"00",X"00",X"00",X"80",X"0C",X"0C",X"0C",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"8F",X"8F",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"FB",X"FB",X"00",X"00",X"00",X"00",X"00",X"00",X"84",X"C0",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"70",X"70",X"73",X"33",X"00",X"00",X"00",X"00",X"C0",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",
|
||||
X"00",X"40",X"60",X"20",X"38",X"78",X"1C",X"0C",X"00",X"00",X"00",X"10",X"12",X"47",X"EF",X"FF",
|
||||
X"08",X"08",X"05",X"D7",X"B7",X"3F",X"7F",X"EF",X"08",X"08",X"CC",X"CF",X"CF",X"CF",X"EF",X"FF",
|
||||
X"1C",X"1C",X"1C",X"78",X"28",X"A8",X"C8",X"00",X"FF",X"FF",X"FF",X"77",X"77",X"33",X"11",X"00",
|
||||
X"EF",X"EF",X"DF",X"DF",X"DF",X"DF",X"DF",X"03",X"FD",X"FD",X"FD",X"FB",X"FD",X"FD",X"FE",X"1F",
|
||||
X"00",X"00",X"00",X"00",X"28",X"18",X"1C",X"1C",X"00",X"00",X"00",X"10",X"12",X"47",X"EF",X"FF",
|
||||
X"05",X"05",X"05",X"D7",X"B7",X"3F",X"7F",X"EF",X"00",X"00",X"8C",X"8F",X"CF",X"CF",X"EF",X"FF",
|
||||
X"3C",X"1C",X"1C",X"08",X"08",X"88",X"88",X"00",X"FF",X"FF",X"FF",X"77",X"77",X"33",X"11",X"00",
|
||||
X"EF",X"DF",X"DF",X"BF",X"BF",X"BF",X"BF",X"03",X"FD",X"FD",X"FD",X"FB",X"FB",X"FD",X"FE",X"0F",
|
||||
X"00",X"00",X"10",X"98",X"F8",X"9C",X"9C",X"8C",X"01",X"00",X"11",X"33",X"77",X"77",X"FF",X"FF",
|
||||
X"0F",X"7F",X"EF",X"CF",X"CF",X"EF",X"FF",X"FF",X"0F",X"CC",X"7F",X"3F",X"D3",X"A5",X"AD",X"AD",
|
||||
X"8C",X"9C",X"9C",X"F8",X"98",X"10",X"00",X"00",X"FF",X"FF",X"77",X"77",X"33",X"11",X"00",X"01",
|
||||
X"FF",X"FF",X"EF",X"CF",X"CF",X"EF",X"7F",X"0F",X"AD",X"AD",X"A5",X"D3",X"3F",X"7F",X"CC",X"0F",
|
||||
X"00",X"00",X"18",X"D0",X"F0",X"5C",X"DE",X"CF",X"07",X"11",X"00",X"11",X"33",X"BB",X"FF",X"FF",
|
||||
X"0F",X"FF",X"F1",X"FF",X"FF",X"FF",X"FF",X"FF",X"08",X"8C",X"EF",X"CF",X"CF",X"EF",X"FF",X"FF",
|
||||
X"CF",X"DE",X"5C",X"F0",X"D0",X"18",X"00",X"00",X"FF",X"FF",X"BB",X"33",X"11",X"00",X"11",X"07",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"F1",X"FF",X"0F",X"FF",X"FF",X"EF",X"CF",X"CF",X"EF",X"8C",X"08",
|
||||
X"0C",X"0C",X"0C",X"48",X"40",X"40",X"E0",X"50",X"FF",X"FF",X"EF",X"47",X"03",X"01",X"00",X"00",
|
||||
X"78",X"78",X"A5",X"D3",X"2F",X"5F",X"13",X"37",X"4F",X"6F",X"FF",X"FF",X"FB",X"EC",X"EE",X"FE",
|
||||
X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",
|
||||
X"7F",X"7F",X"FF",X"FF",X"7F",X"7F",X"17",X"01",X"EE",X"CC",X"CC",X"88",X"88",X"CC",X"EE",X"0E",
|
||||
X"0C",X"0C",X"0C",X"48",X"40",X"30",X"20",X"50",X"FF",X"FF",X"EF",X"47",X"03",X"01",X"00",X"00",
|
||||
X"AD",X"AD",X"A5",X"D3",X"2F",X"5F",X"13",X"01",X"CF",X"EF",X"FF",X"FF",X"FB",X"EC",X"EE",X"FF",
|
||||
X"40",X"00",X"88",X"88",X"CC",X"EE",X"FF",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"01",X"13",X"13",X"13",X"01",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"7F",X"07",X"00",
|
||||
X"FF",X"FF",X"DD",X"CC",X"C8",X"A8",X"30",X"30",X"3F",X"37",X"23",X"30",X"30",X"01",X"00",X"00",
|
||||
X"FF",X"FF",X"7F",X"3F",X"3F",X"7F",X"13",X"17",X"FF",X"FF",X"FF",X"FF",X"FF",X"F8",X"FF",X"EE",
|
||||
X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"13",X"13",X"37",X"37",X"7F",X"0F",
|
||||
X"7F",X"FF",X"FF",X"FF",X"FF",X"EE",X"CC",X"00",X"CC",X"CC",X"88",X"88",X"00",X"00",X"00",X"00",
|
||||
X"FF",X"FF",X"DD",X"CC",X"D8",X"B8",X"10",X"10",X"3F",X"37",X"23",X"30",X"30",X"01",X"00",X"00",
|
||||
X"FF",X"FF",X"7F",X"3F",X"3F",X"7F",X"13",X"13",X"FF",X"FF",X"FF",X"FF",X"FF",X"F8",X"FF",X"EE",
|
||||
X"10",X"00",X"00",X"88",X"CC",X"CC",X"EE",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"13",X"01",X"01",X"01",X"00",X"00",X"00",X"00",X"EE",X"FF",X"FF",X"FF",X"7F",X"7F",X"37",X"03",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"08",X"0C",X"0C",X"0E",X"00",X"00",X"00",X"10",X"12",X"47",X"EF",X"FF",
|
||||
X"08",X"08",X"05",X"D7",X"B7",X"3F",X"7F",X"FF",X"08",X"08",X"CC",X"CF",X"CF",X"CF",X"EF",X"FF",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"08",X"0C",X"0C",X"0E",X"00",X"00",X"00",X"10",X"12",X"47",X"EF",X"FF",
|
||||
X"05",X"05",X"05",X"D7",X"B7",X"3F",X"7F",X"FF",X"00",X"00",X"8C",X"8F",X"CF",X"CF",X"EF",X"FF",
|
||||
X"0E",X"0E",X"0C",X"48",X"28",X"A8",X"B8",X"70",X"FF",X"FF",X"FF",X"77",X"77",X"33",X"11",X"00",
|
||||
X"FF",X"EF",X"DF",X"DF",X"DF",X"DF",X"BF",X"37",X"FF",X"FF",X"FF",X"FF",X"FF",X"FD",X"FE",X"FF",
|
||||
X"50",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"13",X"37",X"0F",
|
||||
X"37",X"7F",X"7F",X"FF",X"FF",X"FF",X"FF",X"4C",X"FF",X"FF",X"EE",X"EE",X"CC",X"CC",X"00",X"00",
|
||||
X"0E",X"0E",X"0E",X"2C",X"28",X"A8",X"B8",X"30",X"FF",X"FF",X"FF",X"77",X"77",X"33",X"11",X"00",
|
||||
X"FF",X"FF",X"FF",X"DF",X"DF",X"DF",X"DF",X"13",X"FF",X"FF",X"FF",X"FF",X"FB",X"FD",X"FE",X"EE",
|
||||
X"60",X"00",X"00",X"00",X"88",X"88",X"CC",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"37",X"37",X"13",X"13",X"13",X"01",X"00",X"00",X"EE",X"EE",X"FF",X"FF",X"FF",X"FF",X"7F",X"0F",
|
||||
X"00",X"00",X"10",X"10",X"78",X"1C",X"2C",X"0C",X"00",X"00",X"01",X"03",X"56",X"FE",X"FF",X"FF",
|
||||
X"0F",X"37",X"5F",X"2F",X"B7",X"F5",X"78",X"78",X"0F",X"EE",X"EC",X"FB",X"FF",X"FF",X"6F",X"4F",
|
||||
X"0C",X"1C",X"1C",X"78",X"10",X"20",X"88",X"0C",X"FF",X"FF",X"EF",X"47",X"12",X"10",X"00",X"00",
|
||||
X"78",X"78",X"7D",X"3F",X"A7",X"D7",X"13",X"03",X"4F",X"6F",X"FF",X"FF",X"FB",X"EC",X"FF",X"0F",
|
||||
X"00",X"00",X"10",X"10",X"78",X"1C",X"1C",X"0C",X"0B",X"11",X"01",X"30",X"74",X"EF",X"FF",X"FF",
|
||||
X"0F",X"FF",X"7F",X"3F",X"3F",X"7D",X"78",X"78",X"0C",X"CC",X"CC",X"FB",X"FF",X"FF",X"6F",X"4F",
|
||||
X"0C",X"0C",X"0C",X"48",X"20",X"70",X"A0",X"28",X"FF",X"FF",X"EF",X"47",X"0B",X"01",X"04",X"00",
|
||||
X"78",X"78",X"7D",X"F3",X"E3",X"5F",X"13",X"07",X"4F",X"6F",X"FF",X"FF",X"FB",X"EC",X"FF",X"0F",
|
||||
X"0C",X"0C",X"0C",X"48",X"40",X"40",X"E0",X"50",X"FF",X"FF",X"EF",X"47",X"03",X"01",X"00",X"00",
|
||||
X"78",X"78",X"A5",X"D3",X"2F",X"5F",X"13",X"37",X"4F",X"6F",X"FF",X"FF",X"FB",X"EC",X"EE",X"FE",
|
||||
X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"13",X"13",X"37",X"0F",
|
||||
X"7F",X"7F",X"FF",X"FF",X"FF",X"FF",X"EE",X"0C",X"EE",X"CC",X"CC",X"88",X"88",X"00",X"00",X"00",
|
||||
X"0C",X"0C",X"0C",X"48",X"40",X"30",X"20",X"50",X"0F",X"0F",X"1E",X"07",X"03",X"10",X"0C",X"08",
|
||||
X"2D",X"2D",X"2D",X"C3",X"C3",X"2D",X"03",X"01",X"0F",X"0F",X"0F",X"0F",X"4B",X"2C",X"0E",X"0F",
|
||||
X"40",X"00",X"08",X"08",X"0C",X"0E",X"0F",X"0F",X"01",X"02",X"00",X"08",X"01",X"02",X"00",X"00",
|
||||
X"01",X"03",X"03",X"03",X"01",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"07",X"00",
|
||||
X"00",X"88",X"88",X"CC",X"CC",X"EE",X"EE",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"11",
|
||||
X"10",X"12",X"47",X"67",X"FE",X"DE",X"CF",X"EF",X"80",X"B6",X"3E",X"7E",X"F6",X"B6",X"3E",X"7E",
|
||||
X"EE",X"EE",X"EE",X"CE",X"CF",X"8F",X"01",X"01",X"11",X"11",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"77",X"33",X"11",X"00",X"FE",X"FE",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",
|
||||
X"00",X"88",X"88",X"CC",X"CC",X"EE",X"EE",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"11",
|
||||
X"01",X"03",X"56",X"76",X"EF",X"CF",X"DE",X"FE",X"08",X"3E",X"B6",X"F6",X"7E",X"3E",X"B6",X"F6",
|
||||
X"EE",X"EE",X"EE",X"CE",X"CE",X"8E",X"0E",X"0C",X"11",X"11",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"77",X"33",X"11",X"00",X"FE",X"FE",X"FF",X"FF",X"FF",X"FF",X"FF",X"01",
|
||||
X"00",X"00",X"00",X"00",X"88",X"88",X"8C",X"8E",X"00",X"11",X"33",X"17",X"C3",X"C3",X"17",X"77",
|
||||
X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"88",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"8E",X"8F",X"8B",X"89",X"01",X"02",X"00",X"00",X"77",X"17",X"C3",X"C3",X"17",X"33",X"11",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"EE",X"88",
|
||||
X"00",X"00",X"00",X"00",X"88",X"88",X"8E",X"8E",X"00",X"00",X"11",X"17",X"C3",X"C3",X"17",X"77",
|
||||
X"00",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"88",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"8F",X"8F",X"89",X"88",X"00",X"00",X"00",X"00",X"77",X"17",X"C3",X"C3",X"17",X"11",X"00",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"EE",X"88",X"00",
|
||||
X"00",X"88",X"88",X"C4",X"C4",X"2E",X"2E",X"A6",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"11",
|
||||
X"00",X"31",X"56",X"56",X"AD",X"AD",X"1E",X"1E",X"00",X"FA",X"96",X"87",X"4B",X"5A",X"96",X"87",
|
||||
X"A6",X"2E",X"2E",X"C4",X"4C",X"4C",X"8F",X"06",X"11",X"11",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"2D",X"0F",X"8F",X"8F",X"47",X"23",X"11",X"00",X"4B",X"1E",X"1E",X"0F",X"0F",X"0F",X"FF",X"00",
|
||||
X"00",X"88",X"88",X"4C",X"4C",X"2E",X"A6",X"A6",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"11",
|
||||
X"00",X"31",X"56",X"56",X"AD",X"AD",X"1E",X"1E",X"00",X"FA",X"96",X"96",X"5A",X"5A",X"96",X"87",
|
||||
X"A6",X"A6",X"A6",X"4E",X"4E",X"8E",X"0C",X"08",X"11",X"11",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"2D",X"0F",X"8F",X"8F",X"47",X"23",X"11",X"00",X"4B",X"0F",X"0F",X"0F",X"0F",X"0F",X"FF",X"01",
|
||||
X"00",X"00",X"00",X"00",X"00",X"88",X"4C",X"2E",X"00",X"00",X"00",X"00",X"00",X"33",X"43",X"74",
|
||||
X"00",X"00",X"00",X"33",X"CF",X"0F",X"C3",X"3C",X"00",X"00",X"00",X"CC",X"3F",X"0F",X"87",X"0F",
|
||||
X"2E",X"2E",X"2E",X"2E",X"2F",X"CF",X"03",X"02",X"74",X"43",X"47",X"61",X"76",X"11",X"00",X"00",
|
||||
X"3C",X"C3",X"0F",X"69",X"96",X"8F",X"77",X"00",X"0F",X"87",X"0F",X"69",X"96",X"1F",X"EE",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"88",X"4C",X"2E",X"00",X"00",X"00",X"00",X"00",X"33",X"43",X"74",
|
||||
X"00",X"00",X"00",X"33",X"CF",X"0F",X"C3",X"3C",X"00",X"00",X"00",X"CC",X"3F",X"0F",X"87",X"0F",
|
||||
X"2E",X"2E",X"2E",X"2F",X"4F",X"8E",X"0C",X"00",X"74",X"43",X"47",X"70",X"67",X"11",X"00",X"00",
|
||||
X"3C",X"C3",X"0F",X"E1",X"3C",X"8F",X"77",X"00",X"0F",X"87",X"0F",X"0F",X"E1",X"1F",X"EF",X"00",
|
||||
X"00",X"00",X"88",X"88",X"88",X"88",X"88",X"88",X"00",X"00",X"33",X"22",X"22",X"22",X"22",X"22",
|
||||
X"00",X"00",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"00",X"00",
|
||||
X"88",X"88",X"88",X"88",X"88",X"00",X"00",X"00",X"22",X"22",X"22",X"22",X"33",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",
|
||||
X"CC",X"22",X"22",X"EE",X"00",X"EE",X"44",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"22",X"22",X"33",X"00",X"33",X"00",X"00",
|
||||
X"00",X"EE",X"00",X"22",X"AA",X"AA",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"00",X"22",X"22",X"22",X"33",X"00",
|
||||
X"00",X"44",X"44",X"66",X"66",X"EE",X"EE",X"EE",X"00",X"00",X"11",X"11",X"11",X"33",X"33",X"33",
|
||||
X"60",X"69",X"0F",X"9F",X"F9",X"69",X"0F",X"9F",X"00",X"88",X"88",X"88",X"88",X"88",X"88",X"CC",
|
||||
X"EE",X"EE",X"EE",X"CE",X"CE",X"8E",X"06",X"0C",X"33",X"33",X"11",X"11",X"00",X"00",X"00",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"11",X"00",X"CC",X"DD",X"DD",X"DD",X"FF",X"FF",X"FF",X"00",
|
||||
X"00",X"88",X"88",X"CC",X"CC",X"EE",X"EE",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"11",
|
||||
X"10",X"12",X"47",X"67",X"FE",X"DE",X"CF",X"EF",X"80",X"B6",X"3E",X"7E",X"F6",X"B6",X"3E",X"7E",
|
||||
X"EE",X"EE",X"EE",X"CE",X"CE",X"8E",X"06",X"0C",X"11",X"11",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"77",X"33",X"11",X"00",X"FE",X"FE",X"FE",X"FE",X"FF",X"FF",X"FF",X"00",
|
||||
X"00",X"00",X"00",X"88",X"CC",X"CC",X"EE",X"EE",X"17",X"C3",X"C3",X"17",X"77",X"11",X"00",X"00",
|
||||
X"9F",X"C3",X"C3",X"9F",X"FF",X"FF",X"77",X"11",X"88",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"EE",X"EE",X"66",X"EE",X"CD",X"8F",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"33",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"33",X"FF",X"00",X"77",X"11",X"00",X"11",X"77",X"FF",X"EF",X"00",
|
||||
X"00",X"00",X"00",X"00",X"88",X"CC",X"CC",X"EE",X"00",X"00",X"17",X"C3",X"C3",X"17",X"77",X"00",
|
||||
X"00",X"77",X"9F",X"C3",X"C3",X"9F",X"FF",X"FF",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"EE",X"EE",X"EE",X"EE",X"CD",X"8F",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"33",X"00",
|
||||
X"11",X"00",X"00",X"00",X"11",X"FF",X"FF",X"00",X"FF",X"33",X"00",X"33",X"FF",X"FF",X"EF",X"00",
|
||||
X"00",X"00",X"00",X"00",X"88",X"CC",X"CC",X"EE",X"00",X"00",X"00",X"33",X"17",X"C3",X"C3",X"17",
|
||||
X"00",X"00",X"77",X"FF",X"9F",X"C3",X"C3",X"9F",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"EE",X"EE",X"EE",X"EE",X"CD",X"8F",X"0E",X"00",X"77",X"00",X"00",X"00",X"00",X"77",X"11",X"00",
|
||||
X"FF",X"11",X"00",X"00",X"77",X"FF",X"FF",X"00",X"FF",X"FF",X"00",X"77",X"FF",X"FF",X"EF",X"00",
|
||||
X"00",X"00",X"00",X"88",X"CC",X"CC",X"EE",X"EE",X"00",X"00",X"00",X"11",X"33",X"77",X"17",X"C3",
|
||||
X"00",X"00",X"77",X"FF",X"FF",X"FF",X"9F",X"C3",X"00",X"00",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"EE",X"EE",X"EE",X"EE",X"CD",X"8F",X"0E",X"00",X"C3",X"17",X"77",X"70",X"77",X"11",X"00",X"00",
|
||||
X"C3",X"9F",X"FF",X"F0",X"FF",X"FF",X"77",X"00",X"FF",X"FF",X"FF",X"F0",X"FF",X"FF",X"EF",X"00");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -0,0 +1,38 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity PROM1_DST is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(7 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of PROM1_DST is
|
||||
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09",
|
||||
X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05",
|
||||
X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05",
|
||||
X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02",
|
||||
X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04",
|
||||
X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00",
|
||||
X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02",
|
||||
X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01",
|
||||
X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07",
|
||||
X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07",
|
||||
X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F",
|
||||
X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08",
|
||||
X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F",
|
||||
X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00",
|
||||
X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F",
|
||||
X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -0,0 +1,38 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity C:\Users\hp\Desktop\Birdiy_MiST\rtl\ROM\PROM3_DST is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(7 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of C:\Users\hp\Desktop\Birdiy_MiST\rtl\ROM\PROM3_DST is
|
||||
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",
|
||||
X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",
|
||||
X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",
|
||||
X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",
|
||||
X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",
|
||||
X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",
|
||||
X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",
|
||||
X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -0,0 +1,38 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity PROM4_DST is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(7 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of PROM4_DST is
|
||||
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"01",X"00",X"0F",X"0B",X"03",X"00",X"0F",X"0B",X"0F",
|
||||
X"00",X"0F",X"0B",X"07",X"00",X"0F",X"0B",X"05",X"00",X"0F",X"0B",X"0C",X"00",X"0F",X"0B",X"09",
|
||||
X"00",X"05",X"0B",X"07",X"00",X"0B",X"01",X"09",X"00",X"05",X"0B",X"01",X"00",X"02",X"05",X"01",
|
||||
X"00",X"02",X"0B",X"01",X"00",X"05",X"0B",X"09",X"00",X"0C",X"01",X"07",X"00",X"01",X"0C",X"0F",
|
||||
X"00",X"0F",X"00",X"0B",X"00",X"0C",X"05",X"0F",X"00",X"0F",X"0B",X"0E",X"00",X"0F",X"0B",X"0D",
|
||||
X"00",X"01",X"09",X"0F",X"00",X"09",X"0C",X"09",X"00",X"09",X"05",X"0F",X"00",X"05",X"0C",X"0F",
|
||||
X"00",X"01",X"07",X"0B",X"00",X"0F",X"0B",X"00",X"00",X"0F",X"00",X"0B",X"00",X"0B",X"05",X"09",
|
||||
X"00",X"0B",X"0C",X"02",X"00",X"0B",X"07",X"09",X"00",X"02",X"0B",X"00",X"00",X"02",X"0B",X"07",
|
||||
X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"01",X"00",X"0F",X"0B",X"03",X"00",X"0F",X"0B",X"0F",
|
||||
X"00",X"0F",X"0B",X"07",X"00",X"0F",X"0B",X"05",X"00",X"0F",X"0B",X"0C",X"00",X"0F",X"0B",X"09",
|
||||
X"00",X"05",X"0B",X"07",X"00",X"0B",X"01",X"09",X"00",X"05",X"0B",X"01",X"00",X"02",X"05",X"01",
|
||||
X"00",X"02",X"0B",X"01",X"00",X"05",X"0B",X"09",X"00",X"0C",X"01",X"07",X"00",X"01",X"0C",X"0F",
|
||||
X"00",X"0F",X"00",X"0B",X"00",X"0C",X"05",X"0F",X"00",X"0F",X"0B",X"0E",X"00",X"0F",X"0B",X"0D",
|
||||
X"00",X"01",X"09",X"0F",X"00",X"09",X"0C",X"09",X"00",X"09",X"05",X"0F",X"00",X"05",X"0C",X"0F",
|
||||
X"00",X"01",X"07",X"0B",X"00",X"0F",X"0B",X"00",X"00",X"0F",X"00",X"0B",X"00",X"0B",X"05",X"09",
|
||||
X"00",X"0B",X"0C",X"0F",X"00",X"0B",X"07",X"09",X"00",X"02",X"0B",X"00",X"00",X"02",X"0B",X"07");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -0,0 +1,24 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity PROM7_DST is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(4 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of PROM7_DST is
|
||||
type rom is array(0 to 31) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"00",X"07",X"66",X"EF",X"00",X"F8",X"EA",X"6F",X"00",X"3F",X"00",X"C9",X"38",X"AA",X"AF",X"F6",
|
||||
X"00",X"07",X"66",X"EF",X"00",X"F8",X"EA",X"6F",X"00",X"3F",X"00",X"C9",X"38",X"AA",X"AF",X"F6");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
1046
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/ROM_PGM_0.vhd
Normal file
1046
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/ROM_PGM_0.vhd
Normal file
File diff suppressed because it is too large
Load Diff
35
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/build_id.tcl
Normal file
35
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/build_id.tcl
Normal file
@@ -0,0 +1,35 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
2
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/build_id.v
Normal file
2
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/build_id.v
Normal file
@@ -0,0 +1,2 @@
|
||||
`define BUILD_DATE "190517"
|
||||
`define BUILD_TIME "155807"
|
||||
1080
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/cpu/T80.vhd
Normal file
1080
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/cpu/T80.vhd
Normal file
File diff suppressed because it is too large
Load Diff
371
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/cpu/T80_ALU.vhd
Normal file
371
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/cpu/T80_ALU.vhd
Normal file
@@ -0,0 +1,371 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0247
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
|
||||
--
|
||||
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
|
||||
--
|
||||
-- 0240 : Added GB operations
|
||||
--
|
||||
-- 0242 : Cleanup
|
||||
--
|
||||
-- 0247 : Cleanup
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_ALU is
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_ALU;
|
||||
|
||||
architecture rtl of T80_ALU is
|
||||
|
||||
procedure AddSub(A : std_logic_vector;
|
||||
B : std_logic_vector;
|
||||
Sub : std_logic;
|
||||
Carry_In : std_logic;
|
||||
signal Res : out std_logic_vector;
|
||||
signal Carry : out std_logic) is
|
||||
|
||||
variable B_i : unsigned(A'length - 1 downto 0);
|
||||
variable Res_i : unsigned(A'length + 1 downto 0);
|
||||
begin
|
||||
if Sub = '1' then
|
||||
B_i := not unsigned(B);
|
||||
else
|
||||
B_i := unsigned(B);
|
||||
end if;
|
||||
|
||||
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
|
||||
Carry <= Res_i(A'length + 1);
|
||||
Res <= std_logic_vector(Res_i(A'length downto 1));
|
||||
end;
|
||||
|
||||
-- AddSub variables (temporary signals)
|
||||
signal UseCarry : std_logic;
|
||||
signal Carry7_v : std_logic;
|
||||
signal Overflow_v : std_logic;
|
||||
signal HalfCarry_v : std_logic;
|
||||
signal Carry_v : std_logic;
|
||||
signal Q_v : std_logic_vector(7 downto 0);
|
||||
|
||||
signal BitMask : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
with IR(5 downto 3) select BitMask <= "00000001" when "000",
|
||||
"00000010" when "001",
|
||||
"00000100" when "010",
|
||||
"00001000" when "011",
|
||||
"00010000" when "100",
|
||||
"00100000" when "101",
|
||||
"01000000" when "110",
|
||||
"10000000" when others;
|
||||
|
||||
UseCarry <= not ALU_Op(2) and ALU_Op(0);
|
||||
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
|
||||
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
|
||||
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
|
||||
|
||||
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
|
||||
process (Carry_v, Carry7_v, Q_v)
|
||||
begin
|
||||
if(Mode=2) then
|
||||
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
|
||||
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
|
||||
OverFlow_v <= Carry_v xor Carry7_v;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
|
||||
variable Q_t : std_logic_vector(7 downto 0);
|
||||
variable DAA_Q : unsigned(8 downto 0);
|
||||
begin
|
||||
Q_t := "--------";
|
||||
F_Out <= F_In;
|
||||
DAA_Q := "---------";
|
||||
case ALU_Op is
|
||||
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_C) <= '0';
|
||||
case ALU_OP(2 downto 0) is
|
||||
when "000" | "001" => -- ADD, ADC
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_C) <= Carry_v;
|
||||
F_Out(Flag_H) <= HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "010" | "011" | "111" => -- SUB, SBC, CP
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_N) <= '1';
|
||||
F_Out(Flag_C) <= not Carry_v;
|
||||
F_Out(Flag_H) <= not HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "100" => -- AND
|
||||
Q_t(7 downto 0) := BusA and BusB;
|
||||
F_Out(Flag_H) <= '1';
|
||||
when "101" => -- XOR
|
||||
Q_t(7 downto 0) := BusA xor BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
when others => -- OR "110"
|
||||
Q_t(7 downto 0) := BusA or BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
end case;
|
||||
if ALU_Op(2 downto 0) = "111" then -- CP
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
else
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
end if;
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
if Z16 = '1' then
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
|
||||
end if;
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
case ALU_Op(2 downto 0) is
|
||||
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
|
||||
when others =>
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
end case;
|
||||
if Arith16 = '1' then
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
end if;
|
||||
when "1100" =>
|
||||
-- DAA
|
||||
F_Out(Flag_H) <= F_In(Flag_H);
|
||||
F_Out(Flag_C) <= F_In(Flag_C);
|
||||
DAA_Q(7 downto 0) := unsigned(BusA);
|
||||
DAA_Q(8) := '0';
|
||||
if F_In(Flag_N) = '0' then
|
||||
-- After addition
|
||||
-- Alow > 9 or H = 1
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if (DAA_Q(3 downto 0) > 9) then
|
||||
F_Out(Flag_H) <= '1';
|
||||
else
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q := DAA_Q + 6;
|
||||
end if;
|
||||
-- new Ahigh > 9 or C = 1
|
||||
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q + 96; -- 0x60
|
||||
end if;
|
||||
else
|
||||
-- After subtraction
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if DAA_Q(3 downto 0) > 5 then
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
|
||||
end if;
|
||||
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q - 352; -- 0x160
|
||||
end if;
|
||||
end if;
|
||||
F_Out(Flag_X) <= DAA_Q(3);
|
||||
F_Out(Flag_Y) <= DAA_Q(5);
|
||||
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
|
||||
Q_t := std_logic_vector(DAA_Q(7 downto 0));
|
||||
if DAA_Q(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= DAA_Q(7);
|
||||
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
|
||||
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
|
||||
when "1101" | "1110" =>
|
||||
-- RLD, RRD
|
||||
Q_t(7 downto 4) := BusA(7 downto 4);
|
||||
if ALU_Op(0) = '1' then
|
||||
Q_t(3 downto 0) := BusB(7 downto 4);
|
||||
else
|
||||
Q_t(3 downto 0) := BusB(3 downto 0);
|
||||
end if;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
when "1001" =>
|
||||
-- BIT
|
||||
Q_t(7 downto 0) := BusB and BitMask;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
F_Out(Flag_P) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
F_Out(Flag_P) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_H) <= '1';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= '0';
|
||||
F_Out(Flag_Y) <= '0';
|
||||
if IR(2 downto 0) /= "110" then
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
end if;
|
||||
when "1010" =>
|
||||
-- SET
|
||||
Q_t(7 downto 0) := BusB or BitMask;
|
||||
when "1011" =>
|
||||
-- RES
|
||||
Q_t(7 downto 0) := BusB and not BitMask;
|
||||
when "1000" =>
|
||||
-- ROT
|
||||
case IR(5 downto 3) is
|
||||
when "000" => -- RLC
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "010" => -- RL
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "001" => -- RRC
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(0);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "011" => -- RR
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "100" => -- SLA
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '0';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "110" => -- SLL (Undocumented) / SWAP
|
||||
if Mode = 3 then
|
||||
Q_t(7 downto 4) := BusA(3 downto 0);
|
||||
Q_t(3 downto 0) := BusA(7 downto 4);
|
||||
F_Out(Flag_C) <= '0';
|
||||
else
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '1';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
end if;
|
||||
when "101" => -- SRA
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when others => -- SRL
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := '0';
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
end case;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
if ISet = "00" then
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
Q <= Q_t;
|
||||
end process;
|
||||
end;
|
||||
1944
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/cpu/T80_MCode.vhd
Normal file
1944
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/cpu/T80_MCode.vhd
Normal file
File diff suppressed because it is too large
Load Diff
217
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/cpu/T80_Pack.vhd
Normal file
217
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/cpu/T80_Pack.vhd
Normal file
@@ -0,0 +1,217 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0242
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
package T80_Pack is
|
||||
|
||||
component T80
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
IORQ : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DInst : in std_logic_vector(7 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0);
|
||||
MC : out std_logic_vector(2 downto 0);
|
||||
TS : out std_logic_vector(2 downto 0);
|
||||
IntCycle_n : out std_logic;
|
||||
IntE : out std_logic;
|
||||
Stop : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_Reg
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_MCode
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
MCycle : in std_logic_vector(2 downto 0);
|
||||
F : in std_logic_vector(7 downto 0);
|
||||
NMICycle : in std_logic;
|
||||
IntCycle : in std_logic;
|
||||
MCycles : out std_logic_vector(2 downto 0);
|
||||
TStates : out std_logic_vector(2 downto 0);
|
||||
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
|
||||
Inc_PC : out std_logic;
|
||||
Inc_WZ : out std_logic;
|
||||
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
|
||||
Read_To_Reg : out std_logic;
|
||||
Read_To_Acc : out std_logic;
|
||||
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
|
||||
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
|
||||
ALU_Op : out std_logic_vector(3 downto 0);
|
||||
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
|
||||
Save_ALU : out std_logic;
|
||||
PreserveC : out std_logic;
|
||||
Arith16 : out std_logic;
|
||||
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
|
||||
IORQ : out std_logic;
|
||||
Jump : out std_logic;
|
||||
JumpE : out std_logic;
|
||||
JumpXY : out std_logic;
|
||||
Call : out std_logic;
|
||||
RstP : out std_logic;
|
||||
LDZ : out std_logic;
|
||||
LDW : out std_logic;
|
||||
LDSPHL : out std_logic;
|
||||
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
|
||||
ExchangeDH : out std_logic;
|
||||
ExchangeRp : out std_logic;
|
||||
ExchangeAF : out std_logic;
|
||||
ExchangeRS : out std_logic;
|
||||
I_DJNZ : out std_logic;
|
||||
I_CPL : out std_logic;
|
||||
I_CCF : out std_logic;
|
||||
I_SCF : out std_logic;
|
||||
I_RETN : out std_logic;
|
||||
I_BT : out std_logic;
|
||||
I_BC : out std_logic;
|
||||
I_BTR : out std_logic;
|
||||
I_RLD : out std_logic;
|
||||
I_RRD : out std_logic;
|
||||
I_INRC : out std_logic;
|
||||
SetDI : out std_logic;
|
||||
SetEI : out std_logic;
|
||||
IMode : out std_logic_vector(1 downto 0);
|
||||
Halt : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_ALU
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end;
|
||||
105
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/cpu/T80_Reg.vhd
Normal file
105
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/cpu/T80_Reg.vhd
Normal file
@@ -0,0 +1,105 @@
|
||||
--
|
||||
-- T80 Registers, technology independent
|
||||
--
|
||||
-- Version : 0244
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t51/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0242 : Initial release
|
||||
--
|
||||
-- 0244 : Changed to single register file
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_Reg is
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_Reg;
|
||||
|
||||
architecture rtl of T80_Reg is
|
||||
|
||||
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
|
||||
signal RegsH : Register_Image(0 to 7);
|
||||
signal RegsL : Register_Image(0 to 7);
|
||||
|
||||
begin
|
||||
|
||||
process (Clk)
|
||||
begin
|
||||
if Clk'event and Clk = '1' then
|
||||
if CEN = '1' then
|
||||
if WEH = '1' then
|
||||
RegsH(to_integer(unsigned(AddrA))) <= DIH;
|
||||
end if;
|
||||
if WEL = '1' then
|
||||
RegsL(to_integer(unsigned(AddrA))) <= DIL;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DOAH <= RegsH(to_integer(unsigned(AddrA)));
|
||||
DOAL <= RegsL(to_integer(unsigned(AddrA)));
|
||||
DOBH <= RegsH(to_integer(unsigned(AddrB)));
|
||||
DOBL <= RegsL(to_integer(unsigned(AddrB)));
|
||||
DOCH <= RegsH(to_integer(unsigned(AddrC)));
|
||||
DOCL <= RegsL(to_integer(unsigned(AddrC)));
|
||||
|
||||
end;
|
||||
179
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/cpu/T80sed.vhd
Normal file
179
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/cpu/T80sed.vhd
Normal file
@@ -0,0 +1,179 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
|
||||
--
|
||||
-- Z80 compatible microprocessor core, synchronous top level with clock enable
|
||||
-- Different timing than the original z80
|
||||
-- Inputs needs to be synchronous and outputs may glitch
|
||||
--
|
||||
-- Version : 0238
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0235 : First release
|
||||
--
|
||||
-- 0236 : Added T2Write generic
|
||||
--
|
||||
-- 0237 : Fixed T2Write with wait state
|
||||
--
|
||||
-- 0238 : Updated for T80 interface change
|
||||
--
|
||||
-- 0242 : Updated for T80 interface change
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.T80_Pack.all;
|
||||
|
||||
entity T80sed is
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CLKEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
MREQ_n : out std_logic;
|
||||
IORQ_n : out std_logic;
|
||||
RD_n : out std_logic;
|
||||
WR_n : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80sed;
|
||||
|
||||
architecture rtl of T80sed is
|
||||
|
||||
signal IntCycle_n : std_logic;
|
||||
signal NoRead : std_logic;
|
||||
signal Write : std_logic;
|
||||
signal IORQ : std_logic;
|
||||
signal DI_Reg : std_logic_vector(7 downto 0);
|
||||
signal MCycle : std_logic_vector(2 downto 0);
|
||||
signal TState : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
u0 : T80
|
||||
generic map(
|
||||
Mode => 0,
|
||||
IOWait => 1)
|
||||
port map(
|
||||
CEN => CLKEN,
|
||||
M1_n => M1_n,
|
||||
IORQ => IORQ,
|
||||
NoRead => NoRead,
|
||||
Write => Write,
|
||||
RFSH_n => RFSH_n,
|
||||
HALT_n => HALT_n,
|
||||
WAIT_n => Wait_n,
|
||||
INT_n => INT_n,
|
||||
NMI_n => NMI_n,
|
||||
RESET_n => RESET_n,
|
||||
BUSRQ_n => BUSRQ_n,
|
||||
BUSAK_n => BUSAK_n,
|
||||
CLK_n => CLK_n,
|
||||
A => A,
|
||||
DInst => DI,
|
||||
DI => DI_Reg,
|
||||
DO => DO,
|
||||
MC => MCycle,
|
||||
TS => TState,
|
||||
IntCycle_n => IntCycle_n);
|
||||
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
DI_Reg <= "00000000";
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
if CLKEN = '1' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
if MCycle = "001" then
|
||||
if TState = "001" or (TState = "010" and Wait_n = '0') then
|
||||
RD_n <= not IntCycle_n;
|
||||
MREQ_n <= not IntCycle_n;
|
||||
IORQ_n <= IntCycle_n;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
MREQ_n <= '0';
|
||||
end if;
|
||||
else
|
||||
if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
|
||||
RD_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
if ((TState = "001") or (TState = "010")) and Write = '1' then
|
||||
WR_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
end if;
|
||||
if TState = "010" and Wait_n = '1' then
|
||||
DI_Reg <= DI;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
48
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/dac.vhd
Normal file
48
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/dac.vhd
Normal file
@@ -0,0 +1,48 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Delta-Sigma DAC
|
||||
--
|
||||
-- Refer to Xilinx Application Note XAPP154.
|
||||
--
|
||||
-- This DAC requires an external RC low-pass filter:
|
||||
--
|
||||
-- dac_o 0---XXXXX---+---0 analog audio
|
||||
-- 3k3 |
|
||||
-- === 4n7
|
||||
-- |
|
||||
-- GND
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity dac is
|
||||
generic (
|
||||
C_bits : integer := 10
|
||||
);
|
||||
port (
|
||||
clk_i : in std_logic;
|
||||
res_n_i : in std_logic;
|
||||
dac_i : in std_logic_vector(C_bits-1 downto 0);
|
||||
dac_o : out std_logic
|
||||
);
|
||||
end dac;
|
||||
|
||||
architecture rtl of dac is
|
||||
signal sig_in: unsigned(C_bits downto 0);
|
||||
begin
|
||||
seq: process(clk_i, res_n_i)
|
||||
begin
|
||||
if res_n_i = '0' then
|
||||
sig_in <= to_unsigned(2**C_bits, sig_in'length);
|
||||
dac_o <= '0';
|
||||
elsif rising_edge(clk_i) then
|
||||
-- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
|
||||
--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
|
||||
sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
|
||||
dac_o <= sig_in(C_bits);
|
||||
end if;
|
||||
end process seq;
|
||||
end rtl;
|
||||
58
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/dpram.vhd
Normal file
58
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/dpram.vhd
Normal file
@@ -0,0 +1,58 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity dpram is
|
||||
|
||||
generic (
|
||||
addr_width_g : integer := 8;
|
||||
data_width_g : integer := 8
|
||||
);
|
||||
port (
|
||||
clk_a_i : in std_logic;
|
||||
en_a_i : in std_logic;
|
||||
we_i : in std_logic;
|
||||
addr_a_i : in std_logic_vector(addr_width_g-1 downto 0);
|
||||
data_a_i : in std_logic_vector(data_width_g-1 downto 0);
|
||||
data_a_o : out std_logic_vector(data_width_g-1 downto 0);
|
||||
clk_b_i : in std_logic;
|
||||
addr_b_i : in std_logic_vector(addr_width_g-1 downto 0);
|
||||
data_b_o : out std_logic_vector(data_width_g-1 downto 0)
|
||||
);
|
||||
|
||||
end dpram;
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
architecture rtl of dpram is
|
||||
|
||||
type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0);
|
||||
signal ram_q : ram_t;
|
||||
|
||||
begin
|
||||
|
||||
mem_a: process (clk_a_i)
|
||||
begin
|
||||
if rising_edge(clk_a_i) then
|
||||
if we_i = '1' and en_a_i = '1' then
|
||||
ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i;
|
||||
data_a_o <= data_a_i;
|
||||
else
|
||||
data_a_o <= ram_q(to_integer(unsigned(addr_a_i)));
|
||||
end if;
|
||||
end if;
|
||||
end process mem_a;
|
||||
|
||||
mem_b: process (clk_b_i)
|
||||
begin
|
||||
if rising_edge(clk_b_i) then
|
||||
data_b_o <= ram_q(to_integer(unsigned(addr_b_i)));
|
||||
end if;
|
||||
end process mem_b;
|
||||
|
||||
end rtl;
|
||||
454
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/hq2x.sv
Normal file
454
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/hq2x.sv
Normal file
@@ -0,0 +1,454 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2012-2013 Ludvig Strigeus
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
|
||||
`define BITS_TO_FIT(N) ( \
|
||||
N <= 2 ? 0 : \
|
||||
N <= 4 ? 1 : \
|
||||
N <= 8 ? 2 : \
|
||||
N <= 16 ? 3 : \
|
||||
N <= 32 ? 4 : \
|
||||
N <= 64 ? 5 : \
|
||||
N <= 128 ? 6 : \
|
||||
N <= 256 ? 7 : \
|
||||
N <= 512 ? 8 : \
|
||||
N <=1024 ? 9 : 10 )
|
||||
|
||||
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input [AWIDTH:0] rdaddr,
|
||||
input rdbuf,
|
||||
output[DWIDTH:0] q,
|
||||
|
||||
input [AWIDTH:0] wraddr,
|
||||
input wrbuf,
|
||||
input [DWIDTH:0] data,
|
||||
input wren
|
||||
);
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
wire [DWIDTH:0] out[2];
|
||||
assign q = out[rdbuf];
|
||||
|
||||
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
|
||||
endmodule
|
||||
|
||||
|
||||
module hq2x_out #(parameter LENGTH, parameter DWIDTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input [AWIDTH:0] rdaddr,
|
||||
input [1:0] rdbuf,
|
||||
output[DWIDTH:0] q,
|
||||
|
||||
input [AWIDTH:0] wraddr,
|
||||
input [1:0] wrbuf,
|
||||
input [DWIDTH:0] data,
|
||||
input wren
|
||||
);
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
|
||||
wire [DWIDTH:0] out[4];
|
||||
assign q = out[rdbuf];
|
||||
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
|
||||
endmodule
|
||||
|
||||
|
||||
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
|
||||
(
|
||||
input clock,
|
||||
input [DWIDTH:0] data,
|
||||
input [AWIDTH:0] rdaddress,
|
||||
input [AWIDTH:0] wraddress,
|
||||
input wren,
|
||||
output [DWIDTH:0] q
|
||||
);
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (wraddress),
|
||||
.clock0 (clock),
|
||||
.data_a (data),
|
||||
.wren_a (wren),
|
||||
.address_b (rdaddress),
|
||||
.q_b(q),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.data_b ({(DWIDTH+1){1'b1}}),
|
||||
.eccstatus (),
|
||||
.q_a (),
|
||||
.rden_a (1'b1),
|
||||
.rden_b (1'b1),
|
||||
.wren_b (1'b0));
|
||||
defparam
|
||||
altsyncram_component.address_aclr_b = "NONE",
|
||||
altsyncram_component.address_reg_b = "CLOCK0",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = NUMWORDS,
|
||||
altsyncram_component.numwords_b = NUMWORDS,
|
||||
altsyncram_component.operation_mode = "DUAL_PORT",
|
||||
altsyncram_component.outdata_aclr_b = "NONE",
|
||||
altsyncram_component.outdata_reg_b = "UNREGISTERED",
|
||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
|
||||
altsyncram_component.widthad_a = AWIDTH+1,
|
||||
altsyncram_component.widthad_b = AWIDTH+1,
|
||||
altsyncram_component.width_a = DWIDTH+1,
|
||||
altsyncram_component.width_b = DWIDTH+1,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
endmodule
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module DiffCheck
|
||||
(
|
||||
input [17:0] rgb1,
|
||||
input [17:0] rgb2,
|
||||
output result
|
||||
);
|
||||
|
||||
wire [5:0] r = rgb1[5:1] - rgb2[5:1];
|
||||
wire [5:0] g = rgb1[11:7] - rgb2[11:7];
|
||||
wire [5:0] b = rgb1[17:13] - rgb2[17:13];
|
||||
wire [6:0] t = $signed(r) + $signed(b);
|
||||
wire [6:0] gx = {g[5], g};
|
||||
wire [7:0] y = $signed(t) + $signed(gx);
|
||||
wire [6:0] u = $signed(r) - $signed(b);
|
||||
wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
|
||||
|
||||
// if y is inside (-24..24)
|
||||
wire y_inside = (y < 8'h18 || y >= 8'he8);
|
||||
|
||||
// if u is inside (-4, 4)
|
||||
wire u_inside = (u < 7'h4 || u >= 7'h7c);
|
||||
|
||||
// if v is inside (-6, 6)
|
||||
wire v_inside = (v < 8'h6 || v >= 8'hfA);
|
||||
assign result = !(y_inside && u_inside && v_inside);
|
||||
endmodule
|
||||
|
||||
module InnerBlend
|
||||
(
|
||||
input [8:0] Op,
|
||||
input [5:0] A,
|
||||
input [5:0] B,
|
||||
input [5:0] C,
|
||||
output [5:0] O
|
||||
);
|
||||
|
||||
function [8:0] mul6x3;
|
||||
input [5:0] op1;
|
||||
input [2:0] op2;
|
||||
begin
|
||||
mul6x3 = 9'd0;
|
||||
if(op2[0]) mul6x3 = mul6x3 + op1;
|
||||
if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
|
||||
if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
|
||||
end
|
||||
endfunction
|
||||
|
||||
wire OpOnes = Op[4];
|
||||
wire [8:0] Amul = mul6x3(A, Op[7:5]);
|
||||
wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
|
||||
wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
|
||||
wire [8:0] At = Amul;
|
||||
wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
|
||||
wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
|
||||
wire [9:0] Res = {At, 1'b0} + Bt + Ct;
|
||||
assign O = Op[8] ? A : Res[9:4];
|
||||
endmodule
|
||||
|
||||
module Blend
|
||||
(
|
||||
input [5:0] rule,
|
||||
input disable_hq2x,
|
||||
input [17:0] E,
|
||||
input [17:0] A,
|
||||
input [17:0] B,
|
||||
input [17:0] D,
|
||||
input [17:0] F,
|
||||
input [17:0] H,
|
||||
output [17:0] Result
|
||||
);
|
||||
|
||||
reg [1:0] input_ctrl;
|
||||
reg [8:0] op;
|
||||
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
|
||||
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
|
||||
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
|
||||
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
|
||||
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
|
||||
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
|
||||
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
|
||||
localparam AB = 2'b00;
|
||||
localparam AD = 2'b01;
|
||||
localparam DB = 2'b10;
|
||||
localparam BD = 2'b11;
|
||||
wire is_diff;
|
||||
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
|
||||
|
||||
always @* begin
|
||||
case({!is_diff, rule[5:2]})
|
||||
1,17: {op, input_ctrl} = {BLEND1, AB};
|
||||
2,18: {op, input_ctrl} = {BLEND1, DB};
|
||||
3,19: {op, input_ctrl} = {BLEND1, BD};
|
||||
4,20: {op, input_ctrl} = {BLEND2, DB};
|
||||
5,21: {op, input_ctrl} = {BLEND2, AB};
|
||||
6,22: {op, input_ctrl} = {BLEND2, AD};
|
||||
|
||||
8: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
9: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
10: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
11: {op, input_ctrl} = {BLEND1, AB};
|
||||
12: {op, input_ctrl} = {BLEND1, AB};
|
||||
13: {op, input_ctrl} = {BLEND1, AB};
|
||||
14: {op, input_ctrl} = {BLEND1, DB};
|
||||
15: {op, input_ctrl} = {BLEND1, BD};
|
||||
|
||||
24: {op, input_ctrl} = {BLEND2, DB};
|
||||
25: {op, input_ctrl} = {BLEND5, DB};
|
||||
26: {op, input_ctrl} = {BLEND6, DB};
|
||||
27: {op, input_ctrl} = {BLEND2, DB};
|
||||
28: {op, input_ctrl} = {BLEND4, DB};
|
||||
29: {op, input_ctrl} = {BLEND5, DB};
|
||||
30: {op, input_ctrl} = {BLEND3, BD};
|
||||
31: {op, input_ctrl} = {BLEND3, DB};
|
||||
default: {op, input_ctrl} = 11'bx;
|
||||
endcase
|
||||
|
||||
// Setting op[8] effectively disables HQ2X because blend will always return E.
|
||||
if (disable_hq2x) op[8] = 1;
|
||||
end
|
||||
|
||||
// Generate inputs to the inner blender. Valid combinations.
|
||||
// 00: E A B
|
||||
// 01: E A D
|
||||
// 10: E D B
|
||||
// 11: E B D
|
||||
wire [17:0] Input1 = E;
|
||||
wire [17:0] Input2 = !input_ctrl[1] ? A :
|
||||
!input_ctrl[0] ? D : B;
|
||||
|
||||
wire [17:0] Input3 = !input_ctrl[0] ? B : D;
|
||||
InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]);
|
||||
InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]);
|
||||
InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
|
||||
endmodule
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
input clk,
|
||||
input ce_x4,
|
||||
input [DWIDTH:0] inputpixel,
|
||||
input mono,
|
||||
input disable_hq2x,
|
||||
input reset_frame,
|
||||
input reset_line,
|
||||
input [1:0] read_y,
|
||||
input [AWIDTH+1:0] read_x,
|
||||
output [DWIDTH:0] outpixel
|
||||
);
|
||||
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
localparam DWIDTH = HALF_DEPTH ? 8 : 17;
|
||||
|
||||
wire [5:0] hqTable[256] = '{
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
|
||||
};
|
||||
|
||||
reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
|
||||
reg [17:0] A, B, D, F, G, H;
|
||||
reg [7:0] pattern, nextpatt;
|
||||
reg [1:0] i;
|
||||
reg [7:0] y;
|
||||
|
||||
wire curbuf = y[0];
|
||||
reg prevbuf = 0;
|
||||
wire iobuf = !curbuf;
|
||||
|
||||
wire diff0, diff1;
|
||||
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
|
||||
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
|
||||
|
||||
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
|
||||
|
||||
wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
|
||||
wire [17:0] blend_result;
|
||||
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
|
||||
|
||||
reg Curr2_addr1;
|
||||
reg [AWIDTH:0] Curr2_addr2;
|
||||
wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
|
||||
wire [DWIDTH:0] Curr2tmp;
|
||||
|
||||
reg [AWIDTH:0] wrin_addr2;
|
||||
reg [DWIDTH:0] wrpix;
|
||||
reg wrin_en;
|
||||
|
||||
function [17:0] h2rgb;
|
||||
input [8:0] v;
|
||||
begin
|
||||
h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [8:0] rgb2h;
|
||||
input [17:0] v;
|
||||
begin
|
||||
rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
|
||||
(
|
||||
.clk(clk),
|
||||
|
||||
.rdaddr(Curr2_addr2),
|
||||
.rdbuf(Curr2_addr1),
|
||||
.q(Curr2tmp),
|
||||
|
||||
.wraddr(wrin_addr2),
|
||||
.wrbuf(iobuf),
|
||||
.data(wrpix),
|
||||
.wren(wrin_en)
|
||||
);
|
||||
|
||||
reg [1:0] wrout_addr1;
|
||||
reg [AWIDTH+1:0] wrout_addr2;
|
||||
reg wrout_en;
|
||||
reg [DWIDTH:0] wrdata;
|
||||
|
||||
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
|
||||
(
|
||||
.clk(clk),
|
||||
|
||||
.rdaddr(read_x),
|
||||
.rdbuf(read_y),
|
||||
.q(outpixel),
|
||||
|
||||
.wraddr(wrout_addr2),
|
||||
.wrbuf(wrout_addr1),
|
||||
.data(wrdata),
|
||||
.wren(wrout_en)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [AWIDTH:0] offs;
|
||||
reg old_reset_line;
|
||||
reg old_reset_frame;
|
||||
|
||||
wrout_en <= 0;
|
||||
wrin_en <= 0;
|
||||
|
||||
if(ce_x4) begin
|
||||
|
||||
pattern <= new_pattern;
|
||||
|
||||
if(~&offs) begin
|
||||
if (i == 0) begin
|
||||
Curr2_addr1 <= prevbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 1) begin
|
||||
Prev2 <= Curr2;
|
||||
Curr2_addr1 <= curbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 2) begin
|
||||
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
|
||||
wrpix <= inputpixel;
|
||||
wrin_addr2 <= offs;
|
||||
wrin_en <= 1;
|
||||
end
|
||||
if (i == 3) begin
|
||||
offs <= offs + 1'd1;
|
||||
end
|
||||
|
||||
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
|
||||
else wrdata <= blend_result;
|
||||
|
||||
wrout_addr1 <= {curbuf, i[1]};
|
||||
wrout_addr2 <= {offs, i[1]^i[0]};
|
||||
wrout_en <= 1;
|
||||
end
|
||||
|
||||
if(i==3) begin
|
||||
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
|
||||
{A, G} <= {Prev0, Next0};
|
||||
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
|
||||
{Prev0, Prev1} <= {Prev1, Prev2};
|
||||
{Curr0, Curr1} <= {Curr1, Curr2};
|
||||
{Next0, Next1} <= {Next1, Next2};
|
||||
end else begin
|
||||
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
|
||||
{B, F, H, D} <= {F, H, D, B};
|
||||
end
|
||||
|
||||
i <= i + 1'b1;
|
||||
if(old_reset_line && ~reset_line) begin
|
||||
old_reset_frame <= reset_frame;
|
||||
offs <= 0;
|
||||
i <= 0;
|
||||
y <= y + 1'd1;
|
||||
prevbuf <= curbuf;
|
||||
if(old_reset_frame & ~reset_frame) begin
|
||||
y <= 0;
|
||||
prevbuf <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
old_reset_line <= reset_line;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // Hq2x
|
||||
530
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/mist_io.v
Normal file
530
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/mist_io.v
Normal file
@@ -0,0 +1,530 @@
|
||||
//
|
||||
// mist_io.v
|
||||
//
|
||||
// mist_io for the MiST board
|
||||
// http://code.google.com/p/mist-board/
|
||||
//
|
||||
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2015-2017 Sorgelig
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
//
|
||||
// Use buffer to access SD card. It's time-critical part.
|
||||
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
|
||||
// (Sorgelig)
|
||||
//
|
||||
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
|
||||
// clk_ps2 = clk_sys/(PS2DIV*2)
|
||||
//
|
||||
|
||||
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
|
||||
(
|
||||
|
||||
// parameter STRLEN and the actual length of conf_str have to match
|
||||
input [(8*STRLEN)-1:0] conf_str,
|
||||
|
||||
// Global clock. It should be around 100MHz (higher is better).
|
||||
input clk_sys,
|
||||
|
||||
// Global SPI clock from ARM. 24MHz
|
||||
input SPI_SCK,
|
||||
|
||||
input CONF_DATA0,
|
||||
input SPI_SS2,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
|
||||
output reg [7:0] joystick_0,
|
||||
output reg [7:0] joystick_1,
|
||||
// output reg [31:0] joystick_2,
|
||||
// output reg [31:0] joystick_3,
|
||||
// output reg [31:0] joystick_4,
|
||||
output reg [15:0] joystick_analog_0,
|
||||
output reg [15:0] joystick_analog_1,
|
||||
output [1:0] buttons,
|
||||
output [1:0] switches,
|
||||
output scandoublerD,
|
||||
output ypbpr,
|
||||
|
||||
output reg [31:0] status,
|
||||
|
||||
// SD config
|
||||
input sd_conf,
|
||||
input sd_sdhc,
|
||||
output [1:0] img_mounted, // signaling that new image has been mounted
|
||||
output reg [31:0] img_size, // size of image in bytes
|
||||
|
||||
// SD block level access
|
||||
input [31:0] sd_lba,
|
||||
input [1:0] sd_rd,
|
||||
input [1:0] sd_wr,
|
||||
output reg sd_ack,
|
||||
output reg sd_ack_conf,
|
||||
|
||||
// SD byte level access. Signals for 2-PORT altsyncram.
|
||||
output reg [8:0] sd_buff_addr,
|
||||
output reg [7:0] sd_buff_dout,
|
||||
input [7:0] sd_buff_din,
|
||||
output reg sd_buff_wr,
|
||||
|
||||
// ps2 keyboard emulation
|
||||
output ps2_kbd_clk,
|
||||
output reg ps2_kbd_data,
|
||||
output ps2_mouse_clk,
|
||||
output reg ps2_mouse_data,
|
||||
|
||||
// ps2 alternative interface.
|
||||
|
||||
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
|
||||
output reg [10:0] ps2_key = 0,
|
||||
|
||||
// [24] - toggles with every event
|
||||
output reg [24:0] ps2_mouse = 0,
|
||||
|
||||
// ARM -> FPGA download
|
||||
input ioctl_ce,
|
||||
output reg ioctl_download = 0, // signal indicating an active download
|
||||
output reg [7:0] ioctl_index, // menu index used to upload the file
|
||||
output reg ioctl_wr = 0,
|
||||
output reg [24:0] ioctl_addr,
|
||||
output reg [7:0] ioctl_dout
|
||||
);
|
||||
|
||||
reg [7:0] but_sw;
|
||||
reg [2:0] stick_idx;
|
||||
|
||||
reg [1:0] mount_strobe = 0;
|
||||
assign img_mounted = mount_strobe;
|
||||
|
||||
assign buttons = but_sw[1:0];
|
||||
assign switches = but_sw[3:2];
|
||||
assign scandoublerD = but_sw[4];
|
||||
assign ypbpr = but_sw[5];
|
||||
|
||||
// this variant of user_io is for 8 bit cores (type == a4) only
|
||||
wire [7:0] core_type = 8'ha4;
|
||||
|
||||
// command byte read by the io controller
|
||||
wire drive_sel = sd_rd[1] | sd_wr[1];
|
||||
wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
|
||||
|
||||
reg [7:0] cmd;
|
||||
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
|
||||
reg [9:0] byte_cnt; // counts bytes
|
||||
|
||||
reg spi_do;
|
||||
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
|
||||
|
||||
reg [7:0] spi_data_out;
|
||||
|
||||
// SPI transmitter
|
||||
always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
|
||||
|
||||
reg [7:0] spi_data_in;
|
||||
reg spi_data_ready = 0;
|
||||
|
||||
// SPI receiver
|
||||
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
|
||||
reg [6:0] sbuf;
|
||||
reg [31:0] sd_lba_r;
|
||||
reg drive_sel_r;
|
||||
|
||||
if(CONF_DATA0) begin
|
||||
bit_cnt <= 0;
|
||||
byte_cnt <= 0;
|
||||
spi_data_out <= core_type;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bit_cnt <= bit_cnt + 1'd1;
|
||||
sbuf <= {sbuf[5:0], SPI_DI};
|
||||
|
||||
// finished reading command byte
|
||||
if(bit_cnt == 7) begin
|
||||
if(!byte_cnt) cmd <= {sbuf, SPI_DI};
|
||||
|
||||
spi_data_in <= {sbuf, SPI_DI};
|
||||
spi_data_ready <= ~spi_data_ready;
|
||||
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
|
||||
|
||||
spi_data_out <= 0;
|
||||
case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
|
||||
// reading config string
|
||||
8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
|
||||
|
||||
// reading sd card status
|
||||
8'h16: if(byte_cnt == 0) begin
|
||||
spi_data_out <= sd_cmd;
|
||||
sd_lba_r <= sd_lba;
|
||||
drive_sel_r <= drive_sel;
|
||||
end else if (byte_cnt == 1) begin
|
||||
spi_data_out <= drive_sel_r;
|
||||
end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
|
||||
|
||||
// reading sd card write data
|
||||
8'h18: spi_data_out <= sd_buff_din;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [31:0] ps2_key_raw = 0;
|
||||
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
|
||||
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
|
||||
|
||||
// transfer to clk_sys domain
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_ss1, old_ss2;
|
||||
reg old_ready1, old_ready2;
|
||||
reg [2:0] b_wr;
|
||||
reg got_ps2 = 0;
|
||||
|
||||
old_ss1 <= CONF_DATA0;
|
||||
old_ss2 <= old_ss1;
|
||||
old_ready1 <= spi_data_ready;
|
||||
old_ready2 <= old_ready1;
|
||||
|
||||
sd_buff_wr <= b_wr[0];
|
||||
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
b_wr <= (b_wr<<1);
|
||||
|
||||
if(old_ss2) begin
|
||||
got_ps2 <= 0;
|
||||
sd_ack <= 0;
|
||||
sd_ack_conf <= 0;
|
||||
sd_buff_addr <= 0;
|
||||
if(got_ps2) begin
|
||||
if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24];
|
||||
if(cmd == 5) begin
|
||||
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
|
||||
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
|
||||
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
|
||||
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
|
||||
end
|
||||
end
|
||||
end
|
||||
else
|
||||
if(old_ready2 ^ old_ready1) begin
|
||||
|
||||
if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
|
||||
if(byte_cnt < 2) begin
|
||||
|
||||
if (cmd == 8'h19) sd_ack_conf <= 1;
|
||||
if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
|
||||
mount_strobe <= 0;
|
||||
|
||||
if(cmd == 5) ps2_key_raw <= 0;
|
||||
end else begin
|
||||
|
||||
case(cmd)
|
||||
// buttons and switches
|
||||
8'h01: but_sw <= spi_data_in;
|
||||
8'h02: joystick_0 <= spi_data_in;
|
||||
8'h03: joystick_1 <= spi_data_in;
|
||||
// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// store incoming ps2 mouse bytes
|
||||
8'h04: begin
|
||||
got_ps2 <= 1;
|
||||
case(byte_cnt)
|
||||
2: ps2_mouse[7:0] <= spi_data_in;
|
||||
3: ps2_mouse[15:8] <= spi_data_in;
|
||||
4: ps2_mouse[23:16] <= spi_data_in;
|
||||
endcase
|
||||
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in;
|
||||
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
|
||||
end
|
||||
|
||||
// store incoming ps2 keyboard bytes
|
||||
8'h05: begin
|
||||
got_ps2 <= 1;
|
||||
ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in};
|
||||
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in;
|
||||
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
|
||||
end
|
||||
|
||||
8'h15: status[7:0] <= spi_data_in;
|
||||
|
||||
// send SD config IO -> FPGA
|
||||
// flag that download begins
|
||||
// sd card knows data is config if sd_dout_strobe is asserted
|
||||
// with sd_ack still being inactive (low)
|
||||
8'h19,
|
||||
// send sector IO -> FPGA
|
||||
// flag that download begins
|
||||
8'h17: begin
|
||||
sd_buff_dout <= spi_data_in;
|
||||
b_wr <= 1;
|
||||
end
|
||||
|
||||
// joystick analog
|
||||
8'h1a: begin
|
||||
// first byte is joystick index
|
||||
if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
|
||||
else if(byte_cnt == 3) begin
|
||||
// second byte is x axis
|
||||
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
|
||||
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
|
||||
end else if(byte_cnt == 4) begin
|
||||
// third byte is y axis
|
||||
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
|
||||
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
|
||||
end
|
||||
end
|
||||
|
||||
// notify image selection
|
||||
8'h1c: mount_strobe[spi_data_in[0]] <= 1;
|
||||
|
||||
// send image info
|
||||
8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
|
||||
|
||||
// status, 32bit version
|
||||
8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// PS2 ///////////////////////////////
|
||||
// 8 byte fifos to store ps2 bytes
|
||||
localparam PS2_FIFO_BITS = 3;
|
||||
|
||||
reg clk_ps2;
|
||||
always @(negedge clk_sys) begin
|
||||
integer cnt;
|
||||
cnt <= cnt + 1'd1;
|
||||
if(cnt == PS2DIV) begin
|
||||
clk_ps2 <= ~clk_ps2;
|
||||
cnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// keyboard
|
||||
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_kbd_tx_state;
|
||||
reg [7:0] ps2_kbd_tx_byte;
|
||||
reg ps2_kbd_parity;
|
||||
|
||||
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_kbd_r_inc;
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_clk;
|
||||
old_clk <= clk_ps2;
|
||||
if(~old_clk & clk_ps2) begin
|
||||
ps2_kbd_r_inc <= 0;
|
||||
|
||||
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_kbd_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
|
||||
ps2_kbd_r_inc <= 1;
|
||||
|
||||
// reset parity
|
||||
ps2_kbd_parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
ps2_kbd_tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_kbd_data <= 0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
|
||||
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
|
||||
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
|
||||
if(ps2_kbd_tx_byte[0])
|
||||
ps2_kbd_parity <= !ps2_kbd_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
|
||||
else ps2_kbd_tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// mouse
|
||||
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_mouse_tx_state;
|
||||
reg [7:0] ps2_mouse_tx_byte;
|
||||
reg ps2_mouse_parity;
|
||||
|
||||
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_mouse_r_inc;
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_clk;
|
||||
old_clk <= clk_ps2;
|
||||
if(~old_clk & clk_ps2) begin
|
||||
ps2_mouse_r_inc <= 0;
|
||||
|
||||
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_mouse_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
|
||||
ps2_mouse_r_inc <= 1;
|
||||
|
||||
// reset parity
|
||||
ps2_mouse_parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
ps2_mouse_tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_mouse_data <= 0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
|
||||
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
|
||||
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
|
||||
if(ps2_mouse_tx_byte[0])
|
||||
ps2_mouse_parity <= !ps2_mouse_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
|
||||
else ps2_mouse_tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// DOWNLOADING ///////////////////////////////
|
||||
|
||||
reg [7:0] data_w;
|
||||
reg [24:0] addr_w;
|
||||
reg rclk = 0;
|
||||
|
||||
localparam UIO_FILE_TX = 8'h53;
|
||||
localparam UIO_FILE_TX_DAT = 8'h54;
|
||||
localparam UIO_FILE_INDEX = 8'h55;
|
||||
|
||||
reg rdownload = 0;
|
||||
|
||||
// data_io has its own SPI interface to the io controller
|
||||
always@(posedge SPI_SCK, posedge SPI_SS2) begin
|
||||
reg [6:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
reg [4:0] cnt;
|
||||
reg [24:0] addr;
|
||||
|
||||
if(SPI_SS2) cnt <= 0;
|
||||
else begin
|
||||
// don't shift in last bit. It is evaluated directly
|
||||
// when writing to ram
|
||||
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
|
||||
|
||||
// count 0-7 8-15 8-15 ...
|
||||
if(cnt < 15) cnt <= cnt + 1'd1;
|
||||
else cnt <= 8;
|
||||
|
||||
// finished command byte
|
||||
if(cnt == 7) cmd <= {sbuf, SPI_DI};
|
||||
|
||||
// prepare/end transmission
|
||||
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
|
||||
// prepare
|
||||
if(SPI_DI) begin
|
||||
case(ioctl_index[4:0])
|
||||
1: addr <= 25'h200000; // TRD buffer at 2MB
|
||||
2: addr <= 25'h400000; // tape buffer at 4MB
|
||||
default: addr <= 25'h150000; // boot rom
|
||||
endcase
|
||||
rdownload <= 1;
|
||||
end else begin
|
||||
addr_w <= addr;
|
||||
rdownload <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// command 0x54: UIO_FILE_TX
|
||||
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
|
||||
addr_w <= addr;
|
||||
data_w <= {sbuf, SPI_DI};
|
||||
addr <= addr + 1'd1;
|
||||
rclk <= ~rclk;
|
||||
end
|
||||
|
||||
// expose file (menu) index
|
||||
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
|
||||
end
|
||||
end
|
||||
|
||||
// transfer to ioctl_clk domain.
|
||||
// ioctl_index is set before ioctl_download, so it's stable already
|
||||
always@(posedge clk_sys) begin
|
||||
reg rclkD, rclkD2;
|
||||
|
||||
if(ioctl_ce) begin
|
||||
ioctl_download <= rdownload;
|
||||
|
||||
rclkD <= rclk;
|
||||
rclkD2 <= rclkD;
|
||||
ioctl_wr <= 0;
|
||||
|
||||
if(rclkD != rclkD2) begin
|
||||
ioctl_dout <= data_w;
|
||||
ioctl_addr <= addr_w;
|
||||
ioctl_wr <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
194
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/osd.v
Normal file
194
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/osd.v
Normal file
@@ -0,0 +1,194 @@
|
||||
// A simple OSD implementation. Can be hooked up between a cores
|
||||
// VGA output and the physical VGA pins
|
||||
|
||||
module osd (
|
||||
// OSDs pixel clock, should be synchronous to cores pixel clock to
|
||||
// avoid jitter.
|
||||
input clk_sys,
|
||||
|
||||
// SPI interface
|
||||
input SPI_SCK,
|
||||
input SPI_SS3,
|
||||
input SPI_DI,
|
||||
|
||||
input [1:0] rotate, //[0] - rotate [1] - left or right
|
||||
|
||||
// VGA signals coming from core
|
||||
input [5:0] R_in,
|
||||
input [5:0] G_in,
|
||||
input [5:0] B_in,
|
||||
input HSync,
|
||||
input VSync,
|
||||
|
||||
// VGA signals going to video connector
|
||||
output [5:0] R_out,
|
||||
output [5:0] G_out,
|
||||
output [5:0] B_out
|
||||
);
|
||||
|
||||
parameter OSD_X_OFFSET = 10'd0;
|
||||
parameter OSD_Y_OFFSET = 10'd0;
|
||||
parameter OSD_COLOR = 3'd0;
|
||||
|
||||
localparam OSD_WIDTH = 10'd256;
|
||||
localparam OSD_HEIGHT = 10'd128;
|
||||
|
||||
// *********************************************************************************
|
||||
// spi client
|
||||
// *********************************************************************************
|
||||
|
||||
// this core supports only the display related OSD commands
|
||||
// of the minimig
|
||||
reg osd_enable;
|
||||
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
|
||||
|
||||
// the OSD has its own SPI interface to the io controller
|
||||
always@(posedge SPI_SCK, posedge SPI_SS3) begin
|
||||
reg [4:0] cnt;
|
||||
reg [10:0] bcnt;
|
||||
reg [7:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
|
||||
if(SPI_SS3) begin
|
||||
cnt <= 0;
|
||||
bcnt <= 0;
|
||||
end else begin
|
||||
sbuf <= {sbuf[6:0], SPI_DI};
|
||||
|
||||
// 0:7 is command, rest payload
|
||||
if(cnt < 15) cnt <= cnt + 1'd1;
|
||||
else cnt <= 8;
|
||||
|
||||
if(cnt == 7) begin
|
||||
cmd <= {sbuf[6:0], SPI_DI};
|
||||
|
||||
// lower three command bits are line address
|
||||
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
|
||||
|
||||
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
|
||||
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
|
||||
end
|
||||
|
||||
// command 0x20: OSDCMDWRITE
|
||||
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
|
||||
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
|
||||
bcnt <= bcnt + 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// *********************************************************************************
|
||||
// video timing and sync polarity anaylsis
|
||||
// *********************************************************************************
|
||||
|
||||
// horizontal counter
|
||||
reg [9:0] h_cnt;
|
||||
reg [9:0] hs_low, hs_high;
|
||||
wire hs_pol = hs_high < hs_low;
|
||||
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
|
||||
|
||||
// vertical counter
|
||||
reg [9:0] v_cnt;
|
||||
reg [9:0] vs_low, vs_high;
|
||||
wire vs_pol = vs_high < vs_low;
|
||||
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
|
||||
|
||||
wire doublescan = (dsp_height>350);
|
||||
|
||||
reg ce_pix;
|
||||
always @(negedge clk_sys) begin
|
||||
integer cnt = 0;
|
||||
integer pixsz, pixcnt;
|
||||
reg hs;
|
||||
|
||||
cnt <= cnt + 1;
|
||||
hs <= HSync;
|
||||
|
||||
pixcnt <= pixcnt + 1;
|
||||
if(pixcnt == pixsz) pixcnt <= 0;
|
||||
ce_pix <= !pixcnt;
|
||||
|
||||
if(hs && ~HSync) begin
|
||||
cnt <= 0;
|
||||
pixsz <= (cnt >> 9) - 1;
|
||||
pixcnt <= 0;
|
||||
ce_pix <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
reg hsD, hsD2;
|
||||
reg vsD, vsD2;
|
||||
|
||||
if(ce_pix) begin
|
||||
// bring hsync into local clock domain
|
||||
hsD <= HSync;
|
||||
hsD2 <= hsD;
|
||||
|
||||
// falling edge of HSync
|
||||
if(!hsD && hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_high <= h_cnt;
|
||||
end
|
||||
|
||||
// rising edge of HSync
|
||||
else if(hsD && !hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_low <= h_cnt;
|
||||
v_cnt <= v_cnt + 1'd1;
|
||||
end else begin
|
||||
h_cnt <= h_cnt + 1'd1;
|
||||
end
|
||||
|
||||
vsD <= VSync;
|
||||
vsD2 <= vsD;
|
||||
|
||||
// falling edge of VSync
|
||||
if(!vsD && vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_high <= v_cnt;
|
||||
end
|
||||
|
||||
// rising edge of VSync
|
||||
else if(vsD && !vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_low <= v_cnt;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// area in which OSD is being displayed
|
||||
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
|
||||
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
|
||||
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
|
||||
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
|
||||
wire [9:0] osd_hcnt = h_cnt - h_osd_start;
|
||||
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
|
||||
wire [9:0] osd_hcnt_next = osd_hcnt + 2'd1; // one pixel offset for osd pixel
|
||||
wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2; // two pixel offset for osd byte address register
|
||||
|
||||
wire osd_de = osd_enable &&
|
||||
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
|
||||
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
|
||||
|
||||
reg [10:0] osd_buffer_addr;
|
||||
wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
|
||||
reg osd_pixel;
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
if(ce_pix) begin
|
||||
osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
|
||||
rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
|
||||
(doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} :
|
||||
{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
|
||||
|
||||
osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
|
||||
osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
|
||||
end
|
||||
end
|
||||
|
||||
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
|
||||
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
|
||||
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
|
||||
|
||||
endmodule
|
||||
669
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman.vhd
Normal file
669
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman.vhd
Normal file
@@ -0,0 +1,669 @@
|
||||
--
|
||||
-- A simulation model of Pacman hardware
|
||||
-- Copyright (c) MikeJ - January 2006
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- You are responsible for any legal issues arising from your use of this code.
|
||||
--
|
||||
-- The latest version of this file can be found at: www.fpgaarcade.com
|
||||
--
|
||||
-- Email pacman@fpgaarcade.com
|
||||
--
|
||||
-- Revision list
|
||||
--
|
||||
-- version 005 Papilio release by Jack Gassett
|
||||
-- version 004 spartan3e release
|
||||
-- version 003 Jan 2006 release, general tidy up
|
||||
-- version 002 optional vga scan doubler
|
||||
-- version 001 initial release
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity pacmant is
|
||||
port (
|
||||
O_VIDEO_R : out std_logic_vector(2 downto 0);
|
||||
O_VIDEO_G : out std_logic_vector(2 downto 0);
|
||||
O_VIDEO_B : out std_logic_vector(1 downto 0);
|
||||
O_HSYNC : out std_logic;
|
||||
O_VSYNC : out std_logic;
|
||||
O_HBLANK : out std_logic;
|
||||
O_VBLANK : out std_logic;
|
||||
--
|
||||
O_AUDIO : out std_logic_vector(7 downto 0);
|
||||
--
|
||||
I_JOYSTICK_A : in std_logic_vector(4 downto 0);
|
||||
I_JOYSTICK_B : in std_logic_vector(4 downto 0);
|
||||
|
||||
I_SW : in std_logic_vector(3 downto 0); -- active high
|
||||
--
|
||||
RESET : in std_logic;
|
||||
CLK : in std_logic;
|
||||
ENA_6 : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of pacmant is
|
||||
|
||||
|
||||
-- timing
|
||||
signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80
|
||||
signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8
|
||||
|
||||
signal do_hsync : boolean;
|
||||
signal hsync : std_logic;
|
||||
signal vsync : std_logic;
|
||||
signal hblank : std_logic;
|
||||
signal vblank : std_logic := '1';
|
||||
|
||||
-- cpu
|
||||
signal cpu_ena : std_logic;
|
||||
signal cpu_m1_l : std_logic;
|
||||
signal cpu_mreq_l : std_logic;
|
||||
signal cpu_iorq_l : std_logic;
|
||||
signal cpu_rd_l : std_logic;
|
||||
signal cpu_rfsh_l : std_logic;
|
||||
signal cpu_wait_l : std_logic;
|
||||
signal cpu_int_l : std_logic;
|
||||
signal cpu_nmi_l : std_logic;
|
||||
signal cpu_busrq_l : std_logic;
|
||||
signal cpu_addr : std_logic_vector(15 downto 0);
|
||||
signal cpu_data_out : std_logic_vector(7 downto 0);
|
||||
signal cpu_data_in : std_logic_vector(7 downto 0);
|
||||
|
||||
signal program_rom_dinl : std_logic_vector(7 downto 0);
|
||||
signal sync_bus_cs_l : std_logic;
|
||||
|
||||
signal control_reg : std_logic_vector(7 downto 0);
|
||||
--
|
||||
signal vram_addr_ab : std_logic_vector(11 downto 0);
|
||||
signal ab : std_logic_vector(11 downto 0);
|
||||
|
||||
signal sync_bus_db : std_logic_vector(7 downto 0);
|
||||
signal sync_bus_r_w_l : std_logic;
|
||||
signal sync_bus_wreq_l : std_logic;
|
||||
signal sync_bus_stb : std_logic;
|
||||
|
||||
signal cpu_vec_reg : std_logic_vector(7 downto 0);
|
||||
signal sync_bus_reg : std_logic_vector(7 downto 0);
|
||||
|
||||
signal vram_l : std_logic;
|
||||
signal rams_data_out : std_logic_vector(7 downto 0);
|
||||
-- more decode
|
||||
signal wr0_l : std_logic;
|
||||
signal wr1_l : std_logic;
|
||||
signal wr2_l : std_logic;
|
||||
signal iodec_out_l : std_logic;
|
||||
signal iodec_wdr_l : std_logic;
|
||||
signal iodec_in0_l : std_logic;
|
||||
signal iodec_in1_l : std_logic;
|
||||
signal iodec_dipsw_l : std_logic;
|
||||
|
||||
-- watchdog
|
||||
signal watchdog_cnt : std_logic_vector(3 downto 0);
|
||||
signal watchdog_reset_l : std_logic;
|
||||
signal freeze : std_logic;
|
||||
|
||||
-- ip registers
|
||||
signal button_in : std_logic_vector(13 downto 0);
|
||||
signal button_debounced : std_logic_vector(13 downto 0);
|
||||
signal in0_reg : std_logic_vector(7 downto 0);
|
||||
signal in1_reg : std_logic_vector(7 downto 0);
|
||||
signal dipsw_reg : std_logic_vector(7 downto 0);
|
||||
signal joystick_reg : std_logic_vector(4 downto 0);
|
||||
signal joystick_reg2 : std_logic_vector(4 downto 0);
|
||||
|
||||
|
||||
begin
|
||||
joystick_reg <= I_JOYSTICK_A;
|
||||
joystick_reg2 <= I_JOYSTICK_B;
|
||||
|
||||
--
|
||||
-- video timing
|
||||
--
|
||||
p_hvcnt : process
|
||||
variable hcarry,vcarry : boolean;
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
if (ena_6 = '1') then
|
||||
hcarry := (hcnt = "111111111");
|
||||
if hcarry then
|
||||
hcnt <= "010000000"; -- 080
|
||||
else
|
||||
hcnt <= hcnt +"1";
|
||||
end if;
|
||||
-- hcnt 8 on circuit is 256H_L
|
||||
vcarry := (vcnt = "111111111");
|
||||
if do_hsync then
|
||||
if vcarry then
|
||||
vcnt <= "011111000"; -- 0F8
|
||||
else
|
||||
vcnt <= vcnt +"1";
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_sync_comb : process(hcnt, vcnt)
|
||||
begin
|
||||
vsync <= not vcnt(8);
|
||||
do_hsync <= (hcnt = "010101111"); -- 0AF
|
||||
end process;
|
||||
|
||||
p_sync : process
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
if (ena_6 = '1') then
|
||||
-- Timing hardware is coded differently to the real hw
|
||||
-- to avoid the use of multiple clocks. Result is identical.
|
||||
|
||||
if (hcnt = "010010111") then -- 097
|
||||
O_HBLANK <= '1';
|
||||
elsif (hcnt = "010001111") then -- 08F
|
||||
hblank <= '1';
|
||||
elsif (hcnt = "011101111") then
|
||||
hblank <= '0'; -- 0EF
|
||||
O_HBLANK <= '0';
|
||||
end if;
|
||||
|
||||
if do_hsync then
|
||||
hsync <= '1';
|
||||
elsif (hcnt = "011001111") then -- 0CF
|
||||
hsync <= '0';
|
||||
end if;
|
||||
|
||||
if do_hsync then
|
||||
if (vcnt = "111101111") then -- 1EF
|
||||
vblank <= '1';
|
||||
elsif (vcnt = "100001111") then -- 10F
|
||||
vblank <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--
|
||||
-- cpu
|
||||
--
|
||||
p_cpu_wait_comb : process(freeze, sync_bus_wreq_l)
|
||||
begin
|
||||
cpu_wait_l <= '1';
|
||||
if (freeze = '1') or (sync_bus_wreq_l = '0') then
|
||||
cpu_wait_l <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_irq_req_watchdog : process
|
||||
variable rising_vblank : boolean;
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
if (ena_6 = '1') then
|
||||
rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF
|
||||
--rising_vblank := do_hsync; -- debug
|
||||
-- interrupt 8c
|
||||
|
||||
if (control_reg(1) = '0') then
|
||||
cpu_int_l <= '1';
|
||||
elsif rising_vblank then -- 1EF
|
||||
cpu_int_l <= '0';
|
||||
end if;
|
||||
|
||||
-- watchdog 8c
|
||||
-- note sync reset
|
||||
if (reset = '1') then
|
||||
watchdog_cnt <= "1111";
|
||||
elsif (iodec_wdr_l = '0') then
|
||||
watchdog_cnt <= "0000";
|
||||
elsif rising_vblank and (freeze = '0') then
|
||||
watchdog_cnt <= watchdog_cnt + "1";
|
||||
end if;
|
||||
|
||||
|
||||
watchdog_reset_l <= '1';
|
||||
if (watchdog_cnt = "1111") then
|
||||
watchdog_reset_l <= '0';
|
||||
end if;
|
||||
|
||||
-- simulation
|
||||
-- pragma translate_off
|
||||
-- synopsys translate_off
|
||||
watchdog_reset_l <= not reset; -- watchdog disable
|
||||
-- synopsys translate_on
|
||||
-- pragma translate_on
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- other cpu signals
|
||||
cpu_busrq_l <= '1';
|
||||
cpu_nmi_l <= '1';
|
||||
|
||||
p_cpu_ena : process(hcnt, ena_6)
|
||||
begin
|
||||
cpu_ena <= '0';
|
||||
if (ena_6 = '1') then
|
||||
cpu_ena <= hcnt(0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
u_cpu : entity work.T80sed
|
||||
port map (
|
||||
RESET_n => watchdog_reset_l,
|
||||
CLK_n => clk,
|
||||
CLKEN => cpu_ena,
|
||||
WAIT_n => cpu_wait_l,
|
||||
INT_n => cpu_int_l,
|
||||
NMI_n => cpu_nmi_l,
|
||||
BUSRQ_n => cpu_busrq_l,
|
||||
M1_n => cpu_m1_l,
|
||||
MREQ_n => cpu_mreq_l,
|
||||
IORQ_n => cpu_iorq_l,
|
||||
RD_n => cpu_rd_l,
|
||||
WR_n => open,
|
||||
RFSH_n => cpu_rfsh_l,
|
||||
HALT_n => open,
|
||||
BUSAK_n => open,
|
||||
A => cpu_addr,
|
||||
DI => cpu_data_in,
|
||||
DO => cpu_data_out
|
||||
);
|
||||
--
|
||||
-- primary addr decode
|
||||
--
|
||||
p_mem_decode_comb : process(cpu_rfsh_l, cpu_rd_l, cpu_mreq_l, cpu_addr)
|
||||
begin
|
||||
-- rom 0x0000 - 0x3FFF
|
||||
-- syncbus 0x4000 - 0x7FFF
|
||||
|
||||
-- 7M
|
||||
-- 7N
|
||||
sync_bus_cs_l <= '1';
|
||||
-- program_rom_cs_l <= '1';
|
||||
|
||||
if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then
|
||||
|
||||
-- if (cpu_addr(14) = '0') and (cpu_rd_l = '0') then
|
||||
-- program_rom_cs_l <= '0';
|
||||
-- end if;
|
||||
|
||||
if (cpu_addr(14) = '1') then
|
||||
sync_bus_cs_l <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
--
|
||||
-- sync bus custom ic
|
||||
--
|
||||
p_sync_bus_reg : process
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
if (ena_6 = '1') then
|
||||
-- register on sync bus module that is used to store interrupt vector
|
||||
if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then
|
||||
cpu_vec_reg <= cpu_data_out;
|
||||
end if;
|
||||
|
||||
-- read holding reg
|
||||
if (hcnt(1 downto 0) = "01") then
|
||||
sync_bus_reg <= cpu_data_in;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_sync_bus_comb : process(cpu_rd_l, sync_bus_cs_l, hcnt)
|
||||
begin
|
||||
-- sync_bus_stb is now an active low clock enable signal
|
||||
sync_bus_stb <= '1';
|
||||
sync_bus_r_w_l <= '1';
|
||||
|
||||
if (sync_bus_cs_l = '0') and (hcnt(1) = '0') then
|
||||
if (cpu_rd_l = '1') then
|
||||
sync_bus_r_w_l <= '0';
|
||||
end if;
|
||||
sync_bus_stb <= '0';
|
||||
end if;
|
||||
|
||||
sync_bus_wreq_l <= '1';
|
||||
if (sync_bus_cs_l = '0') and (hcnt(1) = '1') and (cpu_rd_l = '0') then
|
||||
sync_bus_wreq_l <= '0';
|
||||
end if;
|
||||
end process;
|
||||
--
|
||||
-- vram addr custom ic
|
||||
--
|
||||
u_vram_addr : entity work.PACMAN_VRAM_ADDR
|
||||
port map (
|
||||
AB => vram_addr_ab,
|
||||
H256_L => hcnt(8),
|
||||
H128 => hcnt(7),
|
||||
H64 => hcnt(6),
|
||||
H32 => hcnt(5),
|
||||
H16 => hcnt(4),
|
||||
H8 => hcnt(3),
|
||||
H4 => hcnt(2),
|
||||
H2 => hcnt(1),
|
||||
H1 => hcnt(0),
|
||||
V128 => vcnt(7),
|
||||
V64 => vcnt(6),
|
||||
V32 => vcnt(5),
|
||||
V16 => vcnt(4),
|
||||
V8 => vcnt(3),
|
||||
V4 => vcnt(2),
|
||||
V2 => vcnt(1),
|
||||
V1 => vcnt(0),
|
||||
FLIP => '0'--control_reg(3)
|
||||
);
|
||||
|
||||
p_ab_mux_comb : process(hcnt, cpu_addr, vram_addr_ab)
|
||||
begin
|
||||
--When 2H is low, the CPU controls the bus.
|
||||
if (hcnt(1) = '0') then
|
||||
ab <= cpu_addr(11 downto 0);
|
||||
else
|
||||
ab <= vram_addr_ab;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_vram_comb : process(hcnt, cpu_addr, sync_bus_stb)
|
||||
variable a,b : std_logic;
|
||||
begin
|
||||
|
||||
a := not (cpu_addr(12) or sync_bus_stb);
|
||||
b := hcnt(1) and hcnt(0);
|
||||
vram_l <= not (a or b);
|
||||
end process;
|
||||
|
||||
p_io_decode_comb : process(sync_bus_r_w_l, sync_bus_stb, ab, cpu_addr)
|
||||
variable sel : std_logic_vector(2 downto 0);
|
||||
variable dec : std_logic_vector(7 downto 0);
|
||||
variable selb : std_logic_vector(1 downto 0);
|
||||
variable decb : std_logic_vector(3 downto 0);
|
||||
begin
|
||||
-- WRITE
|
||||
|
||||
-- out_l 0x5000 - 0x503F control space
|
||||
|
||||
-- 0x5040 - unused
|
||||
-- 0x5050 - unused
|
||||
-- 0x5060 - 0x506F sprite
|
||||
|
||||
-- wr0_l 0x5080 - 0x508F sound 010100 00 10 000000
|
||||
-- wr1_l 0x5090 - 0x509F sound
|
||||
-- wr2_l 0x50A0 - 0x50AF sprite 010100 00 10 100000
|
||||
-- wdr_l 0x50C0 - 0x50FF watchdog reset
|
||||
|
||||
-- READ
|
||||
|
||||
-- in0_l 0x5000 - 0x503F in port 0
|
||||
-- in1_l 0x5040 - 0x507F in port 1
|
||||
-- dipsw_l 0x5080 - 0x50BF dip switches
|
||||
|
||||
-- 7J
|
||||
dec := "11111111";
|
||||
sel := sync_bus_r_w_l & ab(7) & ab(6);
|
||||
if (cpu_addr(12) = '1') and ( sync_bus_stb = '0') then
|
||||
case sel is-- #
|
||||
when "000" => dec := "11111110";--
|
||||
when "001" => dec := "11111101";
|
||||
when "010" => dec := "11111011";--
|
||||
when "011" => dec := "11110111";
|
||||
when "100" => dec := "11101111";
|
||||
when "101" => dec := "11011111";
|
||||
when "110" => dec := "10111111";
|
||||
when "111" => dec := "01111111";
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
iodec_out_l <= dec(0);
|
||||
iodec_wdr_l <= dec(3);
|
||||
iodec_in0_l <= dec(4);
|
||||
iodec_in1_l <= dec(5);
|
||||
iodec_dipsw_l <= dec(6);
|
||||
|
||||
-- 7M
|
||||
decb := "1111";
|
||||
selb := ab(5) & ab(4);
|
||||
if (dec(2) = '0') then
|
||||
case selb is
|
||||
when "00" => decb := "1110";
|
||||
when "01" => decb := "1101";
|
||||
when "10" => decb := "1011";
|
||||
when "11" => decb := "0111";
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
wr0_l <= decb(0);--101000 00 100000 1010000 10 000000
|
||||
wr1_l <= decb(1);
|
||||
wr2_l <= decb(2);
|
||||
end process;
|
||||
|
||||
p_control_reg : process
|
||||
variable ena : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
-- 8 bit addressable latch 7K
|
||||
-- (made into register)
|
||||
|
||||
-- 0 not used
|
||||
-- 1 interrupt ena
|
||||
-- 2 not used
|
||||
-- 3 flip
|
||||
-- 4 1 player start lamp
|
||||
-- 5 2 player start lamp
|
||||
-- 6 coin lockout
|
||||
-- 7 coin counter
|
||||
|
||||
wait until rising_edge(clk);
|
||||
if (ena_6 = '1') then
|
||||
ena := "00000000";
|
||||
if (iodec_out_l = '0') then
|
||||
case ab(2 downto 0) is
|
||||
when "000" => ena := "00000001";
|
||||
when "001" => ena := "00000010";
|
||||
when "010" => ena := "00000100";
|
||||
when "011" => ena := "00001000";
|
||||
when "100" => ena := "00010000";
|
||||
when "101" => ena := "00100000";
|
||||
when "110" => ena := "01000000";
|
||||
when "111" => ena := "10000000";
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
if (watchdog_reset_l = '0') then
|
||||
control_reg <= (others => '0');
|
||||
else
|
||||
for i in 0 to 7 loop
|
||||
if (ena(i) = '1') then
|
||||
control_reg(i) <= cpu_data_out(0);
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_db_mux_comb : process(hcnt, cpu_data_out, rams_data_out)
|
||||
begin
|
||||
-- simplified data source for video subsystem
|
||||
-- only cpu or ram are sources of interest
|
||||
if (hcnt(1) = '0') then
|
||||
sync_bus_db <= cpu_data_out;
|
||||
else
|
||||
sync_bus_db <= rams_data_out;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_cpu_data_in_mux_comb : process(cpu_addr, cpu_iorq_l, cpu_m1_l, sync_bus_wreq_l,
|
||||
iodec_in0_l, iodec_in1_l, iodec_dipsw_l, cpu_vec_reg, sync_bus_reg, program_rom_dinl,
|
||||
rams_data_out, in0_reg, in1_reg, dipsw_reg)
|
||||
begin
|
||||
-- simplifed again
|
||||
if (cpu_iorq_l = '0') and (cpu_m1_l = '0') then
|
||||
cpu_data_in <= cpu_vec_reg;
|
||||
elsif (sync_bus_wreq_l = '0') then
|
||||
cpu_data_in <= sync_bus_reg;
|
||||
else
|
||||
if (cpu_addr(15 downto 14) = "00") then -- ROM at 0000 - 3fff
|
||||
cpu_data_in <= program_rom_dinl;
|
||||
elsif (cpu_addr(15 downto 13) = "100") then -- ROM at 8000 - 9fff
|
||||
cpu_data_in <= X"00";
|
||||
else
|
||||
cpu_data_in <= rams_data_out;
|
||||
if (iodec_in0_l = '0') then cpu_data_in <= in0_reg; end if;
|
||||
if (iodec_in1_l = '0') then cpu_data_in <= in1_reg; end if;
|
||||
if (iodec_dipsw_l = '0') then cpu_data_in <= dipsw_reg; end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
u_rams : work.dpram generic map (12,8)
|
||||
port map
|
||||
(
|
||||
clk_a_i => clk,
|
||||
en_a_i => ena_6,
|
||||
we_i => not sync_bus_r_w_l and not vram_l,
|
||||
addr_a_i => ab(11 downto 0),
|
||||
data_a_i => cpu_data_out, -- cpu only source of ram data
|
||||
|
||||
clk_b_i => clk,
|
||||
addr_b_i => ab(11 downto 0),
|
||||
data_b_o => rams_data_out
|
||||
);
|
||||
|
||||
-- example of internal program rom, if you have a big enough device
|
||||
u_program_rom : entity work.ROM_PGM_0
|
||||
port map (
|
||||
CLK => clk,
|
||||
ADDR => cpu_addr(13 downto 0),
|
||||
DATA => program_rom_dinl
|
||||
);
|
||||
|
||||
--
|
||||
-- video subsystem
|
||||
--
|
||||
u_video : entity work.PACMAN_VIDEO
|
||||
port map (
|
||||
I_HCNT => hcnt,
|
||||
I_VCNT => vcnt,
|
||||
--
|
||||
I_AB => ab,
|
||||
I_DB => sync_bus_db,
|
||||
--
|
||||
I_HBLANK => hblank,
|
||||
I_VBLANK => vblank,
|
||||
I_FLIP => '0',--control_reg(3),
|
||||
I_WR2_L => wr2_l,
|
||||
--
|
||||
O_RED => O_VIDEO_R,
|
||||
O_GREEN => O_VIDEO_G,
|
||||
O_BLUE => O_VIDEO_B,
|
||||
--
|
||||
ENA_6 => ena_6,
|
||||
CLK => clk
|
||||
);
|
||||
|
||||
O_HSYNC <= hSync;
|
||||
O_VSYNC <= vSync;
|
||||
|
||||
--O_HBLANK <= hblank;
|
||||
O_VBLANK <= vblank;
|
||||
|
||||
--
|
||||
--
|
||||
-- audio subsystem
|
||||
--
|
||||
u_audio : entity work.PACMAN_AUDIO
|
||||
port map (
|
||||
I_HCNT => hcnt,
|
||||
--
|
||||
I_AB => ab,
|
||||
I_DB => sync_bus_db,
|
||||
--
|
||||
I_WR1_L => wr1_l,
|
||||
I_WR0_L => wr0_l,
|
||||
I_SOUND_ON => '1',--control_reg(1),
|
||||
--
|
||||
O_AUDIO => O_AUDIO,
|
||||
ENA_6 => ena_6,
|
||||
CLK => clk
|
||||
);
|
||||
|
||||
button_in(8 downto 5) <= I_SW(3 downto 0);
|
||||
button_in(4 downto 0) <= joystick_reg(4 downto 0);
|
||||
button_in(13 downto 9) <= joystick_reg2(4 downto 0);
|
||||
|
||||
button_debounced <= button_in;
|
||||
|
||||
--button_debounced Arcade MegaWing Location
|
||||
-- 8 RIGHT PushButton
|
||||
-- 7 DOWN PushButton
|
||||
-- 6 UP PushButton
|
||||
-- 5 LEFT PushButton
|
||||
-- 4 Fire Joystick
|
||||
-- 3 RIGHT Joystick
|
||||
-- 2 LEFT Joystick
|
||||
-- 1 DOWN Joystick
|
||||
-- 0 UP Joystick
|
||||
|
||||
p_input_registers : process
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
if (ena_6 = '1') then
|
||||
-- on is low
|
||||
in0_reg(7) <= not button_debounced(6); -- credit SERVICE
|
||||
in0_reg(6) <= '1'; -- coin2
|
||||
in0_reg(5) <= not button_debounced(7); -- coin1
|
||||
in0_reg(4) <= '1'; -- test_l dipswitch (rack advance) CHEAT
|
||||
in0_reg(3) <= button_debounced(1); -- p1 down
|
||||
in0_reg(2) <= button_debounced(3); -- p1 right
|
||||
in0_reg(1) <= button_debounced(2); -- p1 left
|
||||
in0_reg(0) <= button_debounced(0); -- p1 up
|
||||
|
||||
in1_reg(7) <= '1'; -- UNUSED
|
||||
in1_reg(6) <= not button_debounced(8); -- start2
|
||||
in1_reg(5) <= not button_debounced(5); -- start1
|
||||
in1_reg(4) <= button_debounced(13); -- test and fire
|
||||
in1_reg(3) <= button_debounced(10); -- p2 down
|
||||
in1_reg(2) <= button_debounced(12); -- p2 right
|
||||
in1_reg(1) <= button_debounced(11); -- p2 left
|
||||
in1_reg(0) <= button_debounced(9); -- p2 up
|
||||
|
||||
-- on is low
|
||||
freeze <= '0';
|
||||
dipsw_reg(7) <= '1'; -- character set ?
|
||||
dipsw_reg(6) <= '1'; -- difficulty ?
|
||||
dipsw_reg(5 downto 4) <= "00"; -- bonus pacman at 10K
|
||||
dipsw_reg(3 downto 2) <= "11"; -- pacman (3)
|
||||
dipsw_reg(1 downto 0) <= "01"; -- cost (1 coin, 1 play)
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end RTL;
|
||||
209
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman_audio.vhd
Normal file
209
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman_audio.vhd
Normal file
@@ -0,0 +1,209 @@
|
||||
--
|
||||
-- A simulation model of Pacman hardware
|
||||
-- Copyright (c) MikeJ - January 2006
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- You are responsible for any legal issues arising from your use of this code.
|
||||
--
|
||||
-- The latest version of this file can be found at: www.fpgaarcade.com
|
||||
--
|
||||
-- Email pacman@fpgaarcade.com
|
||||
--
|
||||
-- Revision list
|
||||
--
|
||||
-- version 003 Jan 2006 release, general tidy up
|
||||
-- version 002 added volume multiplier
|
||||
-- version 001 initial release
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library UNISIM;
|
||||
|
||||
entity PACMAN_AUDIO is
|
||||
port (
|
||||
I_HCNT : in std_logic_vector(8 downto 0);
|
||||
--
|
||||
I_AB : in std_logic_vector(11 downto 0);
|
||||
I_DB : in std_logic_vector( 7 downto 0);
|
||||
--
|
||||
I_WR1_L : in std_logic;
|
||||
I_WR0_L : in std_logic;
|
||||
I_SOUND_ON : in std_logic;
|
||||
--
|
||||
O_AUDIO : out std_logic_vector(7 downto 0);
|
||||
ENA_6 : in std_logic;
|
||||
CLK : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of PACMAN_AUDIO is
|
||||
|
||||
signal addr : std_logic_vector(3 downto 0);
|
||||
signal data : std_logic_vector(3 downto 0);
|
||||
signal vol_ram_dout : std_logic_vector(3 downto 0);
|
||||
signal frq_ram_dout : std_logic_vector(3 downto 0);
|
||||
|
||||
signal sum : std_logic_vector(5 downto 0);
|
||||
signal accum_reg : std_logic_vector(5 downto 0);
|
||||
signal rom3m_n : std_logic_vector(15 downto 0);
|
||||
signal rom3m_w : std_logic_vector(3 downto 0);
|
||||
signal rom3m : std_logic_vector(3 downto 0);
|
||||
|
||||
signal rom1m_addr : std_logic_vector(7 downto 0);
|
||||
signal rom1m_data : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg)
|
||||
begin
|
||||
if (I_HCNT(1) = '0') then -- 2h,
|
||||
addr <= I_AB(3 downto 0);
|
||||
data <= I_DB(3 downto 0); -- removed invert
|
||||
else
|
||||
addr <= I_HCNT(5 downto 2);
|
||||
data <= accum_reg(4 downto 1);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
vol_ram : work.dpram generic map (4,4)
|
||||
port map
|
||||
(
|
||||
clk_a_i => CLK,
|
||||
en_a_i => ENA_6,
|
||||
we_i => not I_WR1_L,
|
||||
addr_a_i => addr(3 downto 0),
|
||||
data_a_i => data,
|
||||
|
||||
clk_b_i => CLK,
|
||||
addr_b_i => addr(3 downto 0),
|
||||
data_b_o => vol_ram_dout
|
||||
);
|
||||
|
||||
frq_ram : work.dpram generic map (4,4)
|
||||
port map
|
||||
(
|
||||
clk_a_i => CLK,
|
||||
en_a_i => ENA_6,
|
||||
we_i => rom3m(1),
|
||||
addr_a_i => addr(3 downto 0),
|
||||
data_a_i => data,
|
||||
|
||||
clk_b_i => CLK,
|
||||
addr_b_i => addr(3 downto 0),
|
||||
data_b_o => frq_ram_dout
|
||||
);
|
||||
|
||||
p_control_rom_comb : process(I_HCNT)
|
||||
begin
|
||||
rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign
|
||||
case I_HCNT(3 downto 0) is
|
||||
when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0";
|
||||
when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2";
|
||||
when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0";
|
||||
when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0";
|
||||
when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0";
|
||||
when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2";
|
||||
when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0";
|
||||
when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0";
|
||||
when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0";
|
||||
when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2";
|
||||
when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0";
|
||||
when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0";
|
||||
when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0";
|
||||
when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2";
|
||||
when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0";
|
||||
when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0";
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w)
|
||||
begin
|
||||
rom3m <= rom3m_w;
|
||||
if (I_WR0_L = '1') then
|
||||
case I_HCNT(5 downto 4) is
|
||||
when "00" => rom3m <= rom3m_n( 3 downto 0);
|
||||
when "01" => rom3m <= rom3m_n( 7 downto 4);
|
||||
when "10" => rom3m <= rom3m_n(11 downto 8);
|
||||
when "11" => rom3m <= rom3m_n(15 downto 12);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg)
|
||||
begin
|
||||
-- 1K 4 bit adder
|
||||
sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5));
|
||||
end process;
|
||||
|
||||
p_accum_reg : process
|
||||
begin
|
||||
-- 1L
|
||||
wait until rising_edge(CLK);
|
||||
if (ENA_6 = '1') then
|
||||
if (rom3m(3) = '1') then -- clear
|
||||
accum_reg <= "000000";
|
||||
elsif (rom3m(0) = '1') then -- rising edge clk
|
||||
accum_reg <= sum(5 downto 1) & accum_reg(4);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout)
|
||||
begin
|
||||
rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0);
|
||||
rom1m_addr(4 downto 0) <= accum_reg(4 downto 0);
|
||||
|
||||
end process;
|
||||
|
||||
audio_rom_1m : entity work.PROM1_DST
|
||||
port map(
|
||||
CLK => CLK,
|
||||
ADDR => rom1m_addr,
|
||||
DATA => rom1m_data
|
||||
);
|
||||
|
||||
p_original_output_reg : process
|
||||
begin
|
||||
-- 2m used to use async clear
|
||||
wait until rising_edge(CLK);
|
||||
if (ENA_6 = '1') then
|
||||
if (I_SOUND_ON = '0') then
|
||||
O_AUDIO <= "00000000";
|
||||
elsif (rom3m(2) = '1') then
|
||||
O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture RTL;
|
||||
360
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman_video.vhd
Normal file
360
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman_video.vhd
Normal file
@@ -0,0 +1,360 @@
|
||||
--
|
||||
-- A simulation model of Pacman hardware
|
||||
-- Copyright (c) MikeJ - January 2006
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- You are responsible for any legal issues arising from your use of this code.
|
||||
--
|
||||
-- The latest version of this file can be found at: www.fpgaarcade.com
|
||||
--
|
||||
-- Email pacman@fpgaarcade.com
|
||||
--
|
||||
-- Revision list
|
||||
--
|
||||
-- version 003 Jan 2006 release, general tidy up
|
||||
-- version 001 initial release
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library UNISIM;
|
||||
|
||||
entity PACMAN_VIDEO is
|
||||
port (
|
||||
I_HCNT : in std_logic_vector(8 downto 0);
|
||||
I_VCNT : in std_logic_vector(8 downto 0);
|
||||
--
|
||||
I_AB : in std_logic_vector(11 downto 0);
|
||||
I_DB : in std_logic_vector( 7 downto 0);
|
||||
--
|
||||
I_HBLANK : in std_logic;
|
||||
I_VBLANK : in std_logic;
|
||||
I_FLIP : in std_logic;
|
||||
I_WR2_L : in std_logic;
|
||||
--
|
||||
O_RED : out std_logic_vector(2 downto 0);
|
||||
O_GREEN : out std_logic_vector(2 downto 0);
|
||||
O_BLUE : out std_logic_vector(1 downto 0);
|
||||
ENA_6 : in std_logic;
|
||||
CLK : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of PACMAN_VIDEO is
|
||||
|
||||
signal sprite_xy_ram_temp : std_logic_vector(7 downto 0);
|
||||
signal dr : std_logic_vector(7 downto 0);
|
||||
|
||||
signal char_reg : std_logic_vector(7 downto 0);
|
||||
signal char_sum_reg : std_logic_vector(3 downto 0);
|
||||
signal char_match_reg : std_logic;
|
||||
signal char_hblank_reg : std_logic;
|
||||
signal char_hblank_reg_t1 : std_logic;
|
||||
signal db_reg : std_logic_vector(7 downto 0);
|
||||
|
||||
signal xflip : std_logic;
|
||||
signal yflip : std_logic;
|
||||
signal obj_on : std_logic;
|
||||
|
||||
signal ca : std_logic_vector(12 downto 0);
|
||||
signal char_rom_5ef_dout : std_logic_vector(7 downto 0);
|
||||
|
||||
signal shift_regl : std_logic_vector(3 downto 0);
|
||||
signal shift_regu : std_logic_vector(3 downto 0);
|
||||
signal shift_op : std_logic_vector(1 downto 0);
|
||||
signal shift_sel : std_logic_vector(1 downto 0);
|
||||
|
||||
signal vout_obj_on : std_logic;
|
||||
signal vout_yflip : std_logic;
|
||||
signal vout_hblank : std_logic;
|
||||
signal vout_db : std_logic_vector(4 downto 0);
|
||||
|
||||
signal cntr_ld : std_logic;
|
||||
signal ra : std_logic_vector(7 downto 0);
|
||||
signal sprite_ram_ip : std_logic_vector(3 downto 0);
|
||||
signal sprite_ram_op : std_logic_vector(3 downto 0);
|
||||
signal sprite_ram_addr : std_logic_vector(7 downto 0);
|
||||
signal sprite_ram_addr_t1 : std_logic_vector(7 downto 0);
|
||||
signal vout_obj_on_t1 : std_logic;
|
||||
signal col_rom_addr : std_logic_vector(7 downto 0);
|
||||
|
||||
signal lut_4a : std_logic_vector(7 downto 0);
|
||||
signal lut_4a_t1 : std_logic_vector(7 downto 0);
|
||||
signal vout_hblank_t1 : std_logic;
|
||||
signal sprite_ram_reg : std_logic_vector(4 downto 0);
|
||||
|
||||
signal video_out : std_logic_vector(7 downto 0);
|
||||
signal video_op_sel : std_logic;
|
||||
signal final_col : std_logic_vector(4 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- ram enable is low when HBLANK_L is 0 (for sprite access) or
|
||||
-- 2H is low (for cpu writes)
|
||||
-- we can simplify this
|
||||
dr <= not sprite_xy_ram_temp when I_HBLANK = '1' else "11111111"; -- pull ups on board
|
||||
|
||||
sprite_xy_ram : work.dpram generic map (4,8)
|
||||
port map
|
||||
(
|
||||
clk_a_i => CLK,
|
||||
en_a_i => ENA_6,
|
||||
we_i => not I_WR2_L,
|
||||
addr_a_i => I_AB(3 downto 0),
|
||||
data_a_i => I_DB,
|
||||
|
||||
clk_b_i => CLK,
|
||||
addr_b_i => I_AB(3 downto 0),
|
||||
data_b_o => sprite_xy_ram_temp
|
||||
);
|
||||
|
||||
p_char_regs : process
|
||||
variable inc : std_logic;
|
||||
variable sum : std_logic_vector(8 downto 0);
|
||||
variable match : std_logic;
|
||||
begin
|
||||
wait until rising_edge (CLK);
|
||||
if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h
|
||||
inc := (not I_HBLANK);
|
||||
|
||||
-- 1f, 2f
|
||||
sum := (I_VCNT(7 downto 0) & '1') + (dr & inc);
|
||||
|
||||
-- 3e
|
||||
match := '0';
|
||||
|
||||
if (sum(8 downto 5) = "1111") then
|
||||
match := '1';
|
||||
end if;
|
||||
|
||||
-- 1h
|
||||
char_sum_reg <= sum(4 downto 1);
|
||||
char_match_reg <= match;
|
||||
char_hblank_reg <= I_HBLANK;
|
||||
|
||||
-- 4d
|
||||
db_reg <= I_DB; -- character reg
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_flip_comb : process(char_hblank_reg, I_FLIP, db_reg)
|
||||
begin
|
||||
if (char_hblank_reg = '0') then
|
||||
xflip <= I_FLIP;
|
||||
yflip <= I_FLIP;
|
||||
else
|
||||
xflip <= db_reg(1);
|
||||
yflip <= db_reg(0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_char_addr_comb : process(db_reg, I_HCNT,
|
||||
char_match_reg, char_sum_reg, char_hblank_reg,
|
||||
xflip, yflip)
|
||||
begin
|
||||
-- 2h, 4e
|
||||
obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l
|
||||
|
||||
ca(12) <= char_hblank_reg;
|
||||
ca(11 downto 6) <= db_reg(7 downto 2);
|
||||
|
||||
if (char_hblank_reg = '0') then
|
||||
ca(5) <= db_reg(1);
|
||||
ca(4) <= db_reg(0);
|
||||
else
|
||||
ca(5) <= char_sum_reg(3) xor xflip;
|
||||
ca(4) <= I_HCNT(3);
|
||||
end if;
|
||||
|
||||
ca(3) <= I_HCNT(2) xor yflip;
|
||||
ca(2) <= char_sum_reg(2) xor xflip;
|
||||
ca(1) <= char_sum_reg(1) xor xflip;
|
||||
ca(0) <= char_sum_reg(0) xor xflip;
|
||||
end process;
|
||||
|
||||
-- char roms
|
||||
char_rom_5ef : entity work.GFX1
|
||||
port map (
|
||||
CLK => CLK,
|
||||
ADDR => ca,
|
||||
DATA => char_rom_5ef_dout
|
||||
);
|
||||
|
||||
p_char_shift : process
|
||||
begin
|
||||
-- 4 bit shift req
|
||||
wait until rising_edge (CLK);
|
||||
if (ENA_6 = '1') then
|
||||
case shift_sel is
|
||||
when "00" => null;
|
||||
|
||||
when "01" => shift_regu <= '0' & shift_regu(3 downto 1);
|
||||
shift_regl <= '0' & shift_regl(3 downto 1);
|
||||
|
||||
when "10" => shift_regu <= shift_regu(2 downto 0) & '0';
|
||||
shift_regl <= shift_regl(2 downto 0) & '0';
|
||||
|
||||
when "11" => shift_regu <= char_rom_5ef_dout(7 downto 4); -- load
|
||||
shift_regl <= char_rom_5ef_dout(3 downto 0);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_char_shift_comb : process(I_HCNT, vout_yflip, shift_regu, shift_regl)
|
||||
variable ip : std_logic;
|
||||
begin
|
||||
ip := I_HCNT(0) and I_HCNT(1);
|
||||
if (vout_yflip = '0') then
|
||||
|
||||
shift_sel(0) <= ip;
|
||||
shift_sel(1) <= '1';
|
||||
shift_op(0) <= shift_regl(3);
|
||||
shift_op(1) <= shift_regu(3);
|
||||
else
|
||||
|
||||
shift_sel(0) <= '1';
|
||||
shift_sel(1) <= ip;
|
||||
shift_op(0) <= shift_regl(0);
|
||||
shift_op(1) <= shift_regu(0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_video_out_reg : process
|
||||
begin
|
||||
wait until rising_edge (CLK);
|
||||
if (ENA_6 = '1') then
|
||||
if (I_HCNT(2 downto 0) = "111") then
|
||||
vout_obj_on <= obj_on;
|
||||
vout_yflip <= yflip;
|
||||
vout_hblank <= I_HBLANK;
|
||||
vout_db(4 downto 0) <= I_DB(4 downto 0); -- colour reg
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_lut_4a_comb : process(vout_db, shift_op)
|
||||
begin
|
||||
col_rom_addr <= '0' & vout_db(4 downto 0) & shift_op(1 downto 0);
|
||||
end process;
|
||||
|
||||
col_rom_4a : entity work.PROM4_DST
|
||||
port map (
|
||||
CLK => CLK,
|
||||
ADDR => col_rom_addr,
|
||||
DATA => lut_4a
|
||||
);
|
||||
|
||||
cntr_ld <= '1' when (I_HCNT(3 downto 0) = "0111") and (vout_hblank='1' or vout_obj_on='0') else '0';
|
||||
|
||||
p_ra_cnt : process
|
||||
begin
|
||||
wait until rising_edge (CLK);
|
||||
if (ENA_6 = '1') then
|
||||
if (cntr_ld = '1') then
|
||||
ra <= dr;
|
||||
else
|
||||
ra <= ra + "1";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
sprite_ram_addr <= ra;
|
||||
|
||||
u_sprite_ram : work.dpram generic map (8,4)
|
||||
port map
|
||||
(
|
||||
clk_a_i => CLK,
|
||||
en_a_i => ENA_6,
|
||||
we_i => vout_obj_on,
|
||||
addr_a_i => sprite_ram_addr,
|
||||
data_a_i => sprite_ram_ip,
|
||||
|
||||
clk_b_i => CLK,
|
||||
addr_b_i => sprite_ram_addr,
|
||||
data_b_o => sprite_ram_op
|
||||
);
|
||||
|
||||
sprite_ram_reg <= '0' & sprite_ram_op when vout_obj_on_t1 = '1' else "00000";
|
||||
video_op_sel <= '1' when not (sprite_ram_reg = "00000") else '0';
|
||||
|
||||
p_sprite_ram_ip_reg : process
|
||||
begin
|
||||
wait until rising_edge (CLK);
|
||||
if (ENA_6 = '1') then
|
||||
vout_obj_on_t1 <= vout_obj_on;
|
||||
vout_hblank_t1 <= vout_hblank;
|
||||
lut_4a_t1 <= lut_4a;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_sprite_ram_ip_comb : process(vout_hblank_t1, video_op_sel, sprite_ram_reg, lut_4a_t1)
|
||||
begin
|
||||
-- 3a
|
||||
if (vout_hblank_t1 = '0') then
|
||||
sprite_ram_ip <= (others => '0');
|
||||
else
|
||||
if (video_op_sel = '1') then
|
||||
sprite_ram_ip <= sprite_ram_reg(3 downto 0);
|
||||
else
|
||||
sprite_ram_ip <= lut_4a_t1(3 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_video_op_comb : process(vout_hblank, I_VBLANK, video_op_sel, sprite_ram_reg, lut_4a)
|
||||
begin
|
||||
-- 3b
|
||||
if (vout_hblank = '1') or (I_VBLANK = '1') then
|
||||
final_col <= (others => '0');
|
||||
else
|
||||
if (video_op_sel = '1') then
|
||||
final_col <= sprite_ram_reg; -- sprite
|
||||
else
|
||||
final_col <= lut_4a(4 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
col_rom_7f : entity work.PROM7_DST
|
||||
port map (
|
||||
CLK => CLK,
|
||||
ADDR => final_col,
|
||||
DATA => video_out
|
||||
);
|
||||
|
||||
-- assign outputs
|
||||
O_BLUE (1 downto 0) <= video_out(7 downto 6);
|
||||
O_GREEN(2 downto 0) <= video_out(5 downto 3);
|
||||
O_RED (2 downto 0) <= video_out(2 downto 0);
|
||||
|
||||
end architecture;
|
||||
273
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman_vram_addr.vhd
Normal file
273
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman_vram_addr.vhd
Normal file
@@ -0,0 +1,273 @@
|
||||
--
|
||||
-- A simulation model of Pacman hardware
|
||||
-- Copyright (c) MikeJ & CarlW - January 2006
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- You are responsible for any legal issues arising from your use of this code.
|
||||
--
|
||||
-- The latest version of this file can be found at: www.fpgaarcade.com
|
||||
--
|
||||
-- Email pacman@fpgaarcade.com
|
||||
--
|
||||
-- Revision list
|
||||
--
|
||||
-- version 003 Jan 2006 release, general tidy up
|
||||
-- version 001 initial release
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity X74_157 is
|
||||
port (
|
||||
Y : out std_logic_vector (3 downto 0);
|
||||
B : in std_logic_vector (3 downto 0);
|
||||
A : in std_logic_vector (3 downto 0);
|
||||
G : in std_logic;
|
||||
S : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of X74_157 is
|
||||
begin
|
||||
p_y_comb : process(S,G,A,B)
|
||||
begin
|
||||
for i in 0 to 3 loop
|
||||
-- quad 2 line to 1 line mux (true logic)
|
||||
if (G = '1') then
|
||||
Y(i) <= '0';
|
||||
else
|
||||
if (S = '0') then
|
||||
Y(i) <= A(i);
|
||||
else
|
||||
Y(i) <= B(i);
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
end process;
|
||||
end RTL;
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity X74_257 is
|
||||
port (
|
||||
Y : out std_logic_vector (3 downto 0);
|
||||
B : in std_logic_vector (3 downto 0);
|
||||
A : in std_logic_vector (3 downto 0);
|
||||
S : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of X74_257 is
|
||||
signal ab : std_logic_vector (3 downto 0);
|
||||
begin
|
||||
|
||||
Y <= ab; -- no tristate
|
||||
p_ab : process(S,A,B)
|
||||
begin
|
||||
for i in 0 to 3 loop
|
||||
if (S = '0') then
|
||||
AB(i) <= A(i);
|
||||
else
|
||||
AB(i) <= B(i);
|
||||
end if;
|
||||
end loop;
|
||||
end process;
|
||||
end RTL;
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity PACMAN_VRAM_ADDR is
|
||||
port (
|
||||
AB : out std_logic_vector (11 downto 0);
|
||||
H256_L : in std_logic;
|
||||
H128 : in std_logic;
|
||||
H64 : in std_logic;
|
||||
H32 : in std_logic;
|
||||
H16 : in std_logic;
|
||||
H8 : in std_logic;
|
||||
H4 : in std_logic;
|
||||
H2 : in std_logic;
|
||||
H1 : in std_logic;
|
||||
V128 : in std_logic;
|
||||
V64 : in std_logic;
|
||||
V32 : in std_logic;
|
||||
V16 : in std_logic;
|
||||
V8 : in std_logic;
|
||||
V4 : in std_logic;
|
||||
V2 : in std_logic;
|
||||
V1 : in std_logic;
|
||||
FLIP : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of PACMAN_VRAM_ADDR is
|
||||
|
||||
signal v128p : std_logic;
|
||||
signal v64p : std_logic;
|
||||
signal v32p : std_logic;
|
||||
signal v16p : std_logic;
|
||||
signal v8p : std_logic;
|
||||
signal h128p : std_logic;
|
||||
signal h64p : std_logic;
|
||||
signal h32p : std_logic;
|
||||
signal h16p : std_logic;
|
||||
signal h8p : std_logic;
|
||||
signal sel : std_logic;
|
||||
signal y157 : std_logic_vector (11 downto 0);
|
||||
|
||||
component X74_157
|
||||
port (
|
||||
Y : out std_logic_vector (3 downto 0);
|
||||
B : in std_logic_vector (3 downto 0);
|
||||
A : in std_logic_vector (3 downto 0);
|
||||
G : in std_logic;
|
||||
S : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component X74_257
|
||||
port (
|
||||
Y : out std_logic_vector (3 downto 0);
|
||||
B : in std_logic_vector (3 downto 0);
|
||||
A : in std_logic_vector (3 downto 0);
|
||||
S : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
p_vp_comb : process(FLIP, V8, V16, V32, V64, V128)
|
||||
begin
|
||||
v128p <= FLIP xor V128;
|
||||
v64p <= FLIP xor V64;
|
||||
v32p <= FLIP xor V32;
|
||||
v16p <= FLIP xor V16;
|
||||
v8p <= FLIP xor V8;
|
||||
end process;
|
||||
|
||||
p_hp_comb : process(FLIP, H8, H16, H32, H64, H128)
|
||||
begin
|
||||
H128P <= FLIP xor H128;
|
||||
H64P <= FLIP xor H64;
|
||||
H32P <= FLIP xor H32;
|
||||
H16P <= FLIP xor H16;
|
||||
H8P <= FLIP xor H8;
|
||||
end process;
|
||||
|
||||
p_sel : process(H16, H32, H64)
|
||||
begin
|
||||
sel <= not((H32 xor H16) or (H32 xor H64));
|
||||
end process;
|
||||
|
||||
--p_oe257 : process(H2)
|
||||
--begin
|
||||
-- oe <= not(H2);
|
||||
--end process;
|
||||
|
||||
U6 : X74_157
|
||||
port map(
|
||||
Y => y157(11 downto 8),
|
||||
B(3) => '0',
|
||||
B(2) => H4,
|
||||
B(1) => h64p,
|
||||
B(0) => h64p,
|
||||
A => "1111",
|
||||
G => '0',
|
||||
S => sel
|
||||
);
|
||||
|
||||
U5 : X74_157
|
||||
port map(
|
||||
Y => y157(7 downto 4),
|
||||
B(3) => h64p,
|
||||
B(2) => h64p,
|
||||
B(1) => h8p,
|
||||
B(0) => v128p,
|
||||
A => "1111",
|
||||
G => '0',
|
||||
S => sel
|
||||
);
|
||||
|
||||
U4 : X74_157
|
||||
port map(
|
||||
Y => y157(3 downto 0),
|
||||
B(3) => v64p,
|
||||
B(2) => v32p,
|
||||
B(1) => v16p,
|
||||
B(0) => v8p,
|
||||
A(3) => H64,
|
||||
A(2) => H32,
|
||||
A(1) => H16,
|
||||
A(0) => H4,
|
||||
G => '0',
|
||||
S => sel
|
||||
);
|
||||
|
||||
U3 : X74_257
|
||||
port map(
|
||||
Y => AB(11 downto 8),
|
||||
B(3) => '0',
|
||||
B(2) => H4,
|
||||
B(1) => v128p,
|
||||
B(0) => v64p,
|
||||
A => y157(11 downto 8),
|
||||
S => H256_L
|
||||
);
|
||||
|
||||
U2 : X74_257
|
||||
port map(
|
||||
Y => AB(7 downto 4),
|
||||
B(3) => v32p,
|
||||
B(2) => v16p,
|
||||
B(1) => v8p,
|
||||
B(0) => h128p,
|
||||
A => y157(7 downto 4),
|
||||
S => H256_L
|
||||
);
|
||||
|
||||
U1 : X74_257
|
||||
port map(
|
||||
Y => AB(3 downto 0),
|
||||
B(3) => h64p,
|
||||
B(2) => h32p,
|
||||
B(1) => h16p,
|
||||
B(0) => h8p,
|
||||
A => y157(3 downto 0),
|
||||
S => H256_L
|
||||
);
|
||||
|
||||
end RTL;
|
||||
4
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pll.qip
Normal file
4
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pll.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
||||
320
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pll.v
Normal file
320
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pll.v
Normal file
@@ -0,0 +1,320 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll (
|
||||
areset,
|
||||
inclk0,
|
||||
c0,
|
||||
locked);
|
||||
|
||||
input areset;
|
||||
input inclk0;
|
||||
output c0;
|
||||
output locked;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 areset;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire sub_wire0;
|
||||
wire [4:0] sub_wire1;
|
||||
wire [0:0] sub_wire5 = 1'h0;
|
||||
wire locked = sub_wire0;
|
||||
wire [0:0] sub_wire2 = sub_wire1[0:0];
|
||||
wire c0 = sub_wire2;
|
||||
wire sub_wire3 = inclk0;
|
||||
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
|
||||
|
||||
altpll altpll_component (
|
||||
.areset (areset),
|
||||
.inclk (sub_wire4),
|
||||
.locked (sub_wire0),
|
||||
.clk (sub_wire1),
|
||||
.activeclock (),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 9,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 8,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_USED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_UNUSED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
183
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/scandoubler.v
Normal file
183
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/scandoubler.v
Normal file
@@ -0,0 +1,183 @@
|
||||
//
|
||||
// scandoubler.v
|
||||
//
|
||||
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
// TODO: Delay vsync one line
|
||||
|
||||
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
// system interface
|
||||
input clk_sys,
|
||||
input ce_pix,
|
||||
input ce_pix_actual,
|
||||
|
||||
input hq2x,
|
||||
|
||||
// shifter video interface
|
||||
input hs_in,
|
||||
input vs_in,
|
||||
input line_start,
|
||||
|
||||
input [DWIDTH:0] r_in,
|
||||
input [DWIDTH:0] g_in,
|
||||
input [DWIDTH:0] b_in,
|
||||
input mono,
|
||||
|
||||
// output interface
|
||||
output reg hs_out,
|
||||
output vs_out,
|
||||
output [DWIDTH:0] r_out,
|
||||
output [DWIDTH:0] g_out,
|
||||
output [DWIDTH:0] b_out
|
||||
);
|
||||
|
||||
|
||||
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
|
||||
|
||||
assign vs_out = vs_in;
|
||||
|
||||
reg [2:0] phase;
|
||||
reg [2:0] ce_div;
|
||||
reg [7:0] pix_len = 0;
|
||||
wire [7:0] pl = pix_len + 1'b1;
|
||||
|
||||
reg ce_x1, ce_x4;
|
||||
reg req_line_reset;
|
||||
wire ls_in = hs_in | line_start;
|
||||
always @(negedge clk_sys) begin
|
||||
reg old_ce;
|
||||
reg [2:0] ce_cnt;
|
||||
|
||||
reg [7:0] pixsz2, pixsz4 = 0;
|
||||
|
||||
old_ce <= ce_pix;
|
||||
if(~&pix_len) pix_len <= pix_len + 1'd1;
|
||||
|
||||
ce_x4 <= 0;
|
||||
ce_x1 <= 0;
|
||||
|
||||
// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
|
||||
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
|
||||
phase <= phase + 1'd1;
|
||||
ce_x4 <= 1;
|
||||
end
|
||||
|
||||
if(~old_ce & ce_pix) begin
|
||||
pixsz2 <= {1'b0, pl[7:1]};
|
||||
pixsz4 <= {2'b00, pl[7:2]};
|
||||
ce_x1 <= 1;
|
||||
ce_x4 <= 1;
|
||||
pix_len <= 0;
|
||||
phase <= phase + 1'd1;
|
||||
|
||||
ce_cnt <= ce_cnt + 1'd1;
|
||||
if(ce_pix_actual) begin
|
||||
phase <= 0;
|
||||
ce_div <= ce_cnt + 1'd1;
|
||||
ce_cnt <= 0;
|
||||
req_line_reset <= 0;
|
||||
end
|
||||
|
||||
if(ls_in) req_line_reset <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
reg ce_sd;
|
||||
always @(*) begin
|
||||
case(ce_div)
|
||||
2: ce_sd = !phase[0];
|
||||
4: ce_sd = !phase[1:0];
|
||||
default: ce_sd <= 1;
|
||||
endcase
|
||||
end
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
|
||||
(
|
||||
.clk(clk_sys),
|
||||
.ce_x4(ce_x4 & ce_sd),
|
||||
.inputpixel({b_in,g_in,r_in}),
|
||||
.mono(mono),
|
||||
.disable_hq2x(~hq2x),
|
||||
.reset_frame(vs_in),
|
||||
.reset_line(req_line_reset),
|
||||
.read_y(sd_line),
|
||||
.read_x(sd_h_actual),
|
||||
.outpixel({b_out,g_out,r_out})
|
||||
);
|
||||
|
||||
reg [10:0] sd_h_actual;
|
||||
always @(*) begin
|
||||
case(ce_div)
|
||||
2: sd_h_actual = sd_h[10:1];
|
||||
4: sd_h_actual = sd_h[10:2];
|
||||
default: sd_h_actual = sd_h;
|
||||
endcase
|
||||
end
|
||||
|
||||
reg [10:0] sd_h;
|
||||
reg [1:0] sd_line;
|
||||
always @(posedge clk_sys) begin
|
||||
|
||||
reg [11:0] hs_max,hs_rise,hs_ls;
|
||||
reg [10:0] hcnt;
|
||||
reg [11:0] sd_hcnt;
|
||||
|
||||
reg hs, hs2, vs, ls;
|
||||
|
||||
if(ce_x1) begin
|
||||
hs <= hs_in;
|
||||
ls <= ls_in;
|
||||
|
||||
if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
|
||||
|
||||
// falling edge of hsync indicates start of line
|
||||
if(hs && !hs_in) begin
|
||||
hs_max <= {hcnt,1'b1};
|
||||
hcnt <= 0;
|
||||
if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
|
||||
end else begin
|
||||
hcnt <= hcnt + 1'd1;
|
||||
end
|
||||
|
||||
// save position of rising edge
|
||||
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
|
||||
|
||||
vs <= vs_in;
|
||||
if(vs && ~vs_in) sd_line <= 0;
|
||||
end
|
||||
|
||||
if(ce_x4) begin
|
||||
hs2 <= hs_in;
|
||||
|
||||
// output counter synchronous to input and at twice the rate
|
||||
sd_hcnt <= sd_hcnt + 1'd1;
|
||||
sd_h <= sd_h + 1'd1;
|
||||
if(hs2 && !hs_in) sd_hcnt <= hs_max;
|
||||
if(sd_hcnt == hs_max) sd_hcnt <= 0;
|
||||
|
||||
// replicate horizontal sync at twice the speed
|
||||
if(sd_hcnt == hs_max) hs_out <= 0;
|
||||
if(sd_hcnt == hs_rise) hs_out <= 1;
|
||||
|
||||
if(sd_hcnt == hs_ls) sd_h <= 0;
|
||||
if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
243
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/video_mixer.sv
Normal file
243
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/video_mixer.sv
Normal file
@@ -0,0 +1,243 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
// LINE_LENGTH: Length of display line in pixels
|
||||
// Usually it's length from HSync to HSync.
|
||||
// May be less if line_start is used.
|
||||
//
|
||||
// HALF_DEPTH: If =1 then color dept is 3 bits per component
|
||||
// For half depth 6 bits monochrome is available with
|
||||
// mono signal enabled and color = {G, R}
|
||||
|
||||
module video_mixer
|
||||
#(
|
||||
parameter LINE_LENGTH = 480,
|
||||
parameter HALF_DEPTH = 1,
|
||||
|
||||
parameter OSD_COLOR = 3'd4,
|
||||
parameter OSD_X_OFFSET = 10'd0,
|
||||
parameter OSD_Y_OFFSET = 10'd0
|
||||
)
|
||||
(
|
||||
// master clock
|
||||
// it should be multiple by (ce_pix*4).
|
||||
input clk_sys,
|
||||
|
||||
// Pixel clock or clock_enable (both are accepted).
|
||||
input ce_pix,
|
||||
|
||||
// Some systems have multiple resolutions.
|
||||
// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
|
||||
// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
|
||||
// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
|
||||
input ce_pix_actual,
|
||||
|
||||
// OSD SPI interface
|
||||
input SPI_SCK,
|
||||
input SPI_SS3,
|
||||
input SPI_DI,
|
||||
|
||||
// scanlines (00-none 01-25% 10-50% 11-75%)
|
||||
input [1:0] scanlines,
|
||||
|
||||
// 0 = HVSync 31KHz, 1 = CSync 15KHz
|
||||
input scandoublerD,
|
||||
|
||||
// High quality 2x scaling
|
||||
input hq2x,
|
||||
|
||||
// YPbPr always uses composite sync
|
||||
input ypbpr,
|
||||
|
||||
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
|
||||
input ypbpr_full,
|
||||
input [1:0] rotate, //[0] - rotate [1] - left or right
|
||||
// color
|
||||
input [DWIDTH:0] R,
|
||||
input [DWIDTH:0] G,
|
||||
input [DWIDTH:0] B,
|
||||
|
||||
// Monochrome mode (for HALF_DEPTH only)
|
||||
input mono,
|
||||
|
||||
// interlace sync. Positive pulses.
|
||||
input HSync,
|
||||
input VSync,
|
||||
|
||||
// Falling of this signal means start of informative part of line.
|
||||
// It can be horizontal blank signal.
|
||||
// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
|
||||
// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
|
||||
// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
|
||||
// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel
|
||||
// before first informative pixel.
|
||||
input line_start,
|
||||
|
||||
// MiST video output signals
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_VS,
|
||||
output VGA_HS
|
||||
);
|
||||
|
||||
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
|
||||
|
||||
wire [DWIDTH:0] R_sd;
|
||||
wire [DWIDTH:0] G_sd;
|
||||
wire [DWIDTH:0] B_sd;
|
||||
wire hs_sd, vs_sd;
|
||||
|
||||
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
|
||||
(
|
||||
.*,
|
||||
.hs_in(HSync),
|
||||
.vs_in(VSync),
|
||||
.r_in(R),
|
||||
.g_in(G),
|
||||
.b_in(B),
|
||||
|
||||
.hs_out(hs_sd),
|
||||
.vs_out(vs_sd),
|
||||
.r_out(R_sd),
|
||||
.g_out(G_sd),
|
||||
.b_out(B_sd)
|
||||
);
|
||||
|
||||
wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd);
|
||||
wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd);
|
||||
wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd);
|
||||
|
||||
generate
|
||||
if(HALF_DEPTH) begin
|
||||
wire [5:0] r = mono ? {gt,rt} : {rt,rt};
|
||||
wire [5:0] g = mono ? {gt,rt} : {gt,gt};
|
||||
wire [5:0] b = mono ? {gt,rt} : {bt,bt};
|
||||
end else begin
|
||||
wire [5:0] r = rt;
|
||||
wire [5:0] g = gt;
|
||||
wire [5:0] b = bt;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire hs = (scandoublerD ? HSync : hs_sd);
|
||||
wire vs = (scandoublerD ? VSync : vs_sd);
|
||||
|
||||
reg scanline = 0;
|
||||
always @(posedge clk_sys) begin
|
||||
reg old_hs, old_vs;
|
||||
|
||||
old_hs <= hs;
|
||||
old_vs <= vs;
|
||||
|
||||
if(old_hs && ~hs) scanline <= ~scanline;
|
||||
if(old_vs && ~vs) scanline <= 0;
|
||||
end
|
||||
|
||||
wire [5:0] r_out, g_out, b_out;
|
||||
always @(*) begin
|
||||
case(scanlines & {scanline, scanline})
|
||||
1: begin // reduce 25% = 1/2 + 1/4
|
||||
r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
|
||||
g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
|
||||
b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
|
||||
end
|
||||
|
||||
2: begin // reduce 50% = 1/2
|
||||
r_out = {1'b0, r[5:1]};
|
||||
g_out = {1'b0, g[5:1]};
|
||||
b_out = {1'b0, b[5:1]};
|
||||
end
|
||||
|
||||
3: begin // reduce 75% = 1/4
|
||||
r_out = {2'b00, r[5:2]};
|
||||
g_out = {2'b00, g[5:2]};
|
||||
b_out = {2'b00, b[5:2]};
|
||||
end
|
||||
|
||||
default: begin
|
||||
r_out = r;
|
||||
g_out = g;
|
||||
b_out = b;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
wire [5:0] red, green, blue;
|
||||
osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
|
||||
(
|
||||
.*,
|
||||
|
||||
.R_in(r_out),
|
||||
.G_in(g_out),
|
||||
.B_in(b_out),
|
||||
.HSync(hs),
|
||||
.VSync(vs),
|
||||
.rotate(rotate),
|
||||
|
||||
.R_out(red),
|
||||
.G_out(green),
|
||||
.B_out(blue)
|
||||
);
|
||||
|
||||
wire [5:0] yuv_full[225] = '{
|
||||
6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
|
||||
6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
|
||||
6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
|
||||
6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
|
||||
6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
|
||||
6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
|
||||
6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
|
||||
6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
|
||||
6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
|
||||
6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
|
||||
6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
|
||||
6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
|
||||
6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
|
||||
6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
|
||||
6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
|
||||
6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
|
||||
6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
|
||||
6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
|
||||
6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
|
||||
6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
|
||||
6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
|
||||
6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
|
||||
6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
|
||||
6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
|
||||
6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
|
||||
6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
|
||||
6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
|
||||
6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
|
||||
6'd63
|
||||
};
|
||||
|
||||
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
|
||||
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
|
||||
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
|
||||
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
|
||||
|
||||
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
|
||||
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
|
||||
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
|
||||
|
||||
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
|
||||
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
|
||||
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
|
||||
|
||||
assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
|
||||
assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
|
||||
assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
|
||||
assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
|
||||
assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
|
||||
|
||||
endmodule
|
||||
@@ -1,11 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
@@ -1,11 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
@@ -87,6 +87,7 @@ Aviable Arcade Cores
|
||||
|
||||
#Pacman Hardware
|
||||
Ali Baba and 40 Thieves
|
||||
Birdiy
|
||||
Crush Roller
|
||||
Dream Shopper
|
||||
Eeekk
|
||||
|
||||
Reference in New Issue
Block a user