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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-20 09:44:38 +00:00

Donkey Kong: some fixes

This commit is contained in:
Gyorgy Szombathelyi 2020-12-31 20:25:17 +01:00
parent 4a4415d045
commit 3a1c0af5dd
4 changed files with 16 additions and 12 deletions

View File

@ -12,7 +12,7 @@
<buttons names="Jump,Start 1P,Start 2P,Coin" default="A,Start,Select,R" />
<switches default="80">
<switches default="80" base="8">
<dip bits="0,1" name="Lives" ids="3,4,5,6"/>
<dip bits="2,3" name="Bonus" ids="10k,15k,20k,25k"/>
<dip bits="4,6" name="Coins" ids="1C1P,2C1P,1C1P,3C1P,1C1P,4C1P,1C1P,5C1P,1C1P"/>
@ -20,7 +20,7 @@
</switches>
<rom index="1"><part>01</part></rom>
<rom index="0" zip="dkongjr.zip" md5="ebfc471d12606afd1408d62c7f4c90c9" type="merged|nonmerged">
<rom index="0" zip="dkongjr.zip" md5="bb9b77f52d45312bcf08409c76b1b8db" type="merged|nonmerged">
<!-- Main CPU 32k-->
<part crc="dea28158" name="djr1-c_5b_f-2.5b"/>
<part crc="6fb5faf6" name="djr1-c_5c_f-2.5c"/>

View File

@ -14,15 +14,15 @@
<dip bits="2,3" name="Bonus Life" ids="7K,10K,15K,20K"/>
<dip bits="7" name="Cabinet" ids="Cocktail,Upright"/>
</switches>
<rom index="0" zip="dkong.zip" md5="05fb1dd1ce6a786c538275d5776b1db1">
<rom index="0" zip="dkong.zip" md5="ac7807bf1c69c3720888212143af10af">
<!-- Main CPU 32k -->
<part crc="ba70b88b" name="c_5et_g.bin"/>
<part crc="5ec461ec" name="c_5ct_g.bin"/>
<part crc="1c97d324" name="c_5bt_g.bin"/>
<part crc="b9005ac0" name="c_5at_g.bin"/>
<part crc="b9005ac0" name="c_5at_g.bin"/>
<part crc="b9005ac0" name="c_5at_g.bin"/>
<part crc="b9005ac0" name="c_5at_g.bin"/>
<part crc="ba70b88b" name="c_5et_g.bin"/>
<part crc="5ec461ec" name="c_5ct_g.bin"/>
<part crc="1c97d324" name="c_5bt_g.bin"/>
<part crc="b9005ac0" name="c_5at_g.bin"/>
<!-- GFX1 8k -->

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@ -188,7 +188,7 @@ mist_video #(.COLOR_DEPTH(3),.SD_HCNT_WIDTH(10)) mist_video(
.SPI_DI(SPI_DI),
.R(blankn ? r : 0),
.G(blankn ? g : 0),
.B(blankn ? {b, b[1]} : 0),
.B(blankn ? {b, 1'b1} : 0),
.HSync(hs_n),
.VSync(vs_n),
.VGA_R(VGA_R),

View File

@ -124,12 +124,16 @@ end
// CPU NMI
wire W_VBLK = ~I_VBLK_n;
reg O_NMI_n;
always@(posedge W_VBLK or negedge W_5H_Q[4])
always@(posedge I_CLK24M or negedge W_5H_Q[4])
begin
if(~W_5H_Q[4])
O_NMI_n <= 1'b1;
else
O_NMI_n <= 1'b0;
reg W_VBLK_D;
if(~W_5H_Q[4])
O_NMI_n <= 1'b1;
else begin
W_VBLK_D <= W_VBLK;
if (!W_VBLK_D & W_VBLK) O_NMI_n <= 1'b0;
end
end
// ADDR DEC 0000H - 7FFFH