IremM62: CPU clock is pixel clock/2

Arcade_MiST/IremM62 Hardware/rtl/pace.vhd

@@ -16,6 +16,7 @@ entity PACE is
   (
     -- clocks and resets
     clkrst_i        : in from_CLKRST_t;
+    cpu_clk_en_i    : in std_logic;
     
     -- hardware variant
     hwsel           : in integer;
@@ -108,6 +109,7 @@ begin
     (
       -- clocking and reset
       clkrst_i        => clkrst_i,
+      cpu_clk_en_i    => cpu_clk_en_i,
 
       hwsel           => hwsel,
       

Arcade_MiST/IremM62 Hardware/rtl/platform.vhd

@@ -20,6 +20,7 @@ entity platform is
   (
     -- clocking and reset
     clkrst_i        : in from_CLKRST_t;
+    cpu_clk_en_i    : in std_logic;
 
     hwsel           : in integer;
 
@@ -77,7 +78,6 @@ architecture SYN of platform is
   alias clk_video       : std_logic is clkrst_i.clk(1);
 
   -- cpu signals  
-  signal clk_3M072_en   : std_logic;
   signal cpu_clk_en     : std_logic;
   signal cpu_a          : std_logic_vector(15 downto 0);
   signal cpu_d_i        : std_logic_vector(7 downto 0);
@@ -267,7 +267,7 @@ begin
 
   -- sprite registers
   sprite_reg_o.clk <= clk_sys;
-  sprite_reg_o.clk_ena <= clk_3M072_en;
+  sprite_reg_o.clk_ena <= cpu_clk_en_i;
   sprite_reg_o.a <= cpu_a(8 downto 0)  when hwsel = HW_HORIZON else '0' & cpu_a(7 downto 0);
   sprite_reg_o.d <= cpu_d_o;
   sprite_reg_o.wr <= sprite_cs and cpu_mem_wr;
@@ -279,21 +279,8 @@ begin
   BLK_CPU : block
     signal cpu_rst        : std_logic;
   begin
-    -- generate CPU enable clock (3MHz from 27/30MHz)
-    clk_en_inst : entity work.clk_div
-      generic map
-      (
-        DIVISOR		=> M62_CPU_CLK_ENA_DIVIDE_BY
-      )
-      port map
-      (
-        clk				=> clk_sys,
-        reset			=> rst_sys,
-        clk_en		=> clk_3M072_en
-      );
-    
     -- gated CPU signals
-    cpu_clk_en <= clk_3M072_en and not pause;
+    cpu_clk_en <= cpu_clk_en_i and not pause;
     cpu_rst <= rst_sys or rst_platform;
     
     cpu_inst : entity work.Z80                                                

Arcade_MiST/IremM62 Hardware/rtl/target_top.vhd

@@ -72,6 +72,8 @@ architecture SYN of target_top is
 
   signal hires          : std_logic;
   signal count          : std_logic_vector(1 downto 0);
+  signal cpu_clk        : std_logic;
+  signal cpu_clk_en     : std_logic;
 
 begin
 
@@ -85,9 +87,16 @@ begin
       else
         count <= count + 1;
       end if;
+
+      -- CPU clock = vidclk / 2
+      if count = "00" then
+        cpu_clk <= not cpu_clk;
+      end if;
     end if;
   end process;
 
+  cpu_clk_en <= '1' when count = "00" and cpu_clk = '1' else '0';
+
 	clkrst_i.clk(0) <= clock_sys;
 --	clkrst_i.clk(1) <= clock_vid;
 	clkrst_i.clk(1) <= clock_sys;
@@ -134,6 +143,7 @@ Sound_Board : entity work.Sound_Board
 pace_inst : entity work.pace                                            
 	port map(
 		clkrst_i				=> clkrst_i,
+    cpu_clk_en_i    => cpu_clk_en,
 		hwsel           => hwsel,
     hires           => hires,
 		buttons_i         => buttons_i,