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Update single_port_ram.vhd

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Marcel 2023-07-13 12:03:31 +02:00
parent ca0c6feb5f
commit 3da627aa0b
1 changed files with 1 additions and 1 deletions
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Arcade_MiST/Toaplan v1 Hardware/rtl/single_port_ram.vhd
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@ -73,7 +73,7 @@ begin
generic map (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone V",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**ADDR_WIDTH,