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Arcade_MiST/Gremlin Blockade Hardware/Blockade.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 00:21:03 December 03, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "00:21:03 December 03, 2019"
# Revisions
PROJECT_REVISION = "Blockade"

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Arcade_MiST/Gremlin Blockade Hardware/Blockade.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 21:58:05 March 10, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Blockade_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Blockede_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/blockade.v
set_global_assignment -name VERILOG_FILE rtl/vm80a.v
set_global_assignment -name VERILOG_FILE rtl/spram.v
set_global_assignment -name VERILOG_FILE rtl/dpram.v
set_global_assignment -name VERILOG_FILE rtl/astable_555.v
set_global_assignment -name VERILOG_FILE rtl/blockade_lpf.v
set_global_assignment -name VERILOG_FILE rtl/iir_1st_order.v
set_global_assignment -name VERILOG_FILE rtl/jtframe_resync.v
set_global_assignment -name VERILOG_FILE rtl/pause.v
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_MACRO "EXT_ROM=<None>"
set_global_assignment -name FORCE_SYNCH_CLEAR ON
set_global_assignment -name TOP_LEVEL_ENTITY Blockede_MiST
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/tm.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# ---------------------------
# start ENTITY(Blockede_MiST)
# Pin & Location Assignments
# ==========================
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
# Fitter Assignments
# ==================
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Blockede_MiST)
# -------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Arcade_MiST/Gremlin Blockade Hardware/META/Blasto.mra Normal file
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<misterromdescription>
<name>Blasto</name>
<year>1978</year>
<manufacturer>Gremlin</manufacturer>
<setname>blasto</setname>
<mameversion>0229</mameversion>
<rbf>blockade</rbf>
<buttons default="A,Start,R,L" names="Fire,Start,Coin,Pause"></buttons>
<switches default="0" page_id="1" page_name="Switches" base="8">
<dip bits="0,1" name="Coinage" ids="4 coins / 1 credit,3 coins / 1 credit,2 coins / 1 credit,1 coins / 1 credit"/>
<dip bits="2" name="Demo Sounds" ids="Off,On"/>
<dip bits="3" name="Game Time" ids="70 seconds,90 seconds"/>
<dip bits="4,5" name="Overlay Colour" ids="Green,White,Yellow,Red"/>
</switches>
<rom index="1"><part>03</part></rom>
<rom index="0" md5="none" zip="blasto.zip">
<!-- GAME ROMS -->
<part crc="none" name="316-0089.u2"/>
<part crc="none" name="316-0090.u3"/>
<part crc="none" name="316-0091.u4"/>
<part crc="none" name="316-0092.u5"/>
<!-- GFX PROMS -->
<part crc="none" name="316-0093.u29"/>
<part crc="none" name="316-0094.u43"/>
</rom>
<rom index="2"></rom>
<rom index="3"></rom>
<rom index="4"></rom>
<nvram></nvram>
</misterromdescription>

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<misterromdescription>
<name>Blockade</name>
<year>1976</year>
<manufacturer>Gremlin</manufacturer>
<setname>blockade</setname>
<mameversion>0229</mameversion>
<rbf>blockade</rbf>
<buttons default="R,L" names="-,-,Coin,Pause"></buttons>
<switches default="3" page_id="1" page_name="Switches" base="8">
<dip bits="0,1" name="Lives" ids="3,4,5,6"/>
<dip bits="2,3" name="Overlay Colour" ids="Green,White,Yellow,Red"/>
<dip bits="4" name="Boom Switch" ids="On,Off"/>
</switches>
<rom index="1"><part>00</part></rom>
<rom index="0" md5="none" zip="blockade.zip">
<!-- GAME ROMS -->
<part crc="none" name="316-0004.u2" />
<part crc="none" name="316-0003.u3" />
<!-- PADDING -->
<part repeat="2048">00</part>
<!-- GFX PROMS -->
<part crc="none" name="316-0002.u29" repeat="2" />
<part crc="none" name="316-0001.u43" repeat="2" />
</rom>
<rom index="2"></rom>
<rom index="3"></rom>
<rom index="4"></rom>
<nvram></nvram>
</misterromdescription>

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Arcade_MiST/Gremlin Blockade Hardware/META/CoMotion.mra Normal file
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<misterromdescription>
<name>CoMotion</name>
<year>1976</year>
<manufacturer>Gremlin</manufacturer>
<setname>comotion</setname>
<mameversion>0229</mameversion>
<rbf>blockade</rbf>
<buttons default="Start,R,L" names="-,Start,Coin,Pause"></buttons>
<switches default="0" page_id="1" page_name="Switches" base="8">
<dip bits="0" name="Lives" ids="3,4"/>
<dip bits="1,2" name="Overlay Colour" ids="Green,White,Yellow,Red"/>
<dip bits="3" name="Boom Switch" ids="On,Off"/>
</switches>
<rom index="1"><part>01</part></rom>
<rom index="0" md5="none" zip="comotion.zip">
<!-- GAME ROMS -->
<part crc="none" name="316-0007.u2"/>
<part crc="none" name="316-0008.u3"/>
<part crc="none" name="316-0009.u4"/>
<part crc="none" name="316-0010.u5"/>
<!-- GFX PROMS -->
<part crc="none" name="316-0006.u43" repeat="2" />
<part crc="none" name="316-0005.u29" repeat="2" />
</rom>
<rom index="2"></rom>
<rom index="3"></rom>
<rom index="4"></rom>
<nvram></nvram>
</misterromdescription>

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Arcade_MiST/Gremlin Blockade Hardware/META/Hustle.mra Normal file
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<misterromdescription>
<name>Hustle</name>
<year>1977</year>
<manufacturer>Gremlin</manufacturer>
<setname>hustle</setname>
<mameversion>0229</mameversion>
<rbf>blockade</rbf>
<buttons default="Start,R,L" names="-,Start,Coin,Pause"></buttons>
<switches default="20" page_id="1" page_name="Switches" base="8">
<dip bits="0,1" name="Coinage" ids="4 coins / 1 credit,3 coins / 1 credit,2 coins / 1 credit,1 coins / 1 credit"/>
<dip bits="2,3" name="Free Game" ids="11000,13000,15000,17000"/>
<dip bits="4" name="Game Time" ids="2 mins,1.5 mins"/>
<dip bits="5,6" name="Overlay Colour" ids="Green,White,Yellow,Red"/>
</switches>
<rom index="1"><part>02</part></rom>
<rom index="0" md5="none" zip="hustle.zip">
<!-- GAME ROMS -->
<part crc="none" name="316-0016.u2"/>
<part crc="none" name="316-0017.u3"/>
<part crc="none" name="316-0018.u4"/>
<part crc="none" name="316-0019.u5"/>
<!-- GFX PROMS -->
<part crc="none" name="316-0020.u29"/>
<part crc="none" name="316-0021.u43"/>
</rom>
<rom index="2"></rom>
<rom index="3"></rom>
<rom index="4"></rom>
<nvram></nvram>
</misterromdescription>

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Arcade_MiST/Gremlin Blockade Hardware/README.MD Normal file
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# Blockade by Sega/Gremlin Industries for [MiSTer](https://github.com/MiSTer-devel/Main_MiSTer/wiki)
An FPGA implementation of Blockade arcade hardware by Gremlin Industries for the MiSTer platform.
## Credits
- [__JimmyStones__](https://github.com/JimmyStones): Core design and implementation
- [__Vslav__](https://github.com/1801BM1): [vm80a](https://github.com/1801BM1/vm80a) CPU (8080A implementation reverse engineered from a Soviet replica!)
- [__Jotego__](https://github.com/jotego): [jtframe_resync](https://github.com/jotego/jtframe/blob/master/hdl/video/jtframe_resync.v) for analog video H/V re-positioning
- __Soltan_G42__: 1st order low-pass filter for audio circuit - thanks also to __Ace__ for explanations on how to use and tune the filter
- __Ethan__ of [The History of How We Play](https://thehistoryofhowweplay.wordpress.com): Editing and expansion of history
## FPGA implementation
- Built entirely in simulation using original schematics and information from MAME, logic has been simplified where possible
- Supports all Gremlin produced games which use the Blockade 8080A-based hardware
- Monochrome video output with selectable colour overlay (Green,White,Yellow,Red)
## Supported games
- Blockade (1976)
- CoMotion (1977)
- Hustle (1977)
- Blasto (1978)
## History of Blockade
Blockade was created by Lane Hauck in 1976 as a project to get the Gremlin management interested in producing video games.
Initially the game concept began as an expression of the “random walk” in physics, using a 2D plane with tiles to represent spaces where the cursor had been. He developed this into a game which proved popular enough to develop into a full product to be launched at the end of 1976.
The analog circuits used to generate the explosion sound effects were designed by Bob Pecoraro. Additional programming was done by George Kiss. Lonnie Pogue designed the cabinet for the game while Verl “Ole” Olson designed the four player cabinet.
The game was shown at the 1976 AMOA expo from November 12th-14th, along with a 4-player version called CoMotion. It received accolades from the coin-op trade press and was quickly copied by competitors.
Blockade is effectively the original 'light-cycles' game, but unfortunately due to Gremlin's inexperience in producing arcade cabinets they were outpaced by a number of clones, including Ramtek's Barricade, Midway's Checkmate, and Atari's Dominos.
This led to many circuit boards being unsold and so further games were produced using the surplus Blockade hardware, with minor changes including larger ROMs and more RAM.
Hustle was released in May 1977 and was the origin of the 'Snake' genre which later became popular as a casual game on low end computers, web-based Flash applications, and mobile phones. 1 or 2 players compete to collect points while avoiding their ever growing tail and that of their opponent.
Blasto (conceived by Hauck and programmed by Bill Blewett) was released in July 1978, and is a 1 or 2 player shooter where players maneuver around a destructible maze and destroy mines, while avoiding the explosions and chain reactions that occur.
Sources:
- Ethan of [History of How We Play](https://thehistoryofhowweplay.wordpress.com)
- http://allincolorforaquarter.blogspot.com/2015/09/the-ultimate-so-far-history-of-gremlin_25.html
## Known issues
- Square-wave sound circuit is probably not producing the correct frequency (hard to verify without access to a good recording of original machine)
- Boom sound circuit is not implemented, so it uses a sample (from https://samples.mameworld.info/)
- Coin circuit timing is suspect, but it works!
- Free game on Hustle cannot be disabled in DIPs (due to limitation of MiSTer DIPs support)
## Installation
Place `*.rbf` into the "_Arcade/cores" folder on your SD card. Then, place `*.mra` into the "_Arcade" folder and ROM files from MAME into "games/mame".
### ****ATTENTION****
ROMs are not included. In order to use this arcade core, you must provide the correct ROMs.
To simplify the process, .mra files are provided in the releases folder that specify the required ROMs along with their checksums. The ROM's .zip filename refers to the corresponding file in the M.A.M.E. project.
Please refer to https://github.com/MiSTer-devel/Main_MiSTer/wiki/Arcade-Roms-and-MRA-files for information on how to setup and use the environment.
Quick reference for folders and file placement:
/_Arcade/<game name>.mra
/_Arcade/cores/<game rbf>.rbf
/games/mame/<mame rom>.zip
/games/hbmame/<hbmame rom>.zip

36
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
for /d %%i in (sys\*_sim) do rmdir /s /q "%%i"
for /d %%i in (rtl\*_sim) do rmdir /s /q "%%i"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del *.cdf
del *.rpt
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

317
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module Blockede_MiST(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"BLOCKADE;;",
// "O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
// "O5,Blend,Off,On;",
"O7,Pause,Off,On;",
// "O89,Color,Green,White,Yellow,Red;",
"OGJ,Analog Video H-Pos,0,-1,-2,-3,-4,-5,-6,-7,8,7,6,5,4,3,2,1;",
"OKN,Analog Video V-Pos,0,-1,-2,-3,-4,-5,-6,-7,8,7,6,5,4,3,2,1;",
"DIP;",
"T0,Reset;",
"V,v1.50.",`BUILD_DATE
};
//wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire btn_pause = status[7];
assign LED = ~(ioctl_downl);
assign AUDIO_R = AUDIO_L;
wire clk_sys;
wire pll_locked;
pll pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_sys)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire [6:0] core_mod;
wire ypbpr;
wire no_csync;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
wire vid;
wire [2:0] video_rgb = {3{vid}} & overlay_mask;
wire [5:0] rgb_out;
wire hs, vs, vb, hb;
wire blankn = ~(hb | vb);
wire [15:0] audio;
wire ioctl_downl;
wire ioctl_upl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire [7:0] ioctl_din;
data_io data_io(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.SPI_DO ( SPI_DO ),
.ioctl_download( ioctl_downl ),
.ioctl_upload ( ioctl_upl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout ),
.ioctl_din ( ioctl_din )
);
mist_video #(.COLOR_DEPTH(2), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? rgb_out[5:4] : 0 ),
.G ( blankn ? rgb_out[3:2] : 0 ),
.B ( blankn ? rgb_out[1:0] : 0 ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.scanlines ( scanlines ),
// .rotate ( { 1'b0, rotate } ),
.ce_divider ( 1'b0 ),
.blend ( blend ),
.scandoubler_disable(scandoublerD ),
.no_csync ( no_csync ),
.ypbpr ( ypbpr )
);
// H/V offset
wire [3:0] voffset = status[23:20];
wire [3:0] hoffset = status[19:16];
wire hs_original, vs_original;
wire ce_pix;
jtframe_resync jtframe_resync
(
.clk(clk_sys),
.pxl_cen(ce_pix),
.hs_in(hs_original),
.vs_in(vs_original),
.LVBL(~vb),
.LHBL(~hb),
.hoffset(hoffset),
.voffset(voffset),
.hs_out(hs),
.vs_out(vs)
);
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.core_mod (core_mod ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.C_bits(16))
dac (
.clk_i(clk_sys),
.res_n_i(1),
.dac_i({~audio[15],audio[14:0]}),
.dac_o(AUDIO_L)
);
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_up3, m_down3, m_left3, m_right3, m_fire3A, m_fire3B, m_fire3C, m_fire3D, m_fire3E, m_fire3F;
wire m_up4, m_down4, m_left4, m_right4, m_fire4A, m_fire4B, m_fire4C, m_fire4D, m_fire4E, m_fire4F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
arcade_inputs inputs (
.clk ( clk_sys ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
// .rotate ( rotate ),
// .orientation ( 2'b01 ),
.joyswap ( 1'b0 ),
.oneplayer ( 1'b0 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ),
.player3 ( {m_fire3F, m_fire3E, m_fire3D, m_fire3C, m_fire3B, m_fire3A, m_up3, m_down3, m_left3, m_right3} ),
.player4 ( {m_fire4F, m_fire4E, m_fire4D, m_fire4C, m_fire4B, m_fire4A, m_up4, m_down4, m_left4, m_right4} )
);
/////////////////// DIPS ////////////////////
reg [2:0] dip_blockade_lives;
reg dip_comotion_lives;
reg [1:0] dip_hustle_coin;
reg [7:0] dip_hustle_freegame;
reg dip_hustle_time;
reg [1:0] dip_blasto_coin;
reg dip_blasto_demosounds;
reg dip_blasto_time;
reg dip_boom;
reg [1:0] dip_overlay_type;
reg [2:0] overlay_mask;
reg [7:0] sw;
reg [7:0] IN_1;
reg [7:0] IN_2;
reg [7:0] IN_4;
always @(posedge clk_sys)
begin
// if (ioctl_wr && (ioctl_index==8'd254) && !ioctl_addr[24:3]) sw[ioctl_addr[2:0]] <= ioctl_dout;
sw = status[15:8];
case(core_mod)
7'h0: // GAME_BLOCKADE
begin
// The lives DIP behaves strangely in Blockade, so it is remapped here
case(sw[1:0])
2'd0: dip_blockade_lives <= 3'b011; // 3 lives
2'd1: dip_blockade_lives <= 3'b110; // 4 lives
2'd2: dip_blockade_lives <= 3'b100; // 5 lives
2'd3: dip_blockade_lives <= 3'b000; // 6 lives
endcase
dip_boom <= sw[4];
dip_overlay_type <= sw[3:2];
IN_1 <= ~{m_coin1, dip_blockade_lives, 1'b0, dip_boom, 2'b00};
IN_2 <= ~{m_left, m_down, m_right, m_up, m_left2, m_down2, m_right2, m_up2};
IN_4 <= ~{8'b00000000}; // Unused
end
7'h1: // GAME_COMOTION
begin
dip_comotion_lives <= sw[0];
dip_overlay_type <= sw[2:1];
dip_boom <= sw[3];
IN_1 <= ~{m_coin1, 2'b0, m_one_player, dip_comotion_lives, dip_boom, 2'b00};
IN_2 <= ~{m_left2, m_down2, m_right2, m_up2, m_left, m_down, m_right, m_up};
IN_4 <= ~{m_left4, m_down4, m_right4, m_up4, m_left3, m_down3, m_right3, m_up3};
end
7'h2: // GAME_HUSTLE
begin
dip_hustle_coin <= sw[1:0];
case(sw[3:2])
2'd0: dip_hustle_freegame <= 8'b11100001;
2'd1: dip_hustle_freegame <= 8'b11010001;
2'd2: dip_hustle_freegame <= 8'b10110001;
2'd3: dip_hustle_freegame <= 8'b01110001;
endcase
dip_hustle_time <= sw[4];
dip_overlay_type <= sw[6:5];
IN_1 <= ~{m_coin1, 2'b0, m_two_players, m_one_player, dip_hustle_time, dip_hustle_coin};
IN_2 <= ~{m_left, m_down, m_right, m_up, m_left2, m_down2, m_right2, m_up2};
IN_4 <= dip_hustle_freegame; // Extra DIPS
end
7'h3: // GAME_BLASTO
begin
dip_blasto_coin = sw[1:0];
dip_blasto_demosounds = sw[2];
dip_blasto_time = sw[3];
dip_overlay_type <= sw[5:4];
IN_1 <= ~{m_coin1, 3'b0, dip_blasto_time, dip_blasto_demosounds, dip_blasto_coin};
IN_2 <= ~{m_fireA, m_two_players, m_one_player, 4'b0000, m_fire2A};
IN_4 <= ~{m_up, m_left, m_down, m_right, m_up2, m_left2, m_down2, m_right2};
end
endcase
// Generate overlay colour mask
case(dip_overlay_type)
2'd0: overlay_mask <= 3'b010; // Green
2'd1: overlay_mask <= 3'b111; // White
2'd2: overlay_mask <= 3'b011; // Yellow
2'd3: overlay_mask <= 3'b001; // Red
endcase
end
wire pause_cpu;
pause #(2,2,2,24) pause (
.rgb_out(rgb_out),
.r({2{video_rgb[0]}}),
.g({2{video_rgb[1]}}),
.b({2{video_rgb[2]}}),
.user_button(btn_pause),
.pause_request(),
.options(~status[26:25])
);
/////////////////// GAME ////////////////////
reg rom_downloaded = 1'b0;
wire rom_download = ioctl_downl && ioctl_index == 8'b0;
wire reset = (status[0] | buttons[1] | rom_download | ~rom_downloaded);
// Latch release reset if ROM data is received (stops sound circuit from going off if ROMs are not found)
always @(posedge clk_sys) if(rom_download && ioctl_dout > 8'b0) rom_downloaded <= 1'b1;
blockade blockade(
.clk (clk_sys),
.reset (reset),
.pause (pause),
.game_mode (core_mod),
.ce_pix (ce_pix),
.video (vid),
.vsync (vs_original),
.hsync (hs_original),
.vblank (vb),
.hblank (hb),
.audio_l (audio),
.in_1 (IN_1),
.in_2 (IN_2),
.in_4 (IN_4),
.coin (m_coin1),
.dn_addr (ioctl_addr[13:0]),
.dn_wr (ioctl_wr & rom_download),
.dn_data (ioctl_dout)
);

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/*============================================================================
Astable 555 generator - based on a version from Space Race by bellwood420
Author: Jim Gregory - https://github.com/JimmyStones/
Version: 1.0
Date: 2022-02-13
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>.
===========================================================================*/
`timescale 1 ps / 1 ps
module astable_555 #(
parameter HIGH_PERIOD = 1000,
parameter LOW_PERIOD = 1000
)(
input clk,
input reset,
output out
);
localparam BIT_WIDTH_HIGH = $clog2(HIGH_PERIOD);
localparam BIT_WIDTH_LOW = $clog2(LOW_PERIOD);
// State constants
localparam STATE_RESET = 0;
localparam STATE_HIGH_COUNT = 1;
localparam STATE_LOW_COUNT = 2;
// State and timers
reg [1:0] state;
reg [BIT_WIDTH_HIGH-1:0] high_count;
reg [BIT_WIDTH_LOW-1:0] low_count;
assign out = (state == STATE_HIGH_COUNT) ? 1'b1 : 1'b0;
always @(posedge clk)
begin
if (reset) state <= STATE_RESET;
// Increment relevant counters
case(state)
STATE_RESET:
begin
high_count <= {BIT_WIDTH_HIGH{1'b0}};
low_count <= {BIT_WIDTH_LOW{1'b0}};
state <= STATE_HIGH_COUNT;
end
STATE_HIGH_COUNT:
begin
high_count <= high_count + 1'b1;
if ((high_count == HIGH_PERIOD-1)) state <= STATE_LOW_COUNT;
end
STATE_LOW_COUNT:
begin
low_count <= low_count + 1'b1;
if ((low_count == LOW_PERIOD-1)) state <= STATE_HIGH_COUNT;
end
endcase
end
endmodule

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/*============================================================================
FPGA implementation of Blockade by Gremlin Industries for MiSTer
Author: Jim Gregory - https://github.com/JimmyStones/
Version: 1.0
Date: 2022-02-13
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>.
===========================================================================*/
`timescale 1 ps / 1 ps
module blockade (
input clk,
input reset,
input pause,
input [1:0] game_mode,
output ce_pix,
output video,
output vsync,
output hsync,
output vblank,
output hblank,
output signed [15:0] audio_l,
output signed [15:0] audio_r,
input [7:0] in_1,
input [7:0] in_2,
input [7:0] in_4,
input coin,
input [13:0] dn_addr,
input dn_wr,
input [7:0] dn_data
);
// Game mode constants
localparam GAME_BLOCKADE = 0;
localparam GAME_COMOTION = 1;
localparam GAME_HUSTLE = 2;
localparam GAME_BLASTO = 3;
// CPU and Video system clock enables
// ----------------------------------
// - Replaces U31, U17, U8, U18 section of circuit
reg [3:0] phi_count;
reg [1:0] vid_count;
always @(posedge clk) begin
// Phi counter is 0-9, generates PHI_1 and PHI_2 enable signals for CPU
phi_count <= (phi_count == 4'd9) ? 4'b0 : phi_count + 1'b1;
// Video counter is 0-3, generates ce_vid and ce_pix signals for video circuit
vid_count <= vid_count + 2'b1;
end
// Video and pixel clock every 4 cycles of system clock
// - Video system clock one cycle ahead of pixel clock so video memory reads have time to complete
wire ce_vid = (vid_count == 2'd0);
assign ce_pix = (vid_count == 2'd3);
// 8080A CPU timing
// PHI1: XX--------
// PHI2: ---XXXXXX-
wire PHI_1 = phi_count[3:1] == 3'b000;
wire PHI_2 = phi_count >= 4'd3 && phi_count <= 4'd8;
// U21 - Video RAM address select
wire a12_n_a15 = ADDR[15] && ~ADDR[12];
// CPU
// ---
// U9 D flip-flop - Disables CPU using READY signal when attempting to write VRAM during vblank
reg u9_q;
reg PHI_2_last;
always @(posedge clk) begin
if(reset)
u9_q <= 1'b1;
else
if(PHI_2) u9_q <= ~(VBLANK_N && a12_n_a15);
end
// Input data address selector
wire INP_1 = INP && ADDR[0];
wire INP_2 = INP && ADDR[1];
wire INP_4 = INP && ADDR[2];
// CPU data in mux
wire [7:0] cpu_data_in = INP_1 ? { ~(coin_latch > 6'b0), in_1[6:0] } :
INP_2 ? in_2 :
INP_4 ? in_4 :
rom1_cs ? rom1_data_out :
rom2_cs ? rom2_data_out :
vram_cs ? vram_data_out_cpu :
sram_cs ? sram_data_out :
8'h00;
// CPU signals
wire [15:0] ADDR;
wire [7:0] DATA;
wire DBIN;
wire WR_N;
wire SYNC /*verilator public_flat*/;
// CPU reset can originate from system reset signal or coin start signal (only for CoMotion, Hustle, and Blasto)
wire RESET = reset || (game_mode != GAME_BLOCKADE && coin_start > 6'b0);
// 8080A CPU
vm80a cpu
(
.pin_clk(clk),
.pin_f1(PHI_1),
.pin_f2(PHI_2),
.pin_reset(RESET),
.pin_a(ADDR),
.pin_d(DATA),
.pin_hold(1'b0),
.pin_hlda(),
.pin_ready(u9_q && !pause),
.pin_wait(),
.pin_int(1'b0),
.pin_inte(),
.pin_sync(SYNC),
.pin_dbin(DBIN),
.pin_wr_n(WR_N)
);
// Handle CPU in/out data buffer
assign DATA = DBIN ? cpu_data_in: 8'hZZ;
reg [7:0] cpu_data_out;
always @(posedge clk) begin
if(!WR_N) cpu_data_out <= DATA;
end
// Video timing generator
// ----------------------
// - Constants
localparam HBLANK_START = 9'd255;
localparam HSYNC_START = 9'd272;
localparam HSYNC_END = 9'd300;
localparam HRESET_LINE = 9'd329;
localparam VSYNC_START = 9'd238;
localparam VSYNC_END = 9'd248;
localparam VBLANK_START = 9'd224;
localparam VBLANK_END = 9'd261;
localparam VRESET_LINE = 9'd261;
// Video counters
reg [8:0] hcnt;
reg [8:0] vcnt;
// Video event signals
reg HBLANK_N = 1'b1;
reg HSYNC_N = 1'b1;
reg HSYNC_N_last = 1'b1;
wire VBLANK_N = ~(vcnt >= VBLANK_START);
wire VSYNC_N = ~(vcnt >= VSYNC_START && vcnt <= VSYNC_END);
// Video RAM read addresses
reg [2:0] prom_col;
wire [9:0] vram_read_addr = { vcnt[7:3], hcnt[7:3] }; // Generate VRAM read address from h/v counters { 128V, 64V, 32V, 16V, 8V, 128H, 64H, 32H, 16H, 8H };
always @(posedge clk)
begin
if(ce_vid)
begin
HSYNC_N_last <= HSYNC_N; // Track last cycle hsync value
if (hcnt == HRESET_LINE) // Horizontal reset point reached
begin
hcnt <= 9'b0000; // Reset horizontal counter
prom_col = 3'b111; // Set prom column to zero
HBLANK_N <= 1'b1; // Leave hblank
end
else
begin
hcnt <= hcnt + 9'b1; // Increment horizontal counter
if(hcnt == HBLANK_START) HBLANK_N <= 1'b0; // Enter hblank when HBLANK_START reached
if(hcnt == HSYNC_START) HSYNC_N <= 1'b0; // Enter hsync when HSYNC_START reached
if(hcnt == HSYNC_END) HSYNC_N <= 1'b1; // Leave hsync when HSYNC_END reached
prom_col = 3'b111 - { hcnt[2:0] + 3'b1}; // Set prom column to reverse of {H1,H2,H4} + 1
end
if(HSYNC_N && !HSYNC_N_last) // Leaving hysnc
begin
if (vcnt == VRESET_LINE) // Vertical reset point reached
vcnt <= 9'b0; // Reset vertical counter
else
vcnt <= vcnt + 9'b1; // Increment vertical counter
end
end
end
// Set video output signals
assign video = prom_data_out[prom_col];
assign hsync = ~HSYNC_N;
assign hblank = ~HBLANK_N;
assign vblank = ~VBLANK_N;
assign vsync = ~VSYNC_N;
// CPU IO control latches
// ----------------------
// U45 AND - Enable for U51 latch
wire u45 = PHI_1 && SYNC;
// U51 latch
reg [3:0] u51_latch;
always @(posedge clk) begin
if(u45) u51_latch <= { DATA[7:6], DATA[4:3] };
end
// U45_1
wire OUTP = u51_latch[1] && ~WR_N;
// U44_1
wire MEMW = (u51_latch[0] && ~WR_N);
// U45_2
wire INP = (u51_latch[2] && DBIN);
// U44_2
wire MEMR = (u51_latch[3] && DBIN);
// Discrete audio circuit
// ----------------------
// 555 timer generates a base square wave at 93Khz-ish
wire u68_out;
reg u68_out_last;
astable_555 #(
.HIGH_PERIOD(70),
.LOW_PERIOD(26)
// .HIGH_PERIOD(140),
// .LOW_PERIOD(51)
) u68 (
.clk(clk),
.reset(RESET),
.out(u68_out)
);
// U66 and U77 make up an 8-bit counter which is preloaded on overflow from U61 and U62 latches.
reg [7:0] u6261;
reg [7:0] u6766_count;
reg u6766_out;
reg u6766_out_last;
wire OUTP2 = OUTP && ADDR[1];
always @(posedge clk)
begin
u68_out_last <= u68_out;
if(RESET)
begin
// Reset preloader and counter outputs
u6766_count <= 8'hFF;
u6766_out <= 1'b0;
u6766_out_last <= 1'b0;
u6261 <= 8'hFF;
end
else
begin
if(OUTP2) u6261 <= DATA; // OUTP2 - Latch CPU data into counter preloaders
u6766_out_last <= u6766_out;
if(u68_out && !u68_out_last)
begin
if((u6766_count == 8'd255)) // Load new inputs when counter overflows
begin
u6766_count <= u6261;
u6766_out <= 1'b0;
end
else
begin // Increment counter and output high if counter is overflowing
u6766_count <= u6766_count + 8'b1;
u6766_out <= (u6766_count == 8'd254);
end
end
end
end
// U60 flip-flop - sound circuit enable and final /2 stage
reg u60_1_q;
reg u60_2_q;
always @(posedge clk)
begin
if(RESET)
u60_1_q <= 1'b0;
else
begin
if(!u6766_out) u60_1_q <= 1'b1;
if(~u60_1_q) u60_2_q <= 1'b0;
else
if(u6766_out && !u6766_out_last) u60_2_q <= ~u60_2_q;
end
end
// Amplify square wave to produce output
wire signed [15:0] sound_out = u6766_count == 8'd255 ? 0 : (!u60_2_q ? -12000 : 12000);
// Low-pass filter the square wave
// - Cut-off frequency of 723.43Hz calculated from 220K resistor and 0.001µF capacitor pairing
wire signed [15:0] sound_filtered;
blockade_lpf lpf
(
.clk(clk),
.reset(RESET),
.in(sound_out),
.out(sound_filtered)
);
// Boom circuit
// ------------
// This is an analog noise generator which I can't replicate, so we have wave playback of a MAME-source sample
// Trigger circuit (OUTP_4 and OUTP_8)
wire u50_1 = ~(OUTP && ADDR[3]);
wire u50_2 = ~(OUTP && ADDR[2]);
/* verilator lint_off UNOPTFLAT */
wire u50_3 = ~(u50_1 && u50_4);
wire u50_4 = ~(u50_2 && u50_3);
/* verilator lint_on UNOPTFLAT */
always @(posedge clk) begin
if(RESET)
wav_play <= 1'b0; // Don't play sample during reset
else
wav_play <= u50_4; // Trigger ENV sound (play boom sample)
end
// Wave player
reg [15:0] wave_rom_addr;
wire [7:0] wave_rom_data_out;
reg [15:0] wave_rom_length = 16'd19082;
// Wave sample for boom sound
spram #(15,8, "rom/boom.hex") wave_rom
(
.clk(clk),
.address(wave_rom_addr),
.wren(1'b0),
.data(),
.q(wave_rom_data_out)
);
reg wav_playing = 1'b0;
reg wav_play = 1'b0;
reg [WAV_COUNTER_SIZE-1:0] wav_counter;
localparam WAV_COUNTER_SIZE = 10;
localparam WAV_COUNTER_MAX = 1000;
reg signed [7:0] wav_signed;
always @(posedge clk)
begin
if(RESET)
begin
wav_signed <= 8'b0;
wav_playing <= 1'b0;
end
else
begin
if(!pause)
begin
if(!wav_playing)
begin
if(wav_play)
begin
wav_playing <= 1'b1;
wave_rom_addr <= 15'b0;
wav_counter <= WAV_COUNTER_MAX;
end
end
else
begin
wav_counter <= wav_counter - 1'b1;
if(wav_counter == {WAV_COUNTER_SIZE{1'b0}})
begin
if(wave_rom_addr < wave_rom_length)
begin
wav_signed <= wave_rom_data_out;
wave_rom_addr <= wave_rom_addr + 15'b1;
wav_counter <= {WAV_COUNTER_SIZE{1'b1}};
end
else
begin
wav_signed <= 8'b0;
wave_rom_addr <= 15'b0;
wav_playing <= 1'b0;
end
end
end
end
end
end
wire signed [15:0] wav_amplified = { wav_signed[7], {1{wav_signed[7]}}, wav_signed[6:0], {7{wav_signed[7]}} };
// Audio mixer
// -----------
// - Combine discrete audio circuit and wave output, then invert
wire signed [15:0] sound_combined = 16'hFFFF - (sound_filtered + wav_amplified);
reg signed [15:0] sound_last;
always @(posedge clk) if(!pause) sound_last <= sound_combined;
assign audio_l = pause ? sound_last : sound_combined;
assign audio_r = audio_l;
// Coin circuit
// ------------
wire OUTP1 = OUTP && ADDR[0];
reg coin_last;
reg [5:0] coin_start;
reg coin_inserted;
reg [5:0] coin_latch;
always @(posedge clk) begin
if(reset)
begin
coin_latch <= 6'b0;
coin_inserted <= 1'b0;
end
else
begin
// Register inserted coin when INP_1 active
if(INP && ADDR[0])
begin
if(coin_inserted)
begin
coin_latch <= 6'b111111;
coin_inserted <= 1'b0;
end
if(coin_latch > 6'b0) coin_latch <= coin_latch - 1'b1;
end
// When coin input is going high, latch coin inserted and start reset pulse
coin_last <= coin;
if(coin && !coin_last)
begin
coin_inserted <= 1'b1;
coin_start <= 6'b111111;
end
// Decrement coin start timer if active
if(coin_start > 6'b0) coin_start <= coin_start - 6'b1;
end
end
// U2, U3 - Program ROM
// --------------------
// Each ROM is 1024 x 4 bytes. Each pair is combined to 8 bytes:
// - U2 as most significant bits, U3 as least significant bits
// - U4 as most significant bits, U5 as least significant bits (not used by Blockade)
// Program ROM data outs
wire [3:0] rom1_data_out_lsb;
wire [3:0] rom1_data_out_msb;
wire [7:0] rom1_data_out = { rom1_data_out_msb, rom1_data_out_lsb };
wire [3:0] rom2_data_out_lsb;
wire [3:0] rom2_data_out_msb;
wire [7:0] rom2_data_out = { rom2_data_out_msb, rom2_data_out_lsb };
// Program ROM CPU address decode
wire rom1_cs = (!ADDR[15] && !ADDR[11] && !ADDR[10] && MEMR);
wire rom2_cs = (!ADDR[15] && !ADDR[11] && ADDR[10] && MEMR);
// Program ROM download write enables
wire rom1_msb_wr = dn_addr[12:10] == 3'b000 && dn_wr;
wire rom1_lsb_wr = dn_addr[12:10] == 3'b001 && dn_wr;
wire rom2_msb_wr = dn_addr[12:10] == 3'b010 && dn_wr;
wire rom2_lsb_wr = dn_addr[12:10] == 3'b011 && dn_wr;
// Program ROM - U2 - Most-significant bits
dpram #(10,4) rom1_msb
(
.clock_a(clk),
.address_a(ADDR[9:0]),
.wren_a(1'b0),
.data_a(),
.q_a(rom1_data_out_msb),
.clock_b(clk),
.address_b(dn_addr[9:0]),
.wren_b(rom1_msb_wr),
.data_b(dn_data[3:0]),
.q_b()
);
// Program ROM - U3 - Least-significant bits
dpram #(10,4) rom1_lsb
(
.clock_a(clk),
.address_a(ADDR[9:0]),
.wren_a(1'b0),
.data_a(),
.q_a(rom1_data_out_lsb),
.clock_b(clk),
.address_b(dn_addr[9:0]),
.wren_b(rom1_lsb_wr),
.data_b(dn_data[3:0]),
.q_b()
);
// Program ROM - U4 - Most-significant bits
dpram #(10,4) rom2_msb
(
.clock_a(clk),
.address_a(ADDR[9:0]),
.wren_a(1'b0),
.data_a(),
.q_a(rom2_data_out_msb),
.clock_b(clk),
.address_b(dn_addr[9:0]),
.wren_b(rom2_msb_wr),
.data_b(dn_data[3:0]),
.q_b()
);
// Program ROM - U5 - Least-significant bits
dpram #(10,4) rom2_lsb
(
.clock_a(clk),
.address_a(ADDR[9:0]),
.wren_a(1'b0),
.data_a(),
.q_a(rom2_data_out_lsb),
.clock_b(clk),
.address_b(dn_addr[9:0]),
.wren_b(rom2_lsb_wr),
.data_b(dn_data[3:0]),
.q_b()
);
// U38, U39, U40, U41, U42 - 2102 - Video RAM
// ------------------------------------------
// The original board used logic to allow CPU to write during VBLANK and the video system to read otherwise - I have used dual port RAM for simplicity
// In Blockade only 5-bits per address is used, but Comotion and others use 8-bits
// Data outs
wire [7:0] vram_data_out_cpu; // Data read by CPU
wire [7:0] vram_data_out; // Data read by video system
// Video RAM address select and write enable
wire vram_cs = ADDR[15] && !ADDR[12];
wire vram_we = vram_cs && !WR_N;
// U38, U39, U40, U41, U42 combined
dpram #(10,8) ram
(
.clock_a(clk),
.address_a(vram_read_addr),
.wren_a(),
.data_a(),
.q_a(vram_data_out),
.clock_b(clk),
.address_b(ADDR[9:0]),
.wren_b(vram_we),
.data_b(cpu_data_out),
.q_b(vram_data_out_cpu)
);
// U6, U7 - 2111 - Static RAM
// --------------------------
// Static RAM Data out
wire [7:0] sram_data_out;
// Static RAM address select and write enable
wire sram_cs = ADDR[15] && ADDR[12];
wire sram_we = sram_cs && !WR_N;
// U6, U7 combined
spram #(8,8) sram
(
.clk(clk),
.address(ADDR[7:0]),
.wren(sram_we),
.data(cpu_data_out),
.q(sram_data_out)
);
// U29, U43 - Graphics PROMs
// --------------------
// Blockade and CoMotion - each ROM is 256 x 4 bytes.
// Hustle - each ROM is 512 x 4 bytes.
// Combined to 8 bytes with U29 as most significant bits, U43 as least significant bits
// Graphics PROM data outs
wire [3:0] prom_data_out_lsb;
wire [3:0] prom_data_out_msb;
wire [7:0] prom_data_out = { prom_data_out_msb, prom_data_out_lsb } ;
// Graphics PROM read adress
wire [8:0] prom_addr = { vram_data_out[5:0], vcnt[2:0] };
// Graphics ROM download write enables
wire prom_msb_wr = dn_addr[12:9] == 4'b1000 && dn_wr;
wire prom_lsb_wr = dn_addr[12:9] == 4'b1001 && dn_wr;
// Graphics PROM - U29 - Most-significant bits
dpram #(9,4) prom_msb
(
.clock_a(clk),
.address_a(prom_addr),
.wren_a(1'b0),
.data_a(),
.q_a(prom_data_out_msb),
.clock_b(clk),
.address_b(dn_addr[8:0]),
.wren_b(prom_msb_wr),
.data_b(dn_data[3:0]),
.q_b()
);
// Graphics ROM - U43 - Least-significant bits
dpram #(9,4) prom_lsb
(
.clock_a(clk),
.address_a(prom_addr),
.wren_a(1'b0),
.data_a(),
.q_a(prom_data_out_lsb),
.clock_b(clk),
.address_b(dn_addr[8:0]),
.wren_b(prom_lsb_wr),
.data_b(dn_data[3:0]),
.q_b()
);
endmodule

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/*MIT License
Copyright (c) 2019 Gregory Hogan (Soltan_G42)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.*/
`timescale 1 ps / 1 ps
module blockade_lpf
(
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 64;
reg signed [17:0] A2;
reg signed [17:0] B2;
reg signed [17:0] B1;
wire signed [15:0] audio_post_lpf1;
// Parameters calculated for a cut-off frequency of 723.43Hz
always @ (*) begin
A2 = -18'd32312;
B1 = 18'd228;
B2 = 18'd228;
end
iir_1st_order lpf6db(.clk(clk),
.reset(reset),
.div(div),
.A2(A2),
.B1(B1),
.B2(B2),
.in(in),
.out(audio_post_lpf1));
assign out = audio_post_lpf1;
endmodule

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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/*============================================================================
Generic dual-port RAM module
Author: Jim Gregory - https://github.com/JimmyStones/
Version: 1.0
Date: 2021-07-03
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>.
===========================================================================*/
`timescale 1 ps / 1 ps
module dpram #(
parameter address_width = 10,
parameter data_width = 8,
parameter init_file= ""
) (
input wire clock_a,
input wire wren_a,
input wire [address_width-1:0] address_a,
input wire [data_width-1:0] data_a,
output reg [data_width-1:0] q_a,
input wire clock_b,
input wire wren_b,
input wire [address_width-1:0] address_b,
input wire [data_width-1:0] data_b,
output reg [data_width-1:0] q_b
);
localparam ramLength = (2**address_width);
reg [data_width-1:0] mem [ramLength-1:0];
initial begin
if (init_file>0) $readmemh(init_file, mem);
end
always @(posedge clock_a) begin
q_a <= mem[address_a];
if(wren_a) begin
q_a <= data_a;
mem[address_a] <= data_a;
end
end
always @(posedge clock_b) begin
q_b <= mem[address_b];
if(wren_b) begin
q_b <= data_b;
mem[address_b] <= data_b;
end
end
endmodule

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/*MIT License
Copyright (c) 2019 Gregory Hogan (Soltan_G42)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.*/
`timescale 1 ps / 1 ps
module iir_1st_order
#(
parameter COEFF_WIDTH = 18,
parameter COEFF_SCALE = 15,
parameter DATA_WIDTH = 16,
parameter COUNT_BITS = 10
)
(
input clk,
input reset,
input [COUNT_BITS - 1 : 0] div,
input signed [COEFF_WIDTH - 1 : 0] A2, B1, B2,
input signed [DATA_WIDTH - 1 :0] in,
output [DATA_WIDTH - 1:0] out
);
reg signed [DATA_WIDTH-1:0] x0,x1,y0;
reg signed [DATA_WIDTH + COEFF_WIDTH - 1 : 0] out32;
reg [COUNT_BITS - 1:0] count;
// Usage:
// Design your 1st order iir low/high-pass with a tool that will give you the
// filter coefficients for the difference equation. Filter coefficients can
// be generated in Octave/matlab/scipy using a command similar to
// [B, A] = butter( 1, 3500/(106528/2), 'low') for a 3500 hz 1st order low-pass
// assuming 106528Hz sample rate.
//
// The Matlab output is:
// B = [0.093863 0.093863]
// A = [1.00000 -0.81227]
//
// Then scale coefficients by multiplying by 2^COEFF_SCALE and round to nearest integer
//
// B = [3076 3076]
// A = [32768 -26616]
//
// Discard A(1) because it is assumed 1.0 before scaling
//
// This leaves you with A2 = -26616 , B1 = 3076 , B2 = 3076
// B1 + B2 - A2 should sum to 2^COEFF_SCALE = 32768
//
// Sample frequency is "clk rate/div": for Genesis this is 53.69mhz/504 = 106528hz
//
// COEFF_WIDTH must be at least COEFF_SCALE+1 and must be large enough to
// handle temporary overflow during this computation: out32 <= (B1*x0 + B2*x1) - A2*y0
assign out = y0;
always @ (posedge clk) begin
out32 <= (B1*x0 + B2*x1) - A2*y0; //Previous output is y0 not y1
end
always @ (posedge clk) begin
if(reset) begin
count <= 0;
x0 <= 0;
x1 <= 0;
y0 <= 0;
end
else begin
count <= count + 1'd1;
if (count == div - 1) begin
count <= 0;
y0 <= {out32[DATA_WIDTH + COEFF_WIDTH - 1] , out32[COEFF_SCALE + DATA_WIDTH - 2 : COEFF_SCALE]};
x1 <= x0;
x0 <= in;
end
end
end
endmodule //iir_1st_order
module iir_2nd_order
#(
parameter COEFF_WIDTH = 18,
parameter COEFF_SCALE = 14,
parameter DATA_WIDTH = 16,
parameter COUNT_BITS = 10
)
(
input clk,
input reset,
input [COUNT_BITS - 1 : 0] div,
input signed [COEFF_WIDTH - 1 : 0] A2, A3, B1, B2, B3,
input signed [DATA_WIDTH - 1 : 0] in,
output [DATA_WIDTH - 1 : 0] out
);
reg signed [DATA_WIDTH-1 : 0] x0,x1,x2;
reg signed [DATA_WIDTH-1 : 0] y0,y1;
reg signed [(DATA_WIDTH + COEFF_WIDTH - 1) : 0] out32;
reg [COUNT_BITS : 0] count;
// Usage:
// Design your 1st order iir low/high-pass with a tool that will give you the
// filter coefficients for the difference equation. Filter coefficients can
// be generated in Octave/matlab/scipy using a command similar to
// [B, A] = butter( 2, 5000/(48000/2), 'low') for a 5000 hz 2nd order low-pass
// assuming 48000Hz sample rate.
//
// Output is:
// B = [ 0.072231 0.144462 0.072231]
// A = [1.00000 -1.10923 0.39815]
//
// Then scale coefficients by multiplying by 2^COEFF_SCALE and round to nearest integer
// Make sure your coefficients can be stored as a signed number with COEFF_WIDTH bits.
//
// B = [1183 2367 1183]
// A = [16384 -18174 6523]
//
// Discard A(1) because it is assumed 1.0 before scaling
//
// This leaves you with A2 = -18174 , A3 = 6523, B1 = 1183 , B2 = 2367 , B3 = 1183
// B1 + B2 + B3 - A2 - A3 should sum to 2^COEFF_SCALE = 16384
//
// Sample frequency is "clk rate/div"
//
// COEFF_WIDTH must be at least COEFF_SCALE+1 and must be large enough to
// handle temporary overflow during this computation:
// out32 <= (B1*x0 + B2*x1 + B3*x2) - (A2*y0 + A3*y1);
assign out = y0;
always @ (*) begin
out32 <= (B1*x0 + B2*x1 + B3*x2) - (A2*y0 + A3*y1); //Previous output is y0 not y1
end
always @ (posedge clk) begin
if(reset) begin
count <= 0;
x0 <= 0;
x1 <= 0;
x2 <= 0;
y0 <= 0;
y1 <= 0;
end
else begin
count <= count + 1'd1;
if (count == div - 1) begin
count <= 0;
y1 <= y0;
y0 <= {out32[DATA_WIDTH + COEFF_WIDTH - 1] , out32[(DATA_WIDTH + COEFF_SCALE - 2) : COEFF_SCALE]};
x2 <= x1;
x1 <= x0;
x0 <= in;
end
end
end
endmodule //iir_2nd_order

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/* This file is part of JT_FRAME.
JTFRAME program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTFRAME program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTFRAME. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 25-9-2019 */
module jtframe_resync(
input clk,
input pxl_cen,
input hs_in,
input vs_in,
input LVBL,
input LHBL,
input [3:0] hoffset,
input [3:0] voffset,
output reg hs_out,
output reg vs_out
);
parameter CNTW = 10; // max 1024 pixels/lines
reg [CNTW-1:0] hs_pos[0:1], vs_hpos[0:1], vs_vpos[0:1],// relative positions of the original sync pulses
hs_len[0:1], vs_len[0:1], // count the length of the original sync pulses
hs_cnt, vs_cnt, // count the position of the original sync pulses
hs_hold, vs_hold;
reg last_LHBL, last_LVBL, last_hsin, last_vsin;
wire hb_edge, hs_edge, hs_n_edge, vb_edge, vs_edge, vs_n_edge;
reg field;
wire [CNTW-1:0] hpos_off = { {CNTW-4{hoffset[3]}}, hoffset[3:0] };
wire [CNTW-1:0] htrip = hs_pos[field] + hpos_off;
wire [CNTW-1:0] vs_htrip = vs_hpos[field] + hpos_off;
wire [CNTW-1:0] vs_vtrip = vs_vpos[field] + { {CNTW-4{voffset[3]}}, voffset[3:0] };
assign hb_edge = LHBL && !last_LHBL;
assign hs_edge = hs_in && !last_hsin;
assign hs_n_edge = !hs_in && last_hsin;
assign vb_edge = LVBL && !last_LVBL;
assign vs_edge = vs_in && !last_vsin;
assign vs_n_edge = !vs_in && last_vsin;
always @(posedge clk) if(pxl_cen) begin
last_LHBL <= LHBL;
last_LVBL <= LVBL;
last_hsin <= hs_in;
last_vsin <= vs_in;
hs_cnt <= hb_edge ? {CNTW{1'b0}} : hs_cnt+1'b1;
if( vb_edge ) begin
vs_cnt <= {CNTW{1'b0}};
field <= ~field;
end else if(hb_edge)
vs_cnt <= vs_cnt+1'b1;
// Horizontal
if( hs_edge ) hs_pos[field] <= hs_cnt;
if( hs_n_edge ) hs_len[field] <= hs_cnt - hs_pos[field];
if( hs_cnt == htrip ) begin
hs_out <= 1;
hs_hold <= hs_len[field] - 1'b1;
end else begin
if( |hs_hold ) hs_hold <= hs_hold - 1'b1;
if( hs_hold == 0 ) hs_out <= 0;
end
// Vertical
if( vs_edge ) begin
vs_hpos[field] <= hs_cnt;
vs_vpos[field] <= vs_cnt;
end
if( vs_n_edge ) vs_len[field] <= vs_cnt - vs_vpos[field];
if( hs_cnt == vs_htrip ) begin
if( vs_cnt == vs_vtrip ) begin
vs_hold <= vs_len[field] - 1'b1;
vs_out <= 1;
end else begin
if( |vs_hold ) vs_hold <= vs_hold - 1'b1;
if( vs_hold == 0 ) vs_out <= 0;
end
end
end
`ifdef SIMULATION
initial begin
hs_cnt = {CNTW{1'b0}};
vs_cnt = {CNTW{1'b0}};
hs_out = 0;
vs_out = 0;
end
`endif
endmodule

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Arcade_MiST/Gremlin Blockade Hardware/rtl/pause.v Normal file
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//============================================================================
// Generic pause handling for MiSTer cores.
//
// https://github.com/JimmyStones/Pause_MiSTer
//
// Copyright (c) 2021 Jim Gregory
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
/*
Features:
- Pause can be triggered by user input, hiscore module or OSD opening (optionally controlled by setting in OSD)
- When paused the RGB outputs will be halved after 10 seconds to reduce burn-in (optionally controlled by setting in OSD)
- Reset signal will cancel user triggered pause
Version history:
0001 - 2021-03-15 - First marked release
0002 - 2021-08-28 - Add optional output of dim_video signal
0003 - 2021-09-22 - Convert dim_video to sequential logic to ease timing issues
0004 - 2021-10-07 - Convert pause_cpu to sequential logic to ease timing issues
============================================================================
*/
module pause #(
parameter RW=8, // Width of red channel
parameter GW=8, // Width of green channel
parameter BW=8, // Width of blue channel
parameter CLKSPD = 12 // Main clock speed in MHz
)
(
input clk_sys, // Core system clock (should match HPS module)
input reset, // CPU reset signal (active-high)
input user_button, // User pause button signal (active-high)
input pause_request, // Pause requested by other code (active-high)
input [1:0] options, // Pause options from OSD
// [0] = pause in OSD (active-high)
// [1] = dim video (active-high)
input OSD_STATUS, // OSD is open (active-high)
input [(RW-1):0] r, // Red channel
input [(GW-1):0] g, // Green channel
input [(BW-1):0] b, // Blue channel
output reg pause_cpu, // Pause signal to CPU (active-high)
`ifdef PAUSE_OUTPUT_DIM
output reg dim_video, // Dim video requested (active-high)
`endif
output [(RW+GW+BW-1):0] rgb_out // RGB output to arcade_video module
);
// Option constants
localparam pause_in_osd = 1'b0; // Index in options for Pause when in OSD
localparam dim_video_timer= 1'b1; // Index in options for Dim video after 10 seconds
localparam dim_timeout = (CLKSPD*10000000); // Time until video output dim (10 seconds @ CLKSPD Mhz)
reg pause_toggle = 1'b0; // User paused (active-high)
reg [31:0] pause_timer = 1'b0; // Time since pause
`ifndef PAUSE_OUTPUT_DIM
reg dim_video; // Dim video requested (active-high)
`endif
always @(posedge clk_sys) begin
// Track user pause button down
reg user_button_last;
user_button_last <= user_button;
if(!user_button_last & user_button) pause_toggle <= ~pause_toggle;
// Clear user pause on reset
if(pause_toggle && reset) pause_toggle <= 0;
if(reset)
begin
pause_cpu <= 1'b0;
end
else
begin
pause_cpu <= (pause_request | pause_toggle | (OSD_STATUS & options[pause_in_osd]));
end
if(pause_cpu && options[dim_video_timer])
begin
// Track pause duration for video dim
if(pause_timer<dim_timeout)
begin
pause_timer <= pause_timer + 1'b1;
dim_video <= 1'b0;
end
else
begin
dim_video <= 1'b1;
end
end
else
begin
dim_video <= 1'b0;
pause_timer <= 1'b0;
end
end
assign rgb_out = dim_video ? {r >> 1,g >> 1, b >> 1} : {r,g,b};
endmodule

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Arcade_MiST/Gremlin Blockade Hardware/rtl/pll.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

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Arcade_MiST/Gremlin Blockade Hardware/rtl/pll.vhd Normal file
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-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 13,
clk0_duty_cycle => 50,
clk0_multiply_by => 10,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "13"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.769230"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.79000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "13"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

2048
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/*============================================================================
Generic single-port RAM module
Author: Jim Gregory - https://github.com/JimmyStones/
Version: 1.0
Date: 2022-01-28
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>.
===========================================================================*/
`timescale 1 ps / 1 ps
module spram # (
parameter address_width = 8,
parameter data_width = 8,
parameter init_file= ""
)
(
input clk,
input [(address_width-1):0] address,
input [(data_width-1):0] data,
output reg [(data_width-1):0] q,
input wren
);
localparam ramLength = (2**address_width);
reg [(data_width-1):0] mem [ramLength-1:0];
initial begin
if (init_file>0) $readmemh(init_file, mem);
end
always @(posedge clk)
begin
if (wren)
begin
mem[address] <= data;
q <= data;
end
else
begin
q <= mem[address];
end
end
endmodule

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`timescale 1 ps / 1 ps
//
// Copyright (c) 2014-2018 by 1801BM1@gmail.com
// Licensed under CC-BY 3.0 (https://creativecommons.org/licenses/by/3.0/)
//
//______________________________________________________________________________
//
// vm80a wrapper for direct replacement of microprocessor package
// extra high-speed clock should be provided to operate, F1 and F2
// phases serve as clock enable gates
//
module vm80a
(
input pin_clk, // global module clock (no in original 8080)
input pin_f1, // clock phase 1 (used as clock enable)
input pin_f2, // clock phase 2 (used as clock enable)
input pin_reset, // module reset
output[15:0] pin_a, // address bus outputs
inout [7:0] pin_d, // data bus inouts
input pin_hold, //
output pin_hlda, //
input pin_ready, //
output pin_wait, //
input pin_int, //
output pin_inte, //
output pin_sync, //
output pin_dbin, //
output pin_wr_n
);
wire pin_aena, pin_dena;
wire [7:0] pin_din, pin_dout;
wire [15:0] pin_addr;
reg f1_core, f2_core;
assign pin_a = pin_aena ? pin_addr : 16'hZZZZ;
assign pin_d = pin_dena ? pin_dout : 8'hZZ;
assign pin_din = pin_d;
always @(posedge pin_clk)
begin
f1_core <= pin_f1;
f2_core <= pin_f2;
end
vm80a_core core
(
.pin_clk (pin_clk),
.pin_f1 (f1_core),
.pin_f2 (f2_core),
.pin_reset (pin_reset),
.pin_a (pin_addr),
.pin_dout (pin_dout),
.pin_din (pin_din),
.pin_aena (pin_aena),
.pin_dena (pin_dena),
.pin_hold (pin_hold),
.pin_hlda (pin_hlda),
.pin_ready (pin_ready),
.pin_wait (pin_wait),
.pin_int (pin_int),
.pin_inte (pin_inte),
.pin_sync (pin_sync),
.pin_dbin (pin_dbin),
.pin_wr_n (pin_wr_n)
);
endmodule
module vm80a_core
(
input pin_clk, // global module clock (no in original 8080)
input pin_f1, // clock phase 1 (used as clock enable)
input pin_f2, // clock phase 2 (used as clock enable)
input pin_reset, // module reset
output[15:0] pin_a, // address bus outputs
output[7:0] pin_dout, // data bus output
input [7:0] pin_din, // data bus input
output pin_aena, // address outputs enable
output pin_dena, // data outputs enable
input pin_hold, //
output pin_hlda, //
input pin_ready, //
output pin_wait, //
input pin_int, //
output pin_inte, //
output pin_sync, //
output pin_dbin, //
output pin_wr_n
);
//______________________________________________________________________________
//
wire [7:0] d;
reg [7:0] db, di;
reg [15:0] a;
wire clk, f1, f2;
reg abufena, db_ena, db_stb, dbin_pin, dbin_ext;
reg reset;
wire ready;
reg t851, t404, t382, t383, t712, t735, t773;
reg hold, hlda_pin;
wire hlda, h889;
reg wr_n, t1124, t1011, sync;
wire ready_int;
reg [15:0] r16_pc, r16_hl, r16_de, r16_bc, r16_sp, r16_wz, mxo;
wire [15:0] mxi;
wire mxr0, mxr1, mxr2, mxr3, mxr4, mxr5;
wire mxwh, mxwl, mxrh, mxrl, mxw16, mxwadr;
wire dec16, inc16, iad16;
reg xchg_dh, xchg_tt, t3144;
wire t1460, t1467, t1513, t1514, t1519;
wire sy_inta, sy_wo_n, sy_hlta, sy_out, sy_m1, sy_inp, sy_memr;
reg sy_stack;
wire thalt, twt2;
reg t1, t2, tw, t3, t4, t5;
reg t1f1, t2f1, twf1, t3f1, t4f1, t5f1;
reg m1, m2, m3, m4, m5;
reg m1f1, m2f1, m3f1, m4f1, m5f1;
wire start, ms0, ms1, m836, m839, m871;
reg eom, t789, t887, t953, t976, t980;
reg intr, inta, inte, mstart, minta;
wire irq;
reg [7:0] i;
reg i25, i14, i03;
wire imx, acc_sel;
wire id_op, id_io, id_in, id_popsw, id_pupsw,
id_nop, id_lxi, id_inx, id_inr, id_dcr, id_idr, id_mvi, id_dad,
id_dcx, id_opa, id_idm, id_hlt, id_mov, id_opm, id_pop, id_rst,
id_cxx, id_jxx, id_rxx, id_ret, id_jmp, id_opi, id_out, id_11x,
id_rlc, id_rxc, id_rar, id_sha, id_daa, id_cma, id_stc, id_cmc,
id_add, id_adc, id_sub, id_sbb, id_ana, id_xra, id_ora, id_cmp,
id_lsax, id_mvim, id_shld, id_lhld, id_mvmr, id_mvrm, id_push,
id_xthl, id_sphl, id_pchl, id_xchg, id_call, id_eidi, id_stlda;
wire id80, id81, id82, id83, id84, id85, id86, id00, id01,
id02, id03, id04, id05, id06, id07, id08, id09, id10;
wire goto, jmpflag;
reg jmptake, tree0, tree1, tree2;
reg t2806, t2817, t2819, t3047, t2998, t3363, t3403, t3335, t3361;
reg [7:0] xr, r, acc;
/* verilator lint_off UNOPTFLAT */
wire [7:0] x, s, c;
/* verilator lint_on UNOPTFLAT */
wire cl, ch, daa, daa_6x, daa_x6;
wire a398;
reg a327, a357, a358;
wire alu_xout, alu_xwr, alu_xrd, alu_ald, alu_awr, alu_ard,
alu_rld, alu_r00, alu_rwr, alu_srd, alu_zrd, alu_frd;
reg psw_z, psw_s, psw_p, psw_c, psw_ac, tmp_c;
reg t2222, t1375, t1497, t1698, t1668, t1780, t1993, t1994;
reg psw_ld, psw_wr, t2046, t2133, t2175;
//_____________________________________________________________________________
//
assign clk = pin_clk;
assign f1 = pin_f1;
assign f2 = pin_f2;
assign pin_a = a;
assign pin_aena = abufena;
assign pin_dout = db;
assign pin_dena = db_ena;
assign d[7] = ~reset & ~alu_zrd &
( dbin_ext & di[7]
| mxrl & mxo[7]
| mxrh & mxo[15]
| t1f1 & sy_memr
| alu_xrd & xr[7]
| alu_ard & acc[7]
| alu_frd & psw_s
| alu_srd & s[7] );
assign d[6] = ~reset & ~alu_zrd &
( dbin_ext & di[6]
| mxrl & mxo[6]
| mxrh & mxo[14]
| t1f1 & sy_inp
| alu_xrd & xr[6]
| alu_ard & acc[6]
| alu_frd & psw_z
| alu_srd & s[6] );
assign d[5] = ~reset & ~alu_zrd &
( dbin_ext & di[5]
| mxrl & mxo[5]
| mxrh & mxo[13]
| t1f1 & sy_m1
| alu_xrd & xr[5]
| alu_ard & acc[5]
| alu_frd & 1'b0
| alu_srd & s[5] );
assign d[4] = ~reset & ~alu_zrd &
( dbin_ext & di[4]
| mxrl & mxo[4]
| mxrh & mxo[12]
| t1f1 & sy_out
| alu_xrd & xr[4]
| alu_ard & acc[4]
| alu_frd & psw_ac
| alu_srd & s[4] );
assign d[3] = ~reset & ~alu_zrd &
( dbin_ext & di[3]
| mxrl & mxo[3]
| mxrh & mxo[11]
| t1f1 & sy_hlta
| alu_xrd & xr[3]
| alu_ard & acc[3]
| alu_frd & 1'b0
| alu_srd & s[3] );
assign d[2] = ~reset & ~alu_zrd &
( dbin_ext & di[2]
| mxrl & mxo[2]
| mxrh & mxo[10]
| t1f1 & sy_stack
| alu_xrd & xr[2]
| alu_ard & acc[2]
| alu_frd & psw_p
| alu_srd & s[2] );
assign d[1] = ~reset & ~alu_zrd &
( dbin_ext & di[1]
| mxrl & mxo[1]
| mxrh & mxo[9]
| t1f1 & sy_wo_n
| alu_xrd & xr[1]
| alu_ard & acc[1]
| alu_frd & 1'b1
| alu_srd & s[1] );
assign d[0] = ~reset & ~alu_zrd &
( dbin_ext & di[0]
| mxrl & mxo[0]
| mxrh & mxo[8]
| t1f1 & sy_inta
| alu_xrd & xr[0]
| alu_ard & acc[0]
| alu_frd & psw_c
| alu_srd & s[0] );
always @(posedge clk)
begin
if (f2 & db_stb) db <= d;
if (f2) abufena <= (~twt2 | ~thalt) & ~hlda_pin;
if (f1) db_stb <= t1 | (~sy_wo_n & t2);
if (f1) t851 <= t1 | (~sy_wo_n & (t2 | tw | t3));
if (f2) db_ena <= ~reset & t851;
end
//______________________________________________________________________________
//
// reset input buffer
//
always @(posedge clk)
begin
if (f1) t404 <= pin_reset;
if (f2) reset <= t404;
end
//______________________________________________________________________________
//
// hold input buffer
//
assign pin_hlda = hlda_pin;
assign hlda = hold & (t773 | (t3 & sy_wo_n) | (~m1 & sy_hlta) | t735);
assign h889 = t2f1 | twf1;
always @(posedge clk)
begin
if (f1) t712 <= ~sy_wo_n & t3;
if (f2) t735 <= t712;
if (~f2) t382 <= pin_hold;
if (f2) t383 <= ((~t382 & hold) | t383); // extend the front detector pulse for entire F2 duration
if (~f2) t383 <= 1'b0;
if (f2) t773 <= hlda_pin;
if (f1) hlda_pin <= hlda;
end
always @(posedge clk)
begin
if (reset)
hold <= 1'b0;
else
if (f2)
begin
if (t382)
begin
if (~sy_inta & h889) hold <= 1'b1;
end
else
hold <= 1'b0;
end
end
//______________________________________________________________________________
//
assign pin_dbin = dbin_pin;
assign pin_wr_n = wr_n;
assign pin_sync = sync;
always @(posedge clk)
begin
dbin_ext <= (f2 | dbin_pin) & ((t1124 & (m1f1 | ~sy_hlta)) | dbin_ext);
if (dbin_pin) di <= pin_din;
if (f2) dbin_pin <= t1124 & (m1f1 | ~sy_hlta);
if (f2) sync <= ~ready_int & t1011;
if (f1) t1011 <= t1 & ~reset;
if (f1) t1124 <= (t2 | tw) & sy_wo_n;
if (f1) wr_n <= ~(t3 | tw) | ready_int | sy_wo_n;
end
//______________________________________________________________________________
//
// ready pin and internal circuits
//
assign ready_int = (m4 | m5) & id_dad;
assign ready = ready_int | pin_ready;
assign pin_wait = twf1;
//______________________________________________________________________________
//
// register unit - 6 16-bit registers
//
// r0 - pc
// r1 - hl, de
// r2 - de, hl
// r3 - bc
// r4 - sp
// r5 - wz
//
assign t1467 = tree1 | (id04 & t4f1 & ~id_xthl);
assign t1519 = tree2 | (id00 & t4f1 & ~id_xthl);
assign mxi = inc16 ? (a + 16'h0001)
: dec16 ? (a - 16'h0001)
: a;
assign inc16 = iad16 & ~dec16;
assign dec16 = iad16 & id05 & (t4f1 | t5f1 | m4f1 | m5f1);
assign iad16 = ~(id00 & (t4f1 | t5f1)) & (~minta | m5 | t3144);
assign mxw16 = t3403;
assign mxwadr = t3363 | (t4f1 & ~id_dad & ~id_hlt);
assign t1513 = (t4f1 & id07) | t3335;
assign t1514 = (t4f1 & id08) | t3361;
assign mxrh = t2998 | (id08 & t4f1 & ~i03);
assign mxrl = t3047 | (id08 & t4f1 & i03);
assign mxwh = t2817 | (t2806 & ~i03);
assign mxwl = t2819 | (t2806 & i03);
assign mxr0 = tree0;
assign mxr1 = xchg_dh & (((t1513 | t1514) & (~i14 & i25)) | t1519)
| ~xchg_dh & (t1513 | t1514) & (i14 & ~i25);
assign mxr2 = xchg_dh & (t1513 | t1514) & (i14 & ~i25)
| ~xchg_dh & (((t1513 | t1514) & (~i14 & i25)) | t1519);
assign mxr3 = (t1513 | t1514) & (~i14 & ~i25);
assign mxr4 = t1467 | (t1513 & i14 & i25);
assign mxr5 = ~(t1467 | t1513 | t1514 | t1519 | mxr0);
always @ (posedge clk)
begin
if (f1) t3144 <= t4 | t5 | (m4 & ~id02);
xchg_tt <= id_xchg & t2;
xchg_dh <= ~reset & ((xchg_tt & ~(id_xchg & t2)) ? ~xchg_dh : xchg_dh);
end
always @ (*)
case ({mxr0, mxr1, mxr2, mxr3, mxr4, mxr5})
6'b100000: mxo = r16_pc;
6'b010000: mxo = r16_hl;
6'b001000: mxo = r16_de;
6'b000100: mxo = r16_bc;
6'b000010: mxo = r16_sp;
6'b000001: mxo = r16_wz;
default: mxo = 16'h0000;
endcase
always @ (posedge clk)
if (f2)
begin
if (mxwadr) a <= mxo;
if (mxw16)
begin
if (mxr0) r16_pc <= mxi;
if (mxr1) r16_hl <= mxi;
if (mxr2) r16_de <= mxi;
if (mxr3) r16_bc <= mxi;
if (mxr4) r16_sp <= mxi;
if (mxr5) r16_wz <= mxi;
end
else
begin
if (mxwl)
begin
if (mxr0) r16_pc[7:0] <= d;
if (mxr1) r16_hl[7:0] <= d;
if (mxr2) r16_de[7:0] <= d;
if (mxr3) r16_bc[7:0] <= d;
if (mxr4) r16_sp[7:0] <= d;
if (mxr5) r16_wz[7:0] <= d;
end
if (mxwh)
begin
if (mxr0) r16_pc[15:8] <= d;
if (mxr1) r16_hl[15:8] <= d;
if (mxr2) r16_de[15:8] <= d;
if (mxr3) r16_bc[15:8] <= d;
if (mxr4) r16_sp[15:8] <= d;
if (mxr5) r16_wz[15:8] <= d;
end
end
end
//______________________________________________________________________________
//
// processor state
//
assign sy_hlta = id_hlt;
assign sy_m1 = m1;
assign sy_inp = m5 & id_in;
assign sy_out = m5 & id_out;
assign sy_inta = inta;
assign sy_memr = sy_wo_n & ~sy_inp & ~minta;
assign sy_wo_n = m1 | m2 | m3 | (((m4 & ~id86) | (m5 & ~id85)) & ~ready_int);
always @(posedge clk)
begin
if (f1)
begin
sy_stack <= (t1 & t1460)
| (t3 & m3 & id_cxx & ~jmptake)
| (t5 & m1 & id_rxx & ~jmptake);
end
end
//______________________________________________________________________________
//
// ticks state machine
//
assign twt2 = (t2f1 | twf1) & ~start;
assign thalt = ~m1 & sy_hlta;
always @(posedge clk)
begin
if (f1)
begin
t1f1 <= t1 & ~reset; // ensure the reliable start after reset
t2f1 <= t2;
twf1 <= tw;
t3f1 <= t3;
t4f1 <= t4;
t5f1 <= t5;
end
if (f2)
begin
t1 <= start;
t2 <= ~start & t1f1;
tw <= ~start & (t2f1 | twf1) & (~ready | thalt);
t3 <= ~start & (t2f1 | twf1) & ready & ~thalt;
t4 <= ~start & t3f1 & ms0 & ~ms1;
t5 <= ~start & t4f1 & ms0 & ~ms1;
end
end
//______________________________________________________________________________
//
assign m836 = m1f1 & id82;
assign m839 = ~t976 | ~sy_hlta;
assign m871 = t789 | id81;
assign start = ~m839
| t953
| (eom & ~(hold & t887))
| (f2 & ((~t382 & hold) | t383) & ~(twf1 | t3f1 | t4f1 | t5f1));
assign ms0 = ~reset & m839 & ~(sy_stack & ~t1f1) & ~(eom & ~m836);
assign ms1 = ~reset & m839 & ~(sy_stack & ~t1f1) & ~(m871 & ~m836) & eom;
always @(posedge clk)
begin
if (f1)
begin
t789 <= (id84 & m3) | (id83 & ~id_mvim & m4) | m5;
t887 <= hold;
t953 <= reset;
t976 <= t980 & m4;
eom <= t5
| t4 & m1 & id80
| t3 & m2
| t3 & m3
| t3 & m4
| t3 & m5 & ~id_xthl;
end
if (f2)
begin
t980 <= sy_inta;
end
end
//______________________________________________________________________________
//
// processor cycles state machine
//
always @(posedge clk)
begin
if (f1)
begin
m1f1 <= m1;
m2f1 <= m2;
m3f1 <= m3;
m4f1 <= m4;
m5f1 <= m5;
end
if (f2)
begin
m1 <= (~ms0 & ~ms1) | (~ms1 & m1f1);
m2 <= (~ms0 | ~ms1) & ((ms0 & m2f1) | (ms1 & m1f1));
m3 <= (ms0 & m3f1) | (ms1 & m2f1);
m4 <= (ms0 & m4f1) | (ms1 & m3f1) | (ms0 & ms1);
m5 <= (ms0 & m5f1) | (ms1 & m4f1);
end
end
//______________________________________________________________________________
//
// interrupt logic
//
assign irq = intr & inte & ~reset & ~hold;
assign pin_inte = inte;
always @(posedge clk)
begin
if (f2) intr <= pin_int;
if (f2) mstart <= ~ms0 & ~ms1;
if (sy_inta) minta <= 1;
if (f1 & t1 & m1) minta <= 0;
end
always @(posedge clk or posedge reset)
begin
if (reset)
begin
inta <= 0;
inte <= 0;
end
else
begin
if (f1)
begin
if (irq & ((tw & sy_hlta) | (mstart & ~id_eidi))) inta <= 1;
if (~intr | id_eidi | (t5 & id_rst)) inta <= 0;
end
if (f2)
begin
if (t1f1 & id_eidi) inte <= i[3];
if (t1f1 & sy_inta) inte <= 0;
end
end
end
//______________________________________________________________________________
//
// instruction register and decoder
//
function cmp
(
input [7:0] i,
input [7:0] c,
input [7:0] m
);
cmp = &(~(i ^ c) | m);
endfunction
assign imx = ~(id_op | (id_mov & t4));
assign acc_sel = imx ? (i[5:3] == 3'b111) : (i[2:0] == 3'b111);
assign jmpflag = (psw_c & i14 & ~i25) // Intel original: d[0] instead of psw_c
| (psw_p & ~i14 & i25) // Intel original: d[2] instead of psw_p
| (psw_z & ~i14 & ~i25) // Intel original: d[6] instead of psw_z
| (psw_s & i14 & i25); // Intel original: d[7] instead of psw_s
always @(posedge clk)
begin
//
// Simplify the D-bus multiplexer and feed the I-register by input pins directly
// if (f2 & dbin_pin & (reset | (m1 & t3))) i <= pin_din;
//
if (~f2 & (reset | (m1 & t3))) i <= pin_din;
if (f1)
begin
i25 <= imx ? i[5] : i[2];
i14 <= imx ? i[4] : i[1];
i03 <= imx ? i[3] : i[0];
end
end
assign goto = id_rst | id_jmp | id_call | (jmptake & (id_cxx | id_jxx));
assign t1460 = (t1 & ((m2 & id00)
| (m3 & id00)
| (m4 & (id01 | id04))
| (m5 & (id01 | id04)))
| t2 & ( (m2 & id00)
| (m4 & id01)
| (m5 & id01))
| t3 & ( (m4 & (id04 | id_sphl)))
| t5 & ( (m1 & (id04 | id_sphl)))) & ~(~jmptake & id_cxx & t5);
always @(posedge clk)
begin
if (f2 & t4f1)
begin
jmptake <= i03 ? jmpflag : ~jmpflag;
end
if (f1)
begin
tree0 <= t1 & ( (m1 & ~goto)
| (m2 & ~id_xthl)
| (m3 & ~id_xthl)
| (m4 & id02))
| t2 & ( m1
| (m2 & ~id_xthl)
| (m3 & ~id_xthl)
| (m4 & (id02 | id_rst | id_cxx | id_call))
| (m5 & (id_rst | id_cxx | id_call)))
| t3 & ( (m4 & (id_ret | id_rxx))
| (m5 & (id_ret | id_rxx)))
| t5 & id_pchl;
tree1 <= t1460;
tree2 <= t1 & ( (m4 & (id_mov | id_idr | id_op))
| (m5 & id08))
| t2 & ( (m4 & (id_shld | id00 | id_dad))
| (m5 & (id_shld | id00 | id_dad)))
| t3 & ( (m4 & (id_lhld | id_dad))
| (m5 & (id_lhld | id_dad)))
| t5 & m5;
t2806 <= id08 & ((t3 & m4) | (t5 & m1));
t2817 <= reset | (t3 & (m1 | m3 | (m4 & id_io) | (m5 & id06)));
t2819 <= reset | (t3 & (m2 | (m4 & id06) | (m5 & id_rst)));
t3047 <= (t1 | t2) & m4 & id_dad
| t2 & ((m4 & id_shld) | (m5 & id03));
t2998 <= (t1 | t2) & m5 & id_dad
| t2 & ((m5 & id_shld) | (m4 & id03));
t3403 <= t2 & ( (m1 | m2)
| (m3 & ~id_xthl)
| ((m4 | m5) & ~id_dad & ~id09))
| t3 & m4 & id09
| t5 & (m5 | (m1 & ~id08));
t3363 <= t1 & (m1 | m2 | m3 | ((m4 | m5) & ~id_hlt & ~id_dad));
t3335 <= id07 & ((t1 & (m4 | m5)) | (t3 & (m2 | m3)) | t5);
t3361 <= t1 & m4 & id_lsax
| t2 & id10 & ~sy_wo_n
| t3 & id10 & sy_wo_n & (m4 | m5)
| t5 & id08 & m1;
end
end
assign id_nop = cmp(i, 8'b00xxx000, 8'b00111000);
assign id_lxi = cmp(i, 8'b00xx0001, 8'b00110000);
assign id_lsax = cmp(i, 8'b000xx010, 8'b00011000);
assign id_inx = cmp(i, 8'b00xx0011, 8'b00110000);
assign id_inr = cmp(i, 8'b00xxx100, 8'b00111000);
assign id_dcr = cmp(i, 8'b00xxx101, 8'b00111000);
assign id_idr = cmp(i, 8'b00xxx10x, 8'b00111001);
assign id_mvi = cmp(i, 8'b00xxx110, 8'b00111000);
assign id_dad = cmp(i, 8'b00xx1001, 8'b00110000);
assign id_dcx = cmp(i, 8'b00xx1011, 8'b00110000);
assign id_opa = cmp(i, 8'b00xxx111, 8'b00111000);
assign id_idm = cmp(i, 8'b0011010x, 8'b00000001);
assign id_stlda = cmp(i, 8'b0011x010, 8'b00001000);
assign id_mvim = cmp(i, 8'b00110110, 8'b00000000);
assign id_shld = cmp(i, 8'b00100010, 8'b00000000);
assign id_lhld = cmp(i, 8'b00101010, 8'b00000000);
assign id_mvmr = cmp(i, 8'b01110xxx, 8'b00000111) & ~id_hlt;
assign id_mvrm = cmp(i, 8'b01xxx110, 8'b00111000) & ~id_hlt;
assign id_hlt = cmp(i, 8'b01110110, 8'b00000000);
assign id_mov = cmp(i, 8'b01xxxxxx, 8'b00111111);
assign id_op = cmp(i, 8'b10xxxxxx, 8'b00111111);
assign id_opm = cmp(i, 8'b10xxx110, 8'b00111000);
assign id_pop = cmp(i, 8'b11xx0001, 8'b00110000);
assign id_push = cmp(i, 8'b11xx0101, 8'b00110000);
assign id_rst = cmp(i, 8'b11xxx111, 8'b00111000);
assign id_xthl = cmp(i, 8'b11100011, 8'b00000000);
assign id_sphl = cmp(i, 8'b11111001, 8'b00000000);
assign id_pchl = cmp(i, 8'b11101001, 8'b00000000);
assign id_xchg = cmp(i, 8'b11101011, 8'b00000000);
assign id_cxx = cmp(i, 8'b11xxx100, 8'b00111000);
assign id_jxx = cmp(i, 8'b11xxx010, 8'b00111000);
assign id_rxx = cmp(i, 8'b11xxx000, 8'b00111000);
assign id_ret = cmp(i, 8'b110x1001, 8'b00010000);
assign id_call = cmp(i, 8'b11xx1101, 8'b00110000);
assign id_eidi = cmp(i, 8'b1111x011, 8'b00001000);
assign id_jmp = cmp(i, 8'b1100x011, 8'b00001000);
assign id_io = cmp(i, 8'b1101x011, 8'b00001000);
assign id_opi = cmp(i, 8'b11xxx110, 8'b00111000);
assign id_in = cmp(i, 8'b11011011, 8'b00000000);
assign id_popsw = cmp(i, 8'b11110001, 8'b00000000);
assign id_out = cmp(i, 8'b11010011, 8'b00000000);
assign id_11x = cmp(i, 8'b11xxxxxx, 8'b00111111);
assign id_pupsw = cmp(i, 8'b11110101, 8'b00000000);
assign id_rxc = ~i[5] & i[3] & id_opa;
assign id_sha = ~i[5] & id_opa;
assign id_rlc = (i[5:3] == 3'b000) & id_opa;
assign id_rar = (i[5:3] == 3'b011) & id_opa;
assign id_daa = (i[5:3] == 3'b100) & id_opa;
assign id_cma = (i[5:3] == 3'b101) & id_opa;
assign id_stc = (i[5:3] == 3'b110) & id_opa;
assign id_cmc = (i[5:3] == 3'b111) & id_opa;
assign id_add = (i[5:3] == 3'b000) & (id_op | id_opi);
assign id_adc = (i[5:3] == 3'b001) & (id_op | id_opi);
assign id_sub = (i[5:3] == 3'b010) & (id_op | id_opi);
assign id_sbb = (i[5:3] == 3'b011) & (id_op | id_opi);
assign id_ana = (i[5:3] == 3'b100) & (id_op | id_opi);
assign id_xra = (i[5:3] == 3'b101) & (id_op | id_opi);
assign id_ora = (i[5:3] == 3'b110) & (id_op | id_opi);
assign id_cmp = (i[5:3] == 3'b111) & (id_op | id_opi);
assign id80 = id_lxi | id_pop | id_opm | id_idm | id_dad
| id_xthl | id_xchg | id_jxx | id_ret | id_eidi
| id_nop | id_stlda | id_mvmr | id_mvrm | id_hlt
| id_opa | id_mvim | id_jmp | id_io | id_opi
| id_mvi | id_lsax | id_lhld | id_shld | id_op;
assign id81 = id_dcx | id_inx | id_sphl | id_pchl | id_xchg
| id_eidi | id_nop | id_opa | id_op | id_mov
| (id_idr & ~id82);
assign id82 = id_pop | id_push | id_opm | id_idm | id_dad
| id_rst | id_ret | id_rxx | id_mvrm | id_mvmr
| id_hlt | id_mvim | id_io | id_opi | id_mvi
| id_lsax;
assign id83 = id_opm | id_stlda | id_mvmr | id_mvrm | id_opi
| id_mvi | id_lsax;
assign id84 = id_lxi | id_jxx | id_jmp;
assign id85 = id_push | id_idm | id_rst | id_xthl | id_cxx
| id_call | id_mvim | id_shld | (id_io & ~i[3]);
assign id86 = id_push | id_rst | id_xthl | id_cxx | id_call
| id_mvmr | id_shld | (~i[3] & (id_lsax | id_stlda));
assign id00 = id_xthl | id_pchl | id_sphl;
assign id01 = id_pop | id_rxx | id_ret;
assign id02 = id_mvi | id_opi | id_io;
assign id03 = id_rst | id_push | id_xthl | id_cxx | id_call;
assign id04 = id_rst | id_push | id_xthl | id_cxx | id_call;
assign id05 = id_rst | id_push | id_xthl | id_cxx | id_call | id_dcx;
assign id06 = id_pop | id_rxx | id_ret | id_dad | id_lhld | id_io;
assign id07 = id_dcx | id_inx | id_lxi | id_dad;
assign id08 = id_mov | id_mvi | id_idr | id_op;
assign id09 = id_rst | id_push | id_xthl | id_cxx | id_call | id_shld;
assign id10 = id_pop | id_push | id_mvrm | id_mvi;
//______________________________________________________________________________
//
// function alu
// (
// input rxc,
// input ora,
// input ana,
// input xra,
// input x,
// input r,
// input nc,
// input rn,
// input cp
// );
// alu = x & r & cp & ~(rxc | ora | ana | xra)
// | nc & (cp | x | r) & ~(rxc | ora | ana | xra)
// | rxc & rn
// | ora & (x | r)
// | ana & (x & r)
// | xra & (x ^ r);
// endfunction
//
//
// assign s[0] = alu(id_rxc, id_ora, id_ana, id_xra, x[0], r[0], ~c[0], r[1], cl) | (id_rlc & c[7]);
// assign s[1] = alu(id_rxc, id_ora, id_ana, id_xra, x[1], r[1], ~c[1], r[2], c[0]);
// assign s[2] = alu(id_rxc, id_ora, id_ana, id_xra, x[2], r[2], ~c[2], r[3], c[1]);
// assign s[3] = alu(id_rxc, id_ora, id_ana, id_xra, x[3], r[3], ~c[3], r[4], c[2]);
// assign s[4] = alu(id_rxc, id_ora, id_ana, id_xra, x[4], r[4], ~c[4], r[5], c[3]);
// assign s[5] = alu(id_rxc, id_ora, id_ana, id_xra, x[5], r[5], ~c[5], r[6], c[4]);
// assign s[6] = alu(id_rxc, id_ora, id_ana, id_xra, x[6], r[6], ~c[6], r[7], c[5]);
// assign s[7] = alu(id_rxc, id_ora, id_ana, id_xra, x[7], r[7], ~c[7], ch, c[6]);
//
//______________________________________________________________________________
//
// arithmetic and logic unit
//
// assign alu_xwr = (f1 & m1 & t3) | (f2 & (a327 | t4f1 & (id_out | ~id_11x)));
//
assign alu_xwr = (a327 | t4f1 & (id_rst | id_out | ~id_11x));
assign alu_xout = ~(id_sub | id_sbb | id_cmp | id_cma);
assign alu_xrd = t1698 | a358;
assign x = alu_xout ? xr : ~xr;
assign alu_ald = t2222 & ( id_adc | id_add | id_daa | id_xra | id_sbb
| id_sub | id_ana | id_ora | id_sha | id_cma);
assign alu_ard = t1375 | a398;
assign alu_awr = t1497 | a357;
assign alu_r00 = id_dcr & t4f1;
assign alu_srd = t1668;
assign alu_rwr = t1780;
assign alu_rld = t4f1 & (id_sha | id_op | id_opi);
assign daa = id_daa & t4f1;
assign daa_x6 = (acc[3] & (acc[2] | acc[1])) | psw_ac;
assign daa_6x = ((acc[3] & (acc[2] | acc[1])) & acc[4] & acc[7])
| (acc[7] & (acc[6] | acc[5])) | tmp_c;
/* verilator lint_off WIDTH */
assign s = {7'b0000000, id_rlc & c[7]}
| ((id_rxc | id_ora | id_ana | id_xra) ? 8'h00 : (x + r + cl))
| (id_rxc ? {ch, r[7:1]} : 8'h00)
| (id_ora ? (x | r) : 8'h00)
| (id_ana ? (x & r) : 8'h00)
| (id_xra ? (x ^ r) : 8'h00);
/* verilator lint_on WIDTH */
assign cl = tmp_c & ~id_daa & ~id_rlc & ~id_ora & ~id_xra & ~id_rxc;
assign ch = tmp_c & id_rar | r[0] & ~id_rar;
//
// wire ca0_n, ca2_n, ca1, ca3;
// assign ca0_n = ~(cl & (x[0] | r[0])) & ~(x[0] & r[0]) & ~(id_ana & id_rxc);
// assign ca2_n = ~(ca1 & (x[2] | r[2])) & ~(x[2] & r[2]) & ~(id_ana & id_rxc);
// assign ca1 = ~(~x[1] & ~r[1]) & ~(ca0_n & (~x[1] | ~r[1])) & ~(id_ora | id_rxc | id_xra);
// assign ca3 = ~(~x[3] & ~r[3]) & ~(ca2_n & (~x[3] | ~r[3])) & ~(id_ora | id_rxc | id_xra);
//
assign c[0] = (r[0] & x[0]) | (cl & (r[0] | x[0]));
assign c[1] = (r[1] & x[1]) | (c[0] & (r[1] | x[1]));
assign c[2] = (r[2] & x[2]) | (c[1] & (r[2] | x[2]));
assign c[3] = (r[3] & x[3]) | (c[2] & (r[3] | x[3]));
assign c[4] = (r[4] & x[4]) | (c[3] & (r[4] | x[4]));
assign c[5] = (r[5] & x[5]) | (c[4] & (r[5] | x[5]));
assign c[6] = (r[6] & x[6]) | (c[5] & (r[6] | x[6]));
assign c[7] = (r[7] & x[7]) | (c[6] & (r[7] | x[7]));
assign alu_zrd = m1f1 & t3f1;
assign alu_frd = t2046; /* | t4f1 & (id_11x & ~id_out);
// as we do need to translate flags on the bus for conditional unit anymore */
assign a398 = t1993 & ((t1994 & id08) | id_opa | id_stlda | id_lsax | id_io);
always @(posedge clk)
begin
if (f1)
begin
t1375 <= t2 & m4 & id_pupsw;
t1497 <= t3 & m5 & id_popsw;
t1698 <= t5 & m1 & ~id_inr & ~id_dcr
| t3 & m5 & id_rst;
t1668 <= t2 & m5 & (id_inr | id_dcr)
| t3 & m5 & id_dad
| t3 & m4 & id_dad
| t5 & m1 & (id_inr | id_dcr);
t1780 <= t3 & m1
| t1 & (m4 | m5) & id_dad;
t2222 <= (t2 & m1) | (t1 & m5);
a327 <= t3 & m4 & ~(id_dad | id_out | id_rst)
| t2 & (m4 | m5) & id_dad;
a357 <= t3 & m5 & (id_io | id_mvim) & sy_wo_n
| t3 & m4 & (id_stlda | id_lsax | id_mvmr) & sy_wo_n
| acc_sel & id08 & (t5 & m1 | t3 & m4);
a358 <= t2 & ~sy_wo_n & (id_io | id_mvim | id_stlda | id_lsax | id_mvmr);
psw_ld <= t3 & m4 & id_popsw;
psw_wr <= t2 & m1 & (id_opi | id_inr | id_dcr | id_daa | id_op);
t2046 <= t2 & m5 & id_pupsw; /* | reset | t3 & m1; */
//
// t2047 <= reset
// | t3 & m1
// | t3 & m5 & id_rst;
//
t1993 <= t4 & m1;
t1994 <= acc_sel;
t2133 <= ~id_rxc & c[7];
t2175 <= t3 & m1
| t2 & m5 & id_dad;
end
end
always @(posedge clk)
begin
if (f2)
begin
if (alu_xwr) xr <= id_rst ? (i & 8'b00111000) : d;
if (alu_awr) acc <= d;
if (alu_ald) acc <= s;
if (alu_rld) r <= acc;
if (alu_rwr) r <= d;
if (alu_r00) r <= 8'hff;
if (daa)
begin
r[1] <= daa_x6;
r[2] <= daa_x6;
r[5] <= daa_6x;
r[6] <= daa_6x;
end
if (psw_ld)
begin
psw_c <= d[0]; // x register was in original Intel design
psw_p <= d[2];
psw_ac <= d[4];
psw_z <= d[6];
psw_s <= d[7];
end
if (psw_wr)
begin
psw_p <= ~(^s);
psw_ac <= (c[3] & ~id_xra & ~id_ora & ~id_rxc) | (id_ana & (x[3] | r[3]));
psw_z <= ~(|s);
psw_s <= s[7];
end
if (t2222)
begin
if (id_xra | id_stc | id_ora | id_ana | id_cmc)
psw_c <= ~tmp_c;
if (id_cmp | id_sbb | id_sub)
psw_c <= ~(t2133 | id_rxc & x[0]);
if (id_dad | id_sha | id_adc | id_add)
psw_c <= t2133 | id_rxc & x[0];
end
if (daa & daa_6x)
psw_c <= 1'b1;
if (t2175)
tmp_c <= psw_c;
if (t4f1)
begin
if (id_sbb)
tmp_c <= ~psw_c;
if (id_inr | id_ora | id_xra | id_ana | id_cmp | id_sub)
tmp_c <= 1'b1;
if (id_dad | id_cma | id_dcr | id_add | id_stc)
tmp_c <= 1'b0;
end
end
end
//______________________________________________________________________________
//
endmodule