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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-02-06 16:24:49 +00:00

Merge pull request #132 from gyurco/master

SonSon: fix audio, add DIPs
This commit is contained in:
Marcel
2022-02-20 11:08:58 +01:00
committed by GitHub
7 changed files with 51 additions and 45 deletions

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@@ -7,7 +7,7 @@ MiST port usage
===============
- Create ROM file from the MRA file using the MRA utility.
Example: mra -z /path/to/mame/roms SonSon.mra
Example: mra -A -z /path/to/mame/roms SonSon.mra
- Copy the ROM files to the root of the SD Card
- Copy the RBF files to the SD Card

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@@ -5,6 +5,20 @@
<manufacturer>Capcom</manufacturer>
<rbf>sonson</rbf>
<switches base="8" page_id="1" page_name="Switches">
<!-- DSW1 -->
<dip bits="0,3" name="Coinage" ids="1C_1C,1C_2C,1C_3C,1C_4C,1C_5C,1C_6C,1C_7C,2C_1C,2C_3C,2C_5C,3C_1C,3C_2C,3C_4C,4C_1C,4C_3C,Free Play"/>
<dip bits="5" name="Demo Sounds" ids="Off,On"/>
<dip bits="6" name="Service" ids="Off,On"/>
<!-- dip bits="7" name="Flip Screen" ids="Off,On"/-->
<!-- DSW2 -->
<dip bits="8,9" name="Lives" ids="3,4,5,7"/>
<dip bits="11,12" name="Bonus_Life" ids="20000,30000,20k/80k/100k,30k/90k/120k"/>
<dip bits="13,14" name="Difficulty" ids="Easy,Normal,Hard,Very Hard"/>
<dip bits="15" name="Freeze" ids="Off,On"/>
</switches>
<rom index="0" zip="sonson.zip" md5="d17bc11db95dd6e2d44ac342b3462259" type="merged|nonmerged">
<!-- CPU2, 8k -->
<part name="ss_6.c11"/>

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@@ -35,9 +35,7 @@ localparam CONF_STR = {
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blending,Off,On;",
"O6,Freeze,Off,On;",
//"O7,Flip,Off,On;",
"O8,Test,Off,On;",
"DIP;",
"T0,Reset;",
"V,v1.0.",`BUILD_DATE
};
@@ -45,9 +43,9 @@ localparam CONF_STR = {
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire freeze = status[6];
wire flip = status[7];
wire test = status[8];
wire [7:0] dip1 = status[15:8];
wire [7:0] dip2 = status[23:16];
assign LED = ~ioctl_downl;
assign SDRAM_CKE = 1;
@@ -204,8 +202,8 @@ target_top target_top(
.clk_sys(clk_sys),
.clk_vid_en(clk_vid_en),
.reset_in(reset),
.snd_l(snd_l),
.snd_r(snd_r),
.snd_l(snd_l),
.snd_r(snd_r),
.vid_hs(hs),
.vid_vs(vs),
.vid_hb(hb),
@@ -216,8 +214,8 @@ target_top target_top(
.inputs_p1(~{2'b00,m_down,m_up,m_right,m_left,1'b0,m_fireA}),
.inputs_p2(~{2'b00,m_down2,m_up2,m_right2,m_left2,1'b0,m_fire2A}),
.inputs_sys(~{2'b00,m_coin2,m_coin1,2'b00,m_two_players,m_one_player}),
.inputs_dip1(~{flip,test,6'b011111}),
.inputs_dip2(~{freeze,7'b1111111}),
.inputs_dip1(~dip1),
.inputs_dip2(~dip2),
.cpu_rom_addr(cpu_rom_addr),
.cpu_rom_do(cpu_rom_addr[0] ? rom_do[15:8] : rom_do[7:0]),
.snd_rom_addr(snd_rom_addr),

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@@ -40,9 +40,6 @@ end entity PACE;
architecture SYN of PACE is
constant CLK_1US_COUNTS : integer :=
integer(27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY);
signal to_tilemap_ctl : to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
signal from_tilemap_ctl : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
@@ -52,10 +49,10 @@ architecture SYN of PACE is
signal to_sprite_reg : to_SPRITE_REG_t;
signal to_sprite_ctl : to_SPRITE_CTL_t;
signal from_sprite_ctl : from_SPRITE_CTL_t;
signal spr0_hit : std_logic;
signal spr0_hit : std_logic;
signal to_graphics : to_GRAPHICS_t;
signal from_graphics : from_GRAPHICS_t;
signal from_graphics : from_GRAPHICS_t;
signal snd_irq : std_logic;
signal snd_data : std_logic_vector(7 downto 0);
@@ -88,7 +85,7 @@ begin
sprite_reg_o => to_sprite_reg,
sprite_i => from_sprite_ctl,
sprite_o => to_sprite_ctl,
spr0_hit => spr0_hit,
spr0_hit => spr0_hit,
graphics_i => from_graphics,
graphics_o => to_graphics,
@@ -100,9 +97,9 @@ begin
platform_i => platform_i,
platform_o => platform_o,
cpu_rom_addr => cpu_rom_addr,
cpu_rom_do => cpu_rom_do,
cpu_rom_do => cpu_rom_do,
tile_rom_addr => tile_rom_addr,
tile_rom_do => tile_rom_do
tile_rom_do => tile_rom_do
);
graphics_inst : entity work.Graphics
@@ -135,7 +132,6 @@ begin
sound_irq => snd_irq,
sound_data => snd_data,
vblank => video_out.vblank,
audio_out_l => audio_o.ldata(9 downto 0),
audio_out_r => audio_o.rdata(9 downto 0),

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@@ -193,7 +193,7 @@ begin
end if;
end process;
cpu_reset <= rst_24M;
cpu_reset <= rst_24M;
cpu_inst : mc6809i
port map

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@@ -12,7 +12,6 @@ port(
clkrst_i : in from_CLKRST_t;
sound_irq : in std_logic;
sound_data : in std_logic_vector(7 downto 0);
vblank : in std_logic;
audio_out_l : out std_logic_vector(9 downto 0);
audio_out_r : out std_logic_vector(9 downto 0);
snd_rom_addr : out std_logic_vector(12 downto 0);
@@ -82,8 +81,6 @@ END COMPONENT;
signal ay2_chan_c : std_logic_vector(7 downto 0);
signal ay2_do : std_logic_vector(7 downto 0);
signal vblank_r : std_logic;
begin
-- cs
@@ -125,35 +122,36 @@ begin
end process;
process (clk, reset)
variable count : unsigned(16 downto 0);
begin
if reset = '1' then
cpu_irq <= '0';
elsif rising_edge(clk) then
vblank_r <= vblank;
if vblank_r = '0' and vblank = '1' then
count := count + 1;
if count = 100000 then -- 60Hz*4
cpu_irq <= '1';
count := (others => '0');
elsif cpu_ba = '0' and cpu_bs = '1' then
cpu_irq <= '0';
end if;
end if;
end process;
cpu_inst : mc6809i
port map
(
cpu_inst : mc6809i
port map (
D => cpu_di,
DOut => cpu_do,
ADDR => cpu_addr,
RnW => cpu_rw,
E => clk_E,
Q => clk_Q,
BS => cpu_bs,
BA => cpu_ba,
nIRQ => not cpu_irq,
BS => cpu_bs,
BA => cpu_ba,
nIRQ => not cpu_irq,
nFIRQ => sound_irq,
nNMI => '1',
AVMA => open,
BUSY => open,
nNMI => '1',
AVMA => open,
BUSY => open,
LIC => open,
nHALT => '1',
nRESET => not reset,
@@ -179,13 +177,13 @@ begin
ENA => clk_en_snd,
RESET_L => not reset,
I_A8 => '1',
I_A9_L => not ay1_cs,
I_BDIR => not cpu_rw,
I_BC1 => not cpu_addr(0) or cpu_rw,
I_A9_L => '0',
I_BDIR => ay1_cs and not cpu_rw,
I_BC1 => ay1_cs and not cpu_addr(0) and not cpu_rw,
I_DA => cpu_do,
O_DA => ay1_do,
O_AUDIO_L => audio_out_l,
O_AUDIO_L => audio_out_l,
I_IOA => (others => '0'),
@@ -198,13 +196,13 @@ begin
ENA => clk_en_snd,
RESET_L => not reset,
I_A8 => '1',
I_A9_L => not ay2_cs,
I_BDIR => not cpu_rw,
I_BC1 => not cpu_addr(0) or cpu_rw,
I_A9_L => '0',
I_BDIR => ay2_cs and not cpu_rw,
I_BC1 => ay2_cs and not cpu_addr(0) and not cpu_rw,
I_DA => cpu_do,
O_DA => ay2_do,
O_AUDIO_L => audio_out_r,
O_AUDIO_L => audio_out_r,
I_IOA => (others => '0'),

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@@ -225,7 +225,7 @@ set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/dec_315_5013.vhd
set_global_assignment -name VHDL_FILE rtl/dec_315_5061.vhd
set_global_assignment -name VERILOG_FILE rtl/Sega_Crypt.v
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
set_global_assignment -name SIGNALTAP_FILE output_files/zaxx.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top