mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-02-06 16:24:49 +00:00
@@ -7,7 +7,7 @@ MiST port usage
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===============
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- Create ROM file from the MRA file using the MRA utility.
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Example: mra -z /path/to/mame/roms SonSon.mra
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Example: mra -A -z /path/to/mame/roms SonSon.mra
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- Copy the ROM files to the root of the SD Card
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- Copy the RBF files to the SD Card
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@@ -5,6 +5,20 @@
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<manufacturer>Capcom</manufacturer>
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<rbf>sonson</rbf>
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<switches base="8" page_id="1" page_name="Switches">
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<!-- DSW1 -->
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<dip bits="0,3" name="Coinage" ids="1C_1C,1C_2C,1C_3C,1C_4C,1C_5C,1C_6C,1C_7C,2C_1C,2C_3C,2C_5C,3C_1C,3C_2C,3C_4C,4C_1C,4C_3C,Free Play"/>
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<dip bits="5" name="Demo Sounds" ids="Off,On"/>
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<dip bits="6" name="Service" ids="Off,On"/>
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<!-- dip bits="7" name="Flip Screen" ids="Off,On"/-->
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<!-- DSW2 -->
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<dip bits="8,9" name="Lives" ids="3,4,5,7"/>
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<dip bits="11,12" name="Bonus_Life" ids="20000,30000,20k/80k/100k,30k/90k/120k"/>
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<dip bits="13,14" name="Difficulty" ids="Easy,Normal,Hard,Very Hard"/>
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<dip bits="15" name="Freeze" ids="Off,On"/>
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</switches>
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<rom index="0" zip="sonson.zip" md5="d17bc11db95dd6e2d44ac342b3462259" type="merged|nonmerged">
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<!-- CPU2, 8k -->
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<part name="ss_6.c11"/>
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@@ -35,9 +35,7 @@ localparam CONF_STR = {
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"O2,Rotate Controls,Off,On;",
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"O34,Scanlines,Off,25%,50%,75%;",
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"O5,Blending,Off,On;",
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"O6,Freeze,Off,On;",
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//"O7,Flip,Off,On;",
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"O8,Test,Off,On;",
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"DIP;",
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"T0,Reset;",
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"V,v1.0.",`BUILD_DATE
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};
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@@ -45,9 +43,9 @@ localparam CONF_STR = {
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wire rotate = status[2];
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wire [1:0] scanlines = status[4:3];
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wire blend = status[5];
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wire freeze = status[6];
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wire flip = status[7];
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wire test = status[8];
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wire [7:0] dip1 = status[15:8];
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wire [7:0] dip2 = status[23:16];
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assign LED = ~ioctl_downl;
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assign SDRAM_CKE = 1;
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@@ -204,8 +202,8 @@ target_top target_top(
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.clk_sys(clk_sys),
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.clk_vid_en(clk_vid_en),
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.reset_in(reset),
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.snd_l(snd_l),
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.snd_r(snd_r),
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.snd_l(snd_l),
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.snd_r(snd_r),
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.vid_hs(hs),
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.vid_vs(vs),
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.vid_hb(hb),
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@@ -216,8 +214,8 @@ target_top target_top(
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.inputs_p1(~{2'b00,m_down,m_up,m_right,m_left,1'b0,m_fireA}),
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.inputs_p2(~{2'b00,m_down2,m_up2,m_right2,m_left2,1'b0,m_fire2A}),
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.inputs_sys(~{2'b00,m_coin2,m_coin1,2'b00,m_two_players,m_one_player}),
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.inputs_dip1(~{flip,test,6'b011111}),
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.inputs_dip2(~{freeze,7'b1111111}),
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.inputs_dip1(~dip1),
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.inputs_dip2(~dip2),
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.cpu_rom_addr(cpu_rom_addr),
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.cpu_rom_do(cpu_rom_addr[0] ? rom_do[15:8] : rom_do[7:0]),
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.snd_rom_addr(snd_rom_addr),
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@@ -40,9 +40,6 @@ end entity PACE;
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architecture SYN of PACE is
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constant CLK_1US_COUNTS : integer :=
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integer(27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY);
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signal to_tilemap_ctl : to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
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signal from_tilemap_ctl : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
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@@ -52,10 +49,10 @@ architecture SYN of PACE is
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signal to_sprite_reg : to_SPRITE_REG_t;
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signal to_sprite_ctl : to_SPRITE_CTL_t;
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signal from_sprite_ctl : from_SPRITE_CTL_t;
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signal spr0_hit : std_logic;
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signal spr0_hit : std_logic;
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signal to_graphics : to_GRAPHICS_t;
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signal from_graphics : from_GRAPHICS_t;
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signal from_graphics : from_GRAPHICS_t;
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signal snd_irq : std_logic;
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signal snd_data : std_logic_vector(7 downto 0);
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@@ -88,7 +85,7 @@ begin
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sprite_reg_o => to_sprite_reg,
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sprite_i => from_sprite_ctl,
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sprite_o => to_sprite_ctl,
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spr0_hit => spr0_hit,
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spr0_hit => spr0_hit,
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graphics_i => from_graphics,
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graphics_o => to_graphics,
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@@ -100,9 +97,9 @@ begin
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platform_i => platform_i,
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platform_o => platform_o,
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cpu_rom_addr => cpu_rom_addr,
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cpu_rom_do => cpu_rom_do,
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cpu_rom_do => cpu_rom_do,
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tile_rom_addr => tile_rom_addr,
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tile_rom_do => tile_rom_do
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tile_rom_do => tile_rom_do
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);
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graphics_inst : entity work.Graphics
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@@ -135,7 +132,6 @@ begin
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sound_irq => snd_irq,
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sound_data => snd_data,
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vblank => video_out.vblank,
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audio_out_l => audio_o.ldata(9 downto 0),
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audio_out_r => audio_o.rdata(9 downto 0),
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@@ -193,7 +193,7 @@ begin
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end if;
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end process;
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cpu_reset <= rst_24M;
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cpu_reset <= rst_24M;
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cpu_inst : mc6809i
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port map
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@@ -12,7 +12,6 @@ port(
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clkrst_i : in from_CLKRST_t;
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sound_irq : in std_logic;
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sound_data : in std_logic_vector(7 downto 0);
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vblank : in std_logic;
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audio_out_l : out std_logic_vector(9 downto 0);
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audio_out_r : out std_logic_vector(9 downto 0);
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snd_rom_addr : out std_logic_vector(12 downto 0);
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@@ -82,8 +81,6 @@ END COMPONENT;
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signal ay2_chan_c : std_logic_vector(7 downto 0);
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signal ay2_do : std_logic_vector(7 downto 0);
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signal vblank_r : std_logic;
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begin
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-- cs
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@@ -125,35 +122,36 @@ begin
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end process;
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process (clk, reset)
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variable count : unsigned(16 downto 0);
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begin
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if reset = '1' then
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cpu_irq <= '0';
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elsif rising_edge(clk) then
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vblank_r <= vblank;
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if vblank_r = '0' and vblank = '1' then
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count := count + 1;
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if count = 100000 then -- 60Hz*4
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cpu_irq <= '1';
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count := (others => '0');
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elsif cpu_ba = '0' and cpu_bs = '1' then
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cpu_irq <= '0';
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end if;
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end if;
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end process;
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cpu_inst : mc6809i
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port map
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(
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cpu_inst : mc6809i
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port map (
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D => cpu_di,
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DOut => cpu_do,
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ADDR => cpu_addr,
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RnW => cpu_rw,
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E => clk_E,
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Q => clk_Q,
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BS => cpu_bs,
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BA => cpu_ba,
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nIRQ => not cpu_irq,
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BS => cpu_bs,
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BA => cpu_ba,
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nIRQ => not cpu_irq,
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nFIRQ => sound_irq,
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nNMI => '1',
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AVMA => open,
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BUSY => open,
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nNMI => '1',
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AVMA => open,
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BUSY => open,
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LIC => open,
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nHALT => '1',
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nRESET => not reset,
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@@ -179,13 +177,13 @@ begin
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ENA => clk_en_snd,
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RESET_L => not reset,
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I_A8 => '1',
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I_A9_L => not ay1_cs,
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I_BDIR => not cpu_rw,
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I_BC1 => not cpu_addr(0) or cpu_rw,
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I_A9_L => '0',
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I_BDIR => ay1_cs and not cpu_rw,
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I_BC1 => ay1_cs and not cpu_addr(0) and not cpu_rw,
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I_DA => cpu_do,
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O_DA => ay1_do,
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O_AUDIO_L => audio_out_l,
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O_AUDIO_L => audio_out_l,
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I_IOA => (others => '0'),
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@@ -198,13 +196,13 @@ begin
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ENA => clk_en_snd,
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RESET_L => not reset,
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I_A8 => '1',
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I_A9_L => not ay2_cs,
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I_BDIR => not cpu_rw,
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I_BC1 => not cpu_addr(0) or cpu_rw,
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I_A9_L => '0',
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I_BDIR => ay2_cs and not cpu_rw,
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I_BC1 => ay2_cs and not cpu_addr(0) and not cpu_rw,
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I_DA => cpu_do,
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O_DA => ay2_do,
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O_AUDIO_L => audio_out_r,
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O_AUDIO_L => audio_out_r,
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I_IOA => (others => '0'),
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@@ -225,7 +225,7 @@ set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
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set_global_assignment -name VHDL_FILE rtl/dec_315_5013.vhd
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set_global_assignment -name VHDL_FILE rtl/dec_315_5061.vhd
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set_global_assignment -name VERILOG_FILE rtl/Sega_Crypt.v
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set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
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set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
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set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
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set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
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set_global_assignment -name SIGNALTAP_FILE output_files/zaxx.stp
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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Reference in New Issue
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