mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-03-09 20:18:22 +00:00
Add Williams HW v2 Code
This commit is contained in:
Marcel
@@ -3,7 +3,7 @@
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<year>1977</year>
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<manufacturer>Gremlin</manufacturer>
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<setname>mineswpr</setname>
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<setname>mineswpr4</setname>
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<mameversion>0229</mameversion>
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<rbf>blockade</rbf>
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@@ -16,7 +16,7 @@
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</switches>
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<rom index="1"><part>05</part></rom>
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<rom index="0" md5="none" zip="mineswpr.zip">
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<rom index="0" md5="none" zip="mineswpr.zip|mineswpr4.zip">
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<!-- GAME ROMS -->
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<part crc="none" name="mineswee.h0p"/>
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<part crc="none" name="mineswee.l0p"/>
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180
Arcade_MiST/Williams 6809 rev.2 Hardware/README
Normal file
180
Arcade_MiST/Williams 6809 rev.2 Hardware/README
Normal file
@@ -0,0 +1,180 @@
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-------------------------------------------------------------------------------
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-- Turkey shoot by Dar (darfpga@aol.fr) (05 March 2022)
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-- http://darfpga.blogspot.fr
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-- https://sourceforge.net/projects/darfpga/files
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-- github.com/darfpga
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--
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-- Terasic board MAX10 DE10 Lite
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-------------------------------------------------------------------------------
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-- gen_ram.vhd & io_ps2_keyboard
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--------------------------------
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-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
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-- http://www.syntiac.com/fpga64.html
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-------------------------------------------------------------------------------
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-- cpu09l - Version : 0128
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-- Synthesizable 6809 instruction compatible VHDL CPU core
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-- Copyright (C) 2003 - 2010 John Kent
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-------------------------------------------------------------------------------
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-- cpu68 - Version 9th Jan 2004 0.8
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-- 6800/01 compatible CPU core
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-- GNU public license - December 2002 : John E. Kent
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-------------------------------------------------------------------------------
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-- Educational use only
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-- Do not redistribute synthetized file with roms
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-- Do not redistribute roms whatever the form
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-- Use at your own risk
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-------------------------------------------------------------------------------
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-- Video 15KHz is OK,
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--
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-- This is not VGA, you have to use a TV set with SCART plug
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--
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-- SCART(TV) pin - signal - VGA(DE10) pin
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-- 15 - red - 1
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-- 11 - green - 2
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-- 7 - blue - 3
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-- 5,9,13 - gnd - 5,6,7
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-- (comp. sync)20 - csync - 13 (HS)
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-- (fast commut)16 - commut - 14 (VS)
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-- 17,18 - gnd - 8,10
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--
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-------------------------------------------------------------------------------
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-- Version 0.0 -- 05/03/2022 --
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-- initial version
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-------------------------------------------------------------------------------
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--
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-- Main features :
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-- PS2 keyboard input @gpio pins 35/34 (beware voltage translation/protection)
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-- Audio pwm output @gpio pins 1/3 (beware voltage translation/protection)
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--
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-- Uses 1 pll for 12MHz and 120MHz generation from 50MHz
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--
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-- Board key :
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-- 0 : reset game
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--
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-- Keyboard players inputs :
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--
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-- F3 : Add coin
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-- F2 : Start 2 players
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-- F1 : Start 1 player
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-- SPACE : Fire
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-- RIGHT arrow : Move gun right
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-- LEFT arrow : Move gun left
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-- UP arrow : Move gun up
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-- DOWN arrow : Move gun down
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-- CTRL : Gobble
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-- W(Z) : Grenade
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--
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-- Keyboard Service inputs French(english) :
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--
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-- A(Q) : advance
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-- U(U) : auto/up (!manual/down)
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-- H(H) : high score reset
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--
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-- To enter service mode press 'advance' key while in game over screen
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-- Enter service mode to tune game parameters (difficulty ...)
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-- Tuning are lost at power OFF, for permanent tuning edit/set parameters
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-- within tshoot_cmos_ram.vhd and recompile.
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--
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-------------------------------------------------------------------------------
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-- Use make_tshoot_proms.bat to build vhd file and bin from binaries
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-- Load sdram with external rom bank -> use sdram_loader_de10_lite.sof + key(0)
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-------------------------------------------------------------------------------
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-- Program sdram content with this turkey shoot rom bank loader before
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-- programming turkey shoot game core :
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--
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-- 1) program DE10_lite with tshoot sdram loader
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-- 2) press key(0) at least once (digit blinks during programming)
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-- 3) program DE10_lite with tshoot core without switching DE10_lite OFF
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-------------------------------------------------------------------------------
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-- Used ROMs by make_tshoot_proms.bat
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> turkey_shoot_prog1
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rom18.ic55 CRC(effc33f1)
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> turkey_shoot_prog2
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rom2.ic9" CRC(fd982687)
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rom3.ic10" CRC(9617054d)
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> turkey_shoot_bank_a
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rom17.ic26 CRC(b02d1ccd)
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rom15.ic24 CRC(11709935)
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> turkey_shoot_bank_b
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rom16.ic25 CRC(69ce38f8)
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rom14.ic23 CRC(769a4ae5)
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rom13.ic21 CRC(ec016c9b)
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rom12.ic19 CRC(98ae7afa)
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> turkey_shoot_bank_c
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rom11.ic18 CRC(60d5fab8)
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rom9.ic16 CRC(a4dd4a0e)
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rom7.ic14 CRC(f25505e6)
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rom5.ic12 CRC(94a7c0ed)
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> turkey_shoot_bank_d
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rom10.ic17 CRC(0f32bad8)
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rom8.ic15 CRC(e9b6cbf7)
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rom6.ic13 CRC(a49f617f)
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rom4.ic11 CRC(b026dc00)
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> turkey_shoot_sound
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rom1.ic8 CRC(011a94a7)
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> turkey_shoot_graph1
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rom20.ic57 CRC(c6e1d253)
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> turkey_shoot_graph2
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rom21.ic58 CRC(9874e90f)
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> turkey_shoot_graph3
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rom19.ic41 CRC(b9ce4d2a)
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-------------------------------------------------------------------------------
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-- Misc. info
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-------------------------------------------------------------------------------
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-- Main bus access
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-- > Main address bus and data bus by CPU 6809
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-- > Main address bus and data bus by DMA (blitter) while CPU is halted.
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--
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-- CPU and DMA can read/write anywhere from/to entire 64K address space
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-- including video ram, color palette, tile map, cmos_ram, peripherals, roms,
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-- switched rom banks, ...
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--
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-- Page register control allows to select misc. banked access (rom, ram).
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-------------------------------------------------------------------------------
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-- Video ram : 3 banks of 16Kx8 (dram with ras/cas)
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-- > interleaved bank access by CPU, 8bits read/write
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-- > interleaved bank access by DMA, 8bits read, 2x4bits independent write
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-- > simultaneous (3 banks) access by video scanner, 24bits at once
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--
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-- In original hardware, every 1us there is 1 access to video ram for CPU/DMA
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-- and 1 access for video scanner. Thus DMA read/write cycle required 2us when
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-- reading source is video ram. DMA read/write cycle required only 1us when
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-- reading source is not video ram.
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--
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-- Higher part of video ram is not displayed on screen and is used as working
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-- ram by CPU including stack (SP).
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-------------------------------------------------------------------------------
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-- Foreground (bitmap - video ram)
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-- > 24 bits / 1us => 6 horizontal pixels of 4bits (16 colors)
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-- > 6 bits register (64 color banks)
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-------------------------------------------------------------------------------
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-- Background (tile map : tile is 24x16 pixels)
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--
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-- > 16 horizontal tiles of 4x6 pixels, 16 vertical tiles of 16 pixels.
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-- > map ram 2048x8
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-- in : 7 bits horizontal (4 bits + scroll) + 4 bits vertical
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-- out : 128 possible tiles + flip control
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--
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-- > Graphics 3x8Kx8 roms
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-- in : 2 bits horizontal + 4 bits vertical + 7 bits tile code
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-- out : 24 bits = 6 pixels x 4 bits
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--
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-- > 24 bits / 1us => 6 horizontal pixels of 4bits (16 colors)
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-- > 3 bits register + 3 bits from vertical video scanner (64 color banks)
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-------------------------------------------------------------------------------
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-- Palette 1024 colors x 16 bits
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-- > in 10 bits from foreground or background data
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-- > out 4 bits red, 4 bits green, 4 bits blue, 4 bits intensity
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-------------------------------------------------------------------------------
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31
Arcade_MiST/Williams 6809 rev.2 Hardware/WilliamsHWv2.qpf
Normal file
31
Arcade_MiST/Williams 6809 rev.2 Hardware/WilliamsHWv2.qpf
Normal file
@@ -0,0 +1,31 @@
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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# Date created = 00:21:03 December 03, 2019
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "13.1"
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DATE = "00:21:03 December 03, 2019"
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# Revisions
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PROJECT_REVISION = "WilliamsHWv2"
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251
Arcade_MiST/Williams 6809 rev.2 Hardware/WilliamsHWv2.qsf
Normal file
251
Arcade_MiST/Williams 6809 rev.2 Hardware/WilliamsHWv2.qsf
Normal file
@@ -0,0 +1,251 @@
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2014 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
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||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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||||
# Altera or its authorized distributors. Please refer to the
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||||
# applicable agreement for further details.
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||||
#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
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# Date created = 19:39:51 March 07, 2022
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# WilliamsHWv2_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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# Project-Wide Assignments
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# ========================
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/WilliamsV2_MiST.sv
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set_global_assignment -name VHDL_FILE rtl/williams2.vhd
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set_global_assignment -name VHDL_FILE rtl/tshoot_sound_board.vhd
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set_global_assignment -name VHDL_FILE rtl/tshoot_cmos_ram.vhd
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set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
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set_global_assignment -name VHDL_FILE rtl/rtl_jkent/cpu09l_128.vhd
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set_global_assignment -name VHDL_FILE rtl/rom/turkey_shoot_decoder.vhd
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set_global_assignment -name VHDL_FILE rtl/rom/gray_code.vhd
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set_global_assignment -name VHDL_FILE rtl/rtl_pace/pia6821.vhd
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set_global_assignment -name VHDL_FILE rtl/rtl_jkent/cpu68_2.vhd
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
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set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
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set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip"
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# Pin & Location Assignments
|
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# ==========================
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set_location_assignment PIN_7 -to LED
|
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set_location_assignment PIN_54 -to CLOCK_27
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||||
set_location_assignment PIN_144 -to VGA_R[5]
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set_location_assignment PIN_143 -to VGA_R[4]
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||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
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set_location_assignment PIN_137 -to VGA_R[1]
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||||
set_location_assignment PIN_135 -to VGA_R[0]
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||||
set_location_assignment PIN_133 -to VGA_B[5]
|
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set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_4 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_6 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_8 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_10 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_11 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_28 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_50 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_30 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_32 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_global_assignment -name VERILOG_MACRO "EXT_ROM=<None>"
|
||||
set_global_assignment -name FORCE_SYNCH_CLEAR ON
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY WilliamsV2_MiST
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name ENABLE_NCE_PIN OFF
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
|
||||
# SignalTap II Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE output_files/tm.stp
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
# -----------------------------
|
||||
# start ENTITY(WilliamsV2_MiST)
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(WilliamsV2_MiST)
|
||||
# ---------------------------
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
134
Arcade_MiST/Williams 6809 rev.2 Hardware/WilliamsHWv2.sdc
Normal file
134
Arcade_MiST/Williams 6809 rev.2 Hardware/WilliamsHWv2.sdc
Normal file
@@ -0,0 +1,134 @@
|
||||
## Generated SDC file "vectrex_MiST.out.sdc"
|
||||
|
||||
## Copyright (C) 1991-2013 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
|
||||
|
||||
## DATE "Sun Jun 24 12:53:00 2018"
|
||||
|
||||
##
|
||||
## DEVICE "EP3C25E144C8"
|
||||
##
|
||||
|
||||
# Clock constraints
|
||||
|
||||
# Automatically constrain PLL and other generated clocks
|
||||
derive_pll_clocks -create_base_clocks
|
||||
|
||||
# Automatically calculate clock uncertainty to jitter and other effects.
|
||||
derive_clock_uncertainty
|
||||
|
||||
# tsu/th constraints
|
||||
|
||||
# tco constraints
|
||||
|
||||
# tpd constraints
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
|
||||
|
||||
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
|
||||
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
|
||||
|
||||
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
|
||||
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
set_output_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
|
||||
set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
|
||||
set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
|
||||
set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
|
||||
set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
|
||||
|
||||
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
set_multicycle_path -to {VGA_*[*]} -setup 2
|
||||
set_multicycle_path -to {VGA_*[*]} -hold 1
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
36
Arcade_MiST/Williams 6809 rev.2 Hardware/clean.bat
Normal file
36
Arcade_MiST/Williams 6809 rev.2 Hardware/clean.bat
Normal file
@@ -0,0 +1,36 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
del /s *~
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
rmdir /s /q hc_output
|
||||
rmdir /s /q .qsys_edit
|
||||
rmdir /s /q hps_isw_handoff
|
||||
rmdir /s /q sys\.qsys_edit
|
||||
rmdir /s /q sys\vip
|
||||
for /d %%i in (sys\*_sim) do rmdir /s /q "%%i"
|
||||
for /d %%i in (rtl\*_sim) do rmdir /s /q "%%i"
|
||||
del build_id.v
|
||||
del c5_pin_model_dump.txt
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del /s *.qws
|
||||
del /s *.ppf
|
||||
del /s *.ddb
|
||||
del /s *.csv
|
||||
del /s *.cmp
|
||||
del /s *.sip
|
||||
del /s *.spd
|
||||
del /s *.bsf
|
||||
del /s *.f
|
||||
del /s *.sopcinfo
|
||||
del /s *.xml
|
||||
del *.cdf
|
||||
del *.rpt
|
||||
del /s new_rtl_netlist
|
||||
del /s old_rtl_netlist
|
||||
pause
|
||||
325
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/WilliamsV2_MiST.sv
Normal file
325
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/WilliamsV2_MiST.sv
Normal file
@@ -0,0 +1,325 @@
|
||||
//============================================================================
|
||||
// Arcade: Williams V2 Hardware by DarFPGA
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//============================================================================
|
||||
|
||||
module WilliamsV2_MiST(
|
||||
output LED,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
inout SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input SPI_SS4,
|
||||
input CONF_DATA0,
|
||||
input CLOCK_27,
|
||||
output [12:0] SDRAM_A,
|
||||
inout [15:0] SDRAM_DQ,
|
||||
output SDRAM_DQML,
|
||||
output SDRAM_DQMH,
|
||||
output SDRAM_nWE,
|
||||
output SDRAM_nCAS,
|
||||
output SDRAM_nRAS,
|
||||
output SDRAM_nCS,
|
||||
output [1:0] SDRAM_BA,
|
||||
output SDRAM_CLK,
|
||||
output SDRAM_CKE
|
||||
);
|
||||
|
||||
`include "rtl/build_id.v"
|
||||
|
||||
localparam CONF_STR = {
|
||||
"TurkeyS;rom;",
|
||||
"O2,Rotate Controls,Off,On;",
|
||||
"O5,Blend,Off,On;",
|
||||
"O6,Autoup,Off,On;",
|
||||
"O8,Advance,Off,On;",
|
||||
"T9,Reset Highscores,Off,On;",
|
||||
"T0,Reset;",
|
||||
"V,v0.0.",`BUILD_DATE
|
||||
};
|
||||
|
||||
wire rotate = status[2];
|
||||
wire blend = status[5];
|
||||
wire autoup = status[6];
|
||||
wire advance = status[8];
|
||||
wire Hreset = status[9];
|
||||
|
||||
assign LED = ~ioctl_downl;
|
||||
assign SDRAM_CLK = clk48;
|
||||
assign SDRAM_CKE = 1;
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
|
||||
wire clk48, clk_sys, clk12;
|
||||
wire pll_locked;
|
||||
pll_mist pll(
|
||||
.inclk0(CLOCK_27),
|
||||
.areset(0),
|
||||
.c0(clk48),
|
||||
.c1(clk_sys),//24
|
||||
.c2(clk12),
|
||||
.locked(pll_locked)
|
||||
);
|
||||
|
||||
wire [63:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [31:0] joystick_0;
|
||||
wire [31:0] joystick_1;
|
||||
wire scandoublerD;
|
||||
wire ypbpr;
|
||||
wire no_csync;
|
||||
wire key_pressed;
|
||||
wire [7:0] key_code;
|
||||
wire key_strobe;
|
||||
|
||||
user_io #(
|
||||
.STRLEN(($size(CONF_STR)>>3)),
|
||||
.ROM_DIRECT_UPLOAD(1'b1))
|
||||
user_io(
|
||||
.clk_sys (clk_sys ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
.SPI_MISO (SPI_DO ),
|
||||
.SPI_MOSI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.no_csync (no_csync ),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.joystick_0 (joystick_0 ),
|
||||
.joystick_1 (joystick_1 ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
wire ioctl_downl;
|
||||
wire ioctl_upl;
|
||||
wire [7:0] ioctl_index;
|
||||
wire ioctl_wr;
|
||||
wire [24:0] ioctl_addr;
|
||||
wire [7:0] ioctl_dout;
|
||||
wire [7:0] ioctl_din;
|
||||
|
||||
data_io #(
|
||||
.ROM_DIRECT_UPLOAD(1'b1))
|
||||
data_io(
|
||||
.clk_sys ( clk_sys ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS2 ( SPI_SS2 ),
|
||||
.SPI_SS4 ( SPI_SS4 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.SPI_DO ( SPI_DO ),
|
||||
.ioctl_download( ioctl_downl ),
|
||||
.ioctl_upload ( ioctl_upl ),
|
||||
.ioctl_index ( ioctl_index ),
|
||||
.ioctl_wr ( ioctl_wr ),
|
||||
.ioctl_addr ( ioctl_addr ),
|
||||
.ioctl_dout ( ioctl_dout ),
|
||||
.ioctl_din ( ioctl_din )
|
||||
);
|
||||
|
||||
wire [24:0] sp_ioctl_addr = ioctl_addr - 18'h22000;//check
|
||||
|
||||
wire [13:0] prg_rom_addr;
|
||||
wire [7:0] prg_rom_do;
|
||||
wire [12:0] snd_rom_addr;
|
||||
wire [7:0] snd_rom_do;
|
||||
wire [16:0] bank_rom_addr;
|
||||
wire [7:0] bank_rom_do;
|
||||
wire [12:0] gfx_rom_addr;
|
||||
wire [23:0] gfx_rom_do;
|
||||
reg port1_req, port2_req;
|
||||
sdram sdram(
|
||||
.*,
|
||||
.init_n ( pll_locked ),
|
||||
.clk ( clk48 ),
|
||||
|
||||
// port1 used for main + sound CPUs
|
||||
.port1_req ( port1_req ),
|
||||
.port1_ack ( ),
|
||||
.port1_a ( ioctl_addr ),
|
||||
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
|
||||
.port1_we ( ioctl_downl ),
|
||||
.port1_d ( {ioctl_dout, ioctl_dout} ),
|
||||
.port1_q ( ),
|
||||
|
||||
.cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, prg_rom_addr[13:1]} ),
|
||||
.cpu1_q ( prg_rom_do ),
|
||||
|
||||
.cpu2_addr ( ioctl_downl ? 16'hffff : (16'h2000 + bank_rom_addr[16:1]) ),
|
||||
.cpu2_q ( bank_rom_do ),
|
||||
.cpu3_addr ( ioctl_downl ? 16'hffff : (16'hE000 + snd_rom_addr[12:1]) ),
|
||||
.cpu3_q ( snd_rom_do ),
|
||||
|
||||
// port2 for sprite graphics
|
||||
.port2_req ( port2_req ),
|
||||
.port2_ack ( ),
|
||||
.port2_a ( {sp_ioctl_addr[23:17], sp_ioctl_addr[14:0], sp_ioctl_addr[16]} ), // merge sprite roms to 32-bit wide words
|
||||
.port2_ds ( {sp_ioctl_addr[15], ~sp_ioctl_addr[15]} ),
|
||||
.port2_we ( ioctl_downl ),
|
||||
.port2_d ( {ioctl_dout, ioctl_dout} ),
|
||||
.port2_q ( ),
|
||||
|
||||
.sp_addr ( ioctl_downl ? 15'h7fff : gfx_rom_addr ),//todo
|
||||
.sp_q ( gfx_rom_do )
|
||||
);
|
||||
|
||||
// ROM download controller
|
||||
always @(posedge clk_sys) begin
|
||||
reg ioctl_wr_last = 0;
|
||||
|
||||
ioctl_wr_last <= ioctl_wr;
|
||||
if (ioctl_downl) begin
|
||||
if (~ioctl_wr_last && ioctl_wr && ioctl_index == 0) begin
|
||||
port1_req <= ~port1_req;
|
||||
port2_req <= ~port2_req;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg reset = 1;
|
||||
reg rom_loaded = 0;
|
||||
always @(posedge clk_sys) begin
|
||||
reg ioctl_downlD;
|
||||
ioctl_downlD <= ioctl_downl;
|
||||
|
||||
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
|
||||
reset <= status[0] | buttons[1] | ~rom_loaded;
|
||||
end
|
||||
|
||||
|
||||
wire [7:0] audio;
|
||||
wire hs, vs, cs;
|
||||
wire blankn;
|
||||
wire [3:0] g, r, b, intensity;
|
||||
|
||||
williams2 williams2(
|
||||
.clock_12 (clk12),
|
||||
.reset (reset),
|
||||
//prg low
|
||||
.prg_rom_addr (prg_rom_addr),//(13 downto 0);
|
||||
.prg_rom_do (prg_rom_do),//(7 downto 0);
|
||||
//banks
|
||||
.rom_addr (bank_rom_addr),//(16 downto 0);
|
||||
.rom_do (bank_rom_do),//( 7 downto 0);
|
||||
.rom_rd (),//
|
||||
//snd
|
||||
.snd_rom_addr (snd_rom_addr),//(12 downto 0);
|
||||
.snd_rom_do (snd_rom_do),//(7 downto 0);
|
||||
//gfx
|
||||
.gfx_rom_addr (gfx_rom_addr),//(12 downto 0);
|
||||
.gfx_rom_do (gfx_rom_do),//(23 downto 0);
|
||||
//dec hardcoded for now
|
||||
.dec_rom_addr (),//(8 downto 0);
|
||||
.dec_rom_do (),//(7 downto 0);
|
||||
|
||||
.video_r (r),
|
||||
.video_g (g),
|
||||
.video_b (b),
|
||||
.video_i (intensity),
|
||||
.video_csync (cs),
|
||||
.video_blankn (blankn),
|
||||
.video_hs (hs),
|
||||
.video_vs (vs),
|
||||
|
||||
.audio_out (audio),
|
||||
|
||||
.btn_auto_up (autoup),
|
||||
.btn_advance (advance),
|
||||
.btn_high_score_reset (Hreset),
|
||||
|
||||
.btn_gobble (m_fireC),
|
||||
.btn_grenade (m_fireB),
|
||||
.btn_coin (m_coin1),
|
||||
.btn_start_2 (m_two_players),
|
||||
.btn_start_1 (m_one_player),
|
||||
.btn_trigger (m_fireA),
|
||||
.btn_left (m_left),
|
||||
.btn_right (m_right),
|
||||
.btn_up (m_up),
|
||||
.btn_down (m_down),
|
||||
|
||||
.sw_coktail_table (1'b0)
|
||||
);
|
||||
|
||||
wire [7:0]ri = r*intensity;
|
||||
wire [7:0]gi = g*intensity;
|
||||
wire [7:0]bi = b*intensity;
|
||||
|
||||
mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(
|
||||
.clk_sys ( clk_sys ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS3 ( SPI_SS3 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.R ( blankn ? ri[7:4] : 0 ),
|
||||
.G ( blankn ? gi[7:4] : 0 ),
|
||||
.B ( blankn ? bi[7:4] : 0 ),
|
||||
.HSync ( hs ),
|
||||
.VSync ( vs ),
|
||||
.VGA_R ( VGA_R ),
|
||||
.VGA_G ( VGA_G ),
|
||||
.VGA_B ( VGA_B ),
|
||||
.VGA_VS ( VGA_VS ),
|
||||
.VGA_HS ( VGA_HS ),
|
||||
.rotate ( { 1'b1, rotate } ),
|
||||
.ce_divider ( 1 ),
|
||||
.blend ( blend ),
|
||||
.scandoubler_disable(scandoublerD ),
|
||||
.no_csync ( 1'b1 ),//todo
|
||||
.ypbpr ( ypbpr )
|
||||
);
|
||||
|
||||
dac #(
|
||||
.C_bits(8))
|
||||
dac_(
|
||||
.clk_i(clk_sys),
|
||||
.res_n_i(1),
|
||||
.dac_i(audio),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
|
||||
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
|
||||
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
|
||||
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
|
||||
|
||||
arcade_inputs inputs (
|
||||
.clk ( clk_sys ),
|
||||
.key_strobe ( key_strobe ),
|
||||
.key_pressed ( key_pressed ),
|
||||
.key_code ( key_code ),
|
||||
.joystick_0 ( joystick_0 ),
|
||||
.joystick_1 ( joystick_1 ),
|
||||
.rotate ( rotate ),
|
||||
.orientation ( 2'b11 ),//check
|
||||
.joyswap ( 1'b0 ),
|
||||
.oneplayer ( 1'b1 ),
|
||||
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
|
||||
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
|
||||
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
|
||||
);
|
||||
|
||||
endmodule
|
||||
35
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/build_id.tcl
Normal file
35
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/build_id.tcl
Normal file
@@ -0,0 +1,35 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
84
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/gen_ram.vhd
Normal file
84
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/gen_ram.vhd
Normal file
@@ -0,0 +1,84 @@
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- Syntiac's generic VHDL support files.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
|
||||
-- http://www.syntiac.com/fpga64.html
|
||||
--
|
||||
-- Modified April 2016 by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
-- Remove address register when writing
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- gen_rwram.vhd
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- generic ram.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
entity gen_ram is
|
||||
generic (
|
||||
dWidth : integer := 8;
|
||||
aWidth : integer := 10
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
we : in std_logic;
|
||||
addr : in std_logic_vector((aWidth-1) downto 0);
|
||||
d : in std_logic_vector((dWidth-1) downto 0);
|
||||
q : out std_logic_vector((dWidth-1) downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
architecture rtl of gen_ram is
|
||||
subtype addressRange is integer range 0 to ((2**aWidth)-1);
|
||||
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
|
||||
signal ram: ramDef;
|
||||
|
||||
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
|
||||
signal qReg : std_logic_vector((dWidth-1) downto 0);
|
||||
begin
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Signals to entity interface
|
||||
-- -----------------------------------------------------------------------
|
||||
-- q <= qReg;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory write
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if we = '1' then
|
||||
ram(to_integer(unsigned(addr))) <= d;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory read
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
|
||||
-- rAddrReg <= addr;
|
||||
---- qReg <= ram(to_integer(unsigned(addr)));
|
||||
q <= ram(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
--q <= ram(to_integer(unsigned(addr)));
|
||||
end architecture;
|
||||
|
||||
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]
|
||||
429
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/pll_mist.vhd
Normal file
429
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/pll_mist.vhd
Normal file
@@ -0,0 +1,429 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: pll_mist.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.1.4 Build 182 03/12/2014 SJ Full Version
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2014 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY pll_mist IS
|
||||
PORT
|
||||
(
|
||||
areset : IN STD_LOGIC := '0';
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
c2 : OUT STD_LOGIC ;
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
END pll_mist;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF pll_mist IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC ;
|
||||
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
bandwidth_type : STRING;
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
clk2_divide_by : NATURAL;
|
||||
clk2_duty_cycle : NATURAL;
|
||||
clk2_multiply_by : NATURAL;
|
||||
clk2_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
pll_type : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
self_reset_on_loss_lock : STRING;
|
||||
width_clock : NATURAL
|
||||
);
|
||||
PORT (
|
||||
areset : IN STD_LOGIC ;
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire7_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
|
||||
sub_wire4 <= sub_wire0(2);
|
||||
sub_wire3 <= sub_wire0(0);
|
||||
sub_wire1 <= sub_wire0(1);
|
||||
c1 <= sub_wire1;
|
||||
locked <= sub_wire2;
|
||||
c0 <= sub_wire3;
|
||||
c2 <= sub_wire4;
|
||||
sub_wire5 <= inclk0;
|
||||
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
bandwidth_type => "AUTO",
|
||||
clk0_divide_by => 9,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 32,
|
||||
clk0_phase_shift => "0",
|
||||
clk1_divide_by => 9,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 8,
|
||||
clk1_phase_shift => "0",
|
||||
clk2_divide_by => 9,
|
||||
clk2_duty_cycle => 50,
|
||||
clk2_multiply_by => 4,
|
||||
clk2_phase_shift => "0",
|
||||
compensate_clock => "CLK0",
|
||||
inclk0_input_frequency => 37037,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_hint => "CBX_MODULE_PREFIX=pll_mist",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "NORMAL",
|
||||
pll_type => "AUTO",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_USED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_USED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_USED",
|
||||
port_clk3 => "PORT_UNUSED",
|
||||
port_clk4 => "PORT_UNUSED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
self_reset_on_loss_lock => "OFF",
|
||||
width_clock => 5
|
||||
)
|
||||
PORT MAP (
|
||||
areset => areset,
|
||||
inclk => sub_wire6,
|
||||
clk => sub_wire0,
|
||||
locked => sub_wire2
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "32"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
|
||||
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
11
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/rom/make..bat
Normal file
11
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/rom/make..bat
Normal file
@@ -0,0 +1,11 @@
|
||||
make_vhdl_prom.exe 7649.ic60 turkey_shoot_decoder.vhd
|
||||
|
||||
copy /B rom17.ic26 + rom15.ic24 turkey_shoot_bank_a.bin
|
||||
copy /B rom16.ic25 + rom14.ic23 + rom13.ic21 + rom12.ic19 turkey_shoot_bank_b.bin
|
||||
copy /B rom11.ic18 + rom9.ic16 + rom7.ic14 + rom5.ic12 turkey_shoot_bank_c.bin
|
||||
copy /B rom10.ic17 + rom8.ic15 + rom6.ic13 + rom4.ic11 turkey_shoot_bank_d.bin
|
||||
copy /B rom20.ic57 + rom21.ic58 + rom19.ic41 gfx.bin
|
||||
|
||||
copy /b rom18.ic55 + rom2.ic9 + rom3.ic10 + rom3.ic10 + turkey_shoot_bank_a.bin + turkey_shoot_bank_b.bin + turkey_shoot_bank_c.bin + turkey_shoot_bank_d.bin + rom1.ic8 + gfx.bin turkeys.rom
|
||||
|
||||
pause
|
||||
Binary file not shown.
@@ -0,0 +1,54 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity turkey_shoot_decoder is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(8 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of turkey_shoot_decoder is
|
||||
type rom is array(0 to 511) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"00",X"40",X"80",X"01",X"41",X"81",X"02",X"42",X"82",X"03",X"43",X"83",X"04",X"44",X"84",X"05",
|
||||
X"45",X"85",X"06",X"46",X"86",X"07",X"47",X"87",X"08",X"48",X"88",X"09",X"49",X"89",X"0A",X"4A",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"8A",X"0B",X"4B",X"8B",X"0C",X"4C",X"8C",X"0D",X"4D",X"8D",X"0E",X"4E",X"8E",X"0F",X"4F",X"8F",
|
||||
X"10",X"50",X"90",X"11",X"51",X"91",X"12",X"52",X"92",X"13",X"53",X"93",X"14",X"54",X"94",X"15",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"55",X"95",X"16",X"56",X"96",X"17",X"57",X"97",X"18",X"58",X"98",X"19",X"59",X"99",X"1A",X"5A",
|
||||
X"9A",X"1B",X"5B",X"9B",X"1C",X"5C",X"9C",X"1D",X"5D",X"9D",X"1E",X"5E",X"9E",X"1F",X"5F",X"9F",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"20",X"60",X"A0",X"21",X"61",X"A1",X"22",X"62",X"A2",X"23",X"63",X"A3",X"24",X"64",X"A4",X"25",
|
||||
X"65",X"A5",X"26",X"66",X"A6",X"27",X"67",X"A7",X"28",X"68",X"A8",X"29",X"69",X"A9",X"2A",X"6A",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"AA",X"2B",X"6B",X"AB",X"2C",X"6C",X"AC",X"2D",X"6D",X"AD",X"2E",X"6E",X"AE",X"2F",X"6F",X"AF",
|
||||
X"30",X"70",X"B0",X"31",X"71",X"B1",X"32",X"72",X"B2",X"33",X"73",X"B3",X"34",X"74",X"B4",X"35",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"75",X"B5",X"36",X"76",X"B6",X"37",X"77",X"B7",X"38",X"78",X"B8",X"39",X"79",X"B9",X"3A",X"7A",
|
||||
X"BA",X"3B",X"7B",X"BB",X"3C",X"7C",X"BC",X"3D",X"7D",X"BD",X"3E",X"7E",X"BE",X"3F",X"7F",X"BF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
File diff suppressed because it is too large
Load Diff
4019
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/rtl_jkent/cpu68_2.vhd
Normal file
4019
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/rtl_jkent/cpu68_2.vhd
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,553 @@
|
||||
--===========================================================================--
|
||||
--
|
||||
-- S Y N T H E Z I A B L E I/O Port C O R E
|
||||
--
|
||||
-- www.OpenCores.Org - May 2004
|
||||
-- This core adheres to the GNU public license
|
||||
--
|
||||
-- File name : pia6821.vhd
|
||||
--
|
||||
-- Purpose : Implements 2 x 8 bit parallel I/O ports
|
||||
-- with programmable data direction registers
|
||||
--
|
||||
-- Dependencies : ieee.Std_Logic_1164
|
||||
-- ieee.std_logic_unsigned
|
||||
--
|
||||
-- Author : John E. Kent
|
||||
--
|
||||
--===========================================================================----
|
||||
--
|
||||
-- Revision History:
|
||||
--
|
||||
-- Date: Revision Author
|
||||
-- 1 May 2004 0.0 John Kent
|
||||
-- Initial version developed from ioport.vhd
|
||||
--
|
||||
--
|
||||
-- Unkown date 0.0.1 found at Pacedev repository
|
||||
-- remove High Z output and and oe signal
|
||||
--
|
||||
-- 18 October 2017 0.0.2 DarFpga
|
||||
-- Set output to low level when in data is in input mode
|
||||
-- (to avoid infered latch warning)
|
||||
--
|
||||
--===========================================================================----
|
||||
--
|
||||
-- Memory Map
|
||||
--
|
||||
-- IO + $00 - Port A Data & Direction register
|
||||
-- IO + $01 - Port A Control register
|
||||
-- IO + $02 - Port B Data & Direction Direction Register
|
||||
-- IO + $03 - Port B Control Register
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity pia6821 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
cs : in std_logic;
|
||||
rw : in std_logic;
|
||||
addr : in std_logic_vector(1 downto 0);
|
||||
data_in : in std_logic_vector(7 downto 0);
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
irqa : out std_logic;
|
||||
irqb : out std_logic;
|
||||
pa_i : in std_logic_vector(7 downto 0);
|
||||
pa_o : out std_logic_vector(7 downto 0);
|
||||
pa_oe : out std_logic_vector(7 downto 0);
|
||||
ca1 : in std_logic;
|
||||
ca2_i : in std_logic;
|
||||
ca2_o : out std_logic;
|
||||
ca2_oe : out std_logic;
|
||||
pb_i : in std_logic_vector(7 downto 0);
|
||||
pb_o : out std_logic_vector(7 downto 0);
|
||||
pb_oe : out std_logic_vector(7 downto 0);
|
||||
cb1 : in std_logic;
|
||||
cb2_i : in std_logic;
|
||||
cb2_o : out std_logic;
|
||||
cb2_oe : out std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
architecture pia_arch of pia6821 is
|
||||
|
||||
signal porta_ddr : std_logic_vector(7 downto 0);
|
||||
signal porta_data : std_logic_vector(7 downto 0);
|
||||
signal porta_ctrl : std_logic_vector(5 downto 0);
|
||||
signal porta_read : std_logic;
|
||||
|
||||
signal portb_ddr : std_logic_vector(7 downto 0);
|
||||
signal portb_data : std_logic_vector(7 downto 0);
|
||||
signal portb_ctrl : std_logic_vector(5 downto 0);
|
||||
signal portb_read : std_logic;
|
||||
signal portb_write : std_logic;
|
||||
|
||||
signal ca1_del : std_logic;
|
||||
signal ca1_rise : std_logic;
|
||||
signal ca1_fall : std_logic;
|
||||
signal ca1_edge : std_logic;
|
||||
signal irqa1 : std_logic;
|
||||
|
||||
signal ca2_del : std_logic;
|
||||
signal ca2_rise : std_logic;
|
||||
signal ca2_fall : std_logic;
|
||||
signal ca2_edge : std_logic;
|
||||
signal irqa2 : std_logic;
|
||||
signal ca2_out : std_logic;
|
||||
|
||||
signal cb1_del : std_logic;
|
||||
signal cb1_rise : std_logic;
|
||||
signal cb1_fall : std_logic;
|
||||
signal cb1_edge : std_logic;
|
||||
signal irqb1 : std_logic;
|
||||
|
||||
signal cb2_del : std_logic;
|
||||
signal cb2_rise : std_logic;
|
||||
signal cb2_fall : std_logic;
|
||||
signal cb2_edge : std_logic;
|
||||
signal irqb2 : std_logic;
|
||||
signal cb2_out : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------
|
||||
--
|
||||
-- read I/O port
|
||||
--
|
||||
--------------------------------
|
||||
|
||||
pia_read : process( addr, cs,
|
||||
irqa1, irqa2, irqb1, irqb2,
|
||||
porta_ddr, portb_ddr,
|
||||
porta_data, portb_data,
|
||||
porta_ctrl, portb_ctrl,
|
||||
pa_i, pb_i )
|
||||
variable count : integer;
|
||||
begin
|
||||
case addr is
|
||||
when "00" =>
|
||||
for count in 0 to 7 loop
|
||||
if porta_ctrl(2) = '0' then
|
||||
data_out(count) <= porta_ddr(count);
|
||||
porta_read <= '0';
|
||||
else
|
||||
if porta_ddr(count) = '1' then
|
||||
data_out(count) <= porta_data(count);
|
||||
else
|
||||
data_out(count) <= pa_i(count);
|
||||
end if;
|
||||
porta_read <= cs;
|
||||
end if;
|
||||
end loop;
|
||||
portb_read <= '0';
|
||||
|
||||
when "01" =>
|
||||
data_out <= irqa1 & irqa2 & porta_ctrl;
|
||||
porta_read <= '0';
|
||||
portb_read <= '0';
|
||||
|
||||
when "10" =>
|
||||
for count in 0 to 7 loop
|
||||
if portb_ctrl(2) = '0' then
|
||||
data_out(count) <= portb_ddr(count);
|
||||
portb_read <= '0';
|
||||
else
|
||||
if portb_ddr(count) = '1' then
|
||||
data_out(count) <= portb_data(count);
|
||||
else
|
||||
data_out(count) <= pb_i(count);
|
||||
end if;
|
||||
portb_read <= cs;
|
||||
end if;
|
||||
end loop;
|
||||
porta_read <= '0';
|
||||
|
||||
when "11" =>
|
||||
data_out <= irqb1 & irqb2 & portb_ctrl;
|
||||
porta_read <= '0';
|
||||
portb_read <= '0';
|
||||
|
||||
when others =>
|
||||
data_out <= "00000000";
|
||||
porta_read <= '0';
|
||||
portb_read <= '0';
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
---------------------------------
|
||||
--
|
||||
-- Write I/O ports
|
||||
--
|
||||
---------------------------------
|
||||
|
||||
pia_write : process( clk, rst, addr, cs, rw, data_in,
|
||||
porta_ctrl, portb_ctrl,
|
||||
porta_data, portb_data,
|
||||
porta_ddr, portb_ddr )
|
||||
begin
|
||||
if rst = '1' then
|
||||
porta_ddr <= "00000000";
|
||||
porta_data <= "00000000";
|
||||
porta_ctrl <= "000000";
|
||||
portb_ddr <= "00000000";
|
||||
portb_data <= "00000000";
|
||||
portb_ctrl <= "000000";
|
||||
portb_write <= '0';
|
||||
elsif clk'event and clk = '1' then
|
||||
if cs = '1' and rw = '0' then
|
||||
case addr is
|
||||
when "00" =>
|
||||
if porta_ctrl(2) = '0' then
|
||||
porta_ddr <= data_in;
|
||||
porta_data <= porta_data;
|
||||
else
|
||||
porta_ddr <= porta_ddr;
|
||||
porta_data <= data_in;
|
||||
end if;
|
||||
porta_ctrl <= porta_ctrl;
|
||||
portb_ddr <= portb_ddr;
|
||||
portb_data <= portb_data;
|
||||
portb_ctrl <= portb_ctrl;
|
||||
portb_write <= '0';
|
||||
when "01" =>
|
||||
porta_ddr <= porta_ddr;
|
||||
porta_data <= porta_data;
|
||||
porta_ctrl <= data_in(5 downto 0);
|
||||
portb_ddr <= portb_ddr;
|
||||
portb_data <= portb_data;
|
||||
portb_ctrl <= portb_ctrl;
|
||||
portb_write <= '0';
|
||||
when "10" =>
|
||||
porta_ddr <= porta_ddr;
|
||||
porta_data <= porta_data;
|
||||
porta_ctrl <= porta_ctrl;
|
||||
if portb_ctrl(2) = '0' then
|
||||
portb_ddr <= data_in;
|
||||
portb_data <= portb_data;
|
||||
portb_write <= '0';
|
||||
else
|
||||
portb_ddr <= portb_ddr;
|
||||
portb_data <= data_in;
|
||||
portb_write <= '1';
|
||||
end if;
|
||||
portb_ctrl <= portb_ctrl;
|
||||
when "11" =>
|
||||
porta_ddr <= porta_ddr;
|
||||
porta_data <= porta_data;
|
||||
porta_ctrl <= porta_ctrl;
|
||||
portb_ddr <= portb_ddr;
|
||||
portb_data <= portb_data;
|
||||
portb_ctrl <= data_in(5 downto 0);
|
||||
portb_write <= '0';
|
||||
when others =>
|
||||
porta_ddr <= porta_ddr;
|
||||
porta_data <= porta_data;
|
||||
porta_ctrl <= porta_ctrl;
|
||||
portb_ddr <= portb_ddr;
|
||||
portb_data <= portb_data;
|
||||
portb_ctrl <= portb_ctrl;
|
||||
portb_write <= '0';
|
||||
end case;
|
||||
else
|
||||
porta_ddr <= porta_ddr;
|
||||
porta_data <= porta_data;
|
||||
porta_ctrl <= porta_ctrl;
|
||||
portb_data <= portb_data;
|
||||
portb_ddr <= portb_ddr;
|
||||
portb_ctrl <= portb_ctrl;
|
||||
portb_write <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------
|
||||
--
|
||||
-- direction control port a
|
||||
--
|
||||
---------------------------------
|
||||
porta_direction : process ( porta_data, porta_ddr )
|
||||
variable count : integer;
|
||||
begin
|
||||
for count in 0 to 7 loop
|
||||
if porta_ddr(count) = '1' then
|
||||
pa_o(count) <= porta_data(count);
|
||||
pa_oe(count) <= '1';
|
||||
else
|
||||
pa_o(count) <= '0';
|
||||
pa_oe(count) <= '0';
|
||||
end if;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
---------------------------------
|
||||
--
|
||||
-- CA1 Edge detect
|
||||
--
|
||||
---------------------------------
|
||||
ca1_input : process( clk, rst, ca1, ca1_del,
|
||||
ca1_rise, ca1_fall, ca1_edge,
|
||||
irqa1, porta_ctrl, porta_read )
|
||||
begin
|
||||
if rst = '1' then
|
||||
ca1_del <= '0';
|
||||
ca1_rise <= '0';
|
||||
ca1_fall <= '0';
|
||||
ca1_edge <= '0';
|
||||
irqa1 <= '0';
|
||||
elsif clk'event and clk = '0' then
|
||||
ca1_del <= ca1;
|
||||
ca1_rise <= (not ca1_del) and ca1;
|
||||
ca1_fall <= ca1_del and (not ca1);
|
||||
if ca1_edge = '1' then
|
||||
irqa1 <= '1';
|
||||
elsif porta_read = '1' then
|
||||
irqa1 <= '0';
|
||||
else
|
||||
irqa1 <= irqa1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if porta_ctrl(1) = '0' then
|
||||
ca1_edge <= ca1_fall;
|
||||
else
|
||||
ca1_edge <= ca1_rise;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------
|
||||
--
|
||||
-- CA2 Edge detect
|
||||
--
|
||||
---------------------------------
|
||||
ca2_input : process( clk, rst, ca2_i, ca2_del,
|
||||
ca2_rise, ca2_fall, ca2_edge,
|
||||
irqa2, porta_ctrl, porta_read )
|
||||
begin
|
||||
if rst = '1' then
|
||||
ca2_del <= '0';
|
||||
ca2_rise <= '0';
|
||||
ca2_fall <= '0';
|
||||
ca2_edge <= '0';
|
||||
irqa2 <= '0';
|
||||
elsif clk'event and clk = '0' then
|
||||
ca2_del <= ca2_i;
|
||||
ca2_rise <= (not ca2_del) and ca2_i;
|
||||
ca2_fall <= ca2_del and (not ca2_i);
|
||||
if porta_ctrl(5) = '0' and ca2_edge = '1' then
|
||||
irqa2 <= '1';
|
||||
elsif porta_read = '1' then
|
||||
irqa2 <= '0';
|
||||
else
|
||||
irqa2 <= irqa2;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if porta_ctrl(4) = '0' then
|
||||
ca2_edge <= ca2_fall;
|
||||
else
|
||||
ca2_edge <= ca2_rise;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------
|
||||
--
|
||||
-- CA2 output control
|
||||
--
|
||||
---------------------------------
|
||||
ca2_output : process( clk, rst, porta_ctrl, porta_read, ca1_edge, ca2_out )
|
||||
begin
|
||||
if rst='1' then
|
||||
ca2_out <= '0';
|
||||
elsif clk'event and clk='0' then
|
||||
case porta_ctrl(5 downto 3) is
|
||||
when "100" => -- read PA clears, CA1 edge sets
|
||||
if porta_read = '1' then
|
||||
ca2_out <= '0';
|
||||
elsif ca1_edge = '1' then
|
||||
ca2_out <= '1';
|
||||
else
|
||||
ca2_out <= ca2_out;
|
||||
end if;
|
||||
when "101" => -- read PA clears, E sets
|
||||
ca2_out <= not porta_read;
|
||||
when "110" => -- set low
|
||||
ca2_out <= '0';
|
||||
when "111" => -- set high
|
||||
ca2_out <= '1';
|
||||
when others => -- no change
|
||||
ca2_out <= ca2_out;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------
|
||||
--
|
||||
-- CA2 direction control
|
||||
--
|
||||
---------------------------------
|
||||
ca2_direction : process( porta_ctrl, ca2_out )
|
||||
begin
|
||||
if porta_ctrl(5) = '0' then
|
||||
ca2_oe <= '0';
|
||||
ca2_o <= '0';
|
||||
else
|
||||
ca2_o <= ca2_out;
|
||||
ca2_oe <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------
|
||||
--
|
||||
-- direction control port b
|
||||
--
|
||||
---------------------------------
|
||||
portb_direction : process ( portb_data, portb_ddr )
|
||||
variable count : integer;
|
||||
begin
|
||||
for count in 0 to 7 loop
|
||||
if portb_ddr(count) = '1' then
|
||||
pb_o(count) <= portb_data(count);
|
||||
pb_oe(count) <= '1';
|
||||
else
|
||||
pb_o(count) <= '0';
|
||||
pb_oe(count) <= '0';
|
||||
end if;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
---------------------------------
|
||||
--
|
||||
-- CB1 Edge detect
|
||||
--
|
||||
---------------------------------
|
||||
cb1_input : process( clk, rst, cb1, cb1_del,
|
||||
cb1_rise, cb1_fall, cb1_edge,
|
||||
irqb1, portb_ctrl, portb_read )
|
||||
begin
|
||||
if rst = '1' then
|
||||
cb1_del <= '0';
|
||||
cb1_rise <= '0';
|
||||
cb1_fall <= '0';
|
||||
cb1_edge <= '0';
|
||||
irqb1 <= '0';
|
||||
elsif clk'event and clk = '0' then
|
||||
cb1_del <= cb1;
|
||||
cb1_rise <= (not cb1_del) and cb1;
|
||||
cb1_fall <= cb1_del and (not cb1);
|
||||
if cb1_edge = '1' then
|
||||
irqb1 <= '1';
|
||||
elsif portb_read = '1' then
|
||||
irqb1 <= '0';
|
||||
else
|
||||
irqb1 <= irqb1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if portb_ctrl(1) = '0' then
|
||||
cb1_edge <= cb1_fall;
|
||||
else
|
||||
cb1_edge <= cb1_rise;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------
|
||||
--
|
||||
-- CB2 Edge detect
|
||||
--
|
||||
---------------------------------
|
||||
cb2_input : process( clk, rst, cb2_i, cb2_del,
|
||||
cb2_rise, cb2_fall, cb2_edge,
|
||||
irqb2, portb_ctrl, portb_read )
|
||||
begin
|
||||
if rst = '1' then
|
||||
cb2_del <= '0';
|
||||
cb2_rise <= '0';
|
||||
cb2_fall <= '0';
|
||||
cb2_edge <= '0';
|
||||
irqb2 <= '0';
|
||||
elsif clk'event and clk = '0' then
|
||||
cb2_del <= cb2_i;
|
||||
cb2_rise <= (not cb2_del) and cb2_i;
|
||||
cb2_fall <= cb2_del and (not cb2_i);
|
||||
if portb_ctrl(5) = '0' and cb2_edge = '1' then
|
||||
irqb2 <= '1';
|
||||
elsif portb_read = '1' then
|
||||
irqb2 <= '0';
|
||||
else
|
||||
irqb2 <= irqb2;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if portb_ctrl(4) = '0' then
|
||||
cb2_edge <= cb2_fall;
|
||||
else
|
||||
cb2_edge <= cb2_rise;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
---------------------------------
|
||||
--
|
||||
-- CB2 output control
|
||||
--
|
||||
---------------------------------
|
||||
cb2_output : process( clk, rst, portb_ctrl, portb_write, cb1_edge, cb2_out )
|
||||
begin
|
||||
if rst='1' then
|
||||
cb2_out <= '0';
|
||||
elsif clk'event and clk='0' then
|
||||
case portb_ctrl(5 downto 3) is
|
||||
when "100" => -- write PB clears, CA1 edge sets
|
||||
if portb_write = '1' then
|
||||
cb2_out <= '0';
|
||||
elsif cb1_edge = '1' then
|
||||
cb2_out <= '1';
|
||||
else
|
||||
cb2_out <= cb2_out;
|
||||
end if;
|
||||
when "101" => -- write PB clears, E sets
|
||||
cb2_out <= not portb_write;
|
||||
when "110" => -- set low
|
||||
cb2_out <= '0';
|
||||
when "111" => -- set high
|
||||
cb2_out <= '1';
|
||||
when others => -- no change
|
||||
cb2_out <= cb2_out;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------
|
||||
--
|
||||
-- CB2 direction control
|
||||
--
|
||||
---------------------------------
|
||||
cb2_direction : process( portb_ctrl, cb2_out )
|
||||
begin
|
||||
if portb_ctrl(5) = '0' then
|
||||
cb2_oe <= '0';
|
||||
cb2_o <= '0';
|
||||
else
|
||||
cb2_o <= cb2_out;
|
||||
cb2_oe <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------
|
||||
--
|
||||
-- IRQ control
|
||||
--
|
||||
---------------------------------
|
||||
pia_irq : process( irqa1, irqa2, irqb1, irqb2, porta_ctrl, portb_ctrl )
|
||||
begin
|
||||
irqa <= (irqa1 and porta_ctrl(0)) or (irqa2 and porta_ctrl(3));
|
||||
irqb <= (irqb1 and portb_ctrl(0)) or (irqb2 and portb_ctrl(3));
|
||||
end process;
|
||||
|
||||
end pia_arch;
|
||||
|
||||
355
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/sdram.sv
Normal file
355
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/sdram.sv
Normal file
@@ -0,0 +1,355 @@
|
||||
//
|
||||
// sdram.v
|
||||
//
|
||||
// sdram controller implementation for the MiST board
|
||||
// https://github.com/mist-devel/mist-board
|
||||
//
|
||||
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2019 Gyorgy Szombathelyi
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
|
||||
module sdram (
|
||||
|
||||
// interface to the MT48LC16M16 chip
|
||||
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
|
||||
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
|
||||
output reg SDRAM_DQML, // two byte masks
|
||||
output reg SDRAM_DQMH, // two byte masks
|
||||
output reg [1:0] SDRAM_BA, // two banks
|
||||
output SDRAM_nCS, // a single chip select
|
||||
output SDRAM_nWE, // write enable
|
||||
output SDRAM_nRAS, // row address select
|
||||
output SDRAM_nCAS, // columns address select
|
||||
|
||||
// cpu/chipset interface
|
||||
input init_n, // init signal after FPGA config to initialize RAM
|
||||
input clk, // sdram clock
|
||||
|
||||
input port1_req,
|
||||
output reg port1_ack,
|
||||
input port1_we,
|
||||
input [23:1] port1_a,
|
||||
input [1:0] port1_ds,
|
||||
input [15:0] port1_d,
|
||||
output reg [15:0] port1_q,
|
||||
|
||||
input [16:1] cpu1_addr,
|
||||
output reg [15:0] cpu1_q,
|
||||
input [16:1] cpu2_addr,
|
||||
output reg [15:0] cpu2_q,
|
||||
input [16:1] cpu3_addr,
|
||||
output reg [15:0] cpu3_q,
|
||||
|
||||
input port2_req,
|
||||
output reg port2_ack,
|
||||
input port2_we,
|
||||
input [23:1] port2_a,
|
||||
input [1:0] port2_ds,
|
||||
input [15:0] port2_d,
|
||||
output reg [31:0] port2_q,
|
||||
|
||||
input [16:2] sp_addr,
|
||||
output reg [31:0] sp_q
|
||||
);
|
||||
|
||||
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
|
||||
localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
|
||||
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
|
||||
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
|
||||
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
|
||||
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
|
||||
|
||||
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
|
||||
|
||||
// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
|
||||
localparam RFRSH_CYCLES = 10'd842;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// ------------------------ cycle state machine ------------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
/*
|
||||
SDRAM state machine for 2 bank interleaved access
|
||||
1 word burst, CL2
|
||||
cmd issued registered
|
||||
0 RAS0 cas1 - data0 read burst terminated
|
||||
1 ras0
|
||||
2 data1 returned
|
||||
3 CAS0 data1 returned
|
||||
4 RAS1 cas0
|
||||
5 ras1
|
||||
6 CAS1 data0 returned
|
||||
*/
|
||||
|
||||
localparam STATE_RAS0 = 3'd0; // first state in cycle
|
||||
localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
|
||||
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
|
||||
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
|
||||
localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
|
||||
localparam STATE_READ1 = 3'd3;
|
||||
localparam STATE_DS1b = 3'd0;
|
||||
localparam STATE_READ1b = 3'd4;
|
||||
localparam STATE_LAST = 3'd6;
|
||||
|
||||
reg [2:0] t;
|
||||
|
||||
always @(posedge clk) begin
|
||||
t <= t + 1'd1;
|
||||
if (t == STATE_LAST) t <= STATE_RAS0;
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// --------------------------- startup/reset ---------------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
|
||||
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
|
||||
reg [4:0] reset;
|
||||
reg init = 1'b1;
|
||||
always @(posedge clk, negedge init_n) begin
|
||||
if(!init_n) begin
|
||||
reset <= 5'h1f;
|
||||
init <= 1'b1;
|
||||
end else begin
|
||||
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
|
||||
init <= !(reset == 0);
|
||||
end
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// ------------------ generate ram control signals ---------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// all possible commands
|
||||
localparam CMD_INHIBIT = 4'b1111;
|
||||
localparam CMD_NOP = 4'b0111;
|
||||
localparam CMD_ACTIVE = 4'b0011;
|
||||
localparam CMD_READ = 4'b0101;
|
||||
localparam CMD_WRITE = 4'b0100;
|
||||
localparam CMD_BURST_TERMINATE = 4'b0110;
|
||||
localparam CMD_PRECHARGE = 4'b0010;
|
||||
localparam CMD_AUTO_REFRESH = 4'b0001;
|
||||
localparam CMD_LOAD_MODE = 4'b0000;
|
||||
|
||||
reg [3:0] sd_cmd; // current command sent to sd ram
|
||||
reg [15:0] sd_din;
|
||||
// drive control signals according to current command
|
||||
assign SDRAM_nCS = sd_cmd[3];
|
||||
assign SDRAM_nRAS = sd_cmd[2];
|
||||
assign SDRAM_nCAS = sd_cmd[1];
|
||||
assign SDRAM_nWE = sd_cmd[0];
|
||||
|
||||
reg [24:1] addr_latch[3];
|
||||
reg [24:1] addr_latch_next[2];
|
||||
reg [16:1] addr_last[4];
|
||||
reg [16:2] addr_last2[2];
|
||||
reg [15:0] din_latch[2];
|
||||
reg [1:0] oe_latch;
|
||||
reg [1:0] we_latch;
|
||||
reg [1:0] ds[2];
|
||||
|
||||
reg port1_state;
|
||||
reg port2_state;
|
||||
|
||||
localparam PORT_NONE = 3'd0;
|
||||
localparam PORT_CPU1 = 3'd1;
|
||||
localparam PORT_CPU2 = 3'd2;
|
||||
localparam PORT_CPU3 = 3'd3;
|
||||
localparam PORT_SP = 3'd1;
|
||||
localparam PORT_REQ = 3'd4;
|
||||
|
||||
reg [2:0] next_port[2];
|
||||
reg [2:0] port[2];
|
||||
|
||||
reg refresh;
|
||||
reg [10:0] refresh_cnt;
|
||||
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
|
||||
|
||||
// PORT1: bank 0,1
|
||||
always @(*) begin
|
||||
if (refresh) begin
|
||||
next_port[0] = PORT_NONE;
|
||||
addr_latch_next[0] = addr_latch[0];
|
||||
end else if (port1_req ^ port1_state) begin
|
||||
next_port[0] = PORT_REQ;
|
||||
addr_latch_next[0] = { 1'b0, port1_a };
|
||||
end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
|
||||
next_port[0] = PORT_CPU1;
|
||||
addr_latch_next[0] = { 8'd0, cpu1_addr };
|
||||
end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
|
||||
next_port[0] = PORT_CPU2;
|
||||
addr_latch_next[0] = { 8'd0, cpu2_addr };
|
||||
end else if (cpu3_addr != addr_last[PORT_CPU3]) begin
|
||||
next_port[0] = PORT_CPU3;
|
||||
addr_latch_next[0] = { 8'd0, cpu3_addr };
|
||||
end else begin
|
||||
next_port[0] = PORT_NONE;
|
||||
addr_latch_next[0] = addr_latch[0];
|
||||
end
|
||||
end
|
||||
|
||||
// PORT1: bank 2,3
|
||||
always @(*) begin
|
||||
if (port2_req ^ port2_state) begin
|
||||
next_port[1] = PORT_REQ;
|
||||
addr_latch_next[1] = { 1'b1, port2_a };
|
||||
end else if (sp_addr != addr_last2[PORT_SP]) begin
|
||||
next_port[1] = PORT_SP;
|
||||
addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
|
||||
end else begin
|
||||
next_port[1] = PORT_NONE;
|
||||
addr_latch_next[1] = addr_latch[1];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
// permanently latch ram data to reduce delays
|
||||
sd_din <= SDRAM_DQ;
|
||||
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
|
||||
sd_cmd <= CMD_NOP; // default: idle
|
||||
refresh_cnt <= refresh_cnt + 1'd1;
|
||||
|
||||
if(init) begin
|
||||
// initialization takes place at the end of the reset phase
|
||||
if(t == STATE_RAS0) begin
|
||||
|
||||
if(reset == 15) begin
|
||||
sd_cmd <= CMD_PRECHARGE;
|
||||
SDRAM_A[10] <= 1'b1; // precharge all banks
|
||||
end
|
||||
|
||||
if(reset == 10 || reset == 8) begin
|
||||
sd_cmd <= CMD_AUTO_REFRESH;
|
||||
end
|
||||
|
||||
if(reset == 2) begin
|
||||
sd_cmd <= CMD_LOAD_MODE;
|
||||
SDRAM_A <= MODE;
|
||||
SDRAM_BA <= 2'b00;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
// RAS phase
|
||||
// bank 0,1
|
||||
if(t == STATE_RAS0) begin
|
||||
addr_latch[0] <= addr_latch_next[0];
|
||||
port[0] <= next_port[0];
|
||||
{ oe_latch[0], we_latch[0] } <= 2'b00;
|
||||
|
||||
if (next_port[0] != PORT_NONE) begin
|
||||
sd_cmd <= CMD_ACTIVE;
|
||||
SDRAM_A <= addr_latch_next[0][22:10];
|
||||
SDRAM_BA <= addr_latch_next[0][24:23];
|
||||
addr_last[next_port[0]] <= addr_latch_next[0][16:1];
|
||||
if (next_port[0] == PORT_REQ) begin
|
||||
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
|
||||
ds[0] <= port1_ds;
|
||||
din_latch[0] <= port1_d;
|
||||
port1_state <= port1_req;
|
||||
end else begin
|
||||
{ oe_latch[0], we_latch[0] } <= 2'b10;
|
||||
ds[0] <= 2'b11;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// bank 2,3
|
||||
if(t == STATE_RAS1) begin
|
||||
refresh <= 1'b0;
|
||||
addr_latch[1] <= addr_latch_next[1];
|
||||
{ oe_latch[1], we_latch[1] } <= 2'b00;
|
||||
port[1] <= next_port[1];
|
||||
|
||||
if (next_port[1] != PORT_NONE) begin
|
||||
sd_cmd <= CMD_ACTIVE;
|
||||
SDRAM_A <= addr_latch_next[1][22:10];
|
||||
SDRAM_BA <= addr_latch_next[1][24:23];
|
||||
addr_last2[next_port[1]] <= addr_latch_next[1][16:2];
|
||||
if (next_port[1] == PORT_REQ) begin
|
||||
{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
|
||||
ds[1] <= port2_ds;
|
||||
din_latch[1] <= port2_d;
|
||||
port2_state <= port2_req;
|
||||
end else begin
|
||||
{ oe_latch[1], we_latch[1] } <= 2'b10;
|
||||
ds[1] <= 2'b11;
|
||||
end
|
||||
end
|
||||
|
||||
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
|
||||
refresh <= 1'b1;
|
||||
refresh_cnt <= 0;
|
||||
sd_cmd <= CMD_AUTO_REFRESH;
|
||||
end
|
||||
end
|
||||
|
||||
// CAS phase
|
||||
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
|
||||
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
|
||||
if (we_latch[0]) begin
|
||||
SDRAM_DQ <= din_latch[0];
|
||||
port1_ack <= port1_req;
|
||||
end
|
||||
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
|
||||
SDRAM_BA <= addr_latch[0][24:23];
|
||||
end
|
||||
|
||||
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
|
||||
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
|
||||
if (we_latch[1]) begin
|
||||
SDRAM_DQ <= din_latch[1];
|
||||
port2_ack <= port2_req;
|
||||
end
|
||||
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
|
||||
SDRAM_BA <= addr_latch[1][24:23];
|
||||
end
|
||||
|
||||
// Data returned
|
||||
if(t == STATE_READ0 && oe_latch[0]) begin
|
||||
case(port[0])
|
||||
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
|
||||
PORT_CPU1: begin cpu1_q <= sd_din; end
|
||||
PORT_CPU2: begin cpu2_q <= sd_din; end
|
||||
PORT_CPU3: begin cpu3_q <= sd_din; end
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
|
||||
if(t == STATE_READ1 && oe_latch[1]) begin
|
||||
case(port[1])
|
||||
PORT_REQ: port2_q[15:0] <= sd_din;
|
||||
PORT_SP : sp_q[15:0] <= sd_din;
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
|
||||
if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
|
||||
|
||||
if(t == STATE_READ1b && oe_latch[1]) begin
|
||||
case(port[1])
|
||||
PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
|
||||
PORT_SP : begin sp_q[31:16] <= sd_din; end
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
182
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/tshoot_cmos_ram.vhd
Normal file
182
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/tshoot_cmos_ram.vhd
Normal file
@@ -0,0 +1,182 @@
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- Syntiac's generic VHDL support",x"iles.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
|
||||
-- http://www.syntiac.com/fpga64.html
|
||||
--
|
||||
-- Modified April 2016 by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
-- Remove address register when writing
|
||||
--
|
||||
-- Modifies March 2022 by Dar
|
||||
-- Add init data with tshoot cmos value
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- gen_rwram.vhd init with tshoot cmos value
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- generic ram.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
-- tshoot cmos settings --
|
||||
--
|
||||
--@00-03:Extra fowl every (XXYY XX=value*1000 YY=index default 320A)
|
||||
-- 0000/0501/0A02/0F03/1404/1905/1E06/2307
|
||||
-- 2808/2D09/320A/370B/3C0C/410D/460E/4B0F
|
||||
-- 5010/5511/5A12/5F13
|
||||
--
|
||||
--@04-07: Missions for 1 credit (XXYY XX=value YY=index default 0301)
|
||||
-- 0200/0301/0402/0503
|
||||
--
|
||||
--@08-0B: attract mode no/yes (XXYY XX=value YY=index default 0101)
|
||||
-- 0000/0101
|
||||
--
|
||||
--@0C-0F: pricing selection (XXYY XX=value YY=index [0000 custom, 0909 free play] default 0303)
|
||||
-- 0000/0101/.../0909
|
||||
--
|
||||
--@10-13 -> CC1C-CC1F: coin slot units (XXYY XX=value YY=index, index is used only when custom)
|
||||
-- 0000/0101/.../6262
|
||||
--
|
||||
--@20-23 -> CC24-CC27: unit for credit/bonus credit (XXYY XX=value YY=index)
|
||||
-- 0000/0101/.../6262
|
||||
--
|
||||
--@28-2B: difficulty (XXYY XX=value YY=index default 0505)
|
||||
-- 0000/0101/../0909
|
||||
--
|
||||
--@2C-2F: ?
|
||||
-- 0300
|
||||
--
|
||||
--@30-33: gun recoil no/yes (XXYY XX=value YY=index default 0101)
|
||||
-- 0000/0101
|
||||
--
|
||||
--@34-35: control sum : sum of nibbles from @00 to @33 + 3
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
-- -----------------------------------------------------------------------
|
||||
entity t_shoot_cmos_ram is
|
||||
generic (
|
||||
dWidth : integer := 8; -- must be 4",x"or tshoot_cmos_ram
|
||||
aWidth : integer := 10 -- must be 10",x"or tshoot_cmos_ram
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
we : in std_logic;
|
||||
addr : in std_logic_vector((aWidth-1) downto 0);
|
||||
d : in std_logic_vector((dWidth-1) downto 0);
|
||||
q : out std_logic_vector((dWidth-1) downto 0)
|
||||
);
|
||||
end entity;
|
||||
-- -----------------------------------------------------------------------
|
||||
-- tshoot cmos data
|
||||
-- (ram is 128x4 => only 4 bits/address, that is only 1 hex digit/address)
|
||||
|
||||
architecture rtl of t_shoot_cmos_ram is
|
||||
subtype addressRange is integer range 0 to ((2**aWidth)-1);
|
||||
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
|
||||
|
||||
signal ram: ramDef := (
|
||||
x"3",x"2",x"0",x"A",x"0",x"3",x"0",x"1",x"0",x"1",x"0",x"1",x"0",x"3",x"0",x"3",
|
||||
x"0",x"1",x"0",x"0",x"0",x"4",x"0",x"0",x"0",x"1",x"0",x"0",x"0",x"1",x"0",x"0",
|
||||
x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"5",x"0",x"5",x"0",x"3",x"0",x"0",
|
||||
x"0",x"1",x"0",x"1",x"5",x"F",x"A",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
x"0",x"7",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",
|
||||
x"0",x"0",x"0",x"7",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"6",
|
||||
x"0",x"0",x"0",x"0",x"1",x"5",x"0",x"0",x"0",x"0",x"0",x"5",x"0",x"0",x"0",x"0",
|
||||
x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"5",x"0",x"0",x"0",x"0",x"1",x"7",x"0",x"1",
|
||||
x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"1",x"8",x"1",x"0",x"0",x"0",x"0",x"0",x"5",
|
||||
x"0",x"2",x"D",x"5",x"5",x"7",x"4",x"9",x"4",x"C",x"0",x"0",x"4",x"0",x"3",x"5",
|
||||
x"4",x"D",x"5",x"2",x"5",x"3",x"0",x"0",x"4",x"0",x"2",x"0",x"5",x"2",x"4",x"F",
|
||||
x"4",x"E",x"0",x"0",x"3",x"9",x"1",x"5",x"4",x"A",x"5",x"2",x"4",x"E",x"0",x"0",
|
||||
x"3",x"8",x"3",x"4",x"5",x"4",x"4",x"E",x"4",x"4",x"0",x"0",x"3",x"7",x"2",x"5",
|
||||
x"5",x"7",x"5",x"0",x"4",x"2",x"0",x"0",x"3",x"6",x"1",x"0",x"4",x"3",x"4",x"C",
|
||||
x"5",x"3",x"0",x"0",x"3",x"5",x"0",x"3",x"4",x"C",x"4",x"5",x"4",x"F",x"0",x"0",
|
||||
x"3",x"4",x"7",x"8",x"4",x"4",x"5",x"2",x"5",x"9",x"0",x"0",x"3",x"3",x"2",x"1",
|
||||
x"4",x"A",x"5",x"3",x"4",x"3",x"0",x"0",x"3",x"2",x"5",x"0",x"4",x"A",x"4",x"5",
|
||||
x"4",x"8",x"0",x"0",x"3",x"1",x"3",x"6",x"5",x"2",x"4",x"D",x"4",x"9",x"0",x"0",
|
||||
x"3",x"0",x"1",x"8",x"4",x"B",x"4",x"5",x"4",x"E",x"0",x"0",x"2",x"9",x"1",x"0",
|
||||
x"5",x"0",x"4",x"7",x"4",x"4",x"0",x"0",x"2",x"8",x"0",x"0",x"5",x"0",x"4",x"1",
|
||||
x"4",x"8",x"0",x"0",x"2",x"7",x"9",x"8",x"4",x"E",x"5",x"6",x"4",x"2",x"0",x"0",
|
||||
x"2",x"6",x"7",x"2",x"4",x"1",x"4",x"7",x"5",x"2",x"0",x"0",x"2",x"5",x"2",x"9",
|
||||
x"5",x"6",x"4",x"C",x"4",x"7",x"0",x"0",x"2",x"4",x"7",x"3",x"4",x"4",x"4",x"F",
|
||||
x"4",x"E",x"0",x"0",x"2",x"3",x"9",x"0",x"5",x"7",x"4",x"5",x"5",x"3",x"0",x"0",
|
||||
x"2",x"2",x"6",x"2",x"4",x"A",x"5",x"0",x"4",x"4",x"0",x"0",x"2",x"1",x"8",x"3",
|
||||
x"5",x"0",x"4",x"6",x"5",x"A",x"0",x"0",x"2",x"0",x"2",x"1",x"4",x"B",x"4",x"7",
|
||||
x"4",x"D",x"0",x"0",x"1",x"9",x"1",x"8",x"4",x"B",x"5",x"2",x"4",x"4",x"0",x"0",
|
||||
x"1",x"8",x"9",x"9",x"5",x"3",x"4",x"3",x"4",x"C",x"0",x"0",x"1",x"7",x"2",x"1",
|
||||
x"5",x"2",x"4",x"1",x"5",x"7",x"0",x"0",x"1",x"6",x"7",x"8",x"4",x"2",x"4",x"1",
|
||||
x"4",x"E",x"0",x"0",x"1",x"5",x"2",x"1",x"5",x"0",x"5",x"6",x"4",x"1",x"0",x"0",
|
||||
x"1",x"4",x"5",x"2",x"4",x"A",x"4",x"3",x"2",x"0",x"0",x"0",x"1",x"3",x"7",x"8",
|
||||
x"2",x"0",x"4",x"5",x"5",x"3",x"0",x"0",x"1",x"2",x"6",x"4",x"4",x"8",x"4",x"5",
|
||||
x"4",x"3",x"0",x"0",x"1",x"1",x"3",x"7",x"4",x"D",x"4",x"2",x"5",x"3",x"0",x"0",
|
||||
x"1",x"0",x"6",x"2",x"5",x"2",x"4",x"3",x"4",x"2",x"0",x"0",x"0",x"9",x"3",x"5",
|
||||
x"5",x"0",x"4",x"A",x"4",x"5",x"0",x"0",x"0",x"8",x"2",x"8",x"4",x"2",x"4",x"6",
|
||||
x"4",x"4",x"0",x"0",x"0",x"7",x"9",x"0",x"4",x"4",x"4",x"1",x"5",x"2",x"0",x"0",
|
||||
x"0",x"7",x"5",x"0",x"5",x"3",x"4",x"4",x"5",x"7",x"0",x"0",x"0",x"6",x"7",x"8",
|
||||
x"A",x"D",x"0",x"0",x"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
|
||||
X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0");
|
||||
|
||||
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
|
||||
signal qReg : std_logic_vector((dWidth-1) downto 0);
|
||||
|
||||
begin
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Signals to entity interface
|
||||
-- -----------------------------------------------------------------------
|
||||
-- q <= qReg;
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory write
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if we = '1' then
|
||||
ram(to_integer(unsigned(addr))) <= d;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory read
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
|
||||
-- rAddrReg <= addr;
|
||||
-- qReg <= ram(to_integer(unsigned(addr)));
|
||||
q <= ram(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
--q <= ram(to_integer(unsigned(addr)));
|
||||
end architecture;
|
||||
|
||||
@@ -0,0 +1,202 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Tshoot sound board by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
-- https://sourceforge.net/projects/darfpga/files
|
||||
-- github.com/darfpga
|
||||
---------------------------------------------------------------------------------
|
||||
-- gen_ram.vhd
|
||||
--------------------------------
|
||||
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
|
||||
-- http://www.syntiac.com/fpga64.html
|
||||
---------------------------------------------------------------------------------
|
||||
-- cpu68 - Version 9th Jan 2004 0.8+
|
||||
-- 6800/01 compatible CPU core
|
||||
-- GNU public license - December 2002 : John E. Kent
|
||||
-- + 2019 Jared Boone
|
||||
-- + March 2020 Gyorgy Szombathelyi
|
||||
---------------------------------------------------------------------------------
|
||||
-- Educational use only
|
||||
-- Do not redistribute synthetized file with roms
|
||||
-- Do not redistribute roms whatever the form
|
||||
-- Use at your own risk
|
||||
---------------------------------------------------------------------------------
|
||||
-- Version 0.0 -- 04/03/2022 --
|
||||
-- initial version
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity tshoot_sound_board is
|
||||
port(
|
||||
clock_12 : in std_logic;
|
||||
reset : in std_logic;
|
||||
|
||||
sound_select : in std_logic_vector(7 downto 0);
|
||||
sound_trig : in std_logic;
|
||||
sound_ack : out std_logic;
|
||||
audio_out : out std_logic_vector( 7 downto 0);
|
||||
|
||||
snd_rom_addr : out std_logic_vector(12 downto 0);
|
||||
snd_rom_do : in std_logic_vector(7 downto 0);
|
||||
|
||||
dbg_cpu_addr : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end tshoot_sound_board;
|
||||
|
||||
architecture struct of tshoot_sound_board is
|
||||
|
||||
-- signal reset_n : std_logic;
|
||||
signal clock_div : std_logic_vector(3 downto 0);
|
||||
|
||||
signal cpu_clock : std_logic;
|
||||
signal cpu_addr : std_logic_vector(15 downto 0);
|
||||
signal cpu_di : std_logic_vector( 7 downto 0);
|
||||
signal cpu_do : std_logic_vector( 7 downto 0);
|
||||
signal cpu_rw_n : std_logic;
|
||||
signal cpu_irq : std_logic;
|
||||
|
||||
signal wram_cs : std_logic;
|
||||
signal wram_we : std_logic;
|
||||
signal wram_do : std_logic_vector( 7 downto 0);
|
||||
|
||||
signal rom_cs : std_logic;
|
||||
signal rom_do : std_logic_vector( 7 downto 0);
|
||||
|
||||
-- pia port a
|
||||
-- bit 0-7 audio output
|
||||
|
||||
-- pia port b
|
||||
-- bit 0-7 sound select input
|
||||
|
||||
-- pia io ca/cb
|
||||
-- ca1 => pia_02_cb2 (main cpu part - sound_trig)
|
||||
-- cb1 gnd
|
||||
-- ca2 => pia_02_cb1 (main cpu part - sound ack)
|
||||
-- cb2 gnd
|
||||
|
||||
signal pia_clock : std_logic;
|
||||
signal pia_rw_n : std_logic;
|
||||
signal pia_cs : std_logic;
|
||||
signal pia_irqa : std_logic;
|
||||
signal pia_irqb : std_logic;
|
||||
signal pia_do : std_logic_vector( 7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
dbg_cpu_addr <= cpu_addr;
|
||||
|
||||
-- clock divider
|
||||
process (reset, clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
if clock_div < 11 then
|
||||
clock_div <= clock_div + '1';
|
||||
else
|
||||
clock_div <= (others => '0');
|
||||
end if;
|
||||
if clock_div > 6 then
|
||||
cpu_clock <= '1';
|
||||
else
|
||||
cpu_clock <= '0';
|
||||
end if;
|
||||
|
||||
if clock_div > 7 and clock_div < 9 then
|
||||
pia_clock <= '1';
|
||||
else
|
||||
pia_clock <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- chip select
|
||||
wram_cs <= '1' when cpu_addr(15 downto 13) = "000" else '0';
|
||||
pia_cs <= '1' when cpu_addr(15 downto 13) = "001" else '0';
|
||||
rom_cs <= '1' when cpu_addr(15 downto 13) = "111" else '0';
|
||||
|
||||
-- write enables
|
||||
wram_we <= '1' when cpu_rw_n = '0' and cpu_clock = '1' and wram_cs = '1' else '0';
|
||||
pia_rw_n <= '0' when cpu_rw_n = '0' and pia_cs = '1' else '1';
|
||||
|
||||
-- mux cpu in data between roms/io/wram
|
||||
cpu_di <=
|
||||
wram_do when wram_cs = '1' else
|
||||
pia_do when pia_cs = '1' else
|
||||
rom_do when rom_cs = '1' else X"55";
|
||||
|
||||
-- pia irqs to cpu
|
||||
cpu_irq <= pia_irqa or pia_irqb;
|
||||
|
||||
-- microprocessor 6800
|
||||
main_cpu : entity work.cpu68
|
||||
port map(
|
||||
clk => cpu_clock,-- E clock input (falling edge)
|
||||
rst => reset, -- reset input (active high)
|
||||
rw => cpu_rw_n, -- read not write output
|
||||
vma => open, -- valid memory address (active high)
|
||||
address => cpu_addr, -- address bus output
|
||||
data_in => cpu_di, -- data bus input
|
||||
data_out => cpu_do, -- data bus output
|
||||
hold => '0', -- hold input (active high) extend bus cycle
|
||||
halt => '0', -- halt input (active high) grants DMA
|
||||
irq => cpu_irq, -- interrupt request input (active high)
|
||||
nmi => '0', -- non maskable interrupt request input (active high)
|
||||
test_alu => open,
|
||||
test_cc => open
|
||||
);
|
||||
|
||||
-- cpu program rom
|
||||
--cpu_prog_rom : entity work.turkey_shoot_sound
|
||||
--port map(
|
||||
-- clk => clock_12,
|
||||
-- addr => cpu_addr(12 downto 0),
|
||||
-- data => rom_do
|
||||
--);
|
||||
|
||||
snd_rom_addr <= cpu_addr(12 downto 0);
|
||||
rom_do <= snd_rom_do;
|
||||
|
||||
-- cpu wram
|
||||
cpu_ram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 8)
|
||||
port map(
|
||||
clk => clock_12,
|
||||
we => wram_we,
|
||||
addr => cpu_addr(7 downto 0),
|
||||
d => cpu_do,
|
||||
q => wram_do
|
||||
);
|
||||
|
||||
-- pia
|
||||
pia : entity work.pia6821
|
||||
port map
|
||||
(
|
||||
clk => pia_clock,
|
||||
rst => reset,
|
||||
cs => pia_cs,
|
||||
rw => pia_rw_n,
|
||||
addr => cpu_addr(1 downto 0),
|
||||
data_in => cpu_do,
|
||||
data_out => pia_do,
|
||||
irqa => pia_irqa,
|
||||
irqb => pia_irqb,
|
||||
pa_i => sound_select,
|
||||
pa_o => open,
|
||||
pa_oe => open,
|
||||
ca1 => sound_trig,
|
||||
ca2_i => '0',
|
||||
ca2_o => sound_ack,
|
||||
ca2_oe => open,
|
||||
pb_i => x"00",
|
||||
pb_o => audio_out,
|
||||
pb_oe => open,
|
||||
cb1 => '0',
|
||||
cb2_i => '0',
|
||||
cb2_o => open,
|
||||
cb2_oe => open
|
||||
);
|
||||
|
||||
end struct;
|
||||
1204
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/williams2.vhd
Normal file
1204
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/williams2.vhd
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user