mirror of
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TerraCresta: another port
This commit is contained in:
Gyorgy Szombathelyi
32
Arcade_MiST/Nichibutsu M68000 Hardware/TerraCresta/README.md
Normal file
32
Arcade_MiST/Nichibutsu M68000 Hardware/TerraCresta/README.md
Normal file
@@ -0,0 +1,32 @@
|
||||
# Nichibutsu M68000 (Terra Cresta) FPGA Implementation
|
||||
|
||||
Based on FPGA compatible core of Nichibutsu M68000 (Terra Cresta based) arcade hardware written by [**Darren Olafson**](https://twitter.com/Darren__O).
|
||||
Original core: https://github.com/va7deo/TerraCresta
|
||||
|
||||
Port, factoring out PCB code, SDRAM controller, flip support, clocking and other fixes by Slingshot.
|
||||
|
||||
The intent is for this core to be a 1:1 implementation of the Nichibutsu (Terra Cresta based) 68000 hardware.
|
||||
|
||||
## Supported Games
|
||||
|
||||
| Title | Status | Released | Protection | Protected Sets |
|
||||
|------|---------|----------|------------|----------------|
|
||||
[**Terra Cresta**](https://en.wikipedia.org/wiki/Terra_Cresta) | Implemented | **Y** | None | N/A |
|
||||
[**Sei Senshi Amatelass**](https://en.wikipedia.org/wiki/Nihon_Bussan) | Implemented | **Y** | NB1412M2 | **amatelass, amazon** |
|
||||
[**Kid no Hore Hore Daisakusen**](https://en.wikipedia.org/wiki/Nihon_Bussan) | Implemented | **Y** | NB1412M2 | **horekid** |
|
||||
|
||||
## External Modules
|
||||
|
||||
|Name| Purpose | Author |
|
||||
|----|---------|--------|
|
||||
| [**fx68k**](https://github.com/ijor/fx68k) | [**Motorola 68000 CPU**](https://en.wikipedia.org/wiki/Motorola_68000) | Jorge Cwik |
|
||||
| [**t80**](https://opencores.org/projects/t80) | [**Zilog Z80 CPU**](https://en.wikipedia.org/wiki/Zilog_Z80) | Daniel Wallner |
|
||||
| [**jtopl**](https://github.com/jotego/jtopl) | [**Yamaha OPL**](https://en.wikipedia.org/wiki/Yamaha_OPL#OPL) | Jose Tejada |
|
||||
|
||||
# Support
|
||||
|
||||
Please consider showing support for this and future projects via [**Ko-fi**](https://ko-fi.com/darreno). While it isn't necessary, it's greatly appreciated.
|
||||
|
||||
# Licensing
|
||||
|
||||
Contact the author for special licensing needs. Otherwise follow the GPLv2 license attached.
|
||||
@@ -0,0 +1,31 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel MegaCore Function License Agreement, or other
|
||||
# applicable license agreement, including, without limitation,
|
||||
# that your use is for the sole purpose of programming logic
|
||||
# devices manufactured by Intel and sold by Intel or its
|
||||
# authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
|
||||
# Date created = 04:04:47 October 16, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "17.0"
|
||||
DATE = "04:04:47 October 16, 2017"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "TerraCresta"
|
||||
@@ -0,0 +1,220 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
# Date created = 05:08:48 November 15, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# Arcade-Scramble_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
|
||||
set_location_assignment PIN_54 -to CLOCK_27
|
||||
set_location_assignment PIN_144 -to VGA_R[5]
|
||||
set_location_assignment PIN_143 -to VGA_R[4]
|
||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
||||
set_location_assignment PIN_137 -to VGA_R[1]
|
||||
set_location_assignment PIN_135 -to VGA_R[0]
|
||||
set_location_assignment PIN_133 -to VGA_B[5]
|
||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_90 -to SPI_SS4
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_4 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_6 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_8 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_10 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_11 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_28 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_50 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_30 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_32 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
|
||||
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY TerraCresta_MiST
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# ----------------------
|
||||
# start ENTITY(TerraCresta)
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(TerraCresta)
|
||||
# --------------------
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name ENABLE_NCE_PIN OFF
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE output_files/spr.stp
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name DSP_BLOCK_BALANCING "DSP BLOCKS"
|
||||
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
|
||||
set_global_assignment -name QIP_FILE rtl/pll.qip
|
||||
set_global_assignment -name VERILOG_FILE rtl/chip_select.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/TerraCresta_MiST.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/TerraCresta.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_timing.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/mem/dual_port_ram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/mem/math.vhd
|
||||
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
|
||||
set_global_assignment -name QIP_FILE ../../../common/CPU/68000/FX68k/fx68k.qip
|
||||
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
|
||||
set_global_assignment -name QIP_FILE ../../../common/Sound/jtopl/jt26.qip
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/TerraCresta.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/terracr.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/spr.stp
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -0,0 +1,135 @@
|
||||
## Generated SDC file "vectrex_MiST.out.sdc"
|
||||
|
||||
## Copyright (C) 1991-2013 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
|
||||
|
||||
## DATE "Sun Jun 24 12:53:00 2018"
|
||||
|
||||
##
|
||||
## DEVICE "EP3C25E144C8"
|
||||
##
|
||||
|
||||
# Clock constraints
|
||||
|
||||
# Automatically constrain PLL and other generated clocks
|
||||
derive_pll_clocks -create_base_clocks
|
||||
|
||||
# Automatically calculate clock uncertainty to jitter and other effects.
|
||||
derive_clock_uncertainty
|
||||
|
||||
# tsu/th constraints
|
||||
|
||||
# tco constraints
|
||||
|
||||
# tpd constraints
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
|
||||
|
||||
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
|
||||
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
|
||||
|
||||
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
|
||||
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
set_output_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
|
||||
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
|
||||
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
|
||||
set_output_delay -add_delay -clock [get_clocks $sdram_clk] 1.000 [get_ports {LED}]
|
||||
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
|
||||
|
||||
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
set_multicycle_path -to {VGA_*[*]} -setup 2
|
||||
set_multicycle_path -to {VGA_*[*]} -hold 1
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
@@ -0,0 +1,75 @@
|
||||
<misterromdescription>
|
||||
<name>Kid no Hore Hore Daisakusen</name>
|
||||
<mameversion>0240</mameversion>
|
||||
<setname>horekid</setname>
|
||||
<year>1987</year>
|
||||
<manufacturer>Nichibutsu</manufacturer>
|
||||
<category>Platformer</category>
|
||||
<rbf>terracresta</rbf>
|
||||
|
||||
<switches default="8F,AF" base="16" page_id="1" page_name="Switches">
|
||||
<!-- DSW -->
|
||||
<dip name="Lives" bits="0,1" ids="6,5,4,3"/>
|
||||
<dip name="Bonus Life" bits="2,3" ids="50k/90k(E),20k/90k(E),50k/60k(E),20k/60k(E)"/>
|
||||
<dip name="Demo Sounds" bits="4" ids="On,Off"/>
|
||||
<dip name="Cabinet" bits="5" ids="Upright,Cocktail"/>
|
||||
<dip name="Difficulty" bits="6,7" ids="Hardest,Hard,Normal,Easy"/>
|
||||
<dip name="Coin A" bits="8,9" ids="Free Play,2/1,1/2,1/1"/>
|
||||
<dip name="Coin B" bits="10,11" ids="2/3,2/1,1/2,1/1"/>
|
||||
<dip name="Flip Screen" bits="13" ids="On,Off"/>
|
||||
<dip name="Debug Mode" bits="14,15" ids="Off,Off,On,Off"/>
|
||||
</switches>
|
||||
|
||||
<buttons names="Dig/Burry,Open/Close Door,Start (1p),Start (2p),Coin,Pause" default="A,B,X,R,L,Start"/>
|
||||
|
||||
<rom index="0" zip="horekid.zip" md5="None">
|
||||
|
||||
<!-- maincpu - starts at 0x0 -->
|
||||
<interleave output="16">
|
||||
<part name="horekid.01" crc="a282faf8" map="01"/>
|
||||
<part name="horekid.03" crc="90ec840f" map="10"/>
|
||||
</interleave>
|
||||
<interleave output="16">
|
||||
<part name="horekid.02" crc="ee7d52bb" map="01"/>
|
||||
<part name="horekid.04" crc="375c0c50" map="10"/>
|
||||
</interleave>
|
||||
|
||||
<!-- gfx2 - starts at 0x20000 -->
|
||||
<part name="horekid.05" crc="da25ae10"/>
|
||||
<part name="horekid.06" crc="616e4321"/>
|
||||
<part name="horekid.07" crc="8c7d2be2"/>
|
||||
<part name="horekid.08" crc="a0066b02"/>
|
||||
|
||||
<!-- gfx3 - starts at 0x40000 -->
|
||||
<part name="horekid.12" crc="a3caa07a"/>
|
||||
<part name="horekid.13" crc="0e48ff8e"/>
|
||||
<part name="horekid.14" crc="e300747a"/>
|
||||
<part name="horekid.15" crc="51105741"/>
|
||||
|
||||
<!-- gfx1 - starts at 0x60000 -->
|
||||
<part name="horekid.16" crc="104b77cc"/>
|
||||
<part repeat="0xE000"> FF</part>
|
||||
|
||||
<!-- audiocpu - starts at 0x70000 -->
|
||||
<part name="horekid.09" crc="49cd3b81"/>
|
||||
<part name="horekid.10" crc="c1eaa938"/>
|
||||
<part name="horekid.11" crc="0a2bc702"/>
|
||||
|
||||
<!-- prot_chip - starts at 0x7C000 -->
|
||||
<part name="horekid.17" crc="1d8d592b"/>
|
||||
|
||||
<!-- proms - starts at 0x7E000 -->
|
||||
<part name="kid_prom.10f" crc="ca13ce23"/>
|
||||
<part name="kid_prom.11f" crc="fb44285a"/>
|
||||
<part name="kid_prom.12f" crc="40d41237"/>
|
||||
<part name="kid_prom.2g" crc="4b9be0ed"/>
|
||||
|
||||
<!-- user1 - starts at 0x7E400 -->
|
||||
<part name="kid_prom.4e" crc="e4fb54ee"/>
|
||||
<!-- Total 0x7E500 bytes - 505 kBytes -->
|
||||
</rom>
|
||||
|
||||
<rom index="1">
|
||||
<part>02</part>
|
||||
</rom>
|
||||
</misterromdescription>
|
||||
@@ -0,0 +1,78 @@
|
||||
<misterromdescription>
|
||||
<name>Sei Senshi Amatelass</name>
|
||||
<mameversion>0240</mameversion>
|
||||
<setname>amatelas</setname>
|
||||
<year>1986</year>
|
||||
<manufacturer>Nichibutsu</manufacturer>
|
||||
<category>Shoot 'em up</category>
|
||||
<rbf>terracresta</rbf>
|
||||
|
||||
<switches default="FF,FB" base="16" page_id="1" page_name="Switches">
|
||||
<!-- DSW -->
|
||||
<dip name="Lives" bits="0,1" ids="6,5,4,3"/>
|
||||
<dip name="Bonus Life" bits="2,3" ids="50k/70k(E),20k/70k(E),50k/40k(E),20k/40k(E)"/>
|
||||
<dip name="Demo Sounds" bits="4" ids="Off,On"/>
|
||||
<dip name="Cabinet" bits="5" ids="Upright,Cocktail"/>
|
||||
<dip name="Invincibility" bits="7" ids="On,Off"/>
|
||||
<dip name="Coin A" bits="8,9" ids="Free Play,2/1,1/2,1/1"/>
|
||||
<dip name="Coin B" bits="10,11" ids="3/1,2/3,1/1,1/3"/>
|
||||
<dip name="Difficulty" bits="12" ids="Hard,Easy"/>
|
||||
<dip name="Flip Screen" bits="13" ids="On,Off"/>
|
||||
<dip name="Level" bits="14" ids="High,Low"/>
|
||||
<dip name="Sprite Test" bits="15" ids="On,Off"/>
|
||||
</switches>
|
||||
|
||||
<buttons names="Sword Beam,Stop Bullet,Start (1p),Start (2p),Coin,Pause" default="A,B,X,R,L,Start"/>
|
||||
|
||||
<rom index="0" zip="amatelas.zip|amazon.zip" md5="None">
|
||||
|
||||
<!-- maincpu - starts at 0x0 -->
|
||||
<interleave output="16">
|
||||
<part name="a9.4b" crc="e2a0d21d" map="01"/>
|
||||
<part name="a11.4d" crc="3d226d0b" map="10"/>
|
||||
</interleave>
|
||||
<interleave output="16">
|
||||
<part name="a10.6b" crc="dbc1f1b4" map="01"/>
|
||||
<part name="a12.6d" crc="e6607c51" map="10"/>
|
||||
</interleave>
|
||||
|
||||
<!-- gfx2 - starts at 0x20000 -->
|
||||
<part name="13.15f" crc="415ff4d9"/>
|
||||
<part name="14.17f" crc="492b5c48"/>
|
||||
<part name="15.18f" crc="b1ac0b9d"/>
|
||||
<part repeat="0x8000"> FF</part>
|
||||
|
||||
<!-- gfx3 - starts at 0x40000 -->
|
||||
<part name="4.6e" crc="f77ced7a"/>
|
||||
<part name="a5.7e" crc="5fbf9a16"/>
|
||||
<part name="6.6g" crc="936ec941"/>
|
||||
<part name="7.7g" crc="66dd718e"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
|
||||
<!-- gfx1 - starts at 0x60000 -->
|
||||
<part name="a8.16g" crc="aeba2102"/>
|
||||
<part repeat="0xE000"> FF</part>
|
||||
|
||||
<!-- audiocpu - starts at 0x70000 -->
|
||||
<part name="1.15b" crc="55a8b5e7"/>
|
||||
<part name="2.17b" crc="427a7cca"/>
|
||||
<part name="3.18b" crc="b8cceaf7"/>
|
||||
|
||||
<!-- prot_chip - starts at 0x7C000 -->
|
||||
<part name="16.18g" crc="1d8d592b"/>
|
||||
|
||||
<!-- proms - starts at 0x7E000 -->
|
||||
<part name="clr.10f" crc="6440b341"/>
|
||||
<part name="clr.11f" crc="271e947f"/>
|
||||
<part name="clr.12f" crc="7d38621b"/>
|
||||
<part name="2g" crc="44ca16b9"/>
|
||||
|
||||
<!-- user1 - starts at 0x7E400 -->
|
||||
<part name="4e" crc="035f2c7b"/>
|
||||
<!-- Total 0x7E500 bytes - 505 kBytes -->
|
||||
</rom>
|
||||
|
||||
<rom index="1">
|
||||
<part>01</part>
|
||||
</rom>
|
||||
</misterromdescription>
|
||||
@@ -0,0 +1,70 @@
|
||||
<misterromdescription>
|
||||
<name>Terra Cresta (YM3526 set 1)</name>
|
||||
<mameversion>0240</mameversion>
|
||||
<setname>terracre</setname>
|
||||
<year>1985</year>
|
||||
<manufacturer>Nichibutsu</manufacturer>
|
||||
<category>Shoot 'em up</category>
|
||||
<rbf>terracresta</rbf>
|
||||
|
||||
<switches default="3F,FF" base="16" page_id="1" page_name="Switches">
|
||||
<!-- DSW -->
|
||||
<dip name="Lives" bits="0,1" ids="6,5,4,3"/>
|
||||
<dip name="Bonus Life" bits="2,3" ids="50k/90k(E),40k/80k(E),30k/70k(E),20k/60k(E)"/>
|
||||
<dip name="Demo Sounds" bits="4" ids="Off,On"/>
|
||||
<dip name="Cabinet" bits="5" ids="Upright,Cocktail"/>
|
||||
<dip name="Coin A" bits="8,9" ids="Free Play,2/1,1/2,1/1"/>
|
||||
<dip name="Coin B" bits="10,11" ids="3/1,2/3,1/6,1/3"/>
|
||||
<dip name="Difficulty" bits="12" ids="Hard,Easy"/>
|
||||
<dip name="Flip Screen" bits="13" ids="On,Off"/>
|
||||
<dip name="Complete Invincibility" bits="14" ids="On,Off"/>
|
||||
<dip name="Ship Invincibility" bits="15" ids="On,Off"/>
|
||||
</switches>
|
||||
|
||||
<buttons names="Cannon Beam,Formation,Start (1p),Start (2p),Coin,Pause" default="A,B,X,R,L,Start"/>
|
||||
|
||||
<rom index="0" zip="terracre.zip" md5="None">
|
||||
|
||||
<!-- maincpu - starts at 0x0 -->
|
||||
<interleave output="16">
|
||||
<part name="1.4b" crc="60932770" map="01"/>
|
||||
<part name="3.4d" crc="cb36240e" map="10"/>
|
||||
</interleave>
|
||||
<interleave output="16">
|
||||
<part name="2.6b" crc="539352f2" map="01"/>
|
||||
<part name="4.6d" crc="19387586" map="10"/>
|
||||
</interleave>
|
||||
|
||||
<!-- gfx2 - starts at 0x20000 -->
|
||||
<part name="5.15f" crc="984a597f"/>
|
||||
<part name="6.17f" crc="30e297ff"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
|
||||
<!-- gfx3 - starts at 0x40000 -->
|
||||
<part name="7.6e" crc="bcf7740b"/>
|
||||
<part name="8.7e" crc="a70b565c"/>
|
||||
<part name="9.6g" crc="4a9ec3e6"/>
|
||||
<part name="10.7g" crc="450749fc"/>
|
||||
<part repeat="0x10000"> FF</part>
|
||||
|
||||
<!-- gfx1 - starts at 0x60000 -->
|
||||
<part name="14.16g" crc="591a3804"/>
|
||||
<part repeat="0xE000"> FF</part>
|
||||
|
||||
<!-- audiocpu - starts at 0x70000 -->
|
||||
<part name="11.15b" crc="604c3b11"/>
|
||||
<part name="12.17b" crc="affc898d"/>
|
||||
<part name="13.18b" crc="302dc0ab"/>
|
||||
<part repeat="0x2000"> FF</part>
|
||||
|
||||
<!-- proms - starts at 0x7E000 -->
|
||||
<part name="3.10f" crc="ce07c544"/>
|
||||
<part name="2.11f" crc="566d323a"/>
|
||||
<part name="1.12f" crc="7ea63946"/>
|
||||
<part name="4.2g" crc="08609bad"/>
|
||||
|
||||
<!-- user1 - starts at 0x7E400 -->
|
||||
<part name="5.4e" crc="2c43991f"/>
|
||||
<!-- Total 0x7E500 bytes - 505 kBytes -->
|
||||
</rom>
|
||||
</misterromdescription>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,293 @@
|
||||
//============================================================================
|
||||
// Nichibutsu M68000 HW top-level for MiST
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//============================================================================
|
||||
|
||||
module TerraCresta_MiST
|
||||
(
|
||||
output LED,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
inout SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input SPI_SS4,
|
||||
input CONF_DATA0,
|
||||
input CLOCK_27,
|
||||
|
||||
output [12:0] SDRAM_A,
|
||||
inout [15:0] SDRAM_DQ,
|
||||
output SDRAM_DQML,
|
||||
output SDRAM_DQMH,
|
||||
output SDRAM_nWE,
|
||||
output SDRAM_nCAS,
|
||||
output SDRAM_nRAS,
|
||||
output SDRAM_nCS,
|
||||
output [1:0] SDRAM_BA,
|
||||
output SDRAM_CLK,
|
||||
output SDRAM_CKE
|
||||
);
|
||||
|
||||
`include "rtl\build_id.v"
|
||||
`include "defs.v"
|
||||
|
||||
`define CORE_NAME "TERRACRE"
|
||||
wire [6:0] core_mod;
|
||||
|
||||
localparam CONF_STR = {
|
||||
`CORE_NAME, ";;",
|
||||
"O2,Rotate Controls,Off,On;",
|
||||
"O34,Scanlines,Off,25%,50%,75%;",
|
||||
"O5,Blending,Off,On;",
|
||||
"O6,Joystick Swap,Off,On;",
|
||||
"O7,Pause,Off,On;",
|
||||
"O8,Service mode,Off,On;",
|
||||
// "O9,FG,On,Off;",
|
||||
// "OA,BG,On,Off;",
|
||||
// "OB,SPR,On,Off;",
|
||||
"DIP;",
|
||||
"T0,Reset;",
|
||||
"V,v1.20.",`BUILD_DATE
|
||||
};
|
||||
|
||||
wire rotate = status[2];
|
||||
wire [1:0] scanlines = status[4:3];
|
||||
wire blend = status[5];
|
||||
wire joyswap = status[6];
|
||||
wire pause = status[7];
|
||||
wire service = status[8];
|
||||
|
||||
wire [15:0] dsw = status[31:16];
|
||||
wire [7:0] sys;
|
||||
reg [7:0] p1, p2;
|
||||
wire flipped;
|
||||
wire [1:0] orientation = {flipped, 1'b1};
|
||||
|
||||
always @(*) begin
|
||||
sys = ~{ 2'b00, service, m_fireD /*service*/, m_coin2, m_coin1, m_two_players, m_one_player };
|
||||
|
||||
p1[ 3:0] = ~{ m_right, m_left, m_down, m_up };
|
||||
p2[ 3:0] = ~{ m_right2, m_left2, m_down2, m_up2 };
|
||||
|
||||
p1[ 7:4] = ~{ 1'b0, m_fireC, m_fireB, m_fireA };
|
||||
p2[ 7:4] = ~{ 1'b0, m_fire2C, m_fire2B, m_fire2A };
|
||||
end
|
||||
|
||||
assign LED = ~ioctl_downl;
|
||||
assign SDRAM_CLK = clk_96;
|
||||
assign SDRAM_CKE = 1;
|
||||
|
||||
wire clk_24, clk_96;
|
||||
wire pll_locked;
|
||||
pll pll(
|
||||
.inclk0(CLOCK_27),
|
||||
.areset(0),
|
||||
.c0(clk_96),
|
||||
.c1(clk_24),
|
||||
.locked(pll_locked)
|
||||
);
|
||||
|
||||
// reset generation
|
||||
reg reset = 1;
|
||||
reg rom_loaded = 0;
|
||||
always @(posedge clk_96) begin
|
||||
reg ioctl_downlD;
|
||||
ioctl_downlD <= ioctl_downl;
|
||||
|
||||
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
|
||||
reset <= status[0] | buttons[1] | ~rom_loaded | ioctl_downl;
|
||||
end
|
||||
|
||||
// ARM connection
|
||||
wire [63:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [31:0] joystick_0;
|
||||
wire [31:0] joystick_1;
|
||||
wire scandoublerD;
|
||||
wire ypbpr;
|
||||
wire no_csync;
|
||||
wire key_strobe;
|
||||
wire key_pressed;
|
||||
wire [7:0] key_code;
|
||||
|
||||
user_io #(
|
||||
.STRLEN($size(CONF_STR)>>3),
|
||||
.ROM_DIRECT_UPLOAD(1))
|
||||
user_io(
|
||||
.clk_sys (clk_24 ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
.SPI_MISO (SPI_DO ),
|
||||
.SPI_MOSI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.no_csync (no_csync ),
|
||||
.core_mod (core_mod ),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.joystick_0 (joystick_0 ),
|
||||
.joystick_1 (joystick_1 ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
wire ioctl_downl;
|
||||
wire [7:0] ioctl_index;
|
||||
wire ioctl_wr;
|
||||
wire [24:0] ioctl_addr;
|
||||
wire [7:0] ioctl_dout;
|
||||
|
||||
data_io #(.ROM_DIRECT_UPLOAD(1)) data_io(
|
||||
.clk_sys ( clk_96 ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS2 ( SPI_SS2 ),
|
||||
.SPI_SS4 ( SPI_SS4 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.SPI_DO ( SPI_DO ),
|
||||
.ioctl_download( ioctl_downl ),
|
||||
.ioctl_index ( ioctl_index ),
|
||||
.ioctl_wr ( ioctl_wr ),
|
||||
.ioctl_addr ( ioctl_addr ),
|
||||
.ioctl_dout ( ioctl_dout )
|
||||
);
|
||||
|
||||
wire [15:0] laudio, raudio;
|
||||
wire hs, vs;
|
||||
wire blankn = ~(hb | vb);
|
||||
wire hb, vb;
|
||||
wire [3:0] r,b,g;
|
||||
|
||||
TerraCresta TerraCresta
|
||||
(
|
||||
.pll_locked ( pll_locked ),
|
||||
.clk_96M ( clk_96 ),
|
||||
.clk_24M ( clk_24 ),
|
||||
.reset ( reset ),
|
||||
.pause_cpu ( pause ),
|
||||
|
||||
.pcb ( core_mod ),
|
||||
.fg_enable ( ~status[9] ),
|
||||
.bg_enable ( ~status[10]),
|
||||
.spr_enable ( ~status[11]),
|
||||
|
||||
.p1 ( p1 ),
|
||||
.p2 ( p2 ),
|
||||
.dsw1 ( dsw ),
|
||||
.sys ( sys ),
|
||||
|
||||
.hbl ( hb ),
|
||||
.vbl ( vb ),
|
||||
.hsync ( hs ),
|
||||
.vsync ( vs ),
|
||||
.r ( r ),
|
||||
.g ( g ),
|
||||
.b ( b ),
|
||||
.flipped ( flipped ),
|
||||
|
||||
.audio_l ( laudio ),
|
||||
.audio_r ( raudio ),
|
||||
|
||||
.rom_download ( ioctl_downl && ioctl_index == 0),
|
||||
.ioctl_addr ( ioctl_addr ),
|
||||
.ioctl_wr ( ioctl_wr ),
|
||||
.ioctl_dout ( ioctl_dout ),
|
||||
|
||||
.SDRAM_A ( SDRAM_A ),
|
||||
.SDRAM_BA ( SDRAM_BA ),
|
||||
.SDRAM_DQ ( SDRAM_DQ ),
|
||||
.SDRAM_DQML ( SDRAM_DQML ),
|
||||
.SDRAM_DQMH ( SDRAM_DQMH ),
|
||||
.SDRAM_nCS ( SDRAM_nCS ),
|
||||
.SDRAM_nCAS ( SDRAM_nCAS ),
|
||||
.SDRAM_nRAS ( SDRAM_nRAS ),
|
||||
.SDRAM_nWE ( SDRAM_nWE )
|
||||
);
|
||||
|
||||
mist_video #(.COLOR_DEPTH(4),.SD_HCNT_WIDTH(10)) mist_video(
|
||||
.clk_sys(clk_24),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_SS3(SPI_SS3),
|
||||
.SPI_DI(SPI_DI),
|
||||
.R(blankn ? r : 6'd0),
|
||||
.G(blankn ? g : 6'd0),
|
||||
.B(blankn ? b : 6'd0),
|
||||
.HSync(~hs),
|
||||
.VSync(~vs),
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_HS(VGA_HS),
|
||||
.no_csync(no_csync),
|
||||
.rotate({orientation[1],rotate}),
|
||||
.ce_divider(1'b1),
|
||||
.blend(blend),
|
||||
.scandoubler_disable(scandoublerD),
|
||||
.scanlines(scanlines),
|
||||
.ypbpr(ypbpr)
|
||||
);
|
||||
|
||||
dac #(16) dacl(
|
||||
.clk_i(clk_24),
|
||||
.res_n_i(1),
|
||||
.dac_i({~laudio[15], laudio[14:0]}),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
|
||||
dac #(16) dacr(
|
||||
.clk_i(clk_24),
|
||||
.res_n_i(1),
|
||||
.dac_i({~raudio[15], raudio[14:0]}),
|
||||
.dac_o(AUDIO_R)
|
||||
);
|
||||
|
||||
// Common inputs
|
||||
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF, m_upB, m_downB, m_leftB, m_rightB;
|
||||
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F, m_up2B, m_down2B, m_left2B, m_right2B;
|
||||
wire m_up3, m_down3, m_left3, m_right3, m_fire3A, m_fire3B, m_fire3C, m_fire3D, m_fire3E, m_fire3F, m_up3B, m_down3B, m_left3B, m_right3B;
|
||||
wire m_up4, m_down4, m_left4, m_right4, m_fire4A, m_fire4B, m_fire4C, m_fire4D, m_fire4E, m_fire4F, m_up4B, m_down4B, m_left4B, m_right4B;
|
||||
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
|
||||
|
||||
arcade_inputs inputs (
|
||||
.clk ( clk_24 ),
|
||||
.key_strobe ( key_strobe ),
|
||||
.key_pressed ( key_pressed ),
|
||||
.key_code ( key_code ),
|
||||
.joystick_0 ( joystick_0 ),
|
||||
.joystick_1 ( joystick_1 ),
|
||||
.rotate ( rotate ),
|
||||
.orientation ( orientation ),
|
||||
.joyswap ( joyswap ),
|
||||
.oneplayer ( 1'b0 ),
|
||||
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
|
||||
.player1 ( {m_upB, m_downB, m_leftB, m_rightB, 6'd0, m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
|
||||
.player2 ( {m_up2B, m_down2B, m_left2B, m_right2B, 6'd0, m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ),
|
||||
.player3 ( {m_up3B, m_down3B, m_left3B, m_right3B, 6'd0, m_fire3F, m_fire3E, m_fire3D, m_fire3C, m_fire3B, m_fire3A, m_up3, m_down3, m_left3, m_right3} ),
|
||||
.player4 ( {m_up4B, m_down4B, m_left4B, m_right4B, 6'd0, m_fire4F, m_fire4E, m_fire4D, m_fire4C, m_fire4B, m_fire4A, m_up4, m_down4, m_left4, m_right4} )
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,35 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
@@ -0,0 +1,165 @@
|
||||
//
|
||||
|
||||
module chip_select
|
||||
(
|
||||
input [2:0] pcb,
|
||||
|
||||
input [23:0] m68k_a,
|
||||
input m68k_as_n,
|
||||
input m68k_uds_n,
|
||||
input m68k_lds_n,
|
||||
|
||||
input [15:0] z80_addr,
|
||||
input RFSH_n,
|
||||
input MREQ_n,
|
||||
input IORQ_n,
|
||||
|
||||
// M68K selects
|
||||
output reg prog_rom_cs,
|
||||
output reg m68k_ram_cs,
|
||||
output reg bg_ram_cs,
|
||||
output reg m68k_ram1_cs,
|
||||
output reg fg_ram_cs,
|
||||
output reg flip_cs,
|
||||
|
||||
output reg input_p1_cs,
|
||||
output reg input_p2_cs,
|
||||
output reg input_system_cs,
|
||||
output reg input_dsw_cs,
|
||||
|
||||
output reg scroll_x_cs,
|
||||
output reg scroll_y_cs,
|
||||
|
||||
output reg sound_latch_cs,
|
||||
|
||||
output reg prot_chip_data_cs,
|
||||
output reg prot_chip_cmd_cs,
|
||||
|
||||
// Z80 selects
|
||||
output reg z80_rom_cs,
|
||||
output reg z80_ram_cs,
|
||||
|
||||
output reg z80_sound0_cs,
|
||||
output reg z80_sound1_cs,
|
||||
output reg z80_dac1_cs,
|
||||
output reg z80_dac2_cs,
|
||||
output reg z80_latch_clr_cs,
|
||||
output reg z80_latch_r_cs
|
||||
|
||||
// other params
|
||||
// output reg [15:0] scroll_x,
|
||||
// output reg [15:0] scroll_y,
|
||||
// output reg [7:0] sound_latch
|
||||
);
|
||||
|
||||
`include "defs.v"
|
||||
|
||||
function m68k_cs;
|
||||
input [23:0] start_address;
|
||||
input [23:0] end_address;
|
||||
begin
|
||||
m68k_cs = ( m68k_a[23:0] >= start_address && m68k_a[23:0] <= end_address) & !m68k_as_n & !(m68k_uds_n & m68k_lds_n);
|
||||
end
|
||||
endfunction
|
||||
|
||||
function z80_mem_cs;
|
||||
input [15:0] start_address;
|
||||
input [15:0] end_address;
|
||||
begin
|
||||
z80_mem_cs = ( z80_addr >= start_address && z80_addr <= end_address ) & !MREQ_n & RFSH_n;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function z80_io_cs;
|
||||
input [7:0] address_lo;
|
||||
begin
|
||||
z80_io_cs = ( IORQ_n == 0 && z80_addr[7:0] == address_lo );
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
always @ (*) begin
|
||||
// Memory mapping based on PCB type
|
||||
|
||||
prot_chip_data_cs = 0;
|
||||
prot_chip_cmd_cs = 0;
|
||||
|
||||
if ( pcb == pcb_terra_cresta ) begin
|
||||
prog_rom_cs = m68k_cs( 24'h000000, 24'h01ffff );
|
||||
m68k_ram_cs = m68k_cs( 24'h020000, 24'h021fff );
|
||||
bg_ram_cs = m68k_cs( 24'h022000, 24'h022fff );
|
||||
m68k_ram1_cs = m68k_cs( 24'h023000, 24'h023fff );
|
||||
|
||||
input_p1_cs = m68k_cs( 24'h024000, 24'h024001 );
|
||||
input_p2_cs = m68k_cs( 24'h024002, 24'h024003 );
|
||||
input_system_cs = m68k_cs( 24'h024004, 24'h024005 );
|
||||
input_dsw_cs = m68k_cs( 24'h024006, 24'h024007 );
|
||||
|
||||
flip_cs = m68k_cs( 24'h026000, 24'h026001 );
|
||||
scroll_x_cs = m68k_cs( 24'h026002, 24'h026003 );
|
||||
scroll_y_cs = m68k_cs( 24'h026004, 24'h026005 );
|
||||
|
||||
sound_latch_cs = m68k_cs( 24'h02600c, 24'h02600d );
|
||||
fg_ram_cs = m68k_cs( 24'h028000, 24'h0287ff );
|
||||
end else begin
|
||||
prog_rom_cs = m68k_cs( 24'h000000, 24'h01ffff );
|
||||
m68k_ram_cs = m68k_cs( 24'h040000, 24'h040fff );
|
||||
bg_ram_cs = m68k_cs( 24'h042000, 24'h042fff );
|
||||
m68k_ram1_cs = 0;
|
||||
|
||||
input_p1_cs = m68k_cs( 24'h044000, 24'h044001 );
|
||||
input_p2_cs = m68k_cs( 24'h044002, 24'h044003 );
|
||||
input_system_cs = m68k_cs( 24'h044004, 24'h044005 );
|
||||
input_dsw_cs = m68k_cs( 24'h044006, 24'h044007 );
|
||||
|
||||
flip_cs = m68k_cs( 24'h046000, 24'h046001 );
|
||||
scroll_x_cs = m68k_cs( 24'h046002, 24'h046003 );
|
||||
scroll_y_cs = m68k_cs( 24'h046004, 24'h046004 );
|
||||
|
||||
sound_latch_cs = m68k_cs( 24'h04600c, 24'h04600d );
|
||||
|
||||
fg_ram_cs = m68k_cs( 24'h050000, 24'h050fff );
|
||||
|
||||
|
||||
prog_rom_cs = m68k_cs( 24'h000000, 24'h01ffff );
|
||||
m68k_ram_cs = m68k_cs( 24'h040000, 24'h040fff );
|
||||
bg_ram_cs = m68k_cs( 24'h042000, 24'h042fff );
|
||||
m68k_ram1_cs = 0;
|
||||
|
||||
if ( pcb == pcb_horekid ) begin
|
||||
input_p1_cs = m68k_cs( 24'h044006, 24'h044007 );
|
||||
input_p2_cs = m68k_cs( 24'h044004, 24'h044005 );
|
||||
input_system_cs = m68k_cs( 24'h044002, 24'h044003 );
|
||||
input_dsw_cs = m68k_cs( 24'h044000, 24'h044001 );
|
||||
end else begin
|
||||
input_p1_cs = m68k_cs( 24'h044000, 24'h044001 );
|
||||
input_p2_cs = m68k_cs( 24'h044002, 24'h044003 );
|
||||
input_system_cs = m68k_cs( 24'h044004, 24'h044005 );
|
||||
input_dsw_cs = m68k_cs( 24'h044006, 24'h044007 );
|
||||
end
|
||||
|
||||
scroll_x_cs = m68k_cs( 24'h046002, 24'h046003 );
|
||||
scroll_y_cs = m68k_cs( 24'h046004, 24'h046004 );
|
||||
|
||||
sound_latch_cs = m68k_cs( 24'h04600c, 24'h04600d );
|
||||
|
||||
fg_ram_cs = m68k_cs( 24'h050000, 24'h050fff );
|
||||
end
|
||||
|
||||
if ( pcb == pcb_amazon || pcb == pcb_amazont || pcb == pcb_horekid ) begin
|
||||
prot_chip_data_cs = m68k_cs( 24'h070000, 24'h070001 );
|
||||
prot_chip_cmd_cs = m68k_cs( 24'h070002, 24'h070003 );
|
||||
end
|
||||
|
||||
z80_rom_cs = z80_mem_cs( 16'h0000, 16'hbfff ) ;
|
||||
z80_ram_cs = z80_mem_cs( 16'hc000, 16'hcfff ) ;
|
||||
|
||||
z80_sound0_cs = z80_io_cs( 8'h00 );
|
||||
z80_sound1_cs = z80_io_cs( 8'h01 );
|
||||
z80_dac1_cs = z80_io_cs( 8'h02 );
|
||||
z80_dac2_cs = z80_io_cs( 8'h03 );
|
||||
z80_latch_clr_cs = z80_io_cs( 8'h04 );
|
||||
z80_latch_r_cs = z80_io_cs( 8'h06 );
|
||||
|
||||
end
|
||||
endmodule
|
||||
@@ -0,0 +1,5 @@
|
||||
localparam pcb_terra_cresta = 0;
|
||||
localparam pcb_amazon = 1;
|
||||
localparam pcb_horekid = 2;
|
||||
localparam pcb_amazont = 3;
|
||||
localparam pcb_horekidb2 = 4;
|
||||
@@ -0,0 +1,117 @@
|
||||
-- __ __ __ __ __ __
|
||||
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
|
||||
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
|
||||
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
|
||||
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
|
||||
-- ______ ______ __ ______ ______ ______
|
||||
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
|
||||
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
|
||||
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
|
||||
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
|
||||
--
|
||||
-- https://joshbassett.info
|
||||
-- https://twitter.com/nullobject
|
||||
-- https://github.com/nullobject
|
||||
--
|
||||
-- Copyright (c) 2020 Josh Bassett
|
||||
--
|
||||
-- Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
-- of this software and associated documentation files (the "Software"), to deal
|
||||
-- in the Software without restriction, including without limitation the rights
|
||||
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
-- copies of the Software, and to permit persons to whom the Software is
|
||||
-- furnished to do so, subject to the following conditions:
|
||||
--
|
||||
-- The above copyright notice and this permission notice shall be included in all
|
||||
-- copies or substantial portions of the Software.
|
||||
--
|
||||
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
-- SOFTWARE.
|
||||
|
||||
-- 2022-05-24 Changed to use word count instead of address width
|
||||
-- and renamed ports to match quartus IP naming
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
--use work.common.all;
|
||||
use work.math.all;
|
||||
|
||||
library altera_mf;
|
||||
use altera_mf.altera_mf_components.all;
|
||||
|
||||
entity dual_port_ram is
|
||||
generic (
|
||||
LEN : natural := 8192;
|
||||
DATA_WIDTH : natural := 8
|
||||
);
|
||||
port (
|
||||
-- port A
|
||||
clock_a : in std_logic;
|
||||
address_a : in unsigned(ilog2(LEN)-1 downto 0);
|
||||
data_a : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
q_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
||||
wren_a : in std_logic := '0';
|
||||
|
||||
-- port B
|
||||
clock_b : in std_logic;
|
||||
address_b : in unsigned(ilog2(LEN)-1 downto 0);
|
||||
data_b : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
q_b : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
||||
wren_b : in std_logic := '0'
|
||||
);
|
||||
end dual_port_ram;
|
||||
|
||||
architecture arch of dual_port_ram is
|
||||
|
||||
begin
|
||||
altsyncram_component : altsyncram
|
||||
generic map (
|
||||
address_reg_b => "CLOCK1",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_input_b => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
clock_enable_output_b => "BYPASS",
|
||||
indata_reg_b => "CLOCK1",
|
||||
intended_device_family => "Cyclone V",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => LEN,
|
||||
numwords_b => LEN,
|
||||
operation_mode => "BIDIR_DUAL_PORT",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_aclr_b => "NONE",
|
||||
outdata_reg_a => "UNREGISTERED",
|
||||
outdata_reg_b => "UNREGISTERED",
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
|
||||
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
|
||||
width_a => DATA_WIDTH,
|
||||
width_b => DATA_WIDTH,
|
||||
width_byteena_a => 1,
|
||||
width_byteena_b => 1,
|
||||
widthad_a => ilog2(LEN),
|
||||
widthad_b => ilog2(LEN),
|
||||
wrcontrol_wraddress_reg_b => "CLOCK1"
|
||||
)
|
||||
port map (
|
||||
address_a => std_logic_vector(address_a),
|
||||
address_b => std_logic_vector(address_b),
|
||||
clock0 => clock_a,
|
||||
clock1 => clock_b,
|
||||
data_a => data_a,
|
||||
data_b => data_b,
|
||||
wren_a => wren_a,
|
||||
wren_b => wren_b,
|
||||
q_a => q_a,
|
||||
q_b => q_b
|
||||
);
|
||||
|
||||
|
||||
end architecture arch;
|
||||
@@ -0,0 +1,72 @@
|
||||
-- __ __ __ __ __ __
|
||||
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
|
||||
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
|
||||
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
|
||||
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
|
||||
-- ______ ______ __ ______ ______ ______
|
||||
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
|
||||
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
|
||||
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
|
||||
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
|
||||
--
|
||||
-- https://joshbassett.info
|
||||
-- https://twitter.com/nullobject
|
||||
-- https://github.com/nullobject
|
||||
--
|
||||
-- Copyright (c) 2020 Josh Bassett
|
||||
--
|
||||
-- Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
-- of this software and associated documentation files (the "Software"), to deal
|
||||
-- in the Software without restriction, including without limitation the rights
|
||||
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
-- copies of the Software, and to permit persons to whom the Software is
|
||||
-- furnished to do so, subject to the following conditions:
|
||||
--
|
||||
-- The above copyright notice and this permission notice shall be included in all
|
||||
-- copies or substantial portions of the Software.
|
||||
--
|
||||
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
-- SOFTWARE.
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
package math is
|
||||
-- calculates the log2 of the given number
|
||||
function ilog2(n : natural) return natural;
|
||||
|
||||
-- Masks the given range of bits for a vector.
|
||||
--
|
||||
-- Only the bits between the MSB and LSB (inclusive) will be kept, all other
|
||||
-- bits will be masked out.
|
||||
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector;
|
||||
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector;
|
||||
end package math;
|
||||
|
||||
package body math is
|
||||
function ilog2(n : natural) return natural is
|
||||
begin
|
||||
return natural(ceil(log2(real(n))));
|
||||
end ilog2;
|
||||
|
||||
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector is
|
||||
variable n : natural;
|
||||
variable mask : std_logic_vector(data'length-1 downto 0);
|
||||
begin
|
||||
n := (2**(msb-lsb+1))-1;
|
||||
mask := std_logic_vector(shift_left(to_unsigned(n, mask'length), lsb));
|
||||
return std_logic_vector(shift_right(unsigned(data AND mask), lsb));
|
||||
end mask_bits;
|
||||
|
||||
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector is
|
||||
begin
|
||||
return std_logic_vector(resize(unsigned(mask_bits(data, msb, lsb)), size));
|
||||
end mask_bits;
|
||||
end package body math;
|
||||
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
||||
348
Arcade_MiST/Nichibutsu M68000 Hardware/TerraCresta/rtl/pll.v
Normal file
348
Arcade_MiST/Nichibutsu M68000 Hardware/TerraCresta/rtl/pll.v
Normal file
@@ -0,0 +1,348 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2014 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll (
|
||||
areset,
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
locked);
|
||||
|
||||
input areset;
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output locked;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 areset;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
|
||||
altpll altpll_component (
|
||||
.areset (areset),
|
||||
.inclk (sub_wire5),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.activeclock (),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 9,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 32,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 9,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 8,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_USED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
446
Arcade_MiST/Nichibutsu M68000 Hardware/TerraCresta/rtl/sdram.sv
Normal file
446
Arcade_MiST/Nichibutsu M68000 Hardware/TerraCresta/rtl/sdram.sv
Normal file
@@ -0,0 +1,446 @@
|
||||
//
|
||||
// sdram.v
|
||||
//
|
||||
// sdram controller implementation for the MiST board
|
||||
// https://github.com/mist-devel/mist-board
|
||||
//
|
||||
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2019-2022 Gyorgy Szombathelyi
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
|
||||
module sdram (
|
||||
|
||||
// interface to the MT48LC16M16 chip
|
||||
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
|
||||
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
|
||||
output reg SDRAM_DQML, // two byte masks
|
||||
output reg SDRAM_DQMH, // two byte masks
|
||||
output reg [1:0] SDRAM_BA, // two banks
|
||||
output SDRAM_nCS, // a single chip select
|
||||
output SDRAM_nWE, // write enable
|
||||
output SDRAM_nRAS, // row address select
|
||||
output SDRAM_nCAS, // columns address select
|
||||
|
||||
// cpu/chipset interface
|
||||
input init_n, // init signal after FPGA config to initialize RAM
|
||||
input clk, // sdram clock
|
||||
|
||||
// 1st bank
|
||||
input port1_req,
|
||||
output reg port1_ack,
|
||||
input port1_we,
|
||||
input [23:1] port1_a,
|
||||
input [1:0] port1_ds,
|
||||
input [15:0] port1_d,
|
||||
output reg [15:0] port1_q,
|
||||
|
||||
// cpu1 rom/ram
|
||||
input [20:1] cpu1_rom_addr,
|
||||
input cpu1_rom_cs,
|
||||
output reg [15:0] cpu1_rom_q,
|
||||
output reg cpu1_rom_valid,
|
||||
|
||||
input cpu1_ram_req,
|
||||
output reg cpu1_ram_ack,
|
||||
input [19:1] cpu1_ram_addr,
|
||||
input cpu1_ram_we,
|
||||
input [1:0] cpu1_ram_ds,
|
||||
input [15:0] cpu1_ram_d,
|
||||
output reg [15:0] cpu1_ram_q,
|
||||
|
||||
// cpu2 rom
|
||||
input [20:1] cpu2_addr,
|
||||
input cpu2_rom_cs,
|
||||
output reg [15:0] cpu2_q,
|
||||
output reg cpu2_valid,
|
||||
// cpu3 rom
|
||||
input [20:1] cpu3_addr,
|
||||
input cpu3_rom_cs,
|
||||
output reg [15:0] cpu3_q,
|
||||
output reg cpu3_valid,
|
||||
// cpu4 rom
|
||||
input [20:1] cpu4_addr,
|
||||
output reg [15:0] cpu4_q,
|
||||
output reg cpu4_valid,
|
||||
|
||||
// 2nd bank
|
||||
input port2_req,
|
||||
output reg port2_ack,
|
||||
input port2_we,
|
||||
input [23:1] port2_a,
|
||||
input [1:0] port2_ds,
|
||||
input [15:0] port2_d,
|
||||
output reg [31:0] port2_q,
|
||||
|
||||
input [20:2] gfx1_addr,
|
||||
output reg [31:0] gfx1_q,
|
||||
input [20:2] gfx2_addr,
|
||||
output reg [31:0] gfx2_q,
|
||||
input [20:2] gfx3_addr,
|
||||
output reg [31:0] gfx3_q,
|
||||
|
||||
input [20:2] sp_addr,
|
||||
input sp_req,
|
||||
output reg sp_ack,
|
||||
output reg [31:0] sp_q
|
||||
);
|
||||
|
||||
parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
|
||||
|
||||
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
|
||||
localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
|
||||
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
|
||||
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
|
||||
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
|
||||
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
|
||||
|
||||
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
|
||||
|
||||
// 64ms/8192 rows = 7.8us
|
||||
localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// ------------------------ cycle state machine ------------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
/*
|
||||
SDRAM state machine for 2 bank interleaved access
|
||||
2 words burst, CL2
|
||||
cmd issued registered
|
||||
0 RAS0 cas1 - data0 read burst terminated
|
||||
1 ras0
|
||||
2 data1 returned
|
||||
3 CAS0 data1 returned
|
||||
4 RAS1 cas0
|
||||
5 ras1
|
||||
6 CAS1 data0 returned
|
||||
*/
|
||||
|
||||
localparam STATE_RAS0 = 3'd0; // first state in cycle
|
||||
localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
|
||||
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
|
||||
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
|
||||
localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
|
||||
localparam STATE_READ1 = 3'd3;
|
||||
localparam STATE_DS1b = 3'd0;
|
||||
localparam STATE_READ1b = 3'd4;
|
||||
localparam STATE_LAST = 3'd6;
|
||||
|
||||
reg [2:0] t;
|
||||
|
||||
always @(posedge clk) begin
|
||||
t <= t + 1'd1;
|
||||
if (t == STATE_LAST) t <= STATE_RAS0;
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// --------------------------- startup/reset ---------------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
|
||||
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
|
||||
reg [4:0] reset;
|
||||
reg init = 1'b1;
|
||||
always @(posedge clk, negedge init_n) begin
|
||||
if(!init_n) begin
|
||||
reset <= 5'h1f;
|
||||
init <= 1'b1;
|
||||
end else begin
|
||||
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
|
||||
init <= !(reset == 0);
|
||||
end
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// ------------------ generate ram control signals ---------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// all possible commands
|
||||
localparam CMD_INHIBIT = 4'b1111;
|
||||
localparam CMD_NOP = 4'b0111;
|
||||
localparam CMD_ACTIVE = 4'b0011;
|
||||
localparam CMD_READ = 4'b0101;
|
||||
localparam CMD_WRITE = 4'b0100;
|
||||
localparam CMD_BURST_TERMINATE = 4'b0110;
|
||||
localparam CMD_PRECHARGE = 4'b0010;
|
||||
localparam CMD_AUTO_REFRESH = 4'b0001;
|
||||
localparam CMD_LOAD_MODE = 4'b0000;
|
||||
|
||||
reg [3:0] sd_cmd; // current command sent to sd ram
|
||||
reg [15:0] sd_din;
|
||||
// drive control signals according to current command
|
||||
assign SDRAM_nCS = sd_cmd[3];
|
||||
assign SDRAM_nRAS = sd_cmd[2];
|
||||
assign SDRAM_nCAS = sd_cmd[1];
|
||||
assign SDRAM_nWE = sd_cmd[0];
|
||||
|
||||
reg [24:1] addr_latch[3];
|
||||
reg [24:1] addr_latch_next[2];
|
||||
reg [20:1] addr_last[1:5];
|
||||
reg [20:2] addr_last2[5];
|
||||
reg [15:0] din_next;
|
||||
reg [15:0] din_latch[2];
|
||||
reg oe_next;
|
||||
reg [1:0] oe_latch;
|
||||
reg we_next;
|
||||
reg [1:0] we_latch;
|
||||
reg [1:0] ds_next;
|
||||
reg [1:0] ds[2];
|
||||
|
||||
reg port1_state;
|
||||
reg port2_state;
|
||||
reg cpu1_ram_req_state;
|
||||
|
||||
localparam PORT_NONE = 3'd0;
|
||||
localparam PORT_CPU1_ROM = 3'd1;
|
||||
localparam PORT_CPU1_RAM = 3'd2;
|
||||
localparam PORT_CPU2 = 3'd3;
|
||||
localparam PORT_CPU3 = 3'd4;
|
||||
localparam PORT_CPU4 = 3'd5;
|
||||
localparam PORT_GFX1 = 3'd1;
|
||||
localparam PORT_GFX2 = 3'd2;
|
||||
localparam PORT_GFX3 = 3'd3;
|
||||
localparam PORT_SP = 3'd4;
|
||||
localparam PORT_REQ = 3'd6;
|
||||
|
||||
reg [2:0] next_port[2];
|
||||
reg [2:0] port[2];
|
||||
|
||||
reg refresh;
|
||||
reg [10:0] refresh_cnt;
|
||||
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
|
||||
|
||||
// PORT1: bank 0,1
|
||||
always @(*) begin
|
||||
next_port[0] = PORT_NONE;
|
||||
addr_latch_next[0] = addr_latch[0];
|
||||
ds_next = 2'b00;
|
||||
{ oe_next, we_next } = 2'b00;
|
||||
din_next = 0;
|
||||
|
||||
if (refresh) begin
|
||||
// nothing
|
||||
end else if (port1_req ^ port1_state) begin
|
||||
next_port[0] = PORT_REQ;
|
||||
addr_latch_next[0] = { 1'b0, port1_a };
|
||||
ds_next = port1_ds;
|
||||
{ oe_next, we_next } = { ~port1_we, port1_we };
|
||||
din_next = port1_d;
|
||||
end else if (/*cpu1_rom_addr != addr_last[PORT_CPU1_ROM] &&*/ cpu1_rom_cs && !cpu1_rom_valid) begin
|
||||
next_port[0] = PORT_CPU1_ROM;
|
||||
addr_latch_next[0] = { 4'd0, cpu1_rom_addr };
|
||||
ds_next = 2'b11;
|
||||
{ oe_next, we_next } = 2'b10;
|
||||
end else if (cpu1_ram_req ^ cpu1_ram_req_state) begin
|
||||
next_port[0] = PORT_CPU1_RAM;
|
||||
addr_latch_next[0] = { 2'b00, 3'b100, cpu1_ram_addr };
|
||||
ds_next = cpu1_ram_ds;
|
||||
{ oe_next, we_next } = { ~cpu1_ram_we, cpu1_ram_we };
|
||||
din_next = cpu1_ram_d;
|
||||
end else if (cpu2_addr != addr_last[PORT_CPU2] && cpu2_rom_cs) begin
|
||||
next_port[0] = PORT_CPU2;
|
||||
addr_latch_next[0] = { 4'd0, cpu2_addr };
|
||||
ds_next = 2'b11;
|
||||
{ oe_next, we_next } = 2'b10;
|
||||
end else if (cpu3_addr != addr_last[PORT_CPU3] && cpu3_rom_cs) begin
|
||||
next_port[0] = PORT_CPU3;
|
||||
addr_latch_next[0] = { 4'd0, cpu3_addr };
|
||||
ds_next = 2'b11;
|
||||
{ oe_next, we_next } = 2'b10;
|
||||
end else if (cpu4_addr != addr_last[PORT_CPU4]) begin
|
||||
next_port[0] = PORT_CPU4;
|
||||
addr_latch_next[0] = { 4'd0, cpu4_addr };
|
||||
ds_next = 2'b11;
|
||||
{ oe_next, we_next } = 2'b10;
|
||||
end
|
||||
end
|
||||
|
||||
// PORT1: bank 2,3
|
||||
always @(*) begin
|
||||
if (port2_req ^ port2_state) begin
|
||||
next_port[1] = PORT_REQ;
|
||||
addr_latch_next[1] = { 1'b1, port2_a };
|
||||
end else if (gfx1_addr != addr_last2[PORT_GFX1]) begin
|
||||
next_port[1] = PORT_GFX1;
|
||||
addr_latch_next[1] = { 1'b1, 3'd0, gfx1_addr, 1'b0 };
|
||||
end else if (gfx2_addr != addr_last2[PORT_GFX2]) begin
|
||||
next_port[1] = PORT_GFX2;
|
||||
addr_latch_next[1] = { 1'b1, 3'd0, gfx2_addr, 1'b0 };
|
||||
end else if (gfx3_addr != addr_last2[PORT_GFX3]) begin
|
||||
next_port[1] = PORT_GFX3;
|
||||
addr_latch_next[1] = { 1'b1, 3'd0, gfx3_addr, 1'b0 };
|
||||
end else if (sp_req ^ sp_ack) begin
|
||||
next_port[1] = PORT_SP;
|
||||
addr_latch_next[1] = { 1'b1, 3'd0, sp_addr, 1'b0 };
|
||||
end else begin
|
||||
next_port[1] = PORT_NONE;
|
||||
addr_latch_next[1] = addr_latch[1];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
// permanently latch ram data to reduce delays
|
||||
sd_din <= SDRAM_DQ;
|
||||
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
|
||||
sd_cmd <= CMD_NOP; // default: idle
|
||||
refresh_cnt <= refresh_cnt + 1'd1;
|
||||
|
||||
if(init) begin
|
||||
{ cpu1_rom_valid, cpu2_valid, cpu3_valid, cpu4_valid } <= 0;
|
||||
// initialization takes place at the end of the reset phase
|
||||
if(t == STATE_RAS0) begin
|
||||
|
||||
if(reset == 15) begin
|
||||
sd_cmd <= CMD_PRECHARGE;
|
||||
SDRAM_A[10] <= 1'b1; // precharge all banks
|
||||
end
|
||||
|
||||
if(reset == 10 || reset == 8) begin
|
||||
sd_cmd <= CMD_AUTO_REFRESH;
|
||||
end
|
||||
|
||||
if(reset == 2) begin
|
||||
sd_cmd <= CMD_LOAD_MODE;
|
||||
SDRAM_A <= MODE;
|
||||
SDRAM_BA <= 2'b00;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
if (!cpu1_rom_cs) cpu1_rom_valid <= 0;
|
||||
if (cpu2_addr != addr_last[PORT_CPU2] && cpu2_rom_cs) cpu2_valid <= 0;
|
||||
if (cpu3_addr != addr_last[PORT_CPU3] && cpu3_rom_cs) cpu3_valid <= 0;
|
||||
if (cpu4_addr != addr_last[PORT_CPU4]) cpu4_valid <= 0;
|
||||
|
||||
// RAS phase
|
||||
// bank 0,1
|
||||
if(t == STATE_RAS0) begin
|
||||
addr_latch[0] <= addr_latch_next[0];
|
||||
port[0] <= next_port[0];
|
||||
{ oe_latch[0], we_latch[0] } <= 2'b00;
|
||||
|
||||
if (next_port[0] != PORT_NONE) begin
|
||||
sd_cmd <= CMD_ACTIVE;
|
||||
SDRAM_A <= addr_latch_next[0][22:10];
|
||||
SDRAM_BA <= addr_latch_next[0][24:23];
|
||||
end
|
||||
addr_last[next_port[0]] <= addr_latch_next[0][20:1];
|
||||
ds[0] <= ds_next;
|
||||
{ oe_latch[0], we_latch[0] } <= { oe_next, we_next };
|
||||
din_latch[0] <= din_next;
|
||||
|
||||
if (next_port[0] == PORT_REQ) port1_state <= port1_req;
|
||||
if (next_port[0] == PORT_CPU1_RAM) cpu1_ram_req_state <= cpu1_ram_req;
|
||||
end
|
||||
|
||||
// bank 2,3
|
||||
if(t == STATE_RAS1) begin
|
||||
refresh <= 1'b0;
|
||||
addr_latch[1] <= addr_latch_next[1];
|
||||
{ oe_latch[1], we_latch[1] } <= 2'b00;
|
||||
port[1] <= next_port[1];
|
||||
|
||||
if (next_port[1] != PORT_NONE) begin
|
||||
sd_cmd <= CMD_ACTIVE;
|
||||
SDRAM_A <= addr_latch_next[1][22:10];
|
||||
SDRAM_BA <= addr_latch_next[1][24:23];
|
||||
addr_last2[next_port[1]] <= addr_latch_next[1][20:2];
|
||||
if (next_port[1] == PORT_REQ) begin
|
||||
{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
|
||||
ds[1] <= port2_ds;
|
||||
din_latch[1] <= port2_d;
|
||||
port2_state <= port2_req;
|
||||
end else begin
|
||||
{ oe_latch[1], we_latch[1] } <= 2'b10;
|
||||
ds[1] <= 2'b11;
|
||||
end
|
||||
end
|
||||
|
||||
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
|
||||
refresh <= 1'b1;
|
||||
refresh_cnt <= 0;
|
||||
sd_cmd <= CMD_AUTO_REFRESH;
|
||||
end
|
||||
end
|
||||
|
||||
// CAS phase
|
||||
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
|
||||
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
|
||||
if (we_latch[0]) begin
|
||||
SDRAM_DQ <= din_latch[0];
|
||||
case(port[0])
|
||||
PORT_REQ: port1_ack <= port1_req;
|
||||
PORT_CPU1_RAM: cpu1_ram_ack <= cpu1_ram_req;
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
|
||||
SDRAM_BA <= addr_latch[0][24:23];
|
||||
end
|
||||
|
||||
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
|
||||
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
|
||||
if (we_latch[1]) begin
|
||||
SDRAM_DQ <= din_latch[1];
|
||||
port2_ack <= port2_req;
|
||||
end
|
||||
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
|
||||
SDRAM_BA <= addr_latch[1][24:23];
|
||||
end
|
||||
|
||||
// Data returned
|
||||
if(t == STATE_READ0 && oe_latch[0]) begin
|
||||
case(port[0])
|
||||
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
|
||||
PORT_CPU1_ROM: begin cpu1_rom_q <= sd_din; cpu1_rom_valid <= 1; end
|
||||
PORT_CPU1_RAM: begin cpu1_ram_q <= sd_din; cpu1_ram_ack <= cpu1_ram_req; end
|
||||
PORT_CPU2: begin cpu2_q <= sd_din; cpu2_valid <= 1; end
|
||||
PORT_CPU3: begin cpu3_q <= sd_din; cpu3_valid <= 1; end
|
||||
PORT_CPU4: begin cpu4_q <= sd_din; cpu4_valid <= 1; end
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
|
||||
if(t == STATE_READ1 && oe_latch[1]) begin
|
||||
case(port[1])
|
||||
PORT_REQ : port2_q[15:0] <= sd_din;
|
||||
PORT_GFX1 : gfx1_q[15:0] <= sd_din;
|
||||
PORT_GFX2 : gfx2_q[15:0] <= sd_din;
|
||||
PORT_GFX3 : gfx3_q[15:0] <= sd_din;
|
||||
PORT_SP : sp_q[15:0] <= sd_din;
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
|
||||
if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
|
||||
|
||||
if(t == STATE_READ1b && oe_latch[1]) begin
|
||||
case(port[1])
|
||||
PORT_REQ : begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
|
||||
PORT_GFX1 : begin gfx1_q[31:16] <= sd_din; end
|
||||
PORT_GFX2 : begin gfx2_q[31:16] <= sd_din; end
|
||||
PORT_GFX3 : begin gfx3_q[31:16] <= sd_din; end
|
||||
PORT_SP : begin sp_q[31:16] <= sd_din; sp_ack <= sp_req; end
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,96 @@
|
||||
|
||||
module video_timing
|
||||
(
|
||||
input clk,
|
||||
input clk_pix_en,
|
||||
input reset,
|
||||
|
||||
input signed [3:0] hs_offset,
|
||||
input signed [3:0] vs_offset,
|
||||
|
||||
output [8:0] hc,
|
||||
output [8:0] vc,
|
||||
|
||||
output reg hsync,
|
||||
output reg vsync,
|
||||
|
||||
output reg hbl,
|
||||
output reg vbl
|
||||
);
|
||||
|
||||
// 6MHz
|
||||
wire [8:0] HBL_START = 9'd263;
|
||||
wire [8:0] HBL_END = 9'd7;
|
||||
wire [8:0] HS_START = 9'd300;
|
||||
wire [8:0] HS_END = 9'd332;
|
||||
wire [8:0] HTOTAL = 9'd383;
|
||||
|
||||
wire [8:0] VBL_START = 9'd224;
|
||||
wire [8:0] VBL_END = 9'd0;
|
||||
wire [8:0] VS_START = 9'd235;
|
||||
wire [8:0] VS_END = 9'd243;
|
||||
wire [8:0] VTOTAL = 9'd263;
|
||||
|
||||
reg [8:0] v;
|
||||
reg [8:0] h;
|
||||
|
||||
assign vc = v;
|
||||
assign hc = h;
|
||||
|
||||
//assign hsync = ( h >= (HS_START + $signed(hs_offset)) && h < (HS_END + $signed(hs_offset)) );
|
||||
//assign vsync = ( v >= (VS_START + $signed(vs_offset)) && v < (VS_END + $signed(vs_offset)) );
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (reset) begin
|
||||
h <= 0;
|
||||
v <= 0;
|
||||
|
||||
hbl <= 0;
|
||||
vbl <= 0;
|
||||
|
||||
hsync <= 0;
|
||||
vsync <= 0;
|
||||
end else if ( clk_pix_en ) begin
|
||||
// counter
|
||||
if (h == HTOTAL) begin
|
||||
h <= 0;
|
||||
|
||||
v <= v + 1'd1;
|
||||
|
||||
if ( v == VTOTAL-1 ) begin
|
||||
v <= 0;
|
||||
end
|
||||
|
||||
end else begin
|
||||
h <= h + 1'd1;
|
||||
end
|
||||
|
||||
// h signals
|
||||
if ( h == HBL_START-1 ) hbl <= 1;
|
||||
if ( h == HBL_END-1 ) hbl <= 0;
|
||||
|
||||
// v signals
|
||||
if ( v == VBL_START ) begin
|
||||
vbl <= 1;
|
||||
end else if ( v == VBL_END ) begin
|
||||
vbl <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
if ( v == (VS_START + $signed(vs_offset) ) ) begin
|
||||
vsync <= 1;
|
||||
end else if ( v == (VS_END + $signed(vs_offset) ) ) begin
|
||||
vsync <= 0;
|
||||
end
|
||||
|
||||
if ( h == (HS_START + $signed(hs_offset) ) ) begin
|
||||
hsync <= 1;
|
||||
end else if ( h == (HS_END + $signed(hs_offset) ) ) begin
|
||||
hsync <= 0;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
Reference in New Issue
Block a user