mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-04-13 23:23:50 +00:00
Update Channel F
This commit is contained in:
Marcel
@@ -17,15 +17,15 @@
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
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# Date created = 19:28:53 March 07, 2019
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# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
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# Date created = 20:10:17 February 28, 2021
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# Centipede_assignment_defaults.qdf
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# ChannelF_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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@@ -46,6 +46,15 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/CannelF_MiST.sv
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set_global_assignment -name VHDL_FILE rtl/channel_f.vhd
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set_global_assignment -name VHDL_FILE rtl/f8_cpu.vhd
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set_global_assignment -name VHDL_FILE rtl/f8_psu.vhd
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set_global_assignment -name VHDL_FILE rtl/f8_pack.vhd
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set_global_assignment -name VHDL_FILE rtl/base_pack.vhd
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set_global_assignment -name VHDL_FILE rtl/rom_pack.vhd
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
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# Pin & Location Assignments
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# ==========================
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@@ -116,6 +125,11 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name GENERATE_RBF_FILE ON
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set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
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# SignalTap II Assignments
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# ========================
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/cent.stp
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# Power Estimation Assignments
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# ============================
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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@@ -128,32 +142,21 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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# -----------------------
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# start ENTITY(Centipede)
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# --------------------------
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# start ENTITY(CannelF_MiST)
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# start DESIGN_PARTITION(Top)
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# ---------------------------
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# Incremental Compilation Assignments
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# ===================================
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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# end DESIGN_PARTITION(Top)
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# -------------------------
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# end ENTITY(Centipede)
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# ---------------------
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/cent.stp
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/CannelF_MiST.sv
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set_global_assignment -name VHDL_FILE rtl/channel_f.vhd
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set_global_assignment -name VHDL_FILE rtl/f8_cpu.vhd
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set_global_assignment -name VHDL_FILE rtl/f8_psu.vhd
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set_global_assignment -name VHDL_FILE rtl/f8_pack.vhd
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set_global_assignment -name VHDL_FILE rtl/base_pack.vhd
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set_global_assignment -name VHDL_FILE rtl/rom_pack.vhd
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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# end ENTITY(CannelF_MiST)
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# ------------------------
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153
Console_MiST/ChannelF_MiST/rtl/CannelF_MiST.sv
Normal file
153
Console_MiST/ChannelF_MiST/rtl/CannelF_MiST.sv
Normal file
@@ -0,0 +1,153 @@
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module CannelF_MiST(
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output LED,
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output AUDIO_L,
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output AUDIO_R,
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input SPI_SCK,
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output SPI_DO,
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input SPI_DI,
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input SPI_SS2,
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input SPI_SS3,
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input CONF_DATA0,
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input CLOCK_27
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);
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`include "rtl\build_id.v"
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localparam CONF_STR = {
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"ChannelF;BINCHF;",
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"O1,Swap Joystick,Off,On;",
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"O34,Scanlines,Off,25%,50%,75%;",
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"O6,Blending,Off,On;",
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"T0,Reset;",
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"V,v1.00.",`BUILD_DATE
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};
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assign LED = ~ioctl_downl;
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assign AUDIO_R = AUDIO_L;
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wire pll_locked,clock_48, clk3p579;
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pll pll(
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.locked(pll_locked),
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.inclk0(CLOCK_27),
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.c0(clock_48),
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.c1(clk3p579)//3.579545
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);
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// NTSC : 3.579545MHz * 12 = 42.95454MHz
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// PAL : 4MHz * 12 = 48MHz
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channel_f channel_f(
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.clk(clk3p579),
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.reset(status[0] | buttons[1]),
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.pll_locked(pll_locked),
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.vga_r(r),
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.vga_g(g),
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.vga_b(b),
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.vga_hs(hs),
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.vga_vs(vs),
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.vga_de(blankn),
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.joystick_0(~status[1] ? joystick_0 : joystick_1),
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.joystick_1(~status[1] ? joystick_1 : joystick_0),
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.ioctl_download(ioctl_downl),
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.ioctl_index(ioctl_index),
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.ioctl_wr(1),//ioctl_wr),//todo
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_dout),
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// .ioctl_wait(ioctl_wait),
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.audio(audio)
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);
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wire ioctl_downl;
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wire [7:0] ioctl_index;
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wire ioctl_wr;
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wire [24:0] ioctl_addr;
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wire [7:0] ioctl_dout;
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data_io data_io(
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.clk_sys ( clock_48 ),
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.SPI_SCK ( SPI_SCK ),
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.SPI_SS2 ( SPI_SS2 ),
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.SPI_DI ( SPI_DI ),
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.ioctl_download( ioctl_downl ),
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.ioctl_index ( ioctl_index ),
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.ioctl_wr ( ioctl_wr ),
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.ioctl_addr ( ioctl_addr ),
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.ioctl_dout ( ioctl_dout )
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);
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mist_video #(.COLOR_DEPTH(6),.SD_HCNT_WIDTH(10)) mist_video(
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.clk_sys(clock_48),
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.SPI_SCK(SPI_SCK),
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.SPI_SS3(SPI_SS3),
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.SPI_DI(SPI_DI),
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.R(blankn ? r[7:2] : 0),
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.G(blankn ? g[7:2] : 0),
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.B(blankn ? b[7:2] : 0),
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.HSync(hs),
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.VSync(vs),
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.VGA_R(VGA_R),
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.VGA_G(VGA_G),
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.VGA_B(VGA_B),
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.VGA_VS(VGA_VS),
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.VGA_HS(VGA_HS),
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.ce_divider(1'b0),
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.blend(status[6]),
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.scandoubler_disable(scandoublerD),
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.scanlines(status[4:3]),
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.ypbpr(ypbpr),
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.no_csync(no_csync)
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);
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wire [31:0] status;
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wire [1:0] buttons;
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wire [1:0] switches;
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wire [31:0] joystick_0;
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wire [31:0] joystick_1;
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wire scandoublerD;
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wire [7:0] r, g, b;
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wire hs, vs, blankn;
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wire [15:0] audio;
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wire ypbpr;
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wire no_csync;
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wire key_strobe;
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wire key_pressed;
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wire [7:0] key_code;
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user_io #(
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.STRLEN(($size(CONF_STR)>>3)))
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user_io(
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.clk_sys (clock_48 ),
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.conf_str (CONF_STR ),
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.SPI_CLK (SPI_SCK ),
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.SPI_SS_IO (CONF_DATA0 ),
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.SPI_MISO (SPI_DO ),
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.SPI_MOSI (SPI_DI ),
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.buttons (buttons ),
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.switches (switches ),
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.scandoubler_disable (scandoublerD),
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.ypbpr (ypbpr ),
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.no_csync (no_csync ),
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.key_strobe (key_strobe ),
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.key_pressed (key_pressed ),
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.key_code (key_code ),
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.joystick_0 (joystick_0 ),
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.joystick_1 (joystick_1 ),
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.status (status )
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);
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dac #(
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.C_bits(16))
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dac(
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.clk_i(clock_48),
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.res_n_i(1'b1),
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.dac_i(audio),
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.dac_o(AUDIO_L)
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);
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endmodule
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@@ -61,7 +61,8 @@ USE work.rom_pack.ALL;
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ENTITY channel_f IS
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PORT (
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clk : IN std_logic;
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reset_na : IN std_logic;
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pll_locked : IN std_logic;
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reset : IN std_logic;
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-- VGA
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vga_clk : OUT std_logic;
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vga_ce : OUT std_logic;
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@@ -74,14 +75,13 @@ ENTITY channel_f IS
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-- HPS IO
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joystick_0 : IN unsigned(31 DOWNTO 0);
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joystick_1 : IN unsigned(31 DOWNTO 0);
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iTIME : IN std_logic; -- TIME
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iMODE : IN std_logic; -- MODE
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iHOLD : IN std_logic; -- HOLD
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iSTART : IN std_logic; -- START
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--ROM LOAD
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rom_addr : IN std_logic_vector(10 DOWNTO 0);
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rom_do : IN std_logic_vector(7 DOWNTO 0);
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rom_wr : IN std_logic;
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ioctl_download : IN std_logic;
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ioctl_index : IN std_logic_vector(7 DOWNTO 0);
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ioctl_wr : IN std_logic;
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ioctl_addr : IN std_logic_vector(24 DOWNTO 0);
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ioctl_dout : IN std_logic_vector(7 DOWNTO 0);
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ioctl_wait : OUT std_logic;
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-- AUDIO
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audio : OUT std_logic_vector(15 DOWNTO 0)
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);
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@@ -94,18 +94,20 @@ ARCHITECTURE struct OF channel_f IS
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SIGNAL adrs : uv17;
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----------------------------------------------------------
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SIGNAL dr,dr0,dr1,dr2,dr3,dw_cpu : uv8;
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SIGNAL dv0,dv1,dv2,dv3,dv_cpu : std_logic;
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SIGNAL dr,dr0,dr1,dr2,dr3,dr4,dr5,dw_cpu : uv8;
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SIGNAL dv0,dv1,dv2,dv3,dv4,dv5,dv_cpu : std_logic;
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SIGNAL romc : uv5;
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SIGNAL phase : uint4;
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SIGNAL ce : std_logic :='0';
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SIGNAL pi0,po0,pi1,po1,pi4,po4,pi5,po5 : uv8;
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SIGNAL pi0,po0,pi1,po1,pi1i,pi4,po4,pi4i,pi5,po5 : uv8;
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SIGNAL rdena : std_logic;
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SIGNAL load_a : uv10;
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SIGNAL load_d : uv8;
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SIGNAL load_wr0,load_wr1 : std_logic;
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SIGNAL load_wr0,load_wr1,load_wr2,load_wr3 : std_logic;
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SIGNAL tick : std_logic;
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-- SIGNAL reset_na : std_logic;
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SIGNAL reset_na,areset_na : std_logic;
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SIGNAL vreset_na : unsigned(0 TO 15);
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----------------------------------------------------------
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CONSTANT INIT_ZERO : arr_uv8(0 TO 1023) := (OTHERS => x"00");
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@@ -152,7 +154,10 @@ ARCHITECTURE struct OF channel_f IS
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SIGNAL vdiv : uv16;
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SIGNAL tone : uv2;
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SIGNAL dc0,pc0,pc1 : uv16;
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SIGNAL acc : uv8;
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SIGNAL visar : uv6;
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SIGNAL iozcs : uv5;
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BEGIN
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----------------------------------------------------------
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@@ -175,7 +180,10 @@ BEGIN
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pi_b => pi1,
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clk => clk,
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ce => ce,
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reset_na => reset_na
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reset_na => reset_na,
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acco => acc,
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visaro => visar,
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iozcso => iozcs
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);
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|
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-- PSU SL31253
|
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@@ -205,7 +213,10 @@ BEGIN
|
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load_wr => '0',
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clk => clk,
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ce => ce,
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reset_na => reset_na
|
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reset_na => reset_na,
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pc0o => pc0,
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pc1o => pc1,
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dc0o => dc0
|
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);
|
||||
|
||||
-- PSU SL31254
|
||||
@@ -298,27 +309,92 @@ BEGIN
|
||||
reset_na => reset_na
|
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);
|
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|
||||
-- CARTRIDGE
|
||||
i_psu4:ENTITY work.f8_psu
|
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GENERIC MAP (
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PAGE => "000100", -- 0x1000
|
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IOPAGE => "111100", -- Not used
|
||||
IVEC => x"FFFF", -- Not used
|
||||
ROM => INIT_ZERO)
|
||||
PORT MAP (
|
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dw => dr,
|
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dr => dr4,
|
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dv => dv4,
|
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romc => romc,
|
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tick => tick,
|
||||
phase => phase,
|
||||
ext_int => '0',
|
||||
int_req => OPEN,
|
||||
pri_o => OPEN,
|
||||
pri_i => '1',
|
||||
po_a => OPEN,
|
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pi_a => x"FF",
|
||||
po_b => OPEN,
|
||||
pi_b => x"FF",
|
||||
load_a => load_a,
|
||||
load_d => load_d,
|
||||
load_wr => load_wr2,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
reset_na => reset_na
|
||||
);
|
||||
|
||||
-- CARTRIDGE
|
||||
i_psu5:ENTITY work.f8_psu
|
||||
GENERIC MAP (
|
||||
PAGE => "000101", -- 0x1400
|
||||
IOPAGE => "111011", -- Not used
|
||||
IVEC => x"FFFF", -- Not used
|
||||
ROM => INIT_ZERO)
|
||||
PORT MAP (
|
||||
dw => dr,
|
||||
dr => dr5,
|
||||
dv => dv5,
|
||||
romc => romc,
|
||||
tick => tick,
|
||||
phase => phase,
|
||||
ext_int => '0',
|
||||
int_req => OPEN,
|
||||
pri_o => OPEN,
|
||||
pri_i => '1',
|
||||
po_a => OPEN,
|
||||
pi_a => x"FF",
|
||||
po_b => OPEN,
|
||||
pi_b => x"FF",
|
||||
load_a => load_a,
|
||||
load_d => load_d,
|
||||
load_wr => load_wr3,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
reset_na => reset_na);
|
||||
|
||||
dr <= dr0 WHEN dv0='1' ELSE
|
||||
dr1 WHEN dv1='1' ELSE
|
||||
dr2 WHEN dv2='1' ELSE
|
||||
dr3 WHEN dv3='1' ELSE
|
||||
dr4 WHEN dv4='1' ELSE
|
||||
dr5 WHEN dv5='1' ELSE
|
||||
dw_cpu;
|
||||
|
||||
---------------------------------------------------------
|
||||
|
||||
-- CARTRIDGE LOAD
|
||||
----------------------------------------------------------
|
||||
-- CARTRIDGE LOAD
|
||||
|
||||
PROCESS (clk) IS
|
||||
BEGIN
|
||||
IF rising_edge(clk) THEN
|
||||
load_a <=unsigned(rom_addr(9 DOWNTO 0));
|
||||
load_wr0<=NOT rom_addr(10) AND rom_wr;
|
||||
load_wr1<= rom_addr(10) AND rom_wr;
|
||||
load_d <=unsigned(rom_do);
|
||||
load_a <=unsigned(ioctl_addr(9 DOWNTO 0));
|
||||
load_wr0<=NOT ioctl_addr(10) AND NOT ioctl_addr(11) AND ioctl_wr;
|
||||
load_wr1<= ioctl_addr(10) AND NOT ioctl_addr(11) AND ioctl_wr;
|
||||
load_wr2<=NOT ioctl_addr(10) AND ioctl_addr(11) AND ioctl_wr;
|
||||
load_wr3<= ioctl_addr(10) AND ioctl_addr(11) AND ioctl_wr;
|
||||
load_d <=unsigned(ioctl_dout);
|
||||
ioctl_wait<='0';
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
rdena<=NOT po0(6);
|
||||
|
||||
----------------------------------------------------------
|
||||
-- VIDEO
|
||||
vram_h <= to_integer(NOT po4(6 DOWNTO 0));
|
||||
vram_v <= to_integer(NOT po5(5 DOWNTO 0));
|
||||
@@ -386,31 +462,34 @@ BEGIN
|
||||
|
||||
----------------------------------------------------------
|
||||
-- Joysticks / Buttons
|
||||
pi0(7 DOWNTO 4)<= "1111";
|
||||
pi0(0) <= NOT (joystick_0(4) OR joystick_1(4) OR iTIME); -- TIME
|
||||
pi0(1) <= NOT (joystick_0(5) OR joystick_1(5) OR iMODE); -- MODE
|
||||
pi0(2) <= NOT (joystick_0(6) OR joystick_1(6) OR iHOLD); -- HOLD
|
||||
pi0(3) <= NOT (joystick_0(7) OR joystick_1(7) OR iSTART); -- START
|
||||
pi0(7 DOWNTO 4)<=po0(7 DOWNTO 4);
|
||||
pi0(0) <= NOT (joystick_0(4) OR joystick_1(4)); -- TIME
|
||||
pi0(1) <= NOT (joystick_0(5) OR joystick_1(5)); -- MODE
|
||||
pi0(2) <= NOT (joystick_0(6) OR joystick_1(6)); -- HOLD
|
||||
pi0(3) <= NOT (joystick_0(7) OR joystick_1(7)); -- START
|
||||
|
||||
pi1(7) <= NOT joystick_0(8); -- RIGHT G.DOWN
|
||||
pi1(6) <= NOT joystick_0(9); -- RIGHT G.UP
|
||||
pi1(5) <= NOT joystick_0(10); -- RIGHT CW
|
||||
pi1(4) <= NOT joystick_0(11); -- RIGHT CCW
|
||||
pi1(3) <= NOT joystick_0(3); -- RIGHT UP
|
||||
pi1(2) <= NOT joystick_0(2); -- RIGHT DOWN
|
||||
pi1(1) <= NOT joystick_0(1); -- RIGHT LEFT
|
||||
pi1(0) <= NOT joystick_0(0); -- RIGHT RIGHT
|
||||
pi1i(7) <= NOT joystick_0(8); -- RIGHT G.DOWN
|
||||
pi1i(6) <= NOT joystick_0(9); -- RIGHT G.UP
|
||||
pi1i(5) <= NOT joystick_0(10); -- RIGHT CW
|
||||
pi1i(4) <= NOT joystick_0(11); -- RIGHT CCW
|
||||
pi1i(3) <= NOT joystick_0(3); -- RIGHT UP
|
||||
pi1i(2) <= NOT joystick_0(2); -- RIGHT DOWN
|
||||
pi1i(1) <= NOT joystick_0(1); -- RIGHT LEFT
|
||||
pi1i(0) <= NOT joystick_0(0); -- RIGHT RIGHT
|
||||
|
||||
pi4(7) <= NOT joystick_1(8); -- LEFT G.DOWN
|
||||
pi4(6) <= NOT joystick_1(9); -- LEFT G.UP
|
||||
pi4(5) <= NOT joystick_1(10); -- LEFT CW
|
||||
pi4(4) <= NOT joystick_1(11); -- LEFT CCW
|
||||
pi4(3) <= NOT joystick_1(3); -- LEFT UP
|
||||
pi4(2) <= NOT joystick_1(2); -- LEFT DOWN
|
||||
pi4(1) <= NOT joystick_1(1); -- LEFT LEFT
|
||||
pi4(0) <= NOT joystick_1(0); -- LEFT RIGHT
|
||||
pi4i(7) <= NOT joystick_1(8); -- LEFT G.DOWN
|
||||
pi4i(6) <= NOT joystick_1(9); -- LEFT G.UP
|
||||
pi4i(5) <= NOT joystick_1(10); -- LEFT CW
|
||||
pi4i(4) <= NOT joystick_1(11); -- LEFT CCW
|
||||
pi4i(3) <= NOT joystick_1(3); -- LEFT UP
|
||||
pi4i(2) <= NOT joystick_1(2); -- LEFT DOWN
|
||||
pi4i(1) <= NOT joystick_1(1); -- LEFT LEFT
|
||||
pi4i(0) <= NOT joystick_1(0); -- LEFT RIGHT
|
||||
|
||||
pi1<=pi1i OR po1 WHEN rdena='1' ELSE po1;
|
||||
pi4<=pi4i OR po4 WHEN rdena='1' ELSE po4;
|
||||
|
||||
pi5<=x"FF";
|
||||
pi5<=po5;
|
||||
|
||||
----------------------------------------------------------
|
||||
-- Audio
|
||||
@@ -435,5 +514,9 @@ BEGIN
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
areset_na<=NOT reset AND pll_locked AND NOT ioctl_download;
|
||||
vreset_na<=x"0000" WHEN areset_na='0' ELSE
|
||||
'1' & vreset_na(0 TO 14) WHEN rising_edge(clk);
|
||||
reset_na<=vreset_na(15);
|
||||
|
||||
END struct;
|
||||
@@ -32,7 +32,10 @@ ENTITY f8_cpu IS
|
||||
|
||||
clk : IN std_logic;
|
||||
ce : IN std_logic;
|
||||
reset_na : IN std_logic
|
||||
reset_na : IN std_logic;
|
||||
acco : OUT uv8;
|
||||
visaro : OUT uv6;
|
||||
iozcso : OUT uv5
|
||||
);
|
||||
END ENTITY;
|
||||
|
||||
@@ -126,12 +129,12 @@ BEGIN
|
||||
WHEN 0 =>
|
||||
test<=testp;
|
||||
bcc<=bccp;
|
||||
|
||||
|
||||
WHEN 1 =>
|
||||
NULL;
|
||||
WHEN 2 =>
|
||||
NULL; -- <dw :=> <AVOIR>
|
||||
|
||||
|
||||
WHEN 3 =>
|
||||
CASE mop.rd IS
|
||||
WHEN RACC => rs1_v:=acc;
|
||||
@@ -205,7 +208,7 @@ BEGIN
|
||||
IF mop.rs=RISARM OR mop.rd=RISARM THEN
|
||||
visar(2 DOWNTO 0)<=visar(2 DOWNTO 0)-1;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN 7 =>
|
||||
IF len_v=S THEN
|
||||
IF mop.romc=ROMC_00 THEN -- IFETCH
|
||||
@@ -216,7 +219,7 @@ BEGIN
|
||||
madrs<=madrs+1;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN 11 =>
|
||||
IF len_v=L THEN
|
||||
IF mop.romc=ROMC_00 THEN -- IFETCH
|
||||
@@ -245,6 +248,10 @@ BEGIN
|
||||
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
acco<=acc;
|
||||
visaro<=visar;
|
||||
iozcso<=iozcs;
|
||||
|
||||
END ARCHITECTURE rtl;
|
||||
|
||||
|
||||
@@ -40,7 +40,7 @@ PACKAGE f8_pack IS
|
||||
dstm : OUT std_logic; -- Modified result reg
|
||||
iozcs_o : OUT uv5; -- Flags after
|
||||
test : OUT std_logic); -- Contitional branch test result
|
||||
|
||||
|
||||
--------------------------------------
|
||||
CONSTANT R0 : uint5 := 0;
|
||||
CONSTANT R1 : uint5 := 1;
|
||||
@@ -138,52 +138,52 @@ PACKAGE f8_pack IS
|
||||
(ROMC_00,S,1,I0,OP_MOV,R15,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 07 : r15 <= A : LR QL,A : Store r15
|
||||
(ROMC_07,L,0,I0,OP_MOV,R12,DATA), -- 08 : r12 <= data <= PC1U : LR K,P : Store stack reg.
|
||||
(ROMC_0B,L,0,I0,OP_MOV,R13,DATA), -- r13 <= data <= PC1L
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_15,L,0,I0,OP_MOV,DATA,R12), -- 09 : PC1U <= data <= r12 : LR P,K : Load stack reg.
|
||||
(ROMC_18,L,0,I0,OP_MOV,DATA,R13), -- PC1L <= data <= r13
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_MOV,RACC,ISAR), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 0A : ACC <= ISAR : LR A,IS : Store ISAR
|
||||
(ROMC_00,S,1,I0,OP_MOV,ISAR,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 0B : ISAR <= ACC : LR IS,A : Load ISAR
|
||||
(ROMC_12,L,0,I0,OP_MOV,DATA,R13), -- 0C : PC1 <= PC0 PC0L <= data <= R13 : PK : Call subroutine
|
||||
(ROMC_14,L,0,I0,OP_MOV,DATA,R12), -- PC0U <= data <= R12
|
||||
(ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_17,L,0,I0,OP_MOV,DATA,R15), -- 0D : PC0L <= data <= R15 : LR : Load Program Counter
|
||||
(ROMC_14,L,0,I0,OP_MOV,DATA,R14), -- PC0U <= data <= R14
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_06,L,0,I0,OP_MOV,R14,DATA), -- 0E : R14 <= data <= DC0U : LR Q,DC : Store d count r14/15
|
||||
(ROMC_09,L,0,I0,OP_MOV,R15,DATA), -- R15 <= data <= DC0L
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_16,L,0,I0,OP_MOV,DATA,R14), -- 0F : DC0U <= data <= R14 : LR DC,Q : Load d count r14/15
|
||||
(ROMC_19,L,0,I0,OP_MOV,DATA,R15), -- DC0L <= data <= R15
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_16,L,0,I0,OP_MOV,DATA,R10), -- 10 : DC0U <= data <= R10 : LR DC,H : Load d count r10/11
|
||||
(ROMC_19,L,0,I0,OP_MOV,DATA,R11), -- DC0L <= data <= R11
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_06,L,0,I0,OP_MOV,R10,DATA), -- 11 : R10 <= data <= DC0U : LR H,DC : Store d count r10/11
|
||||
(ROMC_09,L,0,I0,OP_MOV,R11,DATA), -- R11 <= data <= DC0L
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_SR1,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 12 : ACC <= ACC >> 1 : SR 1 : Shift right one
|
||||
(ROMC_00,S,1,I0,OP_SL1,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 13 : ACC <= ACC << 1 : SL 1 : Shift left one
|
||||
(ROMC_00,S,1,I0,OP_SR4,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 14 : ACC <= ACC >> 4 : SR 4 : Shift right four
|
||||
(ROMC_00,S,1,I0,OP_SL4,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 15 : ACC <= ACC << 4 : SL 4 : Shift left four
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_SR1,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 12 : ACC <= ACC >> 1 : SR 1 : Shift right one
|
||||
(ROMC_00,S,1,I0,OP_SL1,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 13 : ACC <= ACC << 1 : SL 1 : Shift left one
|
||||
(ROMC_00,S,1,I0,OP_SR4,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 14 : ACC <= ACC >> 4 : SR 4 : Shift right four
|
||||
(ROMC_00,S,1,I0,OP_SL4,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 15 : ACC <= ACC << 4 : SL 4 : Shift left four
|
||||
(ROMC_02,L,0,I0,OP_MOV,RACC,DATA), -- 16 : ACC <= DATA <= [DC0] : LM : LOAD mem DC0
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_05,L,0,I0,OP_MOV,DATA,RACC), -- 17 : [DC] <= DATA <= ACC : ST : STORE mem DC0
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_COM,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 18 : ACC <= !ACC : COM : Complement acc.
|
||||
(ROMC_00,S,1,I0,OP_LNK,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 19 : ACC <= ACC + carry : LNK : Add Carry acc.
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_COM,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 18 : ACC <= !ACC : COM : Complement acc.
|
||||
(ROMC_00,S,1,I0,OP_LNK,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 19 : ACC <= ACC + carry : LNK : Add Carry acc.
|
||||
(ROMC_1C,S,0,IY,OP_EDI,RACC,RACC), -- 1A : Clear ICB : DI : Disable Interrupt
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_EDI,RACC,RACC), -- 1B : Set ICB : EI : Enable Interrupt
|
||||
(ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_04,S,0,I0,OP_NOP,RACC,RACC), -- 1C : PC0 <= PC1 : POP : Return from sub
|
||||
(ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_MOV,WREG,R9), -- 1D : W <= R9 statusreg : LR W,J : Load Status reg r9
|
||||
(ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_MOV,R9,WREG), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 1E : R9 <= W statusreg : LR J,W : Store Status reg r9
|
||||
(ROMC_00,S,1,I0,OP_INC,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 1F : ACC <= ACC + 1 : INC : Increment
|
||||
(ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_MOV,R9,WREG), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 1E : R9 <= W statusreg : LR J,W : Store Status reg r9
|
||||
(ROMC_00,S,1,I0,OP_INC,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 1F : ACC <= ACC + 1 : INC : Increment
|
||||
(ROMC_03,L,0,I0,OP_MOV,RACC,DATA), -- 20 II : ACC <= IMM : LI ii : LOAD immediate acc.
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_03,L,0,I0,OP_AND,RACC,DATA), -- 21 II : ACC <= ACC & IMM : NI ii : AND immediate acc.
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_03,L,0,I0,OP_OR ,RACC,DATA), -- 22 II : ACC <= ACC | IMM : OI ii : OR immediate acc.
|
||||
@@ -247,7 +247,7 @@ PACKAGE f8_pack IS
|
||||
(ROMC_00,L,1,I0,OP_DEC,R11,R11), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 3B : R11-- : DS R11 : Decrement R11
|
||||
(ROMC_00,L,1,I0,OP_DEC,RISAR,RISAR), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 3C : (ISAR)-- : DS (ISAR) : Decrement (ISAR)
|
||||
(ROMC_00,L,1,I0,OP_DEC,RISARP,RISARP), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 3D : (ISAR++)-- : DS (ISAR+) : Decrement (ISAR++)
|
||||
(ROMC_00,L,1,I0,OP_DEC,RISARM,RISARM), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 3E : (ISAR++)-- : DS (ISAR-) : Decrement (ISAR--)
|
||||
(ROMC_00,L,1,I0,OP_DEC,RISARM,RISARM), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 3E : (ISAR--)-- : DS (ISAR-) : Decrement (ISAR--)
|
||||
(ROMC_00,L,1,I0,OP_DEC,R15,R15), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 3F : R15-- <INVALID> : DS R15 : Decrement R15
|
||||
|
||||
(ROMC_00,S,1,I0,OP_MOV,RACC,R0 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 40 : ACC <= R0 : LR A,R0 : LOAD R0
|
||||
@@ -265,7 +265,7 @@ PACKAGE f8_pack IS
|
||||
(ROMC_00,S,1,I0,OP_MOV,RACC,RISAR), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 4C : ACC <= (ISAR) : LR A,(ISAR) : LOAD (ISAR)
|
||||
(ROMC_00,S,1,I0,OP_MOV,RACC,RISARP), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 4D : ACC <= (ISAR++) : LR A,(ISAR+) : LOAD (ISAR++)
|
||||
(ROMC_00,S,1,I0,OP_MOV,RACC,RISARM), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 4E : ACC <= (ISAR--) : LR A,(ISAR-) : LOAD (ISAR--)
|
||||
(ROMC_00,S,1,I0,OP_MOV,RACC,R15), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 4F : ACC <= R15- <INVALID> : LR A,R15 : LOAD R15
|
||||
(ROMC_00,S,1,I0,OP_MOV,RACC,R15), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 4F : ACC <= R15 <INVALID> : LR A,R15 : LOAD R15
|
||||
|
||||
(ROMC_00,S,1,I0,OP_MOV,R0 ,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 50 : R0 <= ACC : LR R0 ,A : STORE R0
|
||||
(ROMC_00,S,1,I0,OP_MOV,R1 ,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 51 : R1 <= ACC : LR R1 ,A : STORE R1
|
||||
@@ -320,28 +320,28 @@ PACKAGE f8_pack IS
|
||||
(ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 7F : ACC <= 15 : LIS 15 : Load ACC 15
|
||||
|
||||
(ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 80 : Test 0 : Bcc 0 : Branch cond.
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 81 : Test 1 : Bcc 1 : Branch cond.
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 82 : Test 2 : Bcc 2 : Branch cond.
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 83 : Test 3 : Bcc 3 : Branch cond.
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 84 : Test 4 : Bcc 4 : Branch cond.
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 85 : Test 5 : Bcc 5 : Branch cond.
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 86 : Test 6 : Bcc 6 : Branch cond.
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 87 : Test 7 : Bcc 7 : Branch cond.
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
|
||||
(ROMC_02,L,0,I0,OP_ADD,RACC,DATA), -- 88 : ACC = ACC + [DC0] , DC0++ : AM : Add Binary mem
|
||||
@@ -358,56 +358,56 @@ PACKAGE f8_pack IS
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_0A,L,0,I0,OP_MOV,DATA,RACC), -- 8E : DC = DC + ACC (signed) : ADC : Add Data counter
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- 8F aa : Selon ISARL, PC +2 ou +imm : BR7 aa : Branch if ISARlo/=7
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- 8F aa : Test ISARL, PC +2 or +imm : BR7 aa : Branch if ISARlo/=7
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 90 aa : : BF 0 : Branch if negative
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 91 aa : : BF 1 : Branch if no carry
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 92 aa : : BF 2 : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 93 aa : : BF 3 : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 94 aa : : BF 4 : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 95 aa : : BF 5 : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 96 aa : : BF 6 : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 97 aa : : BF 7 : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 98 aa : : BF 8 : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 99 aa : : BF 9 : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 9A aa : : BF A : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 9B aa : : BF B : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 9C aa : : BF C : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 9D aa : : BF D : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 9E aa : : BF E : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
(ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 9F aa : : BF F : Branch if
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm
|
||||
(ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Test, change PC0 + 2 or +imm
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
|
||||
(ROMC_1C,S,0,I0,OP_MOV,RACC,PORT0), -- A0 : ACC <= IOPORT[0] : INS 0 : Input port 0
|
||||
@@ -418,7 +418,6 @@ PACKAGE f8_pack IS
|
||||
(ROMC_1C,L,0,I0,OP_LIS,DATA,R2), -- A2 : DATA <= IOPPORTNUM : INS 2 : Input port 2
|
||||
(ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
|
||||
(ROMC_1C,L,0,I0,OP_LIS,DATA,R3), -- A3 : DATA <= IOPPORTNUM : INS 3 : Input port 3
|
||||
(ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport
|
||||
(ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,
|
||||
@@ -601,14 +600,14 @@ PACKAGE f8_pack IS
|
||||
"SR 4 ", "SL 4 ", "LM ", "ST ",
|
||||
"COM ", "LNK ", "DI ", "EI ",
|
||||
"POP ", "LR W,J ", "LR J,W ", "INC ",
|
||||
"LI ii ", "NI ii ", "OI ii ", "XI ii ", -- 20
|
||||
"LI ii ", "NI ii ", "OI ii ", "XI ii ", -- 20
|
||||
"AI ii ", "CI ii ", "IN aa ", "OUT aa ",
|
||||
"PI aaaa ", "JMP aaaa ", "DCI aaaa ", "NOP ",
|
||||
"XDC ", "NOP ", "<INTERRUPT> ", "<RESET> ",
|
||||
"DEC R0 ", "DEC R1 ", "DEC R2 ", "DEC R3 ", -- 30
|
||||
"DEC R4 ", "DEC R5 ", "DEC R6 ", "DEC R7 ",
|
||||
"DEC R8 ", "DEC R9 ", "DEC R10 ", "DEC R11 ",
|
||||
"DEC (ISAR) ", "DEC (ISAR++)", "DEC (ISAR--)", "Invalid ",
|
||||
"DEC (ISAR) ", "DEC (ISAR+)", "DEC (ISAR-)", "Invalid ",
|
||||
"LR A,R0 ", "LR A,R1 ", "LR A,R2 ", "LR A,R3 ", -- 40
|
||||
"LR A,R4 ", "LR A,R5 ", "LR A,R6 ", "LR A,R7 ",
|
||||
"LR A,R8 ", "LR A,R9 ", "LR A,R10 ", "LR A,R11 ",
|
||||
@@ -625,14 +624,14 @@ PACKAGE f8_pack IS
|
||||
"LIS 4 ", "LIS 5 ", "LIS 6 ", "LIS 7 ",
|
||||
"LIS 8 ", "LIS 9 ", "LIS 10 ", "LIS 11 ",
|
||||
"LIS 12 ", "LIS 13 ", "LIS 14 ", "LIS 15 ",
|
||||
"BT 0 ", "BT 1 ", "BT 2 ", "BT 3 ", -- 80
|
||||
"BT 4 ", "BT 5 ", "BT 6 ", "BT 7 ",
|
||||
"BT 0 aa ", "BT 1 aa ", "BT 2 aa ", "BT 3 aa ", -- 80
|
||||
"BT 4 aa ", "BT 5 aa ", "BT 6 aa ", "BT 7 aa ",
|
||||
"AM ", "AMD ", "NM ", "OM ",
|
||||
"XM ", "CM ", "ADC ", "BR7 aa ",
|
||||
"BF 0 ", "BF 1 ", "BF 2 ", "BF 3 ", -- 90
|
||||
"BF 4 ", "BF 5 ", "BF 6 ", "BF 7 ",
|
||||
"BF 8 ", "BF 9 ", "BF A ", "BF B ",
|
||||
"BF C ", "BF D ", "BF E ", "BF F ",
|
||||
"BF 0 aa ", "BF 1 aa ", "BF 2 aa ", "BF 3 aa ", -- 90
|
||||
"BF 4 aa ", "BF 5 aa ", "BF 6 aa ", "BF 7 aa ",
|
||||
"BF 8 aa ", "BF 9 aa ", "BF A aa ", "BF B aa ",
|
||||
"BF C aa ", "BF D aa ", "BF E aa ", "BF F aa ",
|
||||
"INS 0 ", "INS 1 ", "INS 2 ", "INS 3 ", -- A0
|
||||
"INS 4 ", "INS 5 ", "INS 6 ", "INS 7 ",
|
||||
"INS 8 ", "INS 9 ", "INS 10 ", "INS 11 ",
|
||||
@@ -644,20 +643,39 @@ PACKAGE f8_pack IS
|
||||
"AS R0 ", "AS R1 ", "AS R2 ", "AS R3 ", -- C0
|
||||
"AS R4 ", "AS R5 ", "AS R6 ", "AS R7 ",
|
||||
"AS R8 ", "AS R9 ", "AS R10 ", "AS R11 ",
|
||||
"AS (ISAR) ", "AS (ISAR++) ", "AS (ISAR--) ", "Invalid ",
|
||||
"AS (ISAR) ", "AS (ISAR+) ", "AS (ISAR-) ", "Invalid ",
|
||||
"ASD R0 ", "ASD R1 ", "ASD R2 ", "ASD R3 ", -- D0
|
||||
"ASD R4 ", "ASD R5 ", "ASD R6 ", "ASD R7 ",
|
||||
"ASD R8 ", "ASD R9 ", "ASD R10 ", "ASD R11 ",
|
||||
"ASD (ISAR) ", "ASD (ISAR++)", "ASD (ISAR--)", "Invalid ",
|
||||
"ASD (ISAR) ", "ASD (ISAR+) ", "ASD (ISAR-) ", "Invalid ",
|
||||
"XOR R0 ", "XOR R1 ", "XOR R2 ", "XOR R3 ", -- E0
|
||||
"XOR R4 ", "XOR R5 ", "XOR R6 ", "XOR R7 ",
|
||||
"XOR R8 ", "XOR R9 ", "XOR R10 ", "XOR R11 ",
|
||||
"XOR (ISAR) ", "XOR (ISAR++)", "XOR (ISAR--)", "Invalid ",
|
||||
"XOR (ISAR) ", "XOR (ISAR+) ", "XOR (ISAR-) ", "Invalid ",
|
||||
"AND R0 ", "AND R1 ", "AND R2 ", "AND R3 ", -- F0
|
||||
"AND R4 ", "AND R5 ", "AND R6 ", "AND R7 ",
|
||||
"AND R8 ", "AND R9 ", "AND R10 ", "AND R11 ",
|
||||
"AND (ISAR) ", "AND (ISAR++)", "AND (ISAR--)", "Invalid ");
|
||||
|
||||
"AND (ISAR) ", "AND (ISAR+) ", "AND (ISAR-) ", "Invalid ");
|
||||
|
||||
TYPE arr_ilen IS ARRAY(natural RANGE <>) OF uint3;
|
||||
CONSTANT ILEN : arr_ilen(0 TO 255) :=(
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, --00
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, --10
|
||||
2,2,2,2, 2,2,2,2, 3,3,3,1, 1,1,0,0, --20
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,0, --30
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,0, --40
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,0, --50
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, --60
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, --70
|
||||
2,2,2,2, 2,2,2,2, 1,1,1,1, 1,1,1,2, --80
|
||||
2,2,2,2, 2,2,2,2, 2,2,2,2, 2,2,2,2, --90
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, --A0
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, --B0
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,0, --C0
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,0, --D0
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,0, --E0
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,0); --F0
|
||||
|
||||
END PACKAGE;
|
||||
|
||||
--##############################################################################
|
||||
|
||||
@@ -40,7 +40,7 @@ ENTITY f8_psu IS
|
||||
dv : OUT std_logic;
|
||||
|
||||
romc : IN uv5;
|
||||
tick : IN std_logic; -- 1/8 or 1/12 cycle lenght
|
||||
tick : IN std_logic; -- 1/8 or 1/12 cycle length
|
||||
phase : IN uint4;
|
||||
|
||||
ext_int : IN std_logic;
|
||||
@@ -61,7 +61,11 @@ ENTITY f8_psu IS
|
||||
|
||||
clk : IN std_logic;
|
||||
ce : IN std_logic;
|
||||
reset_na : IN std_logic
|
||||
reset_na : IN std_logic;
|
||||
|
||||
pc0o : OUT uv16;
|
||||
pc1o : OUT uv16;
|
||||
dc0o : OUT uv16
|
||||
);
|
||||
END ENTITY f8_psu;
|
||||
|
||||
@@ -179,8 +183,8 @@ BEGIN
|
||||
|
||||
WHEN "00110" =>
|
||||
-- L : Place the high order byte of DC0 on the data bus.
|
||||
dr <=dc0(15 DOWNTO 8);
|
||||
IF phase=2 THEN
|
||||
dr <=dc0(15 DOWNTO 8);
|
||||
dv <='1';
|
||||
END IF;
|
||||
|
||||
@@ -371,7 +375,7 @@ BEGIN
|
||||
-- port on the data bus. (Note that the contents of timer
|
||||
-- and interrupt control retgisters cannot be read back onto
|
||||
-- the data bus.)
|
||||
IF phase=6 THEN
|
||||
IF phase=2 THEN
|
||||
io_rd<=to_std_logic(io_port(7 DOWNTO 2)=IOPAGE);
|
||||
dr<=io_dr;
|
||||
dv<=to_std_logic(io_port(7 DOWNTO 2)=IOPAGE);
|
||||
@@ -386,10 +390,10 @@ BEGIN
|
||||
WHEN "11101" =>
|
||||
-- S : Devices with DC0 and DC1 registers must switch registers.
|
||||
-- Devices without a DC1 register perform no operation.
|
||||
IF phase=6 THEN
|
||||
dc0<=dc1;
|
||||
dc1<=dc0;
|
||||
END IF;
|
||||
--IF phase=6 THEN
|
||||
-- dc0<=dc1;
|
||||
-- dc1<=dc0;
|
||||
--END IF;
|
||||
|
||||
WHEN "11110" =>
|
||||
-- L : The device whose address space includes the contents of
|
||||
@@ -411,6 +415,12 @@ BEGIN
|
||||
NULL;
|
||||
|
||||
END CASE;
|
||||
|
||||
IF reset_na='0' THEN
|
||||
pc0<=x"0000";
|
||||
pc1<=x"0000";
|
||||
dc0<=x"0000";
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
@@ -483,10 +493,18 @@ BEGIN
|
||||
WHEN OTHERS => icr<=io_dw(1 DOWNTO 0);
|
||||
END CASE;
|
||||
END IF;
|
||||
|
||||
|
||||
IF reset_na='0' THEN
|
||||
po_a_l<=x"00";
|
||||
po_b_l<=x"00";
|
||||
END IF;
|
||||
-------------------------------
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
pc0o<=pc0;
|
||||
pc1o<=pc1;
|
||||
dc0o<=dc0;
|
||||
|
||||
END ARCHITECTURE rtl;
|
||||
|
||||
@@ -40,26 +40,30 @@ module pll (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
locked);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output c2;
|
||||
output locked;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire [0:0] sub_wire7 = 1'h0;
|
||||
wire [2:2] sub_wire4 = sub_wire0[2:2];
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
wire c2 = sub_wire4;
|
||||
wire sub_wire5 = inclk0;
|
||||
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire5),
|
||||
.inclk (sub_wire6),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.activeclock (),
|
||||
@@ -102,10 +106,14 @@ module pll (
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 35,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 181,
|
||||
altpll_component.clk1_divide_by = 400,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 24,
|
||||
altpll_component.clk1_multiply_by = 53,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.clk2_divide_by = 715,
|
||||
altpll_component.clk2_duty_cycle = 50,
|
||||
altpll_component.clk2_multiply_by = 106,
|
||||
altpll_component.clk2_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
@@ -140,7 +148,7 @@ module pll (
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk2 = "PORT_USED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
@@ -180,11 +188,14 @@ endmodule
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "181"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "400"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "715"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.636364"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "3.580111"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "3.577500"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "4.002797"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
@@ -206,25 +217,33 @@ endmodule
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "35"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "24"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "53"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "106"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.63636000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "3.57900000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "3.57954500"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "4.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
@@ -248,13 +267,16 @@ endmodule
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
@@ -263,10 +285,14 @@ endmodule
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "35"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "181"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "400"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "24"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "53"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "715"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "106"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
@@ -300,7 +326,7 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
@@ -319,12 +345,14 @@ endmodule
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
|
||||
Reference in New Issue
Block a user