mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-11 23:43:09 +00:00
ChannelF
This commit is contained in:
Marcel
parent
94051a0399
commit
453d0ce38f
@ -46,15 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/ChannelF_MiST.sv
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set_global_assignment -name VHDL_FILE rtl/channel_f.vhd
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set_global_assignment -name VHDL_FILE rtl/f8_cpu.vhd
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set_global_assignment -name VHDL_FILE rtl/f8_psu.vhd
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set_global_assignment -name VHDL_FILE rtl/f8_pack.vhd
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set_global_assignment -name VHDL_FILE rtl/base_pack.vhd
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set_global_assignment -name VHDL_FILE rtl/rom_pack.vhd
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
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# Pin & Location Assignments
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# ==========================
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@ -159,4 +150,13 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
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# end ENTITY(ChannelF_MiST)
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# -------------------------
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/ChannelF_MiST.sv
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set_global_assignment -name VHDL_FILE rtl/chf_core.vhd
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set_global_assignment -name VHDL_FILE rtl/f8_cpu.vhd
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set_global_assignment -name VHDL_FILE rtl/f8_psu.vhd
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set_global_assignment -name VHDL_FILE rtl/f8_pack.vhd
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set_global_assignment -name VHDL_FILE rtl/base_pack.vhd
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set_global_assignment -name VHDL_FILE rtl/rom_pack.vhd
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -1,127 +0,0 @@
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## Generated SDC file "vectrex_MiST.out.sdc"
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## Copyright (C) 1991-2013 Altera Corporation
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, Altera MegaCore Function License
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## Agreement, or other applicable license agreement, including,
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## without limitation, that your use is for the sole purpose of
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## programming logic devices manufactured by Altera and sold by
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## Altera or its authorized distributors. Please refer to the
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## applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
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## DATE "Sun Jun 24 12:53:00 2018"
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##
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## DEVICE "EP3C25E144C8"
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##
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# Clock constraints
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# Automatically constrain PLL and other generated clocks
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derive_pll_clocks -create_base_clocks
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# Automatically calculate clock uncertainty to jitter and other effects.
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derive_clock_uncertainty
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# tsu/th constraints
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# tco constraints
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# tpd constraints
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
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set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
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set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
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set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
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set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
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set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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set_output_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[4]}] 1.000 [get_ports {AUDIO_L}]
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[4]}] 1.000 [get_ports {AUDIO_R}]
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}]
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
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set_clock_groups -asynchronous -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[4]}]
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#**************************************************************
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# Set False Path
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#**************************************************************
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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set_multicycle_path -to {VGA_*[*]} -setup 2
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set_multicycle_path -to {VGA_*[*]} -hold 1
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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Binary file not shown.
@ -19,10 +19,9 @@ module ChannelF_MiST(
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`include "rtl\build_id.v"
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localparam CONF_STR = {
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"ChannelF;BINCHF;",
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"ChannelF;BINCHFROM;",
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"O1,Swap Joystick,Off,On;",
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"O34,Scanlines,Off,25%,50%,75%;",
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// "O6,Blending,Off,On;",
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"T0,Reset;",
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"V,v1.00.",`BUILD_DATE
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};
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@ -37,9 +36,11 @@ pll pll(
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.c1 ( clk3p579 )//3.579545
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);
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channel_f channel_f(
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chf_core chf_core(
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.clk ( clk3p579 ),
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.reset ( status[0] | buttons[1]),
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.reset ( status[0] | buttons[1] | ioctl_downl),
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.pal (),
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.pll_locked ( pll_locked ),
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.vga_r ( r ),
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.vga_g ( g ),
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@ -47,22 +48,20 @@ channel_f channel_f(
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.vga_hs ( hs ),
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.vga_vs ( vs ),
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.vga_de ( blankn ),
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.Keys ( {m_four_players, m_three_players, m_two_players, m_one_player}),
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.joystick_0 ( {m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right}),
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.joystick_1 ( {m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2}),
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.joystick_0 ( {m_fireD, m_fireC, m_fireB, m_fireA, m_four_players, m_three_players, m_two_players, m_one_player, m_up, m_down, m_left, m_right}),
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.joystick_1 ( {m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_four_players, m_three_players, m_two_players, m_one_player, m_up2, m_down2, m_left2, m_right2}),
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.ioctl_download ( ioctl_downl ),
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.ioctl_index ( ioctl_index ),
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.ioctl_wr ( ~ioctl_wr ),//todo
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.ioctl_wr ( ~ioctl_wr ),//?
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.ioctl_addr ( ioctl_addr ),
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.ioctl_dout ( ioctl_dout ),
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.ioctl_wait ( ioctl_wait ),//todo
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.audio ( audio )
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.ioctl_wait ( ),
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.audio_l ( audio )
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);
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wire ioctl_downl;
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wire [7:0] ioctl_index;
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wire ioctl_wr;
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wire ioctl_wait;
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wire [24:0] ioctl_addr;
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wire [7:0] ioctl_dout;
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@ -146,8 +145,8 @@ dac(
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.dac_o ( AUDIO_L )
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);
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wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
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wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
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wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF, m_fireG, m_fireH;
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wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F, m_fire2G, m_fire2H;
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wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
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arcade_inputs inputs (
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@ -157,12 +156,12 @@ arcade_inputs inputs (
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.key_code ( key_code ),
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.joystick_0 ( joystick_0 ),
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.joystick_1 ( joystick_1 ),
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.rotate ( 0 ),
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.orientation ( 2'b00 ),
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// .rotate ( 0 ),
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// .orientation ( 2'b00 ),
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.joyswap ( status[1] ),
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.oneplayer ( 1'b0 ),
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.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
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.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
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.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
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.player1 ( {m_fireH, m_fireG, m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
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.player2 ( {m_fire2H, m_fire2G, m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
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);
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endmodule
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@ -15,14 +15,14 @@ PACKAGE base_pack IS
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--------------------------------------
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SUBTYPE uv IS unsigned;
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SUBTYPE sv IS signed;
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SUBTYPE uv1_0 IS unsigned(1 DOWNTO 0);
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SUBTYPE uv0_1 IS unsigned(0 TO 1);
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SUBTYPE uv3_0 IS unsigned(3 DOWNTO 0);
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SUBTYPE uv0_3 IS unsigned(0 TO 3);
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SUBTYPE uv7_0 IS unsigned(7 DOWNTO 0);
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SUBTYPE uv0_7 IS unsigned(0 TO 7);
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SUBTYPE uv2 IS unsigned(1 DOWNTO 0);
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SUBTYPE uv3 IS unsigned(2 DOWNTO 0);
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SUBTYPE uv4 IS unsigned(3 DOWNTO 0);
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@ -56,7 +56,7 @@ PACKAGE base_pack IS
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SUBTYPE uv32 IS unsigned(31 DOWNTO 0);
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SUBTYPE uv64 IS unsigned(63 DOWNTO 0);
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SUBTYPE uv128 IS unsigned(127 DOWNTO 0);
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SUBTYPE sv2 IS signed(1 DOWNTO 0);
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SUBTYPE sv4 IS signed(3 DOWNTO 0);
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SUBTYPE sv8 IS signed(7 DOWNTO 0);
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@ -64,10 +64,10 @@ PACKAGE base_pack IS
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SUBTYPE sv32 IS signed(31 DOWNTO 0);
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SUBTYPE sv64 IS signed(63 DOWNTO 0);
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SUBTYPE sv128 IS signed(127 DOWNTO 0);
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TYPE arr_uv0_3 IS ARRAY(natural RANGE <>) OF uv0_3;
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TYPE arr_uv0_7 IS ARRAY(natural RANGE <>) OF uv0_7;
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TYPE arr_uv4 IS ARRAY(natural RANGE <>) OF uv4;
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TYPE arr_uv8 IS ARRAY(natural RANGE <>) OF uv8;
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TYPE arr_uv16 IS ARRAY(natural RANGE <>) OF uv16;
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@ -108,14 +108,14 @@ PACKAGE base_pack IS
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SUBTYPE int15 IS integer RANGE -16384 TO 16383;
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SUBTYPE int16 IS integer RANGE -32768 TO 32767;
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SUBTYPE int17 IS integer RANGE -65536 TO 65535;
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-------------------------------------------------------------
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FUNCTION v_or (CONSTANT v : unsigned) RETURN std_logic;
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FUNCTION v_and (CONSTANT v : unsigned) RETURN std_logic;
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FUNCTION vv (CONSTANT s : std_logic;
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CONSTANT N : natural) RETURN unsigned;
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--------------------------------------
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FUNCTION to_std_logic (a : boolean) RETURN std_logic;
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--------------------------------------
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@ -190,9 +190,9 @@ PACKAGE base_pack IS
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FUNCTION To_Upper (s : string) RETURN string;
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FUNCTION To_String (i : natural; b : integer) RETURN string;
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FUNCTION To_Natural (s : string; b : integer) RETURN natural;
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FUNCTION ilog2 (CONSTANT v : natural) RETURN natural;
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END PACKAGE base_pack;
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--------------------------------------------------------------------------------
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@ -207,7 +207,7 @@ PACKAGE BODY base_pack IS
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v:=(OTHERS => s);
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RETURN v;
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END FUNCTION vv;
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-------------------------------------------------------------
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-- Vector OR (reduce)
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FUNCTION v_or (CONSTANT v : unsigned) RETURN std_logic IS
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@ -231,7 +231,7 @@ PACKAGE BODY base_pack IS
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END IF;
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--pragma synthesis_on
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END FUNCTION v_or;
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-------------------------------------------------------------
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-- Vector AND (reduce)
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FUNCTION v_and (CONSTANT v : unsigned) RETURN std_logic IS
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@ -255,7 +255,7 @@ PACKAGE BODY base_pack IS
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END IF;
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--pragma synthesis_on
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END FUNCTION v_and;
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--------------------------------------
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FUNCTION to_std_logic (a : boolean) RETURN std_logic IS
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BEGIN
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@ -263,7 +263,7 @@ PACKAGE BODY base_pack IS
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ELSE RETURN '0';
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END IF;
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END FUNCTION to_std_logic;
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--------------------------------------
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-- Sélection/Multiplexage s=1:a, s=0:b
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FUNCTION mux (
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@ -282,7 +282,7 @@ PACKAGE BODY base_pack IS
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RETURN x;
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END IF;
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END FUNCTION mux;
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--------------------------------------
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-- Sélection/Multiplexage s=true:a, s=false:b
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FUNCTION mux (
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@ -298,7 +298,7 @@ PACKAGE BODY base_pack IS
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RETURN b;
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END IF;
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END FUNCTION mux;
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||||
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||||
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||||
--------------------------------------
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-- Sélection/Multiplexage s=1:a, s=0:b
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FUNCTION mux (
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@ -309,7 +309,7 @@ PACKAGE BODY base_pack IS
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BEGIN
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RETURN (S AND A) OR (NOT S AND B);
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END FUNCTION mux;
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||||
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||||
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||||
--------------------------------------
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||||
-- Sélection/Multiplexage s=true:a, s=false:b
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FUNCTION mux (
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@ -324,7 +324,7 @@ PACKAGE BODY base_pack IS
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RETURN b;
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END IF;
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||||
END FUNCTION mux;
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||||
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||||
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||||
--------------------------------------
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||||
-- Sélection/Multiplexage s=true:a, s=false:b
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||||
FUNCTION mux (
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@ -339,7 +339,7 @@ PACKAGE BODY base_pack IS
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RETURN b;
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END IF;
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END FUNCTION mux;
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||||
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||||
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||||
--------------------------------------
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||||
-- Sélection/Multiplexage s=1:a, s=0:b
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||||
FUNCTION mux (
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@ -369,7 +369,7 @@ PACKAGE BODY base_pack IS
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RETURN b;
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END IF;
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||||
END FUNCTION mux;
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||||
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||||
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||||
--------------------------------------
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||||
-- Sélection/Multiplexage s=true:a, s=false:b
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FUNCTION mux (
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@ -384,7 +384,7 @@ PACKAGE BODY base_pack IS
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RETURN b;
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END IF;
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||||
END FUNCTION mux;
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||||
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||||
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||||
--------------------------------------
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||||
-- Étend un vecteur avec extension de signe
|
||||
FUNCTION sext (
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||||
@ -397,7 +397,7 @@ PACKAGE BODY base_pack IS
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||||
t(e'length-1 DOWNTO 0):=e;
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||||
RETURN t;
|
||||
END FUNCTION sext;
|
||||
|
||||
|
||||
--------------------------------------
|
||||
-- Étend un vecteur avec extension de signe
|
||||
FUNCTION sext (
|
||||
@ -409,7 +409,7 @@ PACKAGE BODY base_pack IS
|
||||
t:=(OTHERS => e);
|
||||
RETURN t;
|
||||
END FUNCTION sext;
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||||
|
||||
|
||||
--------------------------------------
|
||||
-- Étend un vecteur sans extension de signe
|
||||
FUNCTION uext (
|
||||
@ -422,7 +422,7 @@ PACKAGE BODY base_pack IS
|
||||
t(e'length-1 DOWNTO 0):=e;
|
||||
RETURN t;
|
||||
END FUNCTION uext;
|
||||
|
||||
|
||||
--------------------------------------
|
||||
-- Étend un vecteur sans extension de signe
|
||||
FUNCTION uext (
|
||||
@ -435,7 +435,7 @@ PACKAGE BODY base_pack IS
|
||||
t(0):=e;
|
||||
RETURN t;
|
||||
END FUNCTION uext;
|
||||
|
||||
|
||||
--------------------------------------
|
||||
-- Wait Until Rising Edge
|
||||
PROCEDURE wure(
|
||||
@ -460,7 +460,7 @@ PACKAGE BODY base_pack IS
|
||||
|
||||
--------------------------------------
|
||||
CONSTANT HexString : string(1 TO 16):="0123456789ABCDEF";
|
||||
|
||||
|
||||
-- Conversion unsigned -> Chaîne hexadécimale
|
||||
FUNCTION To_HString(v : unsigned) RETURN string IS
|
||||
VARIABLE r : string(1 TO ((v'length)+3)/4);
|
||||
@ -563,7 +563,7 @@ PACKAGE BODY base_pack IS
|
||||
END LOOP;
|
||||
RETURN r;
|
||||
END To_Upper;
|
||||
|
||||
|
||||
--------------------------------------
|
||||
-- Conversion entier -> chaîne
|
||||
FUNCTION To_String(i: natural; b: integer) RETURN string IS
|
||||
@ -581,7 +581,7 @@ PACKAGE BODY base_pack IS
|
||||
|
||||
RETURN r(k TO 10);
|
||||
END FUNCTION To_String;
|
||||
|
||||
|
||||
--------------------------------------
|
||||
-- Conversion chaîne -> entier
|
||||
FUNCTION To_Natural (s : string; b : integer) RETURN natural IS
|
||||
@ -627,5 +627,5 @@ PACKAGE BODY base_pack IS
|
||||
END LOOP;
|
||||
RETURN n;
|
||||
END FUNCTION ilog2;
|
||||
|
||||
END PACKAGE BODY base_pack;
|
||||
|
||||
END PACKAGE BODY base_pack;
|
||||
@ -5,12 +5,12 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- With help from MAME F8 model
|
||||
|
||||
-- 0000 : ROM : sl90025.rom ou sl31253.rom
|
||||
-- 0000 : ROM : sl90025.rom or sl31253.rom
|
||||
-- 0400 : ROM : sl31254.rom
|
||||
-- 0800+ : CART
|
||||
|
||||
-- COLOR = P[126 + Y*128][2] & P[125 + Y*128][2] & P[X + Y*128][1:0]
|
||||
|
||||
|
||||
-- F3850 : PORT 0 : 7 : NC
|
||||
-- 6 : OUT : ENABLE IN BTN
|
||||
-- 5 : OUT : ARM WRT
|
||||
@ -51,56 +51,62 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.std_logic_1164.all;
|
||||
USE IEEE.numeric_std.all;
|
||||
|
||||
--USE std.textio.ALL;
|
||||
USE std.textio.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.base_pack.ALL;
|
||||
USE work.rom_pack.ALL;
|
||||
USE work.f8_pack.ALL;
|
||||
|
||||
ENTITY channel_f IS
|
||||
ENTITY chf_core IS
|
||||
PORT (
|
||||
clk : IN std_logic;
|
||||
pll_locked : IN std_logic;
|
||||
reset : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
pll_locked : IN std_logic;
|
||||
|
||||
pal : IN std_logic;
|
||||
reset : IN std_logic;
|
||||
|
||||
-- VGA
|
||||
vga_clk : OUT std_logic;
|
||||
vga_ce : OUT std_logic;
|
||||
vga_r : OUT std_logic_vector(7 DOWNTO 0);
|
||||
vga_g : OUT std_logic_vector(7 DOWNTO 0);
|
||||
vga_b : OUT std_logic_vector(7 DOWNTO 0);
|
||||
vga_hs : OUT std_logic; -- positive pulse!
|
||||
vga_vs : OUT std_logic; -- positive pulse!
|
||||
vga_de : OUT std_logic; -- = not (VBlank or HBlank)
|
||||
vga_clk : OUT std_logic;
|
||||
vga_ce : OUT std_logic;
|
||||
vga_r : OUT std_logic_vector(7 DOWNTO 0);
|
||||
vga_g : OUT std_logic_vector(7 DOWNTO 0);
|
||||
vga_b : OUT std_logic_vector(7 DOWNTO 0);
|
||||
vga_hs : OUT std_logic; -- positive pulse!
|
||||
vga_vs : OUT std_logic; -- positive pulse!
|
||||
vga_de : OUT std_logic; -- = not (VBlank or HBlank)
|
||||
|
||||
-- HPS IO
|
||||
Keys : IN unsigned(3 DOWNTO 0);
|
||||
joystick_0 : IN unsigned(7 DOWNTO 0);
|
||||
joystick_1 : IN unsigned(7 DOWNTO 0);
|
||||
--ROM LOAD
|
||||
joystick_0 : IN unsigned(31 DOWNTO 0);
|
||||
joystick_1 : IN unsigned(31 DOWNTO 0);
|
||||
joystick_analog_0 : IN unsigned(15 DOWNTO 0);
|
||||
joystick_analog_1 : IN unsigned(15 DOWNTO 0);
|
||||
status : IN unsigned(31 DOWNTO 0);
|
||||
ioctl_download : IN std_logic;
|
||||
ioctl_index : IN std_logic_vector(7 DOWNTO 0);
|
||||
ioctl_wr : IN std_logic;
|
||||
ioctl_addr : IN std_logic_vector(24 DOWNTO 0);
|
||||
ioctl_dout : IN std_logic_vector(7 DOWNTO 0);
|
||||
ioctl_wait : OUT std_logic;
|
||||
-- AUDIO
|
||||
audio : OUT std_logic_vector(15 DOWNTO 0)
|
||||
);
|
||||
|
||||
END channel_f;
|
||||
|
||||
ARCHITECTURE struct OF channel_f IS
|
||||
-- AUDIO
|
||||
audio_l : OUT std_logic_vector(15 DOWNTO 0);
|
||||
audio_r : OUT std_logic_vector(15 DOWNTO 0)
|
||||
);
|
||||
END chf_core;
|
||||
|
||||
ARCHITECTURE struct OF chf_core IS
|
||||
|
||||
SIGNAL ioctl_wait_l,ioctl_download2,ioctl_wr2 : std_logic;
|
||||
SIGNAL adrs : uv17;
|
||||
|
||||
|
||||
----------------------------------------------------------
|
||||
SIGNAL dr,dr0,dr1,dr2,dr3,dr4,dr5,dw_cpu : uv8;
|
||||
SIGNAL dv0,dv1,dv2,dv3,dv4,dv5,dv_cpu : std_logic;
|
||||
SIGNAL romc : uv5;
|
||||
SIGNAL phase : uint4;
|
||||
SIGNAL ce : std_logic :='0';
|
||||
|
||||
|
||||
SIGNAL pi0,po0,pi1,po1,pi1i,pi4,po4,pi4i,pi5,po5 : uv8;
|
||||
SIGNAL rdena : std_logic;
|
||||
SIGNAL load_a : uv10;
|
||||
@ -109,7 +115,7 @@ ARCHITECTURE struct OF channel_f IS
|
||||
SIGNAL tick : std_logic;
|
||||
SIGNAL reset_na,areset_na : std_logic;
|
||||
SIGNAL vreset_na : unsigned(0 TO 15);
|
||||
|
||||
|
||||
----------------------------------------------------------
|
||||
CONSTANT INIT_ZERO : arr_uv8(0 TO 1023) := (OTHERS => x"00");
|
||||
|
||||
@ -122,7 +128,7 @@ ARCHITECTURE struct OF channel_f IS
|
||||
CONSTANT VSYNCSTART : natural :=242;
|
||||
CONSTANT VSYNCEND : natural :=246;
|
||||
CONSTANT VTOTAL : natural :=262;
|
||||
|
||||
|
||||
-- BLACK WHITE RED GREEN BLUE LTGRAY LTGREEN LTBLUE
|
||||
CONSTANT PAL_R : arr_uv8(0 TO 7) :=
|
||||
(x"10",x"FD",x"FF",x"02",x"4B",x"E0",x"91",x"CE");
|
||||
@ -143,16 +149,16 @@ ARCHITECTURE struct OF channel_f IS
|
||||
SIGNAL vram_v : uint6;
|
||||
SIGNAL vram_dw : uv2;
|
||||
SIGNAL vram_wr : std_logic;
|
||||
|
||||
|
||||
SIGNAL v125 : std_logic_vector(0 TO 63);
|
||||
SIGNAL v126 : std_logic_vector(0 TO 63);
|
||||
|
||||
|
||||
SIGNAL p125,p125p,p126,p126p : std_logic;
|
||||
SIGNAL hpos,hposp : uint8;
|
||||
SIGNAL vpos,vposp : uint9;
|
||||
SIGNAL pos : uint13;
|
||||
SIGNAL pix : uv2;
|
||||
|
||||
|
||||
SIGNAL vdiv : uv16;
|
||||
SIGNAL tone : uv2;
|
||||
SIGNAL dc0,pc0,pc1 : uv16;
|
||||
@ -160,65 +166,36 @@ ARCHITECTURE struct OF channel_f IS
|
||||
SIGNAL visar : uv6;
|
||||
SIGNAL iozcs : uv5;
|
||||
BEGIN
|
||||
|
||||
|
||||
----------------------------------------------------------
|
||||
-- CPU
|
||||
|
||||
|
||||
-- CPUCLK = VIDEOCLK / 2
|
||||
ce <='1'; --NOT ce WHEN rising_edge(clk);
|
||||
|
||||
|
||||
i_cpu: ENTITY work.f8_cpu
|
||||
PORT MAP (
|
||||
dr => dr,
|
||||
dw => dw_cpu,
|
||||
dv => dv_cpu,
|
||||
romc => romc,
|
||||
tick => tick,
|
||||
phase => phase,
|
||||
po_a => po0,
|
||||
pi_a => pi0,
|
||||
po_b => po1,
|
||||
pi_b => pi1,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
reset_na => reset_na,
|
||||
acco => acc,
|
||||
visaro => visar,
|
||||
iozcso => iozcs
|
||||
);
|
||||
dr => dr, dw => dw_cpu, dv => dv_cpu,
|
||||
romc => romc, tick => tick, phase => phase,
|
||||
po_a => po0, pi_a => pi0, po_b => po1, pi_b => pi1,
|
||||
clk => clk, ce => ce, reset_na => reset_na,
|
||||
acco => acc, visaro => visar, iozcso => iozcs);
|
||||
|
||||
-- PSU SL31253
|
||||
i_psu0:ENTITY work.f8_psu
|
||||
GENERIC MAP (
|
||||
PAGE => "000000", -- 0x0000
|
||||
IOPAGE => "000001", -- Not used
|
||||
IOPAGE => "000001", -- Ports 4,5
|
||||
IVEC => x"FFFF", -- Not used
|
||||
ROM => arr_uv8(INIT_SL31253))
|
||||
PORT MAP (
|
||||
dw => dr,
|
||||
dr => dr0,
|
||||
dv => dv0,
|
||||
romc => romc,
|
||||
tick => tick,
|
||||
phase => phase,
|
||||
ext_int => '0',
|
||||
int_req => OPEN,
|
||||
pri_o => OPEN,
|
||||
pri_i => '1',
|
||||
po_a => po4,
|
||||
pi_a => pi4,
|
||||
po_b => po5,
|
||||
pi_b => pi5,
|
||||
load_a => load_a,
|
||||
load_d => load_d,
|
||||
load_wr => '0',
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
reset_na => reset_na,
|
||||
pc0o => pc0,
|
||||
pc1o => pc1,
|
||||
dc0o => dc0
|
||||
);
|
||||
dw => dr, dr => dr0, dv => dv0,
|
||||
romc => romc, tick => tick, phase => phase,
|
||||
ext_int => '0', int_req => OPEN, pri_o => OPEN, pri_i => '1',
|
||||
po_a => po4, pi_a => pi4, po_b => po5, pi_b => pi5,
|
||||
load_a => load_a, load_d => load_d, load_wr => '0',
|
||||
clk => clk, ce => ce, reset_na => reset_na,
|
||||
pc0o => pc0, pc1o => pc1, dc0o => dc0);
|
||||
|
||||
-- PSU SL31254
|
||||
i_psu1:ENTITY work.f8_psu
|
||||
@ -228,27 +205,12 @@ BEGIN
|
||||
IVEC => x"FFFF", -- Not used
|
||||
ROM => arr_uv8(INIT_SL31254))
|
||||
PORT MAP (
|
||||
dw => dr,
|
||||
dr => dr1,
|
||||
dv => dv1,
|
||||
romc => romc,
|
||||
tick => tick,
|
||||
phase => phase,
|
||||
ext_int => '0',
|
||||
int_req => OPEN,
|
||||
pri_o => OPEN,
|
||||
pri_i => '1',
|
||||
po_a => OPEN,
|
||||
pi_a => x"FF",
|
||||
po_b => OPEN,
|
||||
pi_b => x"FF",
|
||||
load_a => load_a,
|
||||
load_d => load_d,
|
||||
load_wr => '0',
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
reset_na => reset_na
|
||||
);
|
||||
dw => dr, dr => dr1, dv => dv1,
|
||||
romc => romc, tick => tick, phase => phase,
|
||||
ext_int => '0', int_req => OPEN, pri_o => OPEN, pri_i => '1',
|
||||
po_a => OPEN, pi_a => x"FF", po_b => OPEN, pi_b => x"FF",
|
||||
load_a => load_a, load_d => load_d, load_wr => '0',
|
||||
clk => clk, ce => ce, reset_na => reset_na);
|
||||
|
||||
-- CARTRIDGE
|
||||
i_psu2:ENTITY work.f8_psu
|
||||
@ -258,27 +220,12 @@ BEGIN
|
||||
IVEC => x"FFFF", -- Not used
|
||||
ROM => INIT_ZERO)
|
||||
PORT MAP (
|
||||
dw => dr,
|
||||
dr => dr2,
|
||||
dv => dv2,
|
||||
romc => romc,
|
||||
tick => tick,
|
||||
phase => phase,
|
||||
ext_int => '0',
|
||||
int_req => OPEN,
|
||||
pri_o => OPEN,
|
||||
pri_i => '1',
|
||||
po_a => OPEN,
|
||||
pi_a => x"FF",
|
||||
po_b => OPEN,
|
||||
pi_b => x"FF",
|
||||
load_a => load_a,
|
||||
load_d => load_d,
|
||||
load_wr => load_wr0,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
reset_na => reset_na
|
||||
);
|
||||
dw => dr, dr => dr2, dv => dv2,
|
||||
romc => romc, tick => tick, phase => phase,
|
||||
ext_int => '0', int_req => OPEN, pri_o => OPEN, pri_i => '1',
|
||||
po_a => OPEN, pi_a => x"FF", po_b => OPEN, pi_b => x"FF",
|
||||
load_a => load_a, load_d => load_d, load_wr => load_wr0,
|
||||
clk => clk, ce => ce, reset_na => reset_na);
|
||||
|
||||
-- CARTRIDGE
|
||||
i_psu3:ENTITY work.f8_psu
|
||||
@ -288,28 +235,13 @@ BEGIN
|
||||
IVEC => x"FFFF", -- Not used
|
||||
ROM => INIT_ZERO)
|
||||
PORT MAP (
|
||||
dw => dr,
|
||||
dr => dr3,
|
||||
dv => dv3,
|
||||
romc => romc,
|
||||
tick => tick,
|
||||
phase => phase,
|
||||
ext_int => '0',
|
||||
int_req => OPEN,
|
||||
pri_o => OPEN,
|
||||
pri_i => '1',
|
||||
po_a => OPEN,
|
||||
pi_a => x"FF",
|
||||
po_b => OPEN,
|
||||
pi_b => x"FF",
|
||||
load_a => load_a,
|
||||
load_d => load_d,
|
||||
load_wr => load_wr1,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
reset_na => reset_na
|
||||
);
|
||||
|
||||
dw => dr, dr => dr3, dv => dv3,
|
||||
romc => romc, tick => tick, phase => phase,
|
||||
ext_int => '0', int_req => OPEN, pri_o => OPEN, pri_i => '1',
|
||||
po_a => OPEN, pi_a => x"FF", po_b => OPEN, pi_b => x"FF",
|
||||
load_a => load_a, load_d => load_d, load_wr => load_wr1,
|
||||
clk => clk, ce => ce, reset_na => reset_na);
|
||||
|
||||
-- CARTRIDGE
|
||||
i_psu4:ENTITY work.f8_psu
|
||||
GENERIC MAP (
|
||||
@ -318,28 +250,13 @@ BEGIN
|
||||
IVEC => x"FFFF", -- Not used
|
||||
ROM => INIT_ZERO)
|
||||
PORT MAP (
|
||||
dw => dr,
|
||||
dr => dr4,
|
||||
dv => dv4,
|
||||
romc => romc,
|
||||
tick => tick,
|
||||
phase => phase,
|
||||
ext_int => '0',
|
||||
int_req => OPEN,
|
||||
pri_o => OPEN,
|
||||
pri_i => '1',
|
||||
po_a => OPEN,
|
||||
pi_a => x"FF",
|
||||
po_b => OPEN,
|
||||
pi_b => x"FF",
|
||||
load_a => load_a,
|
||||
load_d => load_d,
|
||||
load_wr => load_wr2,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
reset_na => reset_na
|
||||
);
|
||||
|
||||
dw => dr, dr => dr4, dv => dv4,
|
||||
romc => romc, tick => tick, phase => phase,
|
||||
ext_int => '0', int_req => OPEN, pri_o => OPEN, pri_i => '1',
|
||||
po_a => OPEN, pi_a => x"FF", po_b => OPEN, pi_b => x"FF",
|
||||
load_a => load_a, load_d => load_d, load_wr => load_wr2,
|
||||
clk => clk, ce => ce, reset_na => reset_na);
|
||||
|
||||
-- CARTRIDGE
|
||||
i_psu5:ENTITY work.f8_psu
|
||||
GENERIC MAP (
|
||||
@ -348,27 +265,13 @@ BEGIN
|
||||
IVEC => x"FFFF", -- Not used
|
||||
ROM => INIT_ZERO)
|
||||
PORT MAP (
|
||||
dw => dr,
|
||||
dr => dr5,
|
||||
dv => dv5,
|
||||
romc => romc,
|
||||
tick => tick,
|
||||
phase => phase,
|
||||
ext_int => '0',
|
||||
int_req => OPEN,
|
||||
pri_o => OPEN,
|
||||
pri_i => '1',
|
||||
po_a => OPEN,
|
||||
pi_a => x"FF",
|
||||
po_b => OPEN,
|
||||
pi_b => x"FF",
|
||||
load_a => load_a,
|
||||
load_d => load_d,
|
||||
load_wr => load_wr3,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
reset_na => reset_na);
|
||||
|
||||
dw => dr, dr => dr5, dv => dv5,
|
||||
romc => romc, tick => tick, phase => phase,
|
||||
ext_int => '0', int_req => OPEN, pri_o => OPEN, pri_i => '1',
|
||||
po_a => OPEN, pi_a => x"FF", po_b => OPEN, pi_b => x"FF",
|
||||
load_a => load_a, load_d => load_d, load_wr => load_wr3,
|
||||
clk => clk, ce => ce, reset_na => reset_na);
|
||||
|
||||
dr <= dr0 WHEN dv0='1' ELSE
|
||||
dr1 WHEN dv1='1' ELSE
|
||||
dr2 WHEN dv2='1' ELSE
|
||||
@ -376,10 +279,10 @@ BEGIN
|
||||
dr4 WHEN dv4='1' ELSE
|
||||
dr5 WHEN dv5='1' ELSE
|
||||
dw_cpu;
|
||||
|
||||
----------------------------------------------------------
|
||||
|
||||
----------------------------------------------------------
|
||||
-- CARTRIDGE LOAD
|
||||
|
||||
|
||||
PROCESS (clk) IS
|
||||
BEGIN
|
||||
IF rising_edge(clk) THEN
|
||||
@ -392,16 +295,16 @@ BEGIN
|
||||
ioctl_wait<='0';
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
rdena<=NOT po0(6);
|
||||
|
||||
|
||||
----------------------------------------------------------
|
||||
-- VIDEO
|
||||
vram_h <= to_integer(NOT po4(6 DOWNTO 0));
|
||||
vram_v <= to_integer(NOT po5(5 DOWNTO 0));
|
||||
vram_dw<= NOT po1(7 DOWNTO 6);
|
||||
vram_wr<= po0(5);
|
||||
|
||||
|
||||
vram_a <= vram_h + vram_v * 128;
|
||||
|
||||
PROCESS(clk) IS
|
||||
@ -418,7 +321,7 @@ BEGIN
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
-- VIDEO SWEEP
|
||||
PROCESS (clk) IS
|
||||
BEGIN
|
||||
@ -436,52 +339,52 @@ BEGIN
|
||||
pos<=((vpos/4) MOD 64) * 128 + ((hpos/2) MOD 128);
|
||||
vposp<=vpos;
|
||||
hposp<=hpos;
|
||||
|
||||
|
||||
pix <=vram(pos);
|
||||
p125<=v125((vposp/4) MOD 64);
|
||||
p126<=v126((vposp/4) MOD 64);
|
||||
|
||||
|
||||
vga_r<=std_logic_vector(PAL_R(CMAP(to_integer(p125 & p126 & pix))));
|
||||
vga_g<=std_logic_vector(PAL_G(CMAP(to_integer(p125 & p126 & pix))));
|
||||
vga_b<=std_logic_vector(PAL_B(CMAP(to_integer(p125 & p126 & pix))));
|
||||
vga_de<=to_std_logic(vposp<=VDISP AND hposp<HDISP);
|
||||
|
||||
|
||||
vga_hs<=to_std_logic(hposp>=HSYNCSTART AND hposp<=HSYNCEND);
|
||||
vga_vs<=to_std_logic(vposp>=VSYNCSTART AND vposp<=VSYNCEND);
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
vga_clk<=clk;
|
||||
vga_ce<=ce;
|
||||
|
||||
|
||||
-- 128 x 64 pixels => 102 x 58 visible => 95 x 58 visible
|
||||
-- CPU : F video / 2
|
||||
-- 1.7897725MHz (NTSC)
|
||||
-- 2.0000000MHz (PAL GEN 1)
|
||||
-- 1.7734475MHz (PAL GEN 2)
|
||||
|
||||
|
||||
----------------------------------------------------------
|
||||
-- Joysticks / Buttons
|
||||
pi0(7 DOWNTO 4)<=po0(7 DOWNTO 4);
|
||||
pi0(0) <= NOT Keys(0); -- TIME
|
||||
pi0(1) <= NOT Keys(1); -- MODE
|
||||
pi0(2) <= NOT Keys(2); -- HOLD
|
||||
pi0(3) <= NOT Keys(3); -- START
|
||||
|
||||
pi1i(7) <= NOT joystick_0(4); -- RIGHT G.DOWN
|
||||
pi1i(6) <= NOT joystick_0(5); -- RIGHT G.UP
|
||||
pi1i(5) <= NOT joystick_0(6); -- RIGHT CW
|
||||
pi1i(4) <= NOT joystick_0(7); -- RIGHT CCW
|
||||
pi0(0) <= NOT (joystick_0(4) OR joystick_1(4)); -- TIME
|
||||
pi0(1) <= NOT (joystick_0(5) OR joystick_1(5)); -- MODE
|
||||
pi0(2) <= NOT (joystick_0(6) OR joystick_1(6)); -- HOLD
|
||||
pi0(3) <= NOT (joystick_0(7) OR joystick_1(7)); -- START
|
||||
|
||||
pi1i(7) <= NOT joystick_0(8); -- RIGHT G.DOWN
|
||||
pi1i(6) <= NOT joystick_0(9); -- RIGHT G.UP
|
||||
pi1i(5) <= NOT joystick_0(10); -- RIGHT CW
|
||||
pi1i(4) <= NOT joystick_0(11); -- RIGHT CCW
|
||||
pi1i(3) <= NOT joystick_0(3); -- RIGHT UP
|
||||
pi1i(2) <= NOT joystick_0(2); -- RIGHT DOWN
|
||||
pi1i(1) <= NOT joystick_0(1); -- RIGHT LEFT
|
||||
pi1i(0) <= NOT joystick_0(0); -- RIGHT RIGHT
|
||||
|
||||
pi4i(7) <= NOT joystick_1(4); -- LEFT G.DOWN
|
||||
pi4i(6) <= NOT joystick_1(5); -- LEFT G.UP
|
||||
pi4i(5) <= NOT joystick_1(6); -- LEFT CW
|
||||
pi4i(4) <= NOT joystick_1(7); -- LEFT CCW
|
||||
|
||||
pi4i(7) <= NOT joystick_1(8); -- LEFT G.DOWN
|
||||
pi4i(6) <= NOT joystick_1(9); -- LEFT G.UP
|
||||
pi4i(5) <= NOT joystick_1(10); -- LEFT CW
|
||||
pi4i(4) <= NOT joystick_1(11); -- LEFT CCW
|
||||
pi4i(3) <= NOT joystick_1(3); -- LEFT UP
|
||||
pi4i(2) <= NOT joystick_1(2); -- LEFT DOWN
|
||||
pi4i(1) <= NOT joystick_1(1); -- LEFT LEFT
|
||||
@ -489,16 +392,16 @@ BEGIN
|
||||
|
||||
pi1<=pi1i OR po1 WHEN rdena='1' ELSE po1;
|
||||
pi4<=pi4i OR po4 WHEN rdena='1' ELSE po4;
|
||||
|
||||
|
||||
pi5<=po5;
|
||||
|
||||
|
||||
----------------------------------------------------------
|
||||
-- Audio
|
||||
-- 00 : Silence
|
||||
-- 01 : 1kHz
|
||||
-- 10 : 500Hz
|
||||
-- 11 : 120Hz
|
||||
|
||||
|
||||
tone <=po5(7 DOWNTO 6);
|
||||
PROCESS (clk) IS
|
||||
VARIABLE s_v : std_logic;
|
||||
@ -511,13 +414,76 @@ BEGIN
|
||||
WHEN "10" => s_v:=vdiv(9);
|
||||
WHEN OTHERS => s_v:=vdiv(7);
|
||||
END CASE;
|
||||
audio<=(OTHERS =>s_v);
|
||||
audio_l<=(OTHERS =>s_v);
|
||||
audio_r<=(OTHERS =>s_v);
|
||||
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
----------------------------------------------------------
|
||||
areset_na<=NOT reset AND pll_locked AND NOT ioctl_download;
|
||||
vreset_na<=x"0000" WHEN areset_na='0' ELSE
|
||||
'1' & vreset_na(0 TO 14) WHEN rising_edge(clk);
|
||||
reset_na<=vreset_na(15);
|
||||
|
||||
|
||||
----------------------------------------------------------
|
||||
--pragma synthesis_off
|
||||
PROCESS IS
|
||||
FILE fil : text OPEN write_mode IS "cpu.log";
|
||||
VARIABLE char_v : character;
|
||||
VARIABLE lin : line;
|
||||
VARIABLE op : uv8;
|
||||
BEGIN
|
||||
wure(clk,10);
|
||||
LOOP
|
||||
wure(clk);
|
||||
IF phase=4 AND romc=0 THEN
|
||||
write(lin,to_hstring(pc0));
|
||||
write(lin,string'(" : "));
|
||||
write(lin,to_hstring(dr));
|
||||
op:=dr;
|
||||
IF ILEN(to_integer(dr))=1 THEN
|
||||
write(lin,string'(" .. .. : "));
|
||||
ELSIF ILEN(to_integer(dr))=2 THEN
|
||||
wure(clk);
|
||||
LOOP
|
||||
wure(clk);
|
||||
EXIT WHEN phase=4 AND (romc=0 OR romc=1 OR romc=3 OR romc=12 OR romc=14);
|
||||
END LOOP;
|
||||
write(lin,string'(" "));
|
||||
write(lin,to_hstring(dr));
|
||||
write(lin,string'(" .. : "));
|
||||
ELSIF ILEN(to_integer(dr))=3 THEN
|
||||
wure(clk);
|
||||
LOOP
|
||||
wure(clk);
|
||||
EXIT WHEN phase=4 AND (romc=0 OR romc=1 OR romc=3 OR romc=12 OR romc=14);
|
||||
END LOOP;
|
||||
write(lin,string'(" "));
|
||||
write(lin,to_hstring(dr));
|
||||
wure(clk);
|
||||
LOOP
|
||||
wure(clk);
|
||||
EXIT WHEN phase=4 AND (romc=0 OR romc=1 OR romc=3 OR romc=12 OR romc=14);
|
||||
END LOOP;
|
||||
write(lin,string'(" "));
|
||||
write(lin,to_hstring(dr));
|
||||
write(lin,string'(" : "));
|
||||
END IF;
|
||||
write(lin,OPTXT(to_integer(op)));
|
||||
write(lin,string'(" DC0=") & to_hstring(dc0));
|
||||
write(lin,string'(" PC1=") & to_hstring(pc1));
|
||||
write(lin,string'(" ACC=") & to_hstring(acc));
|
||||
write(lin,string'(" ISAR=") & to_hstring("00" & visar));
|
||||
write(lin,string'(" "));
|
||||
write(lin,now);
|
||||
writeline(fil,lin);
|
||||
END IF;
|
||||
END LOOP;
|
||||
WAIT;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
--pragma synthesis_on
|
||||
|
||||
END struct;
|
||||
@ -20,7 +20,7 @@ ENTITY f8_cpu IS
|
||||
dr : IN uv8; -- Data Read
|
||||
dw : OUT uv8; -- Data Write / Address
|
||||
dv : OUT std_logic;
|
||||
|
||||
|
||||
romc : OUT uv5;
|
||||
tick : OUT std_logic; -- 1/4 or 1/6 cycle lenght
|
||||
phase : OUT uint4;
|
||||
@ -29,7 +29,7 @@ ENTITY f8_cpu IS
|
||||
pi_a : IN uv8;
|
||||
po_b : OUT uv8;
|
||||
pi_b : IN uv8;
|
||||
|
||||
|
||||
clk : IN std_logic;
|
||||
ce : IN std_logic;
|
||||
reset_na : IN std_logic;
|
||||
@ -49,40 +49,40 @@ ARCHITECTURE rtl OF f8_cpu IS
|
||||
SIGNAL acc : uv8;
|
||||
SIGNAL visar : uv6;
|
||||
ALIAS visarl : uv3 IS visar(2 DOWNTO 0);
|
||||
|
||||
|
||||
SIGNAL rs,rd : uint6;
|
||||
SIGNAL scratch_regs : arr_uv8(0 TO 63); -- Scratch regs
|
||||
SIGNAL sreg_ra,sreg_wa : uint6;
|
||||
SIGNAL sreg_rd,sreg_wd : uv8;
|
||||
SIGNAL sreg_wr : std_logic;
|
||||
|
||||
|
||||
SIGNAL iozcs : uv5;
|
||||
|
||||
|
||||
SIGNAL op : enum_op;
|
||||
|
||||
|
||||
SIGNAL poa_l,pob_l : uv8;
|
||||
SIGNAL alu : uv8;
|
||||
SIGNAL test,bcc,testp,bccp,dstm : std_logic;
|
||||
|
||||
SIGNAL txt : string(1 TO 12);
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
phase<=phase_l;
|
||||
po_a<=poa_l;
|
||||
po_b<=pob_l;
|
||||
|
||||
|
||||
----------------------------------------------------------
|
||||
romc<=ROMC_01 WHEN (bcc='1' AND test='1') OR
|
||||
(opcode=x"8F" AND isarl/=7 AND mop.romc=ROMC_03) ELSE
|
||||
ROMC_03 WHEN (bcc='1' AND test='0') OR
|
||||
(opcode=x"8F" AND isarl=7 AND mop.romc=ROMC_03) ELSE
|
||||
mop.romc;
|
||||
|
||||
|
||||
sreg_ra<=mop.rs WHEN mop.rs<16 ELSE
|
||||
mop.rd WHEN mop.rd<16 ELSE
|
||||
to_integer(visar);
|
||||
|
||||
|
||||
sreg_rd<=scratch_regs(sreg_ra) WHEN rising_edge(clk);
|
||||
|
||||
PROCESS(clk) IS
|
||||
@ -93,7 +93,7 @@ BEGIN
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
----------------------------------------------------------
|
||||
PROCESS(clk,reset_na) IS
|
||||
VARIABLE len_v : enum_len;
|
||||
@ -105,7 +105,7 @@ BEGIN
|
||||
IF ce='1' THEN
|
||||
mop<=MICROCODE(madrs);
|
||||
sreg_wr<='0';
|
||||
|
||||
|
||||
-----------------------------------------
|
||||
len_v:=mop.len;
|
||||
IF (bcc='1' AND test='1') OR (opcode=x"8F" AND visarl=7) THEN
|
||||
@ -115,7 +115,7 @@ BEGIN
|
||||
ELSE
|
||||
len_v:=mop.len;
|
||||
END IF;
|
||||
|
||||
|
||||
IF phase_l=7 AND len_v=S THEN
|
||||
phase_l<=0;
|
||||
ELSIF phase_l=11 AND len_v=L THEN
|
||||
@ -123,18 +123,18 @@ BEGIN
|
||||
ELSE
|
||||
phase_l<=phase_l+1;
|
||||
END IF;
|
||||
|
||||
|
||||
-----------------------------------------
|
||||
CASE phase_l IS
|
||||
WHEN 0 =>
|
||||
test<=testp;
|
||||
bcc<=bccp;
|
||||
|
||||
|
||||
WHEN 1 =>
|
||||
NULL;
|
||||
WHEN 2 =>
|
||||
NULL; -- <dw :=> <AVOIR>
|
||||
|
||||
|
||||
WHEN 3 =>
|
||||
CASE mop.rd IS
|
||||
WHEN RACC => rs1_v:=acc;
|
||||
@ -166,14 +166,14 @@ BEGIN
|
||||
WHEN OTHERS =>
|
||||
rs2_v:=acc;
|
||||
END CASE;
|
||||
|
||||
|
||||
aluop(mop.op,opcode,rs1_v,rs2_v,iozcs,rd_v,dstm_v,iozcs_v,test_v);
|
||||
dstm<=dstm_v;
|
||||
iozcs<=iozcs_v;
|
||||
alu<=rd_v;
|
||||
testp<=test_v;
|
||||
bccp <=to_std_logic(mop.op=OP_TST8 OR mop.op=OP_TST9);
|
||||
|
||||
|
||||
WHEN 4 =>
|
||||
dv<='0';
|
||||
IF dstm='1' THEN
|
||||
@ -200,7 +200,7 @@ BEGIN
|
||||
WHEN OTHERS => NULL;
|
||||
END CASE;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN 5 =>
|
||||
IF mop.rs=RISARP OR mop.rd=RISARP THEN
|
||||
visar(2 DOWNTO 0)<=visar(2 DOWNTO 0)+1;
|
||||
@ -208,7 +208,7 @@ BEGIN
|
||||
IF mop.rs=RISARM OR mop.rd=RISARM THEN
|
||||
visar(2 DOWNTO 0)<=visar(2 DOWNTO 0)-1;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN 7 =>
|
||||
IF len_v=S THEN
|
||||
IF mop.romc=ROMC_00 THEN -- IFETCH
|
||||
@ -219,7 +219,7 @@ BEGIN
|
||||
madrs<=madrs+1;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN 11 =>
|
||||
IF len_v=L THEN
|
||||
IF mop.romc=ROMC_00 THEN -- IFETCH
|
||||
@ -230,12 +230,12 @@ BEGIN
|
||||
madrs<=madrs+1;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN OTHERS =>
|
||||
NULL;
|
||||
|
||||
END CASE;
|
||||
|
||||
|
||||
IF reset_na='0' THEN
|
||||
opcode<=OP_RESET;
|
||||
txt<=OPTXT(to_integer(OP_RESET));
|
||||
@ -243,7 +243,7 @@ BEGIN
|
||||
phase_l<=0;
|
||||
iozcs<="00000";
|
||||
END IF;
|
||||
|
||||
|
||||
END IF;
|
||||
|
||||
END IF;
|
||||
@ -252,6 +252,5 @@ BEGIN
|
||||
acco<=acc;
|
||||
visaro<=visar;
|
||||
iozcso<=iozcs;
|
||||
|
||||
END ARCHITECTURE rtl;
|
||||
|
||||
END ARCHITECTURE rtl;
|
||||
@ -40,7 +40,7 @@ PACKAGE f8_pack IS
|
||||
dstm : OUT std_logic; -- Modified result reg
|
||||
iozcs_o : OUT uv5; -- Flags after
|
||||
test : OUT std_logic); -- Contitional branch test result
|
||||
|
||||
|
||||
--------------------------------------
|
||||
CONSTANT R0 : uint5 := 0;
|
||||
CONSTANT R1 : uint5 := 1;
|
||||
@ -656,7 +656,7 @@ PACKAGE f8_pack IS
|
||||
"AND R4 ", "AND R5 ", "AND R6 ", "AND R7 ",
|
||||
"AND R8 ", "AND R9 ", "AND R10 ", "AND R11 ",
|
||||
"AND (ISAR) ", "AND (ISAR+) ", "AND (ISAR-) ", "Invalid ");
|
||||
|
||||
|
||||
TYPE arr_ilen IS ARRAY(natural RANGE <>) OF uint3;
|
||||
CONSTANT ILEN : arr_ilen(0 TO 255) :=(
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, --00
|
||||
@ -675,7 +675,7 @@ PACKAGE f8_pack IS
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,0, --D0
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,0, --E0
|
||||
1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,0); --F0
|
||||
|
||||
|
||||
END PACKAGE;
|
||||
|
||||
--##############################################################################
|
||||
@ -831,7 +831,7 @@ PACKAGE BODY f8_pack IS
|
||||
iozcs_o(3):=(src1(7) XOR dst9_v(7)) AND (NOT dst9_v(7));
|
||||
dstm:='1';
|
||||
dst_v:=dst9_v(7 DOWNTO 0);
|
||||
|
||||
|
||||
WHEN OP_SL1 => -- SHIFT LEFT 1
|
||||
dst_v:=src1(6 DOWNTO 0) & '0';
|
||||
iozcs_o(0):=NOT dst_v(7);
|
||||
@ -917,4 +917,4 @@ PACKAGE BODY f8_pack IS
|
||||
END PROCEDURE;
|
||||
|
||||
|
||||
END PACKAGE BODY;
|
||||
END PACKAGE BODY;
|
||||
@ -38,31 +38,31 @@ ENTITY f8_psu IS
|
||||
dw : IN uv8; -- Data Write
|
||||
dr : OUT uv8; -- Data Read
|
||||
dv : OUT std_logic;
|
||||
|
||||
|
||||
romc : IN uv5;
|
||||
tick : IN std_logic; -- 1/8 or 1/12 cycle length
|
||||
phase : IN uint4;
|
||||
|
||||
ext_int : IN std_logic;
|
||||
int_req : OUT std_logic;
|
||||
|
||||
|
||||
pri_o : OUT std_logic;
|
||||
pri_i : IN std_logic;
|
||||
|
||||
|
||||
po_a : OUT uv8; -- IO port A
|
||||
pi_a : IN uv8;
|
||||
|
||||
|
||||
po_b : OUT uv8; -- IO port B
|
||||
pi_b : IN uv8;
|
||||
|
||||
|
||||
load_a : IN uv10;
|
||||
load_d : IN uv8;
|
||||
load_wr : IN std_logic;
|
||||
|
||||
|
||||
clk : IN std_logic;
|
||||
ce : IN std_logic;
|
||||
reset_na : IN std_logic;
|
||||
|
||||
|
||||
pc0o : OUT uv16;
|
||||
pc1o : OUT uv16;
|
||||
dc0o : OUT uv16
|
||||
@ -88,11 +88,11 @@ ARCHITECTURE rtl OF f8_psu IS
|
||||
SIGNAL ext_int_d,tim_int_d,tim_int : std_logic;
|
||||
SIGNAL inta,inta_set,inta_clr : std_logic;
|
||||
SIGNAL int_req_l : std_logic;
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
mem_a<=dc0 WHEN romc="00010" OR romc="00101" ELSE pc0;
|
||||
|
||||
|
||||
----------------------------------------------------------
|
||||
-- ROMC BUS
|
||||
PROCESS(clk,reset_na) IS
|
||||
@ -108,9 +108,9 @@ BEGIN
|
||||
IF phase=2 THEN
|
||||
dv<='0';
|
||||
END IF;
|
||||
|
||||
|
||||
io_wr<='0';
|
||||
|
||||
|
||||
CASE romc IS
|
||||
WHEN "00000" =>
|
||||
-- S,L : Instruction fetch. The device whose address space includes
|
||||
@ -124,7 +124,7 @@ BEGIN
|
||||
IF phase=6 THEN
|
||||
pc0<= pc0 + 1;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "00001" =>
|
||||
-- L : The device whose address space includes the contents of
|
||||
-- the PC0 register must place on the data bus the contents of
|
||||
@ -137,7 +137,7 @@ BEGIN
|
||||
IF phase=6 THEN
|
||||
pc0<= pc0 + sext(dw,16);
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "00010" =>
|
||||
-- L : The device whose DC0 addresses a memory word within the
|
||||
-- address space of that device must place on the data bus the
|
||||
@ -150,7 +150,7 @@ BEGIN
|
||||
IF phase=6 THEN
|
||||
dc0<= dc0 + 1;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "00011" =>
|
||||
-- L,S : Similar to 00, except that it is used for Immediate Operand
|
||||
-- fetches (using PC0) instead of instruction fetches.
|
||||
@ -162,13 +162,13 @@ BEGIN
|
||||
pc0<= pc0 + 1;
|
||||
io_port<=dw;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "00100" =>
|
||||
-- S : Copy the contents of PC1 into PC0.
|
||||
IF phase=6 THEN
|
||||
pc0<= pc1;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "00101" =>
|
||||
-- L : Store the data bus contents into the memory
|
||||
-- location pointed to by DC0. Increment DC0.
|
||||
@ -180,21 +180,21 @@ BEGIN
|
||||
--IF phase=6 THEN
|
||||
-- dc0<=dc0 + 1;
|
||||
--END IF;
|
||||
|
||||
|
||||
WHEN "00110" =>
|
||||
-- L : Place the high order byte of DC0 on the data bus.
|
||||
IF phase=2 THEN
|
||||
dr <=dc0(15 DOWNTO 8);
|
||||
dv <='1';
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "00111" =>
|
||||
-- L : Place the high order byte of PC1 on the data bus.
|
||||
IF phase=2 THEN
|
||||
dr <=pc1(15 DOWNTO 8);
|
||||
dv <='1';
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "01000" =>
|
||||
-- L : All devices copy the contents of PC0 into PC1. The CPU
|
||||
-- outputs zero on the data bus in this ROMC state. Load the
|
||||
@ -203,7 +203,7 @@ BEGIN
|
||||
pc1<=pc0;
|
||||
pc0<=x"0000";
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "01001" =>
|
||||
-- The device whose address space includes the contents of the DC0
|
||||
-- register must place the low order byte of DC0 onto the data bus.
|
||||
@ -211,14 +211,14 @@ BEGIN
|
||||
dr <=dc0(7 DOWNTO 0);
|
||||
dv <=pchk(dc0);
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "01010" =>
|
||||
-- L : All devices add the 8-bit value on the data bus, treated
|
||||
-- as a signed binary number, to the Data Counter.
|
||||
IF phase=6 THEN
|
||||
dc0<=dc0 + sext(dw,16);
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "01011" =>
|
||||
-- L : The device whose address space includes the value in PC1
|
||||
-- must place the low order byte of PC1 on the data bus.
|
||||
@ -226,7 +226,7 @@ BEGIN
|
||||
dr <=pc1(7 DOWNTO 0);
|
||||
dv <=pchk(pc1);
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "01100" =>
|
||||
-- L : The device whose address space includes the contents of
|
||||
-- the PC0 register must place the contents of the memory word
|
||||
@ -240,12 +240,12 @@ BEGIN
|
||||
IF phase=6 THEN
|
||||
pc0(7 DOWNTO 0)<= dw;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "01101" =>
|
||||
-- S : All devices store in PC1 the current contents of PC0,
|
||||
-- incremented by 1. PC0 is unaltered.
|
||||
pc1 <= pc0 +1;
|
||||
|
||||
|
||||
WHEN "01110" =>
|
||||
-- L : The device whose address space includes the contents of
|
||||
-- PC0 must place the contents of the word addressed by PC0
|
||||
@ -258,7 +258,7 @@ BEGIN
|
||||
IF phase=6 THEN
|
||||
dc0(7 DOWNTO 0)<= dw;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "01111" =>
|
||||
-- L : The interrupting device with highest priority must place
|
||||
-- the low order byte of the interrupt vector on the data bus.
|
||||
@ -273,11 +273,11 @@ BEGIN
|
||||
pc1 <= pc0;
|
||||
pc0(7 DOWNTO 0) <= dw;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "10000" =>
|
||||
-- L : Inhibit any modification to the interrupt priority logic.
|
||||
-- <TODO>
|
||||
|
||||
|
||||
WHEN "10001" =>
|
||||
-- L : The device whose memory space includes the contents of
|
||||
-- PC0 must place the contents of the addressed memory word
|
||||
@ -290,7 +290,7 @@ BEGIN
|
||||
IF phase=6 THEN
|
||||
dc0(15 DOWNTO 8)<=dw;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "10010" =>
|
||||
-- L : All devices copy the contents of PC0 into PC1. All
|
||||
-- devices then move the contents of the data bus into
|
||||
@ -299,7 +299,7 @@ BEGIN
|
||||
pc1<=pc0;
|
||||
pc0(7 DOWNTO 0)<=dw;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "10011" =>
|
||||
-- L : The interrupting device with highest priority must move
|
||||
-- the high order half of the interrupt vector onto the data bus.
|
||||
@ -315,49 +315,49 @@ BEGIN
|
||||
pc0(15 DOWNTO 8) <= dw;
|
||||
inta_clr<=int_req_l;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "10100" =>
|
||||
-- L : All devices move the contents of the data bus into the
|
||||
-- high order byte of PC0.
|
||||
IF phase=6 THEN
|
||||
pc0(15 DOWNTO 8)<=dw;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "10101" =>
|
||||
-- L : All devices move contents of the data bus into the
|
||||
-- high order byte of PC1.
|
||||
IF phase=6 THEN
|
||||
pc1(15 DOWNTO 8)<=dw;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "10110" =>
|
||||
-- L : All devices move the contents of the data bus into the
|
||||
-- high order byte of DC0.
|
||||
IF phase=6 THEN
|
||||
dc0(15 DOWNTO 8)<=dw;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "10111" =>
|
||||
-- L : All devices move the contents of the data bus into the
|
||||
-- low order byte of PC0.
|
||||
IF phase=6 THEN
|
||||
pc0(7 DOWNTO 0)<=dw;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "11000" =>
|
||||
-- L : All devices move contents of the data bus into the low
|
||||
-- order byte of PC1.
|
||||
IF phase=6 THEN
|
||||
pc1(7 DOWNTO 0)<=dw;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "11001" =>
|
||||
-- L : All devices move contents of the data bus into the low
|
||||
-- order byte of DC0.
|
||||
IF phase=6 THEN
|
||||
dc0(7 DOWNTO 0)<=dw;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "11010" =>
|
||||
-- L : During the prior cycle an I/O port timer or interrupt
|
||||
-- control register was addressed, The device containing
|
||||
@ -367,7 +367,7 @@ BEGIN
|
||||
io_dw<=dw;
|
||||
io_wr<=to_std_logic(io_port(7 DOWNTO 2)=IOPAGE);
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "11011" =>
|
||||
-- L : During the prior cycle the data bus specified the
|
||||
-- address of an I/O port. The device containing the
|
||||
@ -380,13 +380,13 @@ BEGIN
|
||||
dr<=io_dr;
|
||||
dv<=to_std_logic(io_port(7 DOWNTO 2)=IOPAGE);
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "11100" =>
|
||||
-- L/S : None. Before IO port access
|
||||
IF phase=6 THEN
|
||||
io_port<=dw;
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "11101" =>
|
||||
-- S : Devices with DC0 and DC1 registers must switch registers.
|
||||
-- Devices without a DC1 register perform no operation.
|
||||
@ -394,7 +394,7 @@ BEGIN
|
||||
-- dc0<=dc1;
|
||||
-- dc1<=dc0;
|
||||
--END IF;
|
||||
|
||||
|
||||
WHEN "11110" =>
|
||||
-- L : The device whose address space includes the contents of
|
||||
-- PC0 must place the low order byte of PC0 onto the data bus.
|
||||
@ -402,7 +402,7 @@ BEGIN
|
||||
dr <=pc0(7 DOWNTO 0);
|
||||
dv <=pchk(pc0);
|
||||
END IF;
|
||||
|
||||
|
||||
WHEN "11111" =>
|
||||
-- L : The device whose address space includes the contents of
|
||||
-- PC0 must place the high order byte of PC0 on the data bus.
|
||||
@ -413,9 +413,9 @@ BEGIN
|
||||
|
||||
WHEN OTHERS =>
|
||||
NULL;
|
||||
|
||||
|
||||
END CASE;
|
||||
|
||||
|
||||
IF reset_na='0' THEN
|
||||
pc0<=x"0000";
|
||||
pc1<=x"0000";
|
||||
@ -440,14 +440,14 @@ BEGIN
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
----------------------------------------------------------
|
||||
-- IO PORTS
|
||||
|
||||
po_a<=po_a_l;
|
||||
po_b<=po_b_l;
|
||||
int_req<=int_req_l;
|
||||
|
||||
|
||||
PROCESS(clk,reset_na) IS
|
||||
BEGIN
|
||||
IF rising_edge(clk) THEN
|
||||
@ -461,18 +461,18 @@ BEGIN
|
||||
END IF;
|
||||
tim_int<=to_std_logic(tim=x"FE");
|
||||
tim_int_d<=tim_int;
|
||||
|
||||
|
||||
-- Interrupts
|
||||
ext_int_d<=ext_int;
|
||||
|
||||
|
||||
inta_set<=(NOT ext_int_d AND ext_int AND to_std_logic(icr="01")) OR
|
||||
(NOT tim_int_d AND tim_int AND to_std_logic(icr="11"));
|
||||
|
||||
|
||||
inta <=(inta OR inta_set) AND NOT inta_clr;
|
||||
|
||||
|
||||
int_req_l<=inta AND pri_i;
|
||||
pri_o<=pri_i AND NOT inta;
|
||||
|
||||
|
||||
-------------------------------
|
||||
CASE io_port(1 DOWNTO 0) IS
|
||||
WHEN "00" => -- IO PORT A READ
|
||||
@ -484,7 +484,7 @@ BEGIN
|
||||
WHEN OTHERS => -- Timer
|
||||
io_dr<=x"00"; -- <TBD>
|
||||
END CASE;
|
||||
|
||||
|
||||
IF io_wr='1' THEN
|
||||
CASE io_port(1 DOWNTO 0) IS
|
||||
WHEN "00" => po_a_l<=io_dw;
|
||||
@ -506,5 +506,5 @@ BEGIN
|
||||
pc0o<=pc0;
|
||||
pc1o<=pc1;
|
||||
dc0o<=dc0;
|
||||
|
||||
END ARCHITECTURE rtl;
|
||||
|
||||
END ARCHITECTURE rtl;
|
||||
4
Console_MiST/ChannelF_MiST/rtl/pll.qip
Normal file
4
Console_MiST/ChannelF_MiST/rtl/pll.qip
Normal file
@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
||||
@ -40,26 +40,30 @@ module pll (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
locked);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output c2;
|
||||
output locked;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire [0:0] sub_wire7 = 1'h0;
|
||||
wire [2:2] sub_wire4 = sub_wire0[2:2];
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
wire c2 = sub_wire4;
|
||||
wire sub_wire5 = inclk0;
|
||||
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire5),
|
||||
.inclk (sub_wire6),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.activeclock (),
|
||||
@ -106,6 +110,10 @@ module pll (
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 53,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.clk2_divide_by = 715,
|
||||
altpll_component.clk2_duty_cycle = 50,
|
||||
altpll_component.clk2_multiply_by = 106,
|
||||
altpll_component.clk2_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
@ -140,7 +148,7 @@ module pll (
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk2 = "PORT_USED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
@ -181,10 +189,13 @@ endmodule
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "50"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "400"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "715"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.620001"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "3.577500"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "4.002797"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
@ -206,25 +217,33 @@ endmodule
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "53"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "53"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "106"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.63636000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "3.57954500"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "4.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
@ -248,13 +267,16 @@ endmodule
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
@ -267,6 +289,10 @@ endmodule
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "53"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "715"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "106"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
@ -300,7 +326,7 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
@ -319,12 +345,14 @@ endmodule
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
|
||||
@ -137,4 +137,4 @@ PACKAGE rom_pack IS
|
||||
x"10",x"20",x"40",x"40",x"08",x"10",x"20",x"40",x"80",x"00",x"18",x"20",x"C0",x"00",x"00",x"C0",
|
||||
x"20",x"18",x"00",x"80",x"40",x"20",x"10",x"08",x"40",x"40",x"20",x"10",x"10",x"00",x"00",x"00");
|
||||
|
||||
END PACKAGE;
|
||||
END PACKAGE;
|
||||
Loading…
x
Reference in New Issue
Block a user