mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-20 17:47:33 +00:00
Spy Hunter: update CTC, use common inputs
This commit is contained in:
parent
0f982bbfc6
commit
45697c5ce6
@ -13,9 +13,9 @@ down down : Decelerate
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left left : Left
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right right : Right
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ESC : Coin
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start TAB : VAN
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Y Z : Shift
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X shift left : Oil
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start TAB,LShift : VAN
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Y X : Shift
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X Z : Oil
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C ctrl left : Smoke
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B alt left : Missle
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A Space : Gun
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@ -41,7 +41,7 @@
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# ========================
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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# Pin & Location Assignments
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@ -225,8 +225,6 @@ set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/SpyHunter_MiST.sv
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set_global_assignment -name VHDL_FILE rtl/spy_hunter.vhd
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set_global_assignment -name VHDL_FILE rtl/ctc_counter.vhd
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set_global_assignment -name VHDL_FILE rtl/ctc_controler.vhd
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set_global_assignment -name VHDL_FILE rtl/spy_hunter_sound_board.vhd
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set_global_assignment -name VHDL_FILE rtl/spy_hunter_control.vhd
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set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
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@ -239,6 +237,7 @@ set_global_assignment -name VHDL_FILE rtl/rom/midssio_82s123.vhd
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
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set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
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set_global_assignment -name VHDL_FILE rtl/cheap_squeak_deluxe.vhd
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set_global_assignment -name QIP_FILE ../../../common/IO/Z80CTC/z80ctc.qip
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set_global_assignment -name VHDL_FILE ../../../common/IO/pia6821.vhd
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set_global_assignment -name QIP_FILE ../../../common/CPU/68000/FX68k/fx68k.qip
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set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
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@ -58,6 +58,12 @@ localparam CONF_STR = {
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"V,v1.1.",`BUILD_DATE
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};
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wire rotate = status[2];
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wire blend = status[5];
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wire service = status[6];
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wire demosnd = status[8];
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wire lamps = status[9];
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assign LED = ~ioctl_downl;
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assign SDRAM_CLK = clk_mem;
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assign SDRAM_CKE = 1;
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@ -84,6 +90,10 @@ wire [9:0] csd_audio;
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wire hs, vs, cs;
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wire blankn;
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wire [2:0] g, r, b;
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wire key_pressed;
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wire [7:0] key_code;
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wire key_strobe;
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wire [15:0] rom_addr;
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wire [15:0] rom_do;
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wire [12:0] snd_addr;
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@ -97,8 +107,6 @@ wire [7:0] ioctl_index;
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wire ioctl_wr;
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wire [24:0] ioctl_addr;
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wire [7:0] ioctl_dout;
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wire [7:0] steering;
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wire [7:0] gas;
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data_io data_io(
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.clk_sys ( clk_sys ),
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@ -217,24 +225,24 @@ spy_hunter spy_hunter(
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.video_vs(vs),
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.video_csync(cs),
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.tv15Khz_mode(scandoublerD),
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.separate_audio(1'b0),
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.separate_audio(1'b1),
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.audio_out_l(audio_l),
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.audio_out_r(audio_r),
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.csd_audio_out(csd_audio),
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.coin1(btn_coin),
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.coin2(1'b0),
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.shift(m_shift),
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.oil(m_fire4),
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.missile(m_fire2),
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.van(m_van),
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.smoke(m_fire3),
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.gun(m_fire1),
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.coin1(m_coin1),
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.coin2(m_coin2),
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.shift(shift),
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.oil(oil),
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.missile(missile),
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.van(van),
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.smoke(smoke),
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.gun(gun),
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.steering(steering),
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.gas(gas),
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.timer(1),
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.show_lamps(status[9]),
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.demo_sound(status[8]),
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.service(status[6]),
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.show_lamps(lamps),
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.demo_sound(demosnd),
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.service(service),
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.cpu_rom_addr ( rom_addr ),
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.cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
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.snd_rom_addr ( snd_addr ),
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@ -265,9 +273,9 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
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.VGA_B ( VGA_B ),
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.VGA_VS ( vs_out ),
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.VGA_HS ( hs_out ),
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.rotate ( {1'b1,status[2]} ),
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.rotate ( { 1'b1, rotate } ),
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.ce_divider ( 1 ),
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.blend ( status[5] ),
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.blend ( blend ),
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.scandoubler_disable(1),//scandoublerD ),
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.no_csync ( 1'b1 ),
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.ypbpr ( ypbpr )
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@ -312,47 +320,40 @@ dac_r(
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.dac_o(AUDIO_R)
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);
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// Rotated Normal
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wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
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wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
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wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
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wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
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wire m_fire1 = btn_fire1 | joystick_0[4] | joystick_1[4]; // A
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wire m_fire2 = btn_fire2 | joystick_0[5] | joystick_1[5]; // B
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wire m_fire3 = btn_fire3 | joystick_0[6] | joystick_1[6]; // C (Select)
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wire m_fire4 = btn_fire4 | joystick_0[8] | joystick_1[8]; // X
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wire m_van = btn_van | joystick_0[7] | joystick_1[7]; // Start
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wire m_shift = btn_shift | joystick_0[9] | joystick_1[9]; // Y
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wire [7:0] steering;
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wire [7:0] gas;
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wire gun = m_fireA;
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wire missile = m_fireB;
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wire smoke = m_fireC;
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wire van = m_fireD | btn_van;
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wire oil = m_fireE;
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wire shift = m_fireF;
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wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
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wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
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wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
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arcade_inputs inputs (
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.clk ( clk_sys ),
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.key_strobe ( key_strobe ),
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.key_pressed ( key_pressed ),
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.key_code ( key_code ),
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.joystick_0 ( joystick_0 ),
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.joystick_1 ( joystick_1 ),
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.rotate ( rotate ),
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.orientation ( 2'b11 ),
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.joyswap ( 1'b0 ),
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.oneplayer ( 1'b1 ),
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.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
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.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
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.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
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);
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reg btn_shift = 0;
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reg btn_left = 0;
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reg btn_right = 0;
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reg btn_down = 0;
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reg btn_up = 0;
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reg btn_van = 0;
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reg btn_fire1 = 0;
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reg btn_fire2 = 0;
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reg btn_fire3 = 0;
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reg btn_fire4 = 0;
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reg btn_coin = 0;
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wire key_pressed;
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wire [7:0] key_code;
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wire key_strobe;
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always @(posedge clk_sys) begin
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if(key_strobe) begin
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case(key_code)
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'h75: btn_up <= key_pressed; // up
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'h72: btn_down <= key_pressed; // down
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'h6B: btn_left <= key_pressed; // left
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'h74: btn_right <= key_pressed; // right
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'h76: btn_coin <= key_pressed; // ESC
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'h0D: btn_van <= key_pressed; // TAB
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'h1A: btn_shift <= key_pressed; // Y 35
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'h12: btn_fire4 <= key_pressed; // shift left
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'h14: btn_fire3 <= key_pressed; // ctrl left
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'h11: btn_fire2 <= key_pressed; // alt left
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'h29: btn_fire1 <= key_pressed; // Space
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endcase
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end
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end
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@ -1,106 +0,0 @@
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---------------------------------------------------------------------------------
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-- Z80-CTC controler by Dar (darfpga@aol.fr) (19/10/2019)
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-- http://darfpga.blogspot.fr
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---------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity ctc_controler is
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port(
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clock : in std_logic;
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clock_ena : in std_logic;
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reset : in std_logic;
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d_in : in std_logic_vector( 7 downto 0);
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load_data : in std_logic;
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int_ack : in std_logic;
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int_pulse_0 : in std_logic;
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int_pulse_1 : in std_logic;
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int_pulse_2 : in std_logic;
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int_pulse_3 : in std_logic;
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d_out : out std_logic_vector( 7 downto 0);
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int_n : out std_logic
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);
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end ctc_controler;
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architecture struct of ctc_controler is
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signal int_vector : std_logic_vector(4 downto 0);
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signal wait_for_time_constant : std_logic;
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signal load_data_r : std_logic; -- make sure load_data toggles to get one new data
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signal int_reg_0 : std_logic;
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signal int_reg_1 : std_logic;
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signal int_reg_2 : std_logic;
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signal int_reg_3 : std_logic;
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signal int_ack_r : std_logic;
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begin
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int_n <= '0' when (int_reg_0 or int_reg_1 or int_reg_2 or int_reg_3) = '1' else '1';
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d_out <= int_vector & "000" when int_reg_0 = '1' else
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int_vector & "010" when int_reg_1 = '1' else
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int_vector & "100" when int_reg_2 = '1' else
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int_vector & "110" when int_reg_3 = '1' else (others => '0');
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process (reset, clock)
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begin
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if reset = '1' then -- hardware and software reset
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wait_for_time_constant <= '0';
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int_reg_0 <= '0';
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int_reg_1 <= '0';
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int_reg_2 <= '0';
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int_reg_3 <= '0';
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load_data_r <= load_data;
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int_vector <= (others => '0');
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else
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if rising_edge(clock) then
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if clock_ena = '1' then
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load_data_r <= load_data;
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int_ack_r <= int_ack;
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if load_data = '1' and load_data_r = '0' then
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if wait_for_time_constant = '1' then
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wait_for_time_constant <= '0';
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else
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if d_in(0) = '1' then -- check if its a control world
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wait_for_time_constant <= d_in(2);
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-- if d_in(1) = '1' then -- software reset
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-- wait_for_time_constant <= '0';
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-- end if;
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else -- its an interrupt vector
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int_vector <= d_in(7 downto 3);
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end if;
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end if;
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end if;
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if int_pulse_0 = '1' then int_reg_0 <= '1'; end if;
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if int_pulse_1 = '1' then int_reg_1 <= '1'; end if;
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if int_pulse_2 = '1' then int_reg_2 <= '1'; end if;
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if int_pulse_3 = '1' then int_reg_3 <= '1'; end if;
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if int_ack_r = '1' and int_ack = '0' then
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if int_reg_0 = '1' then int_reg_0 <= '0';
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elsif int_reg_1 = '1' then int_reg_1 <= '0';
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elsif int_reg_2 = '1' then int_reg_2 <= '0';
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elsif int_reg_3 = '1' then int_reg_3 <= '0'; end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end struct;
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@ -1,152 +0,0 @@
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---------------------------------------------------------------------------------
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-- Z80-CTC counter by Dar (darfpga@aol.fr) (19/10/2019)
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-- http://darfpga.blogspot.fr
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---------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity ctc_counter is
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port(
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clock : in std_logic;
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clock_ena : in std_logic;
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reset : in std_logic;
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d_in : in std_logic_vector( 7 downto 0);
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load_data : in std_logic;
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clk_trg : in std_logic;
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d_out : out std_logic_vector(7 downto 0);
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zc_to : out std_logic;
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int_pulse : out std_logic
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);
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end ctc_counter;
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architecture struct of ctc_counter is
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signal control_word : std_logic_vector(7 downto 0);
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signal wait_for_time_constant : std_logic;
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signal time_constant_loaded : std_logic;
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signal restart_on_next_clock : std_logic;
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signal restart_on_next_trigger : std_logic;
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signal prescale_max : std_logic_vector(7 downto 0);
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signal prescale_in : std_logic_vector(7 downto 0) := (others => '0');
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signal count_max : std_logic_vector(8 downto 0);
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signal count_in : std_logic_vector(8 downto 0) := (others => '0');
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signal zc_to_in : std_logic;
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signal clk_trg_r : std_logic;
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signal trigger : std_logic;
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signal count_ena : std_logic;
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signal load_data_r : std_logic; -- make sure load_data toggles to get one new data
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begin
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prescale_max <=
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(others => '0') when control_word(6) = '1' else -- counter mode (prescale max = 0)
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X"0F" when control_word(6 downto 5) = "00" else -- timer mode prescale 16
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X"FF"; -- timer mode prescale 256
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trigger <=
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'1' when (clk_trg = '0' and clk_trg_r = '1' and control_word(4) = '0') or -- falling edge
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(clk_trg = '1' and clk_trg_r = '0' and control_word(4) = '1') else '0'; -- rising edge
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d_out <= count_in(7 downto 0);
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zc_to <= zc_to_in;
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int_pulse <= zc_to_in when control_word(7) = '1' else '0';
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process (reset, clock)
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begin
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if reset = '1' then -- hardware reset
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count_ena <= '0';
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wait_for_time_constant <= '0';
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time_constant_loaded <= '0';
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restart_on_next_clock <= '0';
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restart_on_next_trigger <= '0';
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count_in <= (others=> '0');
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zc_to_in <= '0';
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clk_trg_r <= clk_trg;
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else
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if rising_edge(clock) then
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if clock_ena = '1' then
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clk_trg_r <= clk_trg;
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load_data_r <= load_data;
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if (restart_on_next_trigger = '1' and trigger = '1') or (restart_on_next_clock = '1') then
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restart_on_next_clock <= '0';
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restart_on_next_trigger <= '0';
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count_ena <= '1';
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count_in <= count_max;
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prescale_in <= prescale_max;
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end if;
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if load_data = '1' and load_data_r = '0' then
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if wait_for_time_constant = '1' then
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wait_for_time_constant <= '0';
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time_constant_loaded <= '1';
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if d_in = X"00" then
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count_max <= '1'&X"00";
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else
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count_max <= '0'&d_in;
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end if;
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if control_word(6) = '0' and count_ena = '0' then -- in timer mode, if count was stooped
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if control_word(3) = '0' then -- auto start when time_constant loaded
|
||||
restart_on_next_clock <= '1';
|
||||
else -- wait for trigger to start
|
||||
restart_on_next_trigger <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
else -- not waiting for time constant
|
||||
|
||||
if d_in(0) = '1' then -- check if its a control world
|
||||
control_word <= d_in;
|
||||
wait_for_time_constant <= d_in(2);
|
||||
restart_on_next_clock <= '0';
|
||||
restart_on_next_trigger <= '0';
|
||||
|
||||
if d_in(1) = '1' then -- software reset
|
||||
count_ena <= '0';
|
||||
time_constant_loaded <= '0';
|
||||
zc_to_in <= '0';
|
||||
-- zc_to_in_r <= '0';
|
||||
clk_trg_r <= clk_trg;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end if; -- end load data
|
||||
|
||||
-- counter
|
||||
zc_to_in <= '0';
|
||||
if ((control_word(6) = '1' and trigger = '1' ) or
|
||||
(control_word(6) = '0' and count_ena = '1') ) and time_constant_loaded = '1' then
|
||||
if prescale_in = 0 then
|
||||
prescale_in <= '0'&prescale_max(7 downto 1); -- test divide by 2 !
|
||||
if count_in = 0 then
|
||||
zc_to_in <= '1';
|
||||
count_in <= count_max;
|
||||
else
|
||||
count_in <= count_in - '1';
|
||||
end if;
|
||||
else
|
||||
prescale_in <= prescale_in - '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end struct;
|
||||
@ -213,34 +213,17 @@ architecture struct of spy_hunter is
|
||||
signal cpu_ioreq_n : std_logic;
|
||||
signal cpu_irq_n : std_logic;
|
||||
signal cpu_m1_n : std_logic;
|
||||
|
||||
signal ctc_controler_we : std_logic;
|
||||
signal ctc_controler_do : std_logic_vector(7 downto 0);
|
||||
signal ctc_int_ack : std_logic;
|
||||
signal cpu_int_ack_n : std_logic;
|
||||
|
||||
signal ctc_counter_0_we : std_logic;
|
||||
-- signal ctc_counter_0_trg : std_logic;
|
||||
signal ctc_counter_0_do : std_logic_vector(7 downto 0);
|
||||
signal ctc_counter_0_int : std_logic;
|
||||
signal ctc_ce : std_logic;
|
||||
signal ctc_do : std_logic_vector(7 downto 0);
|
||||
|
||||
signal ctc_counter_1_we : std_logic;
|
||||
-- signal ctc_counter_1_trg : std_logic;
|
||||
signal ctc_counter_1_do : std_logic_vector(7 downto 0);
|
||||
signal ctc_counter_1_int : std_logic;
|
||||
|
||||
signal ctc_counter_2_we : std_logic;
|
||||
-- signal ctc_counter_2_trg : std_logic;
|
||||
signal ctc_counter_2_do : std_logic_vector(7 downto 0);
|
||||
signal ctc_counter_2_int : std_logic;
|
||||
|
||||
signal ctc_counter_3_we : std_logic;
|
||||
signal ctc_counter_1_trg : std_logic;
|
||||
signal ctc_counter_2_trg : std_logic;
|
||||
signal ctc_counter_3_trg : std_logic;
|
||||
signal ctc_counter_3_do : std_logic_vector(7 downto 0);
|
||||
signal ctc_counter_3_int : std_logic;
|
||||
|
||||
-- signal cpu_rom_addr: std_logic_vector(15 downto 0);
|
||||
-- signal cpu_rom_do : std_logic_vector( 7 downto 0);
|
||||
|
||||
|
||||
signal wram_we : std_logic;
|
||||
signal wram_do : std_logic_vector( 7 downto 0);
|
||||
|
||||
@ -464,8 +447,8 @@ begin
|
||||
if hcnt >= 2+16+16 and hcnt < 514+16-1 and
|
||||
vcnt >= 1 and vcnt < 241 then video_blankn <= '1';end if;
|
||||
|
||||
if hs_cnt = 0 then hsync0 <= '0';
|
||||
elsif hs_cnt = 47 then hsync0 <= '1';
|
||||
if hs_cnt = 0 then hsync0 <= '0'; video_hs <= '0';
|
||||
elsif hs_cnt = 47 then hsync0 <= '1'; video_hs <= '1';
|
||||
end if;
|
||||
|
||||
if hs_cnt = 0 then hsync1 <= '0';
|
||||
@ -566,13 +549,8 @@ cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"E
|
||||
ch_ram_do_r when cpu_mreq_n = '0' and (cpu_addr and x"FC00") = x"E800" else -- char ram E800-EBFF 1Ko + mirroring 0400
|
||||
wram_do when cpu_mreq_n = '0' and (cpu_addr and X"F800") = x"F000" else -- work ram F000-F7FF 2Ko
|
||||
sp_ram_cache_do_r when cpu_mreq_n = '0' and (cpu_addr and x"FE00") = x"F800" else -- sprite ram F800-F9FF 512o
|
||||
|
||||
ctc_controler_do when cpu_ioreq_n = '0' and cpu_m1_n = '0' else -- ctc ctrl (interrupt vector)
|
||||
ctc_do when cpu_int_ack_n = '0' or ctc_ce = '1' else -- ctc (interrupt vector or counter data)
|
||||
ssio_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 5) = "000" else -- 0x00-0x1F
|
||||
ctc_counter_3_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F3" else
|
||||
ctc_counter_2_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F2" else
|
||||
ctc_counter_1_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F1" else
|
||||
ctc_counter_0_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else
|
||||
X"FF";
|
||||
|
||||
cpu_rom_addr <= cpu_addr when cpu_addr < x"A000" else cpu_addr xor x"6000"; -- last rom has upper/lower part swapped
|
||||
@ -591,14 +569,10 @@ ssio_iowe <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' else '0';
|
||||
------------------------------------------------------------------------
|
||||
-- Misc registers : ctc write enable / interrupt acknowledge
|
||||
------------------------------------------------------------------------
|
||||
ctc_counter_3_trg <= '1' when (vcnt = 246 and tv15Khz_mode = '1') or (vcnt = 493 and tv15Khz_mode = '0')else '0';
|
||||
ctc_counter_3_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F3" else '0';
|
||||
ctc_counter_2_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F2" else '0';
|
||||
ctc_counter_1_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F1" else '0';
|
||||
ctc_counter_0_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else '0';
|
||||
ctc_controler_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else '0'; -- only channel 0 receive int vector
|
||||
ctc_int_ack <= '1' when cpu_ioreq_n = '0' and cpu_m1_n = '0' else '0';
|
||||
|
||||
cpu_int_ack_n <= cpu_ioreq_n or cpu_m1_n;
|
||||
ctc_ce <= '1' when cpu_ioreq_n = '0' and cpu_addr(7 downto 4) = x"F" else '0';
|
||||
ctc_counter_2_trg <= '1' when (vcnt >= 240 and vcnt <= 262 and tv15Khz_mode = '1') or (vcnt >= 480 and tv15Khz_mode = '0') else '0';
|
||||
ctc_counter_3_trg <= '1' when top_frame = '1' and ((vcnt = 246 and tv15Khz_mode = '1') or (vcnt = 493 and tv15Khz_mode = '0')) else '0';
|
||||
|
||||
process (clock_vid)
|
||||
begin
|
||||
@ -664,7 +638,7 @@ begin
|
||||
sp_byte_cnt <= (others => '0');
|
||||
when "000001" =>
|
||||
sp_attr <= sp_ram_do;
|
||||
when "000010" =>
|
||||
when "000010" =>
|
||||
sp_code <= sp_ram_do;
|
||||
sp_addr <= sp_ram_do(7 downto 0) & (sp_line xor sp_vflip) & (sp_byte_cnt xor sp_hflip); -- graphics rom addr
|
||||
when "000011" =>
|
||||
@ -673,7 +647,7 @@ when "000010" =>
|
||||
sp_graphx32_do_r <= sp_graphx32_do; -- latch incoming sprite data
|
||||
sp_addr <= sp_code(7 downto 0) & (sp_line xor sp_vflip) & (sp_byte_cnt+1 xor sp_hflip); -- advance graphics rom addr
|
||||
sp_on_line <= '1';
|
||||
when "010010"|"011010"|"100010" => -- 18,26,34
|
||||
when "010010"|"011010"|"100010" => -- 18,26,34
|
||||
sp_graphx32_do_r <= sp_graphx32_do; -- latch incoming sprite data
|
||||
sp_addr <= sp_code(7 downto 0) & (sp_line xor sp_vflip) & (sp_byte_cnt+2 xor sp_hflip); -- advance graphics rom addr
|
||||
sp_byte_cnt <= sp_byte_cnt + 1;
|
||||
@ -922,92 +896,28 @@ port map(
|
||||
DO => cpu_do
|
||||
);
|
||||
|
||||
-- CTC interrupt controler Z80-CTC (MK3882)
|
||||
ctc_controler : entity work.ctc_controler
|
||||
port map(
|
||||
clock => clock_vid,
|
||||
clock_ena => cpu_ena,
|
||||
reset => reset,
|
||||
|
||||
d_in => cpu_do,
|
||||
load_data => ctc_controler_we,
|
||||
int_ack => ctc_int_ack,
|
||||
|
||||
int_pulse_0 => ctc_counter_0_int,
|
||||
int_pulse_1 => ctc_counter_1_int,
|
||||
int_pulse_2 => ctc_counter_2_int,
|
||||
int_pulse_3 => ctc_counter_3_int,
|
||||
|
||||
d_out => ctc_controler_do,
|
||||
int_n => cpu_irq_n
|
||||
);
|
||||
|
||||
ctc_counter_0 : entity work.ctc_counter
|
||||
port map(
|
||||
clock => clock_vid,
|
||||
clock_ena => cpu_ena,
|
||||
reset => reset,
|
||||
|
||||
d_in => cpu_do,
|
||||
load_data => ctc_counter_0_we,
|
||||
|
||||
clk_trg => '0',
|
||||
|
||||
d_out => ctc_counter_0_do,
|
||||
zc_to => open, -- zc/to #0 (pin 7) connected to clk_trg #1 (pin 22) on schematics (seems to be not used)
|
||||
int_pulse => ctc_counter_0_int
|
||||
|
||||
);
|
||||
|
||||
ctc_counter_1 : entity work.ctc_counter
|
||||
port map(
|
||||
clock => clock_vid,
|
||||
clock_ena => cpu_ena,
|
||||
reset => reset,
|
||||
|
||||
d_in => cpu_do,
|
||||
load_data => ctc_counter_1_we,
|
||||
|
||||
clk_trg => '0',
|
||||
|
||||
d_out => ctc_counter_1_do,
|
||||
zc_to => open,
|
||||
int_pulse => ctc_counter_1_int
|
||||
|
||||
);
|
||||
|
||||
ctc_counter_2 : entity work.ctc_counter
|
||||
port map(
|
||||
clock => clock_vid,
|
||||
clock_ena => cpu_ena,
|
||||
reset => reset,
|
||||
|
||||
d_in => cpu_do,
|
||||
load_data => ctc_counter_2_we,
|
||||
|
||||
clk_trg => '0',
|
||||
|
||||
d_out => ctc_counter_2_do,
|
||||
zc_to => open,
|
||||
int_pulse => ctc_counter_2_int
|
||||
|
||||
);
|
||||
|
||||
ctc_counter_3 : entity work.ctc_counter
|
||||
port map(
|
||||
clock => clock_vid,
|
||||
clock_ena => cpu_ena,
|
||||
reset => reset,
|
||||
|
||||
d_in => cpu_do,
|
||||
load_data => ctc_counter_3_we,
|
||||
|
||||
clk_trg => ctc_counter_3_trg,
|
||||
|
||||
d_out => ctc_counter_3_do,
|
||||
zc_to => open,
|
||||
int_pulse => ctc_counter_3_int
|
||||
|
||||
-- Z80-CTC (MK3882)
|
||||
z80ctc : entity work.z80ctc_top
|
||||
port map (
|
||||
clock => clock_vid,
|
||||
clock_ena => cpu_ena,
|
||||
reset => reset,
|
||||
din => cpu_do,
|
||||
cpu_din => cpu_di,
|
||||
dout => ctc_do,
|
||||
ce_n => not ctc_ce,
|
||||
cs => cpu_addr(1 downto 0),
|
||||
m1_n => cpu_m1_n,
|
||||
iorq_n => cpu_ioreq_n,
|
||||
rd_n => cpu_rd_n,
|
||||
int_n => cpu_irq_n,
|
||||
trg0 => '0',
|
||||
to0 => ctc_counter_1_trg,
|
||||
trg1 => ctc_counter_1_trg,
|
||||
to1 => open,
|
||||
trg2 => '0',
|
||||
to2 => open,
|
||||
trg3 => ctc_counter_3_trg
|
||||
);
|
||||
|
||||
-- cpu program ROM 0x0000-0xDFFF
|
||||
|
||||
@ -75,7 +75,7 @@ architecture struct of spy_hunter_control is
|
||||
gas <= gas_r;
|
||||
steering <= steering_r;
|
||||
|
||||
process (clock_40)
|
||||
process (clock_40, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
gas_r <= x"39";
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user