mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-25 11:35:58 +00:00
add Commen Units
This commit is contained in:
Marcel
@@ -1,5 +0,0 @@
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Acorn - Archimedes in FPGA
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FPGA Board: Mist FPGA
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Changed Clocks Source Code is the same like MiST Github Repo
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Binary file not shown.
380
Computer_MiST/Galaksija_MiST/rtl/ay8912.vhd
Normal file
380
Computer_MiST/Galaksija_MiST/rtl/ay8912.vhd
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@@ -0,0 +1,380 @@
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- --
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-- Copyright (c) 2005-2009 Tobias Gubener --
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-- Subdesign CPC T-REX by TobiFlex --
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-- --
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-- This source file is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published --
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-- by the Free Software Foundation, either version 3 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- This source file is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-- --
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity ay8912 is
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port (
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cpuclk : in STD_LOGIC; --48MHz
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reset : in STD_LOGIC;
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cs : in STD_LOGIC; --H-aktiv
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bc0 : in STD_LOGIC; --
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bdir : in STD_LOGIC;
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Data_in : in STD_LOGIC_VECTOR (7 downto 0);
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Data_out : out STD_LOGIC_VECTOR (7 downto 0);
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IO_A : in STD_LOGIC_VECTOR (7 downto 0);
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chanA : buffer STD_LOGIC_VECTOR (10 downto 0);
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chanB : buffer STD_LOGIC_VECTOR (10 downto 0);
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chanC : buffer STD_LOGIC_VECTOR (10 downto 0);
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Arechts : out STD_LOGIC_VECTOR (15 downto 0);
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Alinks : out STD_LOGIC_VECTOR (15 downto 0);
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Amono : out STD_LOGIC_VECTOR (15 downto 0)
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);
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end ay8912;
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architecture logic of ay8912 is
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signal t_Data : STD_LOGIC_VECTOR (7 downto 0);
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signal PSGReg : STD_LOGIC_VECTOR (3 downto 0);
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signal APeriode : STD_LOGIC_VECTOR (11 downto 0); --Reg 0,1
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signal BPeriode : STD_LOGIC_VECTOR (11 downto 0); --Reg 2,3
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signal CPeriode : STD_LOGIC_VECTOR (11 downto 0); --Reg 4,5
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signal Noise : STD_LOGIC_VECTOR (4 downto 0); --Reg 6
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signal enable : STD_LOGIC_VECTOR (7 downto 0); --Reg 7
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signal AVol : STD_LOGIC_VECTOR (4 downto 0); --Reg 8
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signal BVol : STD_LOGIC_VECTOR (4 downto 0); --Reg 9
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signal CVol : STD_LOGIC_VECTOR (4 downto 0); --Reg 10
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signal HPeriode : STD_LOGIC_VECTOR (15 downto 0); --Reg 11,12
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signal HKurve : STD_LOGIC_VECTOR (3 downto 0); --Reg 13
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signal PortA : STD_LOGIC_VECTOR (7 downto 0); --Reg 14
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signal PortB : STD_LOGIC_VECTOR (7 downto 0); --Reg 15
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signal AVollog : STD_LOGIC_VECTOR (9 downto 0); --Reg 8log
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signal BVollog : STD_LOGIC_VECTOR (9 downto 0); --Reg 9log
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signal CVollog : STD_LOGIC_VECTOR (9 downto 0); --Reg 10log
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signal Alog : STD_LOGIC_VECTOR (9 downto 0);
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signal Blog : STD_LOGIC_VECTOR (9 downto 0);
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signal Clog : STD_LOGIC_VECTOR (9 downto 0);
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signal HVollog : STD_LOGIC_VECTOR (11 downto 0);
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signal ACount : STD_LOGIC_VECTOR (11 downto 0);
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signal BCount : STD_LOGIC_VECTOR (11 downto 0);
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signal CCount : STD_LOGIC_VECTOR (11 downto 0);
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signal NCount : STD_LOGIC_VECTOR (4 downto 0);
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signal HCount : STD_LOGIC_VECTOR (15 downto 0);
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signal HVol : STD_LOGIC_VECTOR (4 downto 0);
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signal nHVol : STD_LOGIC_VECTOR (3 downto 0);
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signal HStart : STD_LOGIC;
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signal Noisebit : STD_LOGIC;
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signal RNG : STD_LOGIC_VECTOR (16 downto 0);
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signal Anot, Bnot, Cnot : STD_LOGIC;
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signal n_setreg : STD_LOGIC;
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signal n_Pegel : STD_LOGIC_VECTOR (11 downto 0);
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signal clockgen : STD_LOGIC_VECTOR (9 downto 0);
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signal S_Tick : STD_LOGIC;
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signal H_Tick : STD_LOGIC;
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begin
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-------------------------------------------------------------------------
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--Clock gen
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-------------------------------------------------------------------------
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process (cpuclk, clockgen)
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begin
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S_Tick <= '0'; --sound
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H_Tick <= '0'; --Hüllkurve
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IF clockgen(9 downto 1)=0 THEN
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S_Tick <= '1';
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IF clockgen(0)='0' THEN
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H_Tick <= '1';
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END IF;
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END IF;
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IF rising_edge(cpuclk) THEN
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Arechts <= (chanA&"00000")+('0'&chanB&"0000");
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Alinks <= (chanC&"00000")+('0'&chanB&"0000");
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Amono <= (chanC&"00000")+('0'&chanB&"0000")+(chanA&"00000");
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IF H_Tick='1' THEN
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-- clockgen <= ((48*16)-1); --48MHz
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clockgen <= "1011111111"; --48MHz
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ELSE
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clockgen <= clockgen-1;
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END IF;
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END IF;
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END process;
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-------------------------------------------------------------------------
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--IO Regs
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-------------------------------------------------------------------------
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process (cpuclk, reset, IO_A, PortA, PortB, Aperiode, Bperiode, Cperiode, Hperiode, AVol, BVol, CVol, Noise, HKurve, enable, Data_in, t_Data, PSGReg, bdir, bc0)
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begin
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IF reset='0' THEN
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enable <= (others => '0');
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PortA <= "11111111";
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PortB <= "11111111";
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ELSIF rising_edge(cpuclk) THEN
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HStart <= '0';
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IF bdir='1' AND bc0='1' THEN
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IF Data_in(7 downto 4)="0000" THEN
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PSGReg <= Data_in(3 downto 0);
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END IF;
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ELSE
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IF bdir='1' AND bc0='0' THEN
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CASE PSGReg IS
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WHEN "0000" =>
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APeriode(7 downto 0) <= Data_in;
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WHEN "0001" =>
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APeriode(11 downto 8) <= Data_in(3 downto 0);
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WHEN "0010" =>
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BPeriode(7 downto 0) <= Data_in;
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WHEN "0011" =>
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BPeriode(11 downto 8) <= Data_in(3 downto 0);
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WHEN "0100" =>
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CPeriode(7 downto 0) <= Data_in;
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WHEN "0101" =>
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CPeriode(11 downto 8) <= Data_in(3 downto 0);
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WHEN "0110" =>
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Noise(4 downto 0) <= Data_in(4 downto 0);
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WHEN "0111" =>
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enable <= Data_in XOR B"00111111";
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WHEN "1000" =>
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AVollog <= n_Pegel(9 downto 0);
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AVol(4 downto 0) <= Data_in(4 downto 0);
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WHEN "1001" =>
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BVollog <= n_Pegel(9 downto 0);
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BVol(4 downto 0) <= Data_in(4 downto 0);
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WHEN "1010" =>
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CVollog <= n_Pegel(9 downto 0);
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CVol(4 downto 0) <= Data_in(4 downto 0);
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WHEN "1011" =>
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HPeriode(7 downto 0) <= Data_in;
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WHEN "1100" =>
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HPeriode(15 downto 8) <= Data_in;
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WHEN "1101" =>
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HStart <= '1';
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HKurve(3 downto 0) <= Data_in(3 downto 0);
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WHEN "1110" =>
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PortA <= Data_in;
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WHEN "1111" =>
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PortB <= Data_in;
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WHEN OTHERS => null;
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END CASE;
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END IF;
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END IF;
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END IF;
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CASE Data_in(3 downto 0) IS
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WHEN "1111" => n_Pegel <= X"2AA"; -- Umsetzung in logarithmische Werte in ca. 3dB Schritten
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WHEN "1110" => n_Pegel <= X"1E2"; -- für Kanäle
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WHEN "1101" => n_Pegel <= X"155";
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WHEN "1100" => n_Pegel <= X"0F1";
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WHEN "1011" => n_Pegel <= X"0AA";
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WHEN "1010" => n_Pegel <= X"078";
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WHEN "1001" => n_Pegel <= X"055";
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WHEN "1000" => n_Pegel <= X"03C";
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WHEN "0111" => n_Pegel <= X"02A";
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WHEN "0110" => n_Pegel <= X"01E";
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WHEN "0101" => n_Pegel <= X"015";
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WHEN "0100" => n_Pegel <= X"00F";
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WHEN "0011" => n_Pegel <= X"00A";
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WHEN "0010" => n_Pegel <= X"007";
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WHEN "0001" => n_Pegel <= X"005";
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WHEN "0000" => n_Pegel <= X"000";
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WHEN OTHERS => null;
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END CASE;
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-- read reg
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IF bc0='1' AND bdir='0' THEN
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Data_out <= t_Data;
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ELSE
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Data_out <= "11111111";
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END IF;
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t_Data <= "00000000";
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CASE PSGReg IS
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WHEN "0000" =>
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t_Data <= Aperiode(7 downto 0);
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WHEN "0001" =>
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t_Data(3 downto 0) <= Aperiode(11 downto 8);
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WHEN "0010" =>
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t_Data <= Bperiode(7 downto 0);
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WHEN "0011" =>
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t_Data(3 downto 0) <= Bperiode(11 downto 8);
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WHEN "0100" =>
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t_Data <= Cperiode(7 downto 0);
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WHEN "0101" =>
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t_Data(3 downto 0) <= Cperiode(11 downto 8);
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WHEN "0110" =>
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t_Data(4 downto 0) <= Noise;
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WHEN "0111" =>
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t_Data <= enable XOR "00111111";
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WHEN "1000" =>
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t_Data(4 downto 0) <= AVol;
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WHEN "1001" =>
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t_Data(4 downto 0) <= BVol;
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WHEN "1010" =>
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t_Data(4 downto 0) <= CVol;
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WHEN "1011" =>
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t_Data <= Hperiode(7 downto 0);
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WHEN "1100" =>
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t_Data <= Hperiode(15 downto 8);
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WHEN "1101" =>
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t_Data(3 downto 0) <= HKurve;
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WHEN "1110" =>
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IF enable(6)='0' THEN
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t_Data <= PortA AND IO_A;
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ELSE
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t_Data <= PortA;
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END IF;
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WHEN "1111" =>
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t_Data <= PortB;
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END CASE;
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END process;
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-------------------------------------------------------------------------
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--Soundgen
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-------------------------------------------------------------------------
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process (cpuclk, reset, AVol, BVol, CVol, HVol, nHVol, AVollog, BVollog, CVollog, HVollog, HKurve)
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begin
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-- channel A
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IF AVol(4)='1' THEN
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Alog <= HVollog(9 downto 0);
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ELSE
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Alog <= AVollog;
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END IF;
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IF rising_edge(cpuclk) THEN
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IF ((enable(3) AND Noisebit) XOR Anot)='1' THEN
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chanA <= ('0'&Alog);
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ELSE
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chanA <= (others => '0');
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END IF;
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IF enable(0)='0' OR APeriode="000000000000" THEN
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Anot <= '1';
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ACount <= "000000000000";
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ELSIF S_Tick='1' THEN
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IF ACount(11 downto 0)>=APeriode THEN
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ACount <= "000000000001";
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Anot <= NOT Anot;
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ELSE
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ACount <= ACount+1;
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END IF;
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END IF;
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END IF;
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-- channel B
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IF BVol(4)='1' THEN
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Blog <= HVollog(9 downto 0);
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ELSE
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Blog <= BVollog;
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END IF;
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IF rising_edge(cpuclk) THEN
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IF ((enable(4) AND Noisebit) XOR Bnot)='1' THEN
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chanB <= ('0'&Blog);
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ELSE
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chanB <= (others => '0');
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END IF;
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IF enable(1)='0' OR BPeriode="000000000000" THEN
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Bnot <= '1';
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BCount <= "000000000000";
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ELSIF S_Tick='1' THEN
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IF BCount(11 downto 0)>=BPeriode THEN
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BCount <= "000000000001";
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Bnot <= NOT Bnot;
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ELSE
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BCount <= BCount+1;
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END IF;
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END IF;
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END IF;
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-- channel C
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IF CVol(4)='1' THEN
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Clog <= HVollog(9 downto 0);
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ELSE
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Clog <= CVollog;
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END IF;
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IF rising_edge(cpuclk) THEN
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IF ((enable(5) AND Noisebit) XOR Cnot)='1' THEN
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chanC <= ('0'&Clog);
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ELSE
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chanC <= (others => '0');
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END IF;
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IF enable(2)='0' OR CPeriode="000000000000" THEN
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Cnot <= '1';
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CCount <= "000000000000";
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ELSIF S_Tick='1' THEN
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IF CCount(11 downto 0)>=CPeriode THEN
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CCount <= "000000000001";
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Cnot <= NOT Cnot;
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ELSE
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CCount <= CCount+1;
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END IF;
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END IF;
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END IF;
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--noise
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--Noise="00000" and Noise="00001" is the same
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IF rising_edge(cpuclk) THEN
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IF S_Tick='1' THEN
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IF NCount(4 downto 1)="0000" THEN
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NCount <= Noise ;
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RNG <= (NOT (RNG(0) XOR RNG(2))& RNG(16 downto 1));
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Noisebit <= RNG(0);
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ELSE
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NCount <= NCount-1;
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END IF;
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END IF;
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END IF;
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-- Huellkurve
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nHVol <= HVol(3 downto 0);
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IF ((HKurve(3) OR NOT HVol(4)) AND ( NOT HKurve(2) XOR ((HKurve(1) XOR HKurve(0)) AND HVol(4))))='1' THEN
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nHVol <= HVol(3 downto 0) XOR "1111";
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END IF;
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IF rising_edge(cpuclk) THEN
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IF HStart='1' THEN
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HCount <= "0000000000000001";
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HVol <= "00000";
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ELSIF H_Tick='1' THEN
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IF HCount>=HPeriode THEN
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HCount <= "0000000000000001";
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IF (NOT HVol(4) OR (NOT HKurve(0) AND HKurve(3)))='1' AND (HPeriode /= 0) THEN --HOLD
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-- IF (NOT HVol(4) OR (NOT HKurve(0) AND HKurve(3)))='1' THEN --HOLD
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HVol <= HVol+1;
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END IF;
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ELSE
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HCount <= HCount+1;
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END IF;
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END IF;
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END IF;
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CASE nHVol(3 downto 0) IS
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WHEN "1111" => HVollog <= X"2AA"; -- Umsetzung in logarithmische Werte in ca. 3dB Schritten
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WHEN "1110" => HVollog <= X"1E2"; -- für Hüllkurve
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WHEN "1101" => HVollog <= X"155";
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WHEN "1100" => HVollog <= X"0F1";
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WHEN "1011" => HVollog <= X"0AA";
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WHEN "1010" => HVollog <= X"078";
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WHEN "1001" => HVollog <= X"055";
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WHEN "1000" => HVollog <= X"03C";
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WHEN "0111" => HVollog <= X"02A";
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WHEN "0110" => HVollog <= X"01E";
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WHEN "0101" => HVollog <= X"015";
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WHEN "0100" => HVollog <= X"00F";
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WHEN "0011" => HVollog <= X"00A";
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WHEN "0010" => HVollog <= X"007";
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WHEN "0001" => HVollog <= X"005";
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WHEN "0000" => HVollog <= X"000";
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WHEN OTHERS => null;
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END CASE;
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END process;
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end logic;
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