mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-20 17:47:33 +00:00
remove one DAC
This commit is contained in:
Marcel
parent
ab8496669a
commit
fa65ff3c9f
@ -25,22 +25,22 @@ localparam CONF_STR = {
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"T9,Reset;",
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"V,v1.00.",`BUILD_DATE
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};
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wire clk_24, clk_12, clk_6;
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wire clk_24, clk_6;
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wire [10:0] ps2_key;
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wire r, g,b;
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wire r, g, b;
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wire hs, vs;
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wire [1:0] buttons, switches;
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wire ypbpr;
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wire scandoublerD;
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wire [31:0] status;
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wire [15:0] audiol, audior;
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wire [15:0] audio;
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assign LED = 1'b1;
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assign AUDIO_R = AUDIO_L;
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pll pll (
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.inclk0 ( CLOCK_27 ),
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.c0 ( clk_24 ),
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.c1 ( clk_12 ),
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.c2 ( clk_6 )
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.c1 ( clk_6 )
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);
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@ -90,8 +90,7 @@ video_mixer video_mixer (
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oricatmos oricatmos(
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.RESET(status[0] | status[9] | buttons[1]),
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.ps2_key(ps2_key),
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.PSG_LEFT(audiol),
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.PSG_RIGHT(audior),
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.PSG_OUT(audio),
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.VIDEO_R(r),
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.VIDEO_G(g),
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.VIDEO_B(b),
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@ -104,22 +103,11 @@ oricatmos oricatmos(
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dac #(
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.msbi_g(15))
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dacl (
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dac(
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.clk_i(clk_24),
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.res_n_i(1'b1),
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.dac_i(audiol),
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.dac_i(audio),
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.dac_o(AUDIO_L)
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);
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dac #(
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.msbi_g(15))
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dacr (
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.clk_i(clk_24),
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.res_n_i(1'b1),
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.dac_i(audior),
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.dac_o(AUDIO_R)
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);
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endmodule
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@ -27,18 +27,20 @@ use ieee.std_logic_unsigned.all;
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entity ay8912 is
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port (
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cpuclk : in STD_LOGIC; --48MHz
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reset : in STD_LOGIC;
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cs : in STD_LOGIC; --H-aktiv
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bc0 : in STD_LOGIC; --
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bdir : in STD_LOGIC;
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Data_in : in STD_LOGIC_VECTOR (7 downto 0);
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oData : out STD_LOGIC_VECTOR (7 downto 0);
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chanA : buffer STD_LOGIC_VECTOR (10 downto 0);
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chanB : buffer STD_LOGIC_VECTOR (10 downto 0);
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chanC : buffer STD_LOGIC_VECTOR (10 downto 0);
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cpuclk : in STD_LOGIC; --48MHz
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reset : in STD_LOGIC;
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cs : in STD_LOGIC; --H-aktiv
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bc0 : in STD_LOGIC; --
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bdir : in STD_LOGIC;
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Data_in : in STD_LOGIC_VECTOR (7 downto 0);
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Data_out : out STD_LOGIC_VECTOR (7 downto 0);
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IO_A : in STD_LOGIC_VECTOR (7 downto 0);
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chanA : buffer STD_LOGIC_VECTOR (10 downto 0);
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chanB : buffer STD_LOGIC_VECTOR (10 downto 0);
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chanC : buffer STD_LOGIC_VECTOR (10 downto 0);
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Arechts : out STD_LOGIC_VECTOR (15 downto 0);
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Alinks : out STD_LOGIC_VECTOR (15 downto 0)
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Alinks : out STD_LOGIC_VECTOR (15 downto 0);
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Amono : out STD_LOGIC_VECTOR (15 downto 0)
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);
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end ay8912;
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@ -92,7 +94,7 @@ begin
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process (cpuclk, clockgen)
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begin
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S_Tick <= '0'; --sound
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H_Tick <= '0'; --Huellkurve
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H_Tick <= '0'; --Hüllkurve
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IF clockgen(9 downto 1)=0 THEN
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S_Tick <= '1';
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IF clockgen(0)='0' THEN
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@ -102,6 +104,7 @@ begin
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IF rising_edge(cpuclk) THEN
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Arechts <= (chanA&"00000")+('0'&chanB&"0000");
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Alinks <= (chanC&"00000")+('0'&chanB&"0000");
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Amono <= (chanC&"00000")+('0'&chanB&"0000")+(chanA&"00000");
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IF H_Tick='1' THEN
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-- clockgen <= ((48*16)-1); --48MHz
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clockgen <= "1011111111"; --48MHz
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@ -113,7 +116,7 @@ END process;
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-------------------------------------------------------------------------
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--IO Regs
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-------------------------------------------------------------------------
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process (cpuclk, reset, PortA, PortB, Aperiode, Bperiode, Cperiode, Hperiode, AVol, BVol, CVol, Noise, HKurve, enable, Data_in, t_Data, PSGReg, bdir, bc0)
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process (cpuclk, reset, IO_A, PortA, PortB, Aperiode, Bperiode, Cperiode, Hperiode, AVol, BVol, CVol, Noise, HKurve, enable, Data_in, t_Data, PSGReg, bdir, bc0)
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begin
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IF reset='0' THEN
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enable <= (others => '0');
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@ -171,7 +174,7 @@ begin
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END IF;
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CASE Data_in(3 downto 0) IS
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WHEN "1111" => n_Pegel <= X"2AA"; -- Umsetzung in logarithmische Werte in ca. 3dB Schritten
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WHEN "1110" => n_Pegel <= X"1E2"; -- f<EFBFBD>r Kan<61>le
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WHEN "1110" => n_Pegel <= X"1E2"; -- für Kanäle
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WHEN "1101" => n_Pegel <= X"155";
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WHEN "1100" => n_Pegel <= X"0F1";
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WHEN "1011" => n_Pegel <= X"0AA";
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@ -191,9 +194,9 @@ begin
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-- read reg
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IF bc0='1' AND bdir='0' THEN
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oData <= t_Data;
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Data_out <= t_Data;
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ELSE
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oData <= "11111111";
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Data_out <= "11111111";
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END IF;
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t_Data <= "00000000";
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@ -227,7 +230,11 @@ begin
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WHEN "1101" =>
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t_Data(3 downto 0) <= HKurve;
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WHEN "1110" =>
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IF enable(6)='0' THEN
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t_Data <= PortA AND IO_A;
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ELSE
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t_Data <= PortA;
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END IF;
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WHEN "1111" =>
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t_Data <= PortB;
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END CASE;
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@ -351,7 +358,7 @@ begin
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CASE nHVol(3 downto 0) IS
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WHEN "1111" => HVollog <= X"2AA"; -- Umsetzung in logarithmische Werte in ca. 3dB Schritten
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WHEN "1110" => HVollog <= X"1E2"; -- f<EFBFBD>r H<>llkurve
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WHEN "1110" => HVollog <= X"1E2"; -- für Hüllkurve
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WHEN "1101" => HVollog <= X"155";
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WHEN "1100" => HVollog <= X"0F1";
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WHEN "1011" => HVollog <= X"0AA";
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@ -67,8 +67,9 @@ entity oricatmos is
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K7_TAPEIN : in std_logic;
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K7_TAPEOUT : out std_logic;
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K7_REMOTE : out std_logic;
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PSG_RIGHT : out std_logic_vector(15 downto 0);
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PSG_LEFT : out std_logic_vector(15 downto 0);
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-- PSG_RIGHT : out std_logic_vector(15 downto 0);
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-- PSG_LEFT : out std_logic_vector(15 downto 0);
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PSG_OUT : out std_logic_vector(15 downto 0);
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VIDEO_R : out std_logic;
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VIDEO_G : out std_logic;
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VIDEO_B : out std_logic;
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@ -297,12 +298,14 @@ ad <= ula_AD_SRAM when ula_PHI2 = '0' else cpu_ad(15 downto 0);
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bc0 => psg_bdir,
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bdir => via_cb2_out,
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Data_in => via_pa_out,
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oData => via_pa_in,
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Data_out => via_pa_in,
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IO_A => x"FF",
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chanA => open,
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chanB => open,
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chanC => open,
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Arechts => PSG_RIGHT,
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Alinks => PSG_LEFT
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-- Arechts => PSG_RIGHT,
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-- Alinks => PSG_LEFT,
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Amono => PSG_OUT
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);
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inst_key : keyboard
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@ -39,27 +39,23 @@
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module pll (
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inclk0,
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c0,
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c1,
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c2);
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c1);
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input inclk0;
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output c0;
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output c1;
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output c2;
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wire [4:0] sub_wire0;
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wire [0:0] sub_wire6 = 1'h0;
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wire [2:2] sub_wire3 = sub_wire0[2:2];
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wire [0:0] sub_wire2 = sub_wire0[0:0];
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wire [1:1] sub_wire1 = sub_wire0[1:1];
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wire c1 = sub_wire1;
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wire c0 = sub_wire2;
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wire c2 = sub_wire3;
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wire sub_wire4 = inclk0;
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wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
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wire [0:0] sub_wire5 = 1'h0;
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wire [1:1] sub_wire2 = sub_wire0[1:1];
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wire [0:0] sub_wire1 = sub_wire0[0:0];
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wire c0 = sub_wire1;
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wire c1 = sub_wire2;
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wire sub_wire3 = inclk0;
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wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
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altpll altpll_component (
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.inclk (sub_wire5),
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.inclk (sub_wire4),
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.clk (sub_wire0),
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.activeclock (),
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.areset (1'b0),
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@ -104,12 +100,8 @@ module pll (
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altpll_component.clk0_phase_shift = "0",
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altpll_component.clk1_divide_by = 9,
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altpll_component.clk1_duty_cycle = 50,
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altpll_component.clk1_multiply_by = 4,
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altpll_component.clk1_multiply_by = 2,
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altpll_component.clk1_phase_shift = "0",
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altpll_component.clk2_divide_by = 9,
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altpll_component.clk2_duty_cycle = 50,
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altpll_component.clk2_multiply_by = 2,
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altpll_component.clk2_phase_shift = "0",
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altpll_component.compensate_clock = "CLK0",
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altpll_component.inclk0_input_frequency = 37037,
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altpll_component.intended_device_family = "Cyclone III",
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@ -144,7 +136,7 @@ module pll (
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altpll_component.port_scanwrite = "PORT_UNUSED",
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altpll_component.port_clk0 = "PORT_USED",
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altpll_component.port_clk1 = "PORT_USED",
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altpll_component.port_clk2 = "PORT_USED",
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altpll_component.port_clk2 = "PORT_UNUSED",
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altpll_component.port_clk3 = "PORT_UNUSED",
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altpll_component.port_clk4 = "PORT_UNUSED",
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altpll_component.port_clk5 = "PORT_UNUSED",
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@ -184,13 +176,10 @@ endmodule
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// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
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// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
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// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
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// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
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// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
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// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
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// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
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// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
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// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
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// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
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// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000"
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// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
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// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
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// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
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@ -212,33 +201,25 @@ endmodule
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// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
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// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
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// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
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// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
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// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
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// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
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// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
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// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
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// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
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// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
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// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
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// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
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// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
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// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
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// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
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// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
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// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
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// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
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// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
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// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
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// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
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// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
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// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
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// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
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// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
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// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
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@ -262,16 +243,13 @@ endmodule
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// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
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// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
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// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
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// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
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// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
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// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
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// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
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// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
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// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
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// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
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// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
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// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
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// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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@ -282,12 +260,8 @@ endmodule
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// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
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// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
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// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
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// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
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// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
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// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
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// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
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// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
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// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
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// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
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// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
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// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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@ -321,7 +295,7 @@ endmodule
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// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
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// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
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// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
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// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
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// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
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// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
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// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
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// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
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@ -339,13 +313,11 @@ endmodule
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// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
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// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
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// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
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// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
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// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
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// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user