add Commen Units

common/CPU/6502_6510/aholme_6502.v

@@ -0,0 +1,32 @@
+module aholme_6502(
+    input clk,
+    input enable,
+    input reset,
+    output [15:0] ab,
+    input [7:0] dbi,
+    output [7:0] dbo,
+    output we,
+    input irq,
+    input nmi,
+    input ready
+);
+
+    wire we_c;
+
+    chip_6502 aholme_cpu (
+        .clk(clk),
+        .phi(clk & enable),
+        .res(~reset),
+        .so(1'b0),
+        .rdy(ready),
+        .nmi(nmi_n),
+        .irq(irq_n),
+        .rw(we_c),
+        .dbi(dbi),
+        .dbo(dbo),
+        .ab(ab)
+    );
+
+    assign we = ~we_c;
+
+endmodule

common/CPU/6502_6510/arlet_6502.v

@@ -0,0 +1,72 @@
+// Licensed to the Apache Software Foundation (ASF) under one
+// or more contributor license agreements.  See the NOTICE file
+// distributed with this work for additional information
+// regarding copyright ownership.  The ASF licenses this file
+// to you under the Apache License, Version 2.0 (the
+// "License"); you may not use this file except in compliance
+// with the License.  You may obtain a copy of the License at
+//
+//   http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing,
+// software distributed under the License is distributed on an
+// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+// KIND, either express or implied.  See the License for the
+// specific language governing permissions and limitations
+// under the License.
+//
+// Description: A wrapper for Arlet Ottens 6502 CPU core
+//
+// Author.....: Alan Garfield
+//              Niels A. Moseley
+// Date.......: 26-1-2018
+//
+
+module arlet_6502(
+    input clk,                  // clock signal
+    input enable,               // clock enable strobe
+    input rst,                  // active high reset signal
+    output reg [15:0] ab,       // address bus
+    input [7:0] dbi,            // 8-bit data bus (input)
+    output reg [7:0] dbo,       // 8-bit data bus (output)
+    output reg we,              // active high write enable strobe
+    input irq_n,                // active low interrupt request
+    input nmi_n,                // active low non-maskable interrupt
+    input ready,                // CPU updates when ready = 1
+    output [15:0] pc_monitor    // program counter monitor signal for debugging
+);
+
+    wire [7:0] dbo_c;
+    wire [15:0] ab_c;
+    wire we_c;
+
+    cpu arlet_cpu(
+        .clk(clk),
+        .reset(rst),
+        .AB(ab_c),
+        .DI(dbi),
+        .DO(dbo_c),
+        .WE(we_c),
+        .IRQ(~irq_n),
+        .NMI(~nmi_n),
+        .RDY(ready),
+        .PC_MONITOR(pc_monitor)
+    );
+
+    always @(posedge clk or posedge rst)
+    begin
+        if (rst)
+        begin
+            ab <= 16'd0;
+            dbo <= 8'd0;
+            we <= 1'b0;
+        end
+        else
+            if (enable)
+            begin
+                ab <= ab_c;
+                dbo <= dbo_c;
+                we <= we_c;
+            end
+    end
+endmodule

common/CPU/6502_6510/chip_6502.v

@@ -0,0 +1,66 @@
+`include "../rtl/cpu/aholme/chip_6502_nodes.inc"
+
+module LOGIC (
+    input  [`NUM_NODES-1:0] i,
+    output [`NUM_NODES-1:0] o);
+
+    `include "chip_6502_logic.inc"
+endmodule
+
+
+module chip_6502 (
+    input           clk,    // FPGA clock
+    input           phi,    // 6502 clock
+    input           res,
+    input           so,
+    input           rdy,
+    input           nmi,
+    input           irq,
+    input     [7:0] dbi,
+    output    [7:0] dbo,
+    output          rw,
+    output          sync,
+    output   [15:0] ab);
+
+    // Node states
+    wire [`NUM_NODES-1:0] no;
+    reg  [`NUM_NODES-1:0] ni;
+    reg  [`NUM_NODES-1:0] q = 0;
+
+    LOGIC logic_00 (.i(ni), .o(no));
+
+    always @ (posedge clk)
+        q <= no;
+
+    always @* begin
+        ni = q;
+
+        ni[`NODE_vcc ]  = 1'b1;
+        ni[`NODE_vss ]  = 1'b0;
+        ni[`NODE_res ]  = res;
+        ni[`NODE_clk0]  = phi;
+        ni[`NODE_so  ]  = so;
+        ni[`NODE_rdy ]  = rdy;
+        ni[`NODE_nmi ]  = nmi;
+        ni[`NODE_irq ]  = irq;
+
+       {ni[`NODE_db7],ni[`NODE_db6],ni[`NODE_db5],ni[`NODE_db4],
+        ni[`NODE_db3],ni[`NODE_db2],ni[`NODE_db1],ni[`NODE_db0]} = dbi[7:0];
+    end
+
+    assign dbo[7:0] = {
+        no[`NODE_db7],no[`NODE_db6],no[`NODE_db5],no[`NODE_db4],
+        no[`NODE_db3],no[`NODE_db2],no[`NODE_db1],no[`NODE_db0]
+    };
+
+    assign ab[15:0] = {
+        no[`NODE_ab15], no[`NODE_ab14], no[`NODE_ab13], no[`NODE_ab12],
+        no[`NODE_ab11], no[`NODE_ab10], no[`NODE_ab9],  no[`NODE_ab8],
+        no[`NODE_ab7],  no[`NODE_ab6],  no[`NODE_ab5],  no[`NODE_ab4],
+        no[`NODE_ab3],  no[`NODE_ab2],  no[`NODE_ab1],  no[`NODE_ab0]
+    };
+
+    assign rw   = no[`NODE_rw];
+    assign sync = no[`NODE_sync];
+
+endmodule

common/CPU/6502_6510/chip_6502_mux.v

@@ -0,0 +1,10 @@
+module MUX #(
+    parameter N=1
+) (
+    output wire o,
+    input  wire i,
+    input  wire [N-1:0] s,
+    input  wire [N-1:0] d);
+
+    assign o = (|s) ? &(d|(~s)) : i;
+endmodule

common/CPU/6502_6510/cpu65xx_e.vhd

@@ -0,0 +1,87 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- Interface to 6502/6510 core
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity cpu65xx is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean
+	);
+	port (
+		clk : in std_logic;
+		enable : in std_logic;
+		reset : in std_logic;
+		nmi_n : in std_logic;
+		irq_n : in std_logic;
+		so_n : in std_logic := '1';
+
+		di : in unsigned(7 downto 0);
+		do : out unsigned(7 downto 0);
+		addr : out unsigned(15 downto 0);
+		we : out std_logic;
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0)
+	);
+end cpu65xx;
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+entity cpu6502 is
+	port(
+		clk    : in std_logic;
+		ce     : in std_logic;
+		reset  : in std_logic;
+		nmi    : in std_logic;
+		irq    : in std_logic;
+		din    : in  unsigned(7 downto 0);
+		dout   : out unsigned(7 downto 0);
+		addr   : out unsigned(15 downto 0);
+		we     : out std_logic
+	);
+end cpu6502;
+
+architecture cpu6502 of cpu6502 is
+begin
+	cpuInstance: entity work.cpu65xx(fast)
+	generic map (
+		pipelineOpcode => false,
+		pipelineAluMux => false,
+		pipelineAluOut => false
+	)
+	port map (
+		clk   => clk,
+		enable=> ce,
+		reset => reset,
+		nmi_n => not nmi,
+		irq_n => not irq,
+		di    => din,
+		do    => dout,
+		addr  => addr,
+		we    => we
+	);
+end architecture;