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Konami Finalizer

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Gyorgy Szombathelyi
2022-01-02 01:01:22 +01:00
parent e64964ce9f
commit 485e09b3a5
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31
Arcade_MiST/Konami Finalizer/Finalizr.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 00:21:03 December 03, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "00:21:03 December 03, 2019"
# Revisions
PROJECT_REVISION = "Finalizr"

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Arcade_MiST/Konami Finalizer/Finalizr.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 19:54:12 November 22, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Finalizr_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY Finalizer_MiST
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/tm.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# ------------------------------
# start ENTITY(Finalizer_MiST)
# Pin & Location Assignments
# ==========================
# Fitter Assignments
# ==================
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Finalizer_MiST)
# ----------------------------
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_MACRO "EXT_ROM=<None>"
set_global_assignment -name FORCE_SYNCH_CLEAR ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Finalizer_MiST.sv
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rom_loader.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/KONAMI1.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/k005885.sv
set_global_assignment -name VERILOG_FILE rtl/jtframe_frac_cen.v
set_global_assignment -name VERILOG_FILE rtl/jt49_dcrm2.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/finalizer_psg_lpf.sv
set_global_assignment -name VERILOG_FILE rtl/finalizer_lpf.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Finalizer.sv
set_global_assignment -name VHDL_FILE rtl/dpram_dc.vhd
set_global_assignment -name VERILOG_FILE rtl/audio_iir_filter.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name VHDL_FILE rtl/t8049_notri.vhd
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name VERILOG_FILE ../../common/CPU/MC6809/mc6809is.v
set_global_assignment -name QIP_FILE ../../common/Sound/sn76489/sn76489.qip
set_global_assignment -name QIP_FILE ../../common/CPU/t48/i8039.qip
set_global_assignment -name SIGNALTAP_FILE output_files/sdram.stp
set_global_assignment -name SIGNALTAP_FILE output_files/tm.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Arcade_MiST/Konami Finalizer/Finalizr.sdc Normal file
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## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

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Arcade_MiST/Konami Finalizer/README.md Normal file
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# MiST port of Konami Finalizer: Super Transformation by ACE
https://github.com/MiSTer-devel/Arcade-Finalizer_MiSTer
## Usage
- Create ROM and ARC files from the MRA files using the MRA utility.
Example: mra -A -z /path/to/mame/roms "Finalizer - Super Transformation (Set 1).mra"
- Copy the ROM files to the root of the SD Card
- Copy the RBF and ARC files to the same folder on the SD Card
- MRA utility: https://github.com/sebdel/mra-tools-c/

150
Arcade_MiST/Konami Finalizer/meta/Finalizer - Super Transformation (Set 1).mra Normal file
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<misterromdescription>
<name>Finalizer: Super Transformation</name>
<region>World</region>
<homebrew>no</homebrew>
<bootleg>no</bootleg>
<version>Set 1</version>
<alternative></alternative>
<platform></platform>
<series></series>
<year>1985</year>
<manufacturer>Konami</manufacturer>
<category>Shooter - Vertical</category>
<setname>finalizr</setname>
<parent>finalizr</parent>
<mameversion>0224</mameversion>
<rbf>Finalizr</rbf>
<about author="Ace" twitter="@Ace9921Tweets"></about>
<resolution>15kHz</resolution>
<rotation>no</rotation>
<flip>no</flip>
<players>2 (alternating)</players>
<joystick>8-way</joystick>
<special_controls></special_controls>
<num_buttons>3</num_buttons>
<buttons default="B,A,Start,R,Select,L" names="Fire 1,Fire 2/Shield,Start P1,Coin,Start P2,Pause"></buttons>
<switches default="00,25,00" base="8" page_id="1" page_name="Switches">
<dip bits="0,3" name="Credits A" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/7cr,1c/6cr,2c/1cr,2c/3cr,3c/1cr,2c/5cr,3c/2cr,3c/4cr,4c/3cr,4c/1cr,Free Play"/>
<dip bits="4,7" name="Credits B" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/6cr,1c/7cr,2c/1cr,2c/3cr,2c/5cr,3c/1cr,3c/2cr,3c/4cr,4c/1cr,4c/3cr,Free Play"/>
<dip bits="8,9" name="Lives" ids="2,3,4,7"/>
<dip bits="10" name="Cabinet Type" ids="Cocktail,Upright"/>
<dip bits="11,12" name="Bonus" ids="30K/150K+,50K/300K+,30K only,50K only"/>
<dip bits="13,14" name="Difficulty" ids="Easy,Normal,Hard,Hardest"/>
<dip bits="15" name="Attract Mode Sound" ids="Off,On"/>
<dip bits="16" name="Flip Screen" ids="Off,On"/>
<dip bits="17" name="Upright Controls" ids="Single,Dual"/>
<dip bits="18" name="Test Mode" ids="Off,On"/>
</switches>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" md5="none" type="merged" zip="finalizr.zip">
<part crc="716633cb" name="523k01.9c"/>
<part crc="1bccc696" name="523k02.12c"/>
<part crc="c48927c6" name="523k03.13c"/>
<part crc="c056d710" name="523h04.5e"/>
<part crc="50e512ba" name="523h07.5f"/>
<part crc="ae0d0f76" name="523h05.6e"/>
<part crc="79f44e17" name="523h08.6f"/>
<part crc="d2db9689" name="523h06.7e"/>
<part crc="8896dc85" name="523h09.7f"/>
<part crc="978dfc33" name="d8749hd.bin"/>
<patch offset="0x24000">
04 09 00 04 1E 00 00 04 E3 55 23 00 39 23 00 3A 23 80 3A 04 F3 BA 00 05 FA 04 C9 00 04 1B
C5 80 AA 23 00 3A 23 80 3A B8 08 23 18 A0 B8 09 23 00 A0 23 09 D7 04 36 93 8D 8F 91 93 95
97 97 97 97 97 97 97 97 97 97 97 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 9B 9D 9F
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AD A0 F0 6C 96 FC 18 F8 53 7F C6 EE 1D FD 37 17 AC FD E4 DB B8 20 B0 00 18 F8 53 7F C6 FA
E4 F0 04 15 15 00 E4 FC
</patch>
<part crc="4e0647a0" name="523h13.11f"/>
<part crc="53166a2a" name="523h12.10f"/>
<part crc="ec15dd15" name="523h10.2f"/>
<part crc="54be2e83" name="523h11.3f"/>
</rom>
<rom index="2"></rom>
<rom index="3" md5="none">
<part>
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</part>
</rom>
<nvram index="4" size="43"></nvram>
<remark></remark>
<mratimestamp>20210817165502</mratimestamp>
</misterromdescription>

78
Arcade_MiST/Konami Finalizer/meta/Finalizer - Super Transformation (Set 2) [bl].mra Normal file
View File

@@ -0,0 +1,78 @@
<misterromdescription>
<name>Finalizer: Super Transformation (bootleg)</name>
<region>World</region>
<homebrew>no</homebrew>
<bootleg>yes</bootleg>
<version>Set 2</version>
<alternative></alternative>
<platform></platform>
<series></series>
<year>1986</year>
<manufacturer>Konami</manufacturer>
<category>Shooter - Vertical</category>
<setname>finalizrb</setname>
<parent>finalizr</parent>
<mameversion>0224</mameversion>
<rbf>Finalizr</rbf>
<about author="Ace" twitter="@Ace9921Tweets"></about>
<resolution>15kHz</resolution>
<rotation>no</rotation>
<flip>no</flip>
<players>2 (alternating)</players>
<joystick>8-way</joystick>
<special_controls></special_controls>
<num_buttons>3</num_buttons>
<buttons default="B,A,Start,R,Select,L" names="Fire 1,Fire 2/Shield,Start P1,Coin,Start P2,Pause"></buttons>
<switches default="00,25,00" base="8" page_id="1" page_name="Switches">
<dip bits="0,3" name="Credits A" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/7cr,1c/6cr,2c/1cr,2c/3cr,3c/1cr,2c/5cr,3c/2cr,3c/4cr,4c/3cr,4c/1cr,Free Play"/>
<dip bits="4,7" name="Credits B" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/6cr,1c/7cr,2c/1cr,2c/3cr,2c/5cr,3c/1cr,3c/2cr,3c/4cr,4c/1cr,4c/3cr,Free Play"/>
<dip bits="8,9" name="Lives" ids="2,3,4,7"/>
<dip bits="10" name="Cabinet Type" ids="Cocktail,Upright"/>
<dip bits="11,12" name="Bonus" ids="20K/100K+,30K/150K+,20K only,30K only"/>
<dip bits="13,14" name="Difficulty" ids="Easy,Normal,Hard,Hardest"/>
<dip bits="15" name="Attract Mode Sound" ids="Off,On"/>
<dip bits="16" name="Flip Screen" ids="Off,On"/>
<dip bits="17" name="Upright Controls" ids="Single,Dual"/>
<dip bits="18" name="Test Mode" ids="Off,On"/>
</switches>
<rom index="1">
<part>0F</part>
</rom>
<rom index="0" md5="none" type="merged" zip="finalizr.zip|finalizrb.zip">
<part crc="a55e3f14" name="finalizrb/finalizr.5"/>
<part crc="ce177f6e" name="finalizra/3.13c"/>
<part crc="c056d710" name="523h04.5e"/>
<part crc="50e512ba" name="523h07.5f"/>
<part crc="ae0d0f76" name="523h05.6e"/>
<part crc="79f44e17" name="523h08.6f"/>
<part crc="d2db9689" name="523h06.7e"/>
<part crc="8896dc85" name="523h09.7f"/>
<part crc="978dfc33" name="d8749hd.bin"/>
<part crc="4e0647a0" name="523h13.11f"/>
<part crc="53166a2a" name="523h12.10f"/>
<part crc="ec15dd15" name="523h10.2f"/>
<part crc="54be2e83" name="523h11.3f"/>
</rom>
<rom index="2"></rom>
<rom index="3" md5="none">
<part>
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</part>
</rom>
<nvram index="4" size="43"></nvram>
<remark></remark>
<mratimestamp>20210817165502</mratimestamp>
</misterromdescription>

150
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@@ -0,0 +1,150 @@
<misterromdescription>
<name>Finalizer: Super Transformation (Set 2)</name>
<region>World</region>
<homebrew>no</homebrew>
<bootleg>no</bootleg>
<version>Set 2</version>
<alternative></alternative>
<platform></platform>
<series></series>
<year>1985</year>
<manufacturer>Konami</manufacturer>
<category>Shooter - Vertical</category>
<setname>finalizra</setname>
<parent>finalizr</parent>
<mameversion>0224</mameversion>
<rbf>Finalizr</rbf>
<about author="Ace" twitter="@Ace9921Tweets"></about>
<resolution>15kHz</resolution>
<rotation>no</rotation>
<flip>no</flip>
<players>2 (alternating)</players>
<joystick>8-way</joystick>
<special_controls></special_controls>
<num_buttons>3</num_buttons>
<buttons default="B,A,Start,R,Select,L" names="Fire 1,Fire 2/Shield,Start P1,Coin,Start P2,Pause"></buttons>
<switches default="00,25,00" base="8" page_id="1" page_name="Switches">
<dip bits="0,3" name="Credits A" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/7cr,1c/6cr,2c/1cr,2c/3cr,3c/1cr,2c/5cr,3c/2cr,3c/4cr,4c/3cr,4c/1cr,Free Play"/>
<dip bits="4,7" name="Credits B" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/6cr,1c/7cr,2c/1cr,2c/3cr,2c/5cr,3c/1cr,3c/2cr,3c/4cr,4c/1cr,4c/3cr,Free Play"/>
<dip bits="8,9" name="Lives" ids="2,3,4,7"/>
<dip bits="10" name="Cabinet Type" ids="Cocktail,Upright"/>
<dip bits="11,12" name="Bonus" ids="20K/100K+,30K/150K+,20K only,30K only"/>
<dip bits="13,14" name="Difficulty" ids="Easy,Normal,Hard,Hardest"/>
<dip bits="15" name="Attract Mode Sound" ids="Off,On"/>
<dip bits="16" name="Flip Screen" ids="Off,On"/>
<dip bits="17" name="Upright Controls" ids="Single,Dual"/>
<dip bits="18" name="Test Mode" ids="Off,On"/>
</switches>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" md5="none" type="merged" zip="finalizr.zip|finalizra.zip">
<part crc="7d464e5c" name="finalizra/1.9c"/>
<part crc="383dc94e" name="finalizra/2.12c"/>
<part crc="ce177f6e" name="finalizra/3.13c"/>
<part crc="c056d710" name="523h04.5e"/>
<part crc="50e512ba" name="523h07.5f"/>
<part crc="ae0d0f76" name="523h05.6e"/>
<part crc="79f44e17" name="523h08.6f"/>
<part crc="d2db9689" name="523h06.7e"/>
<part crc="8896dc85" name="523h09.7f"/>
<part crc="978dfc33" name="d8749hd.bin"/>
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D5 CF FF C5 96 00 B8 33 F0 D5 AF C5 B8 3E F0 96 8E F9 D5 6D C5 A9 D5 6A C6 6C 76 00 D5 FC
6B AC C5 AC AD D5 C9 F9 C5 96 00 B8 3D F0 D5 A9 C5 F9 D5 6E C5 A9 D5 68 C5 C6 79 B8 2C F0
AC AD D5 AC E4 00 23 00 E4 0B C5 B8 2D F0 D5 6E C5 A0 A9 D5 6A 96 42 C5 04 1B 18 F0 96 87
FC D5 6F F6 31 E4 00 FC D5 6F E6 31 E4 00 B8 31 F0 6F AF B8 32 60 C6 79 E4 37 B8 34 60 E4
A3 FC 76 9A 6F AC AD B8 35 F0 07 A0 96 00 18 F0 C8 A0 76 B5 B5 E4 00 A5 F9 D5 6D C5 A9 D5
6A C6 6C C5 B8 37 F0 07 A0 96 00 18 F0 C8 A0 E4 42 98 A3 34 F3 96 CE C4 EB B8 20 23 00 AC
AD A0 F0 6C 96 FC 18 F8 53 7F C6 EE 1D FD 37 17 AC FD E4 DB B8 20 B0 00 18 F8 53 7F C6 FA
E4 F0 04 15 15 00 E4 FC
</patch>
<part crc="4e0647a0" name="523h13.11f"/>
<part crc="53166a2a" name="523h12.10f"/>
<part crc="ec15dd15" name="523h10.2f"/>
<part crc="54be2e83" name="523h11.3f"/>
</rom>
<rom index="2"></rom>
<rom index="3" md5="none">
<part>
09 00 00 00 00 FF 00 02
00 02 00 01 00 FF 10 00
00 00 3C 08 00 01 00 00
00 00 3C 09 00 01 02 02
00 00 3C 0A 00 02 00 00
00 00 3B C0 00 27 00 12
</part>
</rom>
<nvram index="4" size="43"></nvram>
<remark></remark>
<mratimestamp>20210817165502</mratimestamp>
</misterromdescription>

572
Arcade_MiST/Konami Finalizer/rtl/Finalizer.sv Normal file
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//============================================================================
//
// Finalizer PCB model
// Copyright (C) 2021 Ace
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
//Module declaration, I/O ports
module Finalizer
(
input reset,
input clk_49m, //Actual frequency: 49.152MHz
input [1:0] coin,
input [1:0] btn_start, //1 = Player 2, 0 = Player 1
input [3:0] p1_joystick, p2_joystick, //3 = down, 2 = up, 1 = right, 0 = left
input [1:0] p1_buttons, p2_buttons, //2 buttons per player
input btn_service,
input [23:0] dipsw,
//The following flag is used to reconfigure the clock division applied to the Konami SND01 sound chip
//as while the original is clocked at 6.144MHz, bootleg boards clock this chip (replaced by a standard
//NEC uPD8749 MCU) at 9.216MHz
input [1:0] is_bootleg,
//Screen centering (alters HSync and VSync timing in the Konami 005885 to reposition the video output)
input [3:0] h_center, v_center,
output video_hsync, video_vsync, video_csync,
output video_vblank, video_hblank,
output [3:0] video_r, video_g, video_b,
output signed [15:0] sound,
input [24:0] ioctl_addr,
input [7:0] ioctl_data,
input ioctl_wr,
input pause,
input [11:0] hs_address,
input [7:0] hs_data_in,
output [7:0] hs_data_out,
input hs_write_enable,
input hs_access_read,
input hs_access_write,
//SDRAM signals
output reg [15:0] main_cpu_rom_addr,
input [7:0] main_cpu_rom_do,
output reg [15:1] char1_rom_addr,
input [15:0] char1_rom_do,
output sp1_req,
input sp1_ack,
output [16:1] sp1_rom_addr,
input [15:0] sp1_rom_do
);
//------------------------------------------------- MiSTer data write selector -------------------------------------------------//
//Instantiate MiSTer data write selector to generate write enables for loading ROMs into the FPGA's BRAM
wire ep1_cs_i, ep2_cs_i, ep3_cs_i, ep4_cs_i, ep5_cs_i, ep6_cs_i, ep7_cs_i, ep8_cs_i, ep9_cs_i, snd01_cs_i;
wire prom1_cs_i, prom2_cs_i, prom3_cs_i, prom4_cs_i;
selector DLSEL
(
.ioctl_addr(ioctl_addr),
.ep1_cs(ep1_cs_i),
.ep2_cs(ep2_cs_i),
.ep3_cs(ep3_cs_i),
.ep4_cs(ep4_cs_i),
.ep5_cs(ep5_cs_i),
.ep6_cs(ep6_cs_i),
.ep7_cs(ep7_cs_i),
.ep8_cs(ep8_cs_i),
.ep9_cs(ep9_cs_i),
.snd01_cs(snd01_cs_i),
.prom1_cs(prom1_cs_i),
.prom2_cs(prom2_cs_i),
.prom3_cs(prom3_cs_i),
.prom4_cs(prom4_cs_i)
);
//------------------------------------------------------- Clock division -------------------------------------------------------//
//Generate 6.144MHz, 3.072MHz and 1.576MHz clock enables (clock division is normally handled inside the Konami 005885)
//Also generate an extra clock enable for DC offset removal in the sound section
reg [6:0] div = 7'd0;
always_ff @(posedge clk_49m) begin
div <= div + 7'd1;
end
wire cen_6m = !div[2:0];
wire cen_3m = !div[3:0];
wire cen_1m5 = !div[4:0];
wire dcrm_cen = !div;
//Phase generator for KONAMI-1 (taken from MiSTer Vectrex core)
//Normally handled internally on the Konami 005885
reg k1_E = 0;
reg k1_Q = 0;
always_ff @(posedge clk_49m) begin
reg [1:0] clk_phase = 0;
k1_E <= 0;
k1_Q <= 0;
if(cen_6m) begin
clk_phase <= clk_phase + 1'd1;
case(clk_phase)
2'b01: k1_E <= 1;
2'b10: k1_Q <= 1;
endcase
end
end
//Use Jotego's fractional clock divider to generate a 9.216MHz clock enable for the Konami SND01 custom chip (to be used by bootlegs
//only)
wire cen_9m;
jtframe_frac_cen #(2) snd01_cen
(
.clk(clk_49m),
.n(10'd48),
.m(10'd256),
.cen({1'bZ, cen_9m})
);
//Select whether to clock the SND01 at 6.144MHz or 9.216MHz depending on whether a bootleg ROM set is loaded
wire cen_snd01 = (is_bootleg == 2'b11) ? cen_9m : cen_6m;
//------------------------------------------------------------ CPUs ------------------------------------------------------------//
//Main CPU (KONAMI-1 custom encrypted MC6809E - uses synchronous version of Greg Miller's cycle-accurate MC6809E made by
//Sorgelig with a wrapper to decrypt XOR/XNOR-encrypted opcodes and a further modification to Greg's MC6809E to directly
//accept the opcodes)
wire k1_rw;
wire [15:0] k1_A;
wire [7:0] k1_Din, k1_Dout;
KONAMI1 u13A
(
.CLK(clk_49m),
.fallE_en(k1_E),
.fallQ_en(k1_Q),
.D(k1_Din),
.DOut(k1_Dout),
.ADDR(k1_A),
.RnW(k1_rw),
.nIRQ(k1_irq),
.nFIRQ(k1_firq),
.nNMI(k1_nmi),
.nHALT(pause),
.nRESET(reset)
);
//Address decoding for data inputs to KONAMI-1
wire cs_k005885 = (k1_A[15:14] == 2'b00);
wire cs_dip3 = ~nioc & (k1_A[4:3] == 2'b00) & k1_rw;
wire cs_dip2 = ~nioc & (k1_A[4:3] == 2'b01) & k1_rw;
wire cs_controls_dip1 = ~nioc & (k1_A[4:3] == 2'b10) & k1_rw;
wire cs_sn76489 = ~nioc & (k1_A[4:0] == 5'b11010) & ~k1_rw;
wire cs_sn76489_latch = ~nioc & (k1_A[4:0] == 5'b11011) & ~k1_rw;
wire cs_snd01_irq = ~nioc & (k1_A[4:0] == 5'b11100) & ~k1_rw;
wire cs_snd01_latch = ~nioc & (k1_A[4:0] == 5'b11101) & ~k1_rw;
wire cs_rom1 = (k1_A[15:14] == 2'b01 & k1_rw);
wire cs_rom2 = (k1_A[15:14] == 2'b10 & k1_rw);
wire cs_rom3 = (k1_A[15:14] == 2'b11 & k1_rw);
//Multiplex data inputs to KONAMI-1
assign k1_Din = (cs_k005885 & nioc) ? k005885_Dout:
cs_dip3 ? {4'hF, dipsw[19:16]}:
cs_dip2 ? dipsw[15:8]:
cs_controls_dip1 ? controls_dip1:
cs_rom1 ? eprom1_D:
cs_rom2 ? eprom2_D:
cs_rom3 ? eprom3_D:
8'hFF;
//Game ROMs
`ifdef EXT_ROM
always_ff @(posedge clk_49m)
if (|k1_A[15:14] & k1_rw)
main_cpu_rom_addr <= k1_A[15:0] - 16'h4000;
wire [7:0] eprom1_D = main_cpu_rom_do;
wire [7:0] eprom2_D = main_cpu_rom_do;
wire [7:0] eprom3_D = main_cpu_rom_do;
`else
wire [7:0] eprom1_D, eprom2_D, eprom3_D;
eprom_1 u9C
(
.ADDR(k1_A[13:0]),
.CLK(clk_49m),
.DATA(eprom1_D),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
.CS_DL(ep1_cs_i),
.WR(ioctl_wr)
);
eprom_2 u12C
(
.ADDR(k1_A[13:0]),
.CLK(clk_49m),
.DATA(eprom2_D),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
.CS_DL(ep2_cs_i),
.WR(ioctl_wr)
);
eprom_3 u13C
(
.ADDR(k1_A[13:0]),
.CLK(clk_49m),
.DATA(eprom3_D),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
.CS_DL(ep3_cs_i),
.WR(ioctl_wr)
);
`endif
//--------------------------------------------------- Controls & DIP switches --------------------------------------------------//
//Multiplex player inputs and DIP switch bank 1 (Finalizer also expects to receive a VBlank on bit 7 along with the start buttons,
//service credit and coin inputs - invert as the game expects an active low VBlank here)
wire [7:0] controls_dip1 = (k1_A[1:0] == 2'b00) ? {~video_vblank, 2'b11, btn_start, btn_service, coin}:
(k1_A[1:0] == 2'b01) ? {2'b11, p1_buttons, p1_joystick}:
(k1_A[1:0] == 2'b10) ? {2'b11, p2_buttons, p2_joystick}:
(k1_A[1:0] == 2'b11) ? dipsw[7:0]:
8'hFF;
//--------------------------------------------------- Video timing & graphics --------------------------------------------------//
//Konami 005885 custom chip - this is a large ceramic pin-grid array IC responsible for the majority of Finalizer's critical
//functions: IRQ generation, clock dividers and all video logic for generating tilemaps and sprites
wire [15:0] tiles_A, sprites_A;
wire [7:0] k005885_Dout, tilemap_lut_A, sprite_lut_A;
wire [4:0] color_A;
wire k1_firq, k1_irq, k1_nmi, nioc;
k005885 u11E
(
.CK49(clk_49m),
.NRD(~k1_rw),
.A(k1_A[13:0]),
.DBi(k1_Dout),
.DBo(k005885_Dout),
.R(tiles_A),
.RDU(tiles_D[15:8]),
.RDL(tiles_D[7:0]),
.S(sprites_A),
.S_req(sp1_req),
.S_ack(sp1_ack),
.SDU(sprites_D[15:8]),
.SDL(sprites_D[7:0]),
.VCF(tilemap_lut_A[7:4]),
.VCB(tilemap_lut_A[3:0]),
.VCD(tilemap_lut_D),
.OCF(sprite_lut_A[7:4]),
.OCB(sprite_lut_A[3:0]),
.OCD(sprite_lut_D),
.COL(color_A),
.NEXR(reset),
.NXCS(~cs_k005885),
.NCSY(video_csync),
.NHSY(video_hsync),
.NVSY(video_vsync),
.HBLK(video_hblank),
.VBLK(video_vblank),
.NFIR(k1_firq),
.NIRQ(k1_irq),
.NNMI(k1_nmi),
.NIOC(nioc),
.HCTR(h_center),
.VCTR(v_center)
`ifdef MISTER_HISCORE
,
.hs_address(hs_address),
.hs_data_out(hs_data_out),
.hs_data_in(hs_data_in),
.hs_write_enable(hs_write_enable),
.hs_access_read(hs_access_read),
.hs_access_write(hs_access_write)
`endif
);
//Graphics ROMs
//Access tilemap ROMs for both the sprite and tilemap sections of the 005885 simultaneously as some of Finalizer's sprites fetch
//data from tilemap ROMs rather than sprite ROMs
//always_ff @(posedge clk_49m)
assign char1_rom_addr = tiles_A[13:0];
assign sp1_rom_addr = {sprites_A[15], ~sprites_A[15] & sprites_A[14], sprites_A[13:0]};
`ifdef EXT_ROM
wire [7:0] eprom4t_D = char1_rom_do[15:8];
wire [7:0] eprom4s_D = sp1_rom_do[15:8];
wire [7:0] eprom5t_D = char1_rom_do[7:0];
wire [7:0] eprom5s_D = sp1_rom_do[7:0];
wire [7:0] eprom6_D = sp1_rom_do[15:8];
wire [7:0] eprom7_D = sp1_rom_do[7:0];
wire [7:0] eprom8_D = sp1_rom_do[15:8];
wire [7:0] eprom9_D = sp1_rom_do[7:0];
`else
wire [7:0] eprom4t_D, eprom4s_D, eprom5t_D, eprom5s_D, eprom6_D, eprom7_D, eprom8_D, eprom9_D;
eprom_4 u5E
(
.ADDR_A(sprites_A[13:0]),
.CLK_A(~clk_49m),
.DATAOUT_A(eprom4s_D),
.ADDR_B(ep4_cs_i ? ioctl_addr : tiles_A[13:0]),
.CLK_B(clk_49m),
.DATA_IN(ioctl_data),
.DATAOUT_B(eprom4t_D),
.CS_DL(ep4_cs_i),
.WR(ioctl_wr)
);
eprom_5 u5F
(
.ADDR_A(sprites_A[13:0]),
.CLK_A(~clk_49m),
.DATAOUT_A(eprom5s_D),
.ADDR_B(ep5_cs_i ? ioctl_addr : tiles_A[13:0]),
.CLK_B(clk_49m),
.DATA_IN(ioctl_data),
.DATAOUT_B(eprom5t_D),
.CS_DL(ep5_cs_i),
.WR(ioctl_wr)
);
eprom_6 u6E
(
.ADDR(sprites_A[13:0]),
.CLK(~clk_49m),
.DATA(eprom6_D),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
.CS_DL(ep6_cs_i),
.WR(ioctl_wr)
);
eprom_7 u6F
(
.ADDR(sprites_A[13:0]),
.CLK(~clk_49m),
.DATA(eprom7_D),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
.CS_DL(ep7_cs_i),
.WR(ioctl_wr)
);
eprom_8 u7E
(
.ADDR(sprites_A[13:0]),
.CLK(~clk_49m),
.DATA(eprom8_D),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
.CS_DL(ep8_cs_i),
.WR(ioctl_wr)
);
eprom_9 u7F
(
.ADDR(sprites_A[13:0]),
.CLK(~clk_49m),
.DATA(eprom9_D),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
.CS_DL(ep9_cs_i),
.WR(ioctl_wr)
);
`endif
//Combine graphics ROM data outputs to 16 bits and multiplex sprite data
reg [15:0] tiles_D, sprites_D;
always @(*) begin
tiles_D <= {eprom4t_D, eprom5t_D};
case(sprites_A[15:14])
2'b00: sprites_D <= {eprom4s_D, eprom5s_D};
2'b01: sprites_D <= {eprom6_D, eprom7_D};
2'b10: sprites_D <= {eprom8_D, eprom9_D};
2'b11: sprites_D <= {eprom8_D, eprom9_D};
endcase
end
//Tilemap LUT PROM
wire [3:0] tilemap_lut_D;
prom_1 u11F
(
.ADDR(tilemap_lut_A),
.CLK(clk_49m),
.DATA(tilemap_lut_D),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
.CS_DL(prom1_cs_i),
.WR(ioctl_wr)
);
//Sprite LUT PROM
wire [3:0] sprite_lut_D;
prom_2 u10F
(
.ADDR(sprite_lut_A),
.CLK(clk_49m),
.DATA(sprite_lut_D),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
.CS_DL(prom2_cs_i),
.WR(ioctl_wr)
);
//--------------------------------------------------------- Sound chips --------------------------------------------------------//
//Generate chip enable for SN76489
wire n_sn76489_ce = (~cs_sn76489 & sn76489_ready);
//Latch data from KONAMI-1 to Konami SND01
reg [7:0] snd01_Din = 8'd0;
always_ff @(posedge clk_49m) begin
if(cen_3m && cs_snd01_latch)
snd01_Din <= k1_Dout;
end
//Latch data from KONAMI-1 to SN76489
reg [7:0] sn76489_D = 8'd0;
always_ff @(posedge clk_49m) begin
if(cen_3m && cs_sn76489_latch)
sn76489_D <= k1_Dout;
end
//Sound chip 1 (Texas Instruments SN76489 - uses Arnim Laeuger's SN76489 implementation with bugfixes)
wire [7:0] sn76489_raw;
wire sn76489_ready;
sn76489_top u7C
(
.clock_i(clk_49m),
.clock_en_i(cen_1m5),
.res_n_i(reset),
.ce_n_i(n_sn76489_ce),
.we_n_i(sn76489_ready),
.ready_o(sn76489_ready),
.d_i(sn76489_D),
.aout_o(sn76489_raw)
);
//Sound chip 2 (Konami SND01, a rebadged NEC uPD8749 MCU - uses a modified version of the t8049_notri variant of T48)
wire [7:0] snd01_raw;
wire [7:0] snd01_port2;
wire snd01_ale, n_snd01_psen, n_snd01_rd, n_snd01_irq_clr, snd01_timer_out;
t8049_notri u8A
(
.xtal_i(clk_49m),
.xtal_en_i(cen_snd01),
.reset_n_i(reset),
.t0_o(snd01_timer_out),
.int_n_i(n_snd01_irq),
.ea_i(0),
.db_i(snd01_Din),
.t1_i(snd01_timer_in),
.p2_o(snd01_port2),
.p1_o(snd01_raw),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
.CS_DL(snd01_cs_i),
.WR(ioctl_wr)
);
assign n_snd01_irq_clr = snd01_port2[7];
//Divide SND01 timer 0 output by 16 for the bootleg MCU timer and connect to the input of timer 1, otherwise pull this input low
reg [3:0] snd01_timer = 4'd0;
reg old_timer;
always_ff @(posedge clk_49m) begin
old_timer <= snd01_timer_out;
if(!old_timer && snd01_timer_out)
snd01_timer <= snd01_timer + 4'd1;
end
wire snd01_timer_in = snd01_timer[3];
//Generate SND01 IRQ
reg n_snd01_irq = 1;
always_ff @(posedge clk_49m) begin
if(!n_snd01_irq_clr)
n_snd01_irq <= 1;
else if(cen_3m && cs_snd01_irq)
n_snd01_irq <= 0;
end
//----------------------------------------------------- Final video output -----------------------------------------------------//
//Finalzer's video output consists of two color LUT PROMs providing 12-bit RGB, 4 bits per color
prom_3 u2F
(
.ADDR(color_A),
.CLK(clk_49m),
.DATA({video_g, video_r}),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
.CS_DL(prom3_cs_i),
.WR(ioctl_wr)
);
prom_4 u3F
(
.ADDR(color_A),
.CLK(clk_49m),
.DATA({4'bZZZZ, video_b}),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
.CS_DL(prom4_cs_i),
.WR(ioctl_wr)
);
//----------------------------------------------------- Final audio output -----------------------------------------------------//
//Remove DC offset from SN76489 and SND01 and apply gain to both
wire signed [15:0] sn76489_gain, snd01_gain;
jt49_dcrm2 #(16) dcrm_sn76489
(
.clk(clk_49m),
.cen(dcrm_cen),
.rst(~reset),
.din({1'd0, sn76489_raw, 7'd0}),
.dout(sn76489_gain)
);
jt49_dcrm2 #(16) dcrm_snd01
(
.clk(clk_49m),
.cen(dcrm_cen),
.rst(~reset),
.din({3'd0, snd01_raw, 5'd0}),
.dout(snd01_gain)
);
//Finalizer - Super Transformation uses a 3.386KHz low-pass filter for its SN76489 - apply this filtering here
wire signed [15:0] sn76489_lpf;
finalizer_psg_lpf psg_lpf
(
.clk(clk_49m),
.reset(~reset),
.in(sn76489_gain),
.out(sn76489_lpf)
);
//Mix the low-pass filtered output of the SN76489 with the SND01 and apply an extra low-pass filter on the mixed output to minimze
//aliasing
wire signed [15:0] sound_mix = sn76489_lpf + snd01_gain;
wire signed [15:0] sound_mix_aa;
finalizer_lpf lpf
(
.clk(clk_49m),
.reset(~reset),
.in(sound_mix),
.out(sound_mix_aa)
);
//Output the anti-aliased audio signal (mute when game is paused)
assign sound = pause ? sound_mix_aa : 16'd0;
endmodule

309
Arcade_MiST/Konami Finalizer/rtl/Finalizer_MiST.sv Normal file
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@@ -0,0 +1,309 @@
module Finalizer_MiST (
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"FINALIZR;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blend,Off,On;",
"O6,Joystick Swap,Off,On;",
"O7,Service,Off,On;",
"O1,Pause,Off,On;",
"DIP;",
"T0,Reset;",
"V,v1.00.",`BUILD_DATE
};
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire joyswap = status[6];
wire service = status[7];
wire pause = status[1];
wire [1:0] orientation = 2'b11;
wire [23:0] dip_sw = ~status[31:8];
wire [1:0] is_bootleg = core_mod[1:0];
assign LED = ~ioctl_downl;
assign SDRAM_CLK = clock_98;
assign SDRAM_CKE = 1;
wire clock_98, clock_49, pll_locked;
pll pll(
.inclk0(CLOCK_27),
.c0(clock_98),
.c1(clock_49),//49.152MHz
.locked(pll_locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire no_csync;
wire [6:0] core_mod;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
.clk_sys (clock_49 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.core_mod (core_mod ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
wire [15:0] main_rom_addr;
wire [15:0] main_rom_do;
wire [15:1] ch1_addr;
wire [15:0] ch1_do;
wire sp1_req, sp1_ack;
wire [16:1] sp1_addr;
wire [15:0] sp1_do;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
data_io data_io(
.clk_sys ( clock_49 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
wire [24:0] bg_ioctl_addr = ioctl_addr - 16'hC000;
reg port1_req, port2_req;
sdram #(98) sdram(
.*,
.init_n ( pll_locked ),
.clk ( clock_98 ),
// port1 for CPUs
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( ioctl_downl ? 16'h0000 : main_rom_addr[15:1] ),
.cpu1_q ( main_rom_do ),
// port2 for graphics
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( {bg_ioctl_addr[23:15], bg_ioctl_addr[13:0]} ), // merge gfx roms to 16-bit wide words
.port2_ds ( {~bg_ioctl_addr[14], bg_ioctl_addr[14]} ),
.port2_we ( ioctl_downl ),
.port2_d ( {ioctl_dout, ioctl_dout} ),
.port2_q ( ),
.ch1_addr ( ioctl_downl ? 16'hffff : ch1_addr ),
.ch1_q ( ch1_do ),
.sp1_req ( sp1_req ),
.sp1_ack ( sp1_ack ),
.sp1_addr ( ioctl_downl ? 16'hffff : sp1_addr ),
.sp1_q ( sp1_do )
);
// ROM download controller
always @(posedge clock_49) begin
reg ioctl_wr_last = 0;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
port1_req <= ~port1_req;
port2_req <= ~port2_req;
end
end
end
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clock_49) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ~rom_loaded;
end
wire [15:0] audio;
wire hs, vs, cs;
wire hblank, vblank;
wire blankn = ~(hblank | vblank);
wire [3:0] r, g, b;
//Instantiate Finalizer top-level module
Finalizer Finalizer_inst
(
.reset(~reset), // input reset
.clk_49m(clock_49), // input clk_49m
.coin({~m_coin2, ~m_coin1}), // input coin
.btn_service(~service), // input btn_service
.btn_start({~m_two_players, ~m_one_player}), // input [1:0] btn_start
.p1_joystick({~m_down, ~m_up, ~m_right, ~m_left}),
.p2_joystick({~m_down2, ~m_up2, ~m_right2, ~m_left2}),
.p1_buttons({~m_fireB, ~m_fireA}),
.p2_buttons({~m_fire2B, ~m_fire2A}),
.dipsw(dip_sw), // input [24:0] dipsw
.is_bootleg(is_bootleg), // Flag to reconfigure core for differences
// present on bootleg Finalizer PCBs
.sound(audio), // output [15:0] sound
.h_center(), // Screen centering
.v_center(),
.video_hsync(hs), // output video_hsync
.video_vsync(vs), // output video_vsync
.video_vblank(vblank), // output video_vblank
.video_hblank(hblank), // output video_hblank
.video_r(r), // output [4:0] video_r
.video_g(g), // output [4:0] video_g
.video_b(b), // output [4:0] video_b
.ioctl_addr(ioctl_addr),
.ioctl_wr(ioctl_wr && ioctl_index == 0),
.ioctl_data(ioctl_dout),
.pause(~pause),
.hs_address(hs_address),
.hs_data_out(hs_data_out),
.hs_data_in(hs_data_in),
.hs_write_enable(hs_write_enable),
.hs_access_read(hs_access_read),
.hs_access_write(hs_access_write),
.main_cpu_rom_addr(main_rom_addr),
.main_cpu_rom_do(main_rom_addr[0] ? main_rom_do[15:8] : main_rom_do[7:0]),
.char1_rom_addr(ch1_addr),
.char1_rom_do(ch1_do),
.sp1_req(sp1_req),
.sp1_ack(sp1_ack),
.sp1_rom_addr(sp1_addr),
.sp1_rom_do(sp1_do)
);
mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clock_49 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? r : 0 ),
.G ( blankn ? g : 0 ),
.B ( blankn ? b : 0 ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.ce_divider ( 0 ),
.rotate ( { orientation[1], rotate } ),
.blend ( blend ),
.scandoubler_disable( scandoublerD ),
.scanlines ( scanlines ),
.ypbpr ( ypbpr ),
.no_csync ( no_csync )
);
wire audio_out;
assign AUDIO_L = audio_out;
assign AUDIO_R = audio_out;
dac #(.C_bits(16))dac(
.clk_i(clock_49),
.res_n_i(1'b1),
.dac_i({~audio[15], audio[14:0]}),
.dac_o(audio_out)
);
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
arcade_inputs inputs (
.clk ( clock_49 ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( orientation ),
.joyswap ( joyswap ),
.oneplayer ( 1'b0 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
endmodule

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//============================================================================
//
// SystemVerilog implementation of the KONAMI-1 custom chip, a custom MC6809E
// variant with XOR/XNOR encryption
// Implements MC6809E core by Greg Miller (synchronous version modified by
// Sorgelig with further modifications to allow direct injection of opcodes)
// Copyright (C) 2021 Ace
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
module KONAMI1
(
input CLK,
input fallE_en,
input fallQ_en,
input [7:0] D,
output [7:0] DOut,
output [15:0] ADDR,
output RnW,
output BS,
output BA,
input nIRQ,
input nFIRQ,
input nNMI,
output AVMA,
output BUSY,
output LIC,
input nHALT,
input nRESET
);
//Decrypt XOR/XNOR encrypted opcode
wire [7:0] opcode = D ^ {ADDR[1], 1'b0, ~ADDR[1], 1'b0, ADDR[3], 1'b0, ~ADDR[3], 1'b0};
//Passthrough to modified MC6809is core with direct opcode injection and IS_KONAMI1 parameter set
//to TRUE
mc6809is #(.IS_KONAMI1("TRUE")) cpucore
(
.CLK(CLK),
.fallE_en(fallE_en),
.fallQ_en(fallQ_en),
.OP(opcode),
.nHALT(nHALT),
.nRESET(nRESET),
.D(D),
.DOut(DOut),
.ADDR(ADDR),
.RnW(RnW),
.BS(BS),
.BA(BA),
.nIRQ(nIRQ),
.nFIRQ(nFIRQ),
.nNMI(nNMI),
.AVMA(AVMA),
.BUSY(BUSY),
.LIC(LIC),
.nDMABREQ(1)
);
endmodule

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/*MIT License
Copyright (c) 2019 Gregory Hogan (Soltan_G42)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.*/
module iir_1st_order
#(
parameter COEFF_WIDTH = 18,
parameter COEFF_SCALE = 15,
parameter DATA_WIDTH = 16,
parameter COUNT_BITS = 10
)
(
input clk,
input reset,
input [COUNT_BITS - 1 : 0] div,
input signed [COEFF_WIDTH - 1 : 0] A2, B1, B2,
input signed [DATA_WIDTH - 1 :0] in,
output [DATA_WIDTH - 1:0] out
);
reg signed [DATA_WIDTH-1:0] x0,x1,y0;
reg signed [DATA_WIDTH + COEFF_WIDTH - 1 : 0] out32;
reg [COUNT_BITS - 1:0] count;
// Usage:
// Design your 1st order iir low/high-pass with a tool that will give you the
// filter coefficients for the difference equation. Filter coefficients can
// be generated in Octave/matlab/scipy using a command similar to
// [B, A] = butter( 1, 3500/(106528/2), 'low') for a 3500 hz 1st order low-pass
// assuming 106528Hz sample rate.
//
// The Matlab output is:
// B = [0.093863 0.093863]
// A = [1.00000 -0.81227]
//
// Then scale coefficients by multiplying by 2^COEFF_SCALE and round to nearest integer
//
// B = [3076 3076]
// A = [32768 -26616]
//
// Discard A(1) because it is assumed 1.0 before scaling
//
// This leaves you with A2 = -26616 , B1 = 3076 , B2 = 3076
// B1 + B2 - A2 should sum to 2^COEFF_SCALE = 32768
//
// Sample frequency is "clk rate/div": for Genesis this is 53.69mhz/504 = 106528hz
//
// COEFF_WIDTH must be at least COEFF_SCALE+1 and must be large enough to
// handle temporary overflow during this computation: out32 <= (B1*x0 + B2*x1) - A2*y0
assign out = y0;
always @ (*) begin
out32 <= (B1*x0 + B2*x1) - A2*y0; //Previous output is y0 not y1
end
always @ (posedge clk) begin
if(reset) begin
count <= 0;
x0 <= 0;
x1 <= 0;
y0 <= 0;
end
else begin
count <= count + 1'd1;
if (count == div - 1) begin
count <= 0;
y0 <= {out32[DATA_WIDTH + COEFF_WIDTH - 1] , out32[COEFF_SCALE + DATA_WIDTH - 2 : COEFF_SCALE]};
x1 <= x0;
x0 <= in;
end
end
end
endmodule //iir_1st_order
module iir_2nd_order
#(
parameter COEFF_WIDTH = 18,
parameter COEFF_SCALE = 14,
parameter DATA_WIDTH = 16,
parameter COUNT_BITS = 10
)
(
input clk,
input reset,
input [COUNT_BITS - 1 : 0] div,
input signed [COEFF_WIDTH - 1 : 0] A2, A3, B1, B2, B3,
input signed [DATA_WIDTH - 1 : 0] in,
output [DATA_WIDTH - 1 : 0] out
);
reg signed [DATA_WIDTH-1 : 0] x0,x1,x2;
reg signed [DATA_WIDTH-1 : 0] y0,y1;
reg signed [(DATA_WIDTH + COEFF_WIDTH - 1) : 0] out32;
reg [COUNT_BITS : 0] count;
// Usage:
// Design your 1st order iir low/high-pass with a tool that will give you the
// filter coefficients for the difference equation. Filter coefficients can
// be generated in Octave/matlab/scipy using a command similar to
// [B, A] = butter( 2, 5000/(48000/2), 'low') for a 5000 hz 2nd order low-pass
// assuming 48000Hz sample rate.
//
// Output is:
// B = [ 0.072231 0.144462 0.072231]
// A = [1.00000 -1.10923 0.39815]
//
// Then scale coefficients by multiplying by 2^COEFF_SCALE and round to nearest integer
// Make sure your coefficients can be stored as a signed number with COEFF_WIDTH bits.
//
// B = [1183 2367 1183]
// A = [16384 -18174 6523]
//
// Discard A(1) because it is assumed 1.0 before scaling
//
// This leaves you with A2 = -18174 , A3 = 6523, B1 = 1183 , B2 = 2367 , B3 = 1183
// B1 + B2 + B3 - A2 - A3 should sum to 2^COEFF_SCALE = 16384
//
// Sample frequency is "clk rate/div"
//
// COEFF_WIDTH must be at least COEFF_SCALE+1 and must be large enough to
// handle temporary overflow during this computation:
// out32 <= (B1*x0 + B2*x1 + B3*x2) - (A2*y0 + A3*y1);
assign out = y0;
always @ (*) begin
out32 <= (B1*x0 + B2*x1 + B3*x2) - (A2*y0 + A3*y1); //Previous output is y0 not y1
end
always @ (posedge clk) begin
if(reset) begin
count <= 0;
x0 <= 0;
x1 <= 0;
x2 <= 0;
y0 <= 0;
y1 <= 0;
end
else begin
count <= count + 1'd1;
if (count == div - 1) begin
count <= 0;
y1 <= y0;
y0 <= {out32[DATA_WIDTH + COEFF_WIDTH - 1] , out32[(DATA_WIDTH + COEFF_SCALE - 2) : COEFF_SCALE]};
x2 <= x1;
x1 <= x0;
x0 <= in;
end
end
end
endmodule //iir_2nd_order

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram_dc IS
GENERIC
(
init_file : string := " ";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0) := (others => '0');
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) := (others => '0');
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) := (others => '0');
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
byteena_a : IN STD_LOGIC_VECTOR (width_a/8-1 DOWNTO 0) := (others => '1');
byteena_b : IN STD_LOGIC_VECTOR (width_a/8-1 DOWNTO 0) := (others => '1');
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END dpram_dc;
ARCHITECTURE SYN OF dpram_dc IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (width_a/8-1 DOWNTO 0) ;
byteena_b : IN STD_LOGIC_VECTOR (width_a/8-1 DOWNTO 0) ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(width_a-1 DOWNTO 0);
q_b <= sub_wire1(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_a,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
widthad_b => widthad_a,
width_a => width_a,
width_b => width_a,
width_byteena_a => width_a/8,
width_byteena_b => width_a/8,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1,
byteena_a => byteena_a,
byteena_b => byteena_b
);
END SYN;

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/*MIT License
Copyright (c) 2019 Gregory Hogan (Soltan_G42)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.*/
//This is a variation of Gregory Hogan's MISTer Genesis core low-pass filter
//tuned to remove aliasing on Finalizer - Super Transformation.
module finalizer_lpf(
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out);
localparam [9:0] div = 128; //Sample at 49.152MHz/128 = 384000Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.045425748, 0.045425748
//1.0000000, -0.90914850
reg signed [17:0] A2;
reg signed [17:0] B2;
reg signed [17:0] B1;
wire signed [15:0] audio_post_lpf1;
always @ (*) begin
A2 = -18'd18211;
B1 = 18'd7278;
B2 = 18'd7278;
end
iir_1st_order lpf6db(.clk(clk),
.reset(reset),
.div(div),
.A2(A2),
.B1(B1),
.B2(B2),
.in(in),
.out(audio_post_lpf1));
assign out = audio_post_lpf1;
endmodule

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/*MIT License
Copyright (c) 2019 Gregory Hogan (Soltan_G42)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.*/
//This is a variation of Gregory Hogan's MISTer Genesis core low-pass filter
//tuned to low-pass filter the SN76489 on Finalizer - Super Transformation.
module finalizer_psg_lpf(
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out);
localparam [9:0] div = 128; //Sample at 49.152MHz/128 = 384000Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.052545856, 0.052545856
//1.0000000, -0.89490829
reg signed [17:0] A2;
reg signed [17:0] B2;
reg signed [17:0] B1;
wire signed [15:0] audio_post_lpf1;
always @ (*) begin
A2 = -18'd29324;
B1 = 18'd1722;
B2 = 18'd1722;
end
iir_1st_order lpf6db(.clk(clk),
.reset(reset),
.div(div),
.A2(A2),
.B1(B1),
.B2(B2),
.in(in),
.out(audio_post_lpf1));
assign out = audio_post_lpf1;
endmodule

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/* This file is part of JT49.
JT49 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT49 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT49. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 15-Jan-2019
*/
// DC removal filter
// input is unsigned
// output is signed
module jt49_dcrm2 #(parameter sw=8) (
input clk,
input cen,
input rst,
input [sw-1:0] din,
output signed [sw-1:0] dout
);
localparam dw=10; // widht of the decimal portion
reg signed [sw+dw:0] integ, exact, error;
//reg signed [2*(9+dw)-1:0] mult;
// wire signed [sw+dw:0] plus1 = { {sw+dw{1'b0}},1'b1};
reg signed [sw:0] pre_dout;
// reg signed [sw+dw:0] dout_ext;
reg signed [sw:0] q;
always @(*) begin
exact = integ+error;
q = exact[sw+dw:dw];
pre_dout = { 1'b0, din } - q;
//dout_ext = { pre_dout, {dw{1'b0}} };
//mult = dout_ext;
end
assign dout = pre_dout[sw-1:0];
always @(posedge clk)
if( rst ) begin
integ <= {sw+dw+1{1'b0}};
error <= {sw+dw+1{1'b0}};
end else if( cen ) begin
integ <= integ + pre_dout; //mult[sw+dw*2:dw];
error <= exact-{q, {dw{1'b0}}};
end
endmodule

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///////////////////////////////////////////////////////////////////////////
// Fractional clock enable signal
// W refers to the number of divided down cen signals available
// each one is divided by 2
module jtframe_frac_cen #(parameter W=2)(
input clk,
input [9:0] n, // numerator
input [9:0] m, // denominator
output reg [W-1:0] cen,
output reg [W-1:0] cenb // 180 shifted
);
wire [10:0] step={1'b0,n};
wire [10:0] lim ={1'b0,m};
wire [10:0] absmax = lim+step;
reg [10:0] cencnt=11'd0;
reg [10:0] next;
reg [10:0] next2;
always @(*) begin
next = cencnt+step;
next2 = next-lim;
end
reg half = 1'b0;
wire over = next>=lim;
wire halfway = next >= (lim>>1) && !half;
reg [W-1:0] edgecnt = {W{1'b0}};
wire [W-1:0] next_edgecnt = edgecnt + 1'b1;
wire [W-1:0] toggle = next_edgecnt & ~edgecnt;
always @(posedge clk) begin
cen <= {W{1'b0}};
cenb <= {W{1'b0}};
if( cencnt >= absmax ) begin
// something went wrong: restart
cencnt <= 11'd0;
end else
if( halfway ) begin
half <= 1'b1;
cenb[0] <= 1'b1;
end
if( over ) begin
cencnt <= next2;
half <= 1'b0;
edgecnt <= next_edgecnt;
cen <= { toggle[W-2:0], 1'b1 };
end else begin
cencnt <= next;
end
end
endmodule

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//============================================================================
//
// SystemVerilog implementation of the Konami 005885 custom tilemap
// generator
// Graphics logic based on the video section of the Green Beret core for
// MiSTer by MiSTer-X
// Copyright (C) 2020, 2022 Ace
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
//Note: This model of the 005885 cannot be used as-is to replace an original 005885.
module k005885
(
input CK49, //49.152MHz clock input
output NCK2, //6.144MHz clock output
output H1O, //3.072MHz clock output
output NCPE, //E clock for MC6809E
output NCPQ, //Q clock for MC6809E
output NEQ, //AND of E and Q clocks for MC6809E
input NRD, //Read enable (active low)
output NRES, //Reset passthrough
input [13:0] A, //Address bus from CPU
input [7:0] DBi, //Data bus input from CPU
output [7:0] DBo, //Data output to CPU
output [3:0] VCF, //Color address to tilemap LUT PROM
output [3:0] VCB, //Tile index to tilemap LUT PROM
input [3:0] VCD, //Data input from tilemap LUT PROM
output [3:0] OCF, //Color address to sprite LUT PROM
output [3:0] OCB, //Sprite index to sprite LUT PROM
input [3:0] OCD, //Data input from sprite LUT PROM
output [4:0] COL, //Color data output from color mixer
input NEXR, //Reset input (active low)
input NXCS, //Chip select (active low)
output NCSY, //Composite sync (active low)
output NHSY, //HSync (active low) - Not exposed on the original chip
output NVSY, //VSync (active low)
output HBLK, //HBlank (active high) - Not exposed on the original chip
output VBLK, //VBlank (active high) - Not exposed on the original chip
input NBUE, //Unknown
output NFIR, //Fast IRQ (FIRQ) output for MC6809E
output NIRQ, //IRQ output for MC6809E (VBlank IRQ)
output NNMI, //Non-maskable IRQ (NMI) for MC6809E
output NIOC, //Inverse of address line A11 for external address decoding logic
output NRMW,
//Split I/O for tile and sprite data
output [15:0] R, //Address output to graphics ROMs (tiles)
input [7:0] RDU, //Upper 8 bits of graphics ROM data (tiles)
input [7:0] RDL, //Lower 8 bits of graphics ROM data (tiles)
output [15:0] S, //Address output to graphics ROMs (sprites)
output reg S_req = 0,
input S_ack,
input [7:0] SDU, //Upper 8 bits of graphics ROM data (sprites)
input [7:0] SDL, //Lower 8 bits of graphics ROM data (sprites)
//Extra inputs for screen centering (alters HSync and VSync timing to reposition the video output)
input [3:0] HCTR, VCTR,
//Special flag for reconfiguring the chip to mimic the anomalies found on bootlegs of games that use the 005885
//Valid values:
//-00: Original behavior
//-01: Jackal bootleg (faster video timings, missing 4 lines from the video signal, misplaced HBlank, altered screen
// centering, sprite layer is missing one line per sprite, sprite layer is misplaced by one line when the screen is
// flipped)
//-10: Iron Horse bootleg (10 extra vertical lines resulting in slower VSync, altered screen centering, sprite layer is
// offset vertically by 1 line, sprite limit significantly lower than normal)
input [1:0] BTLG,
//Extra data outputs for graphics ROMs
output reg ATR4, //Tilemap attribute bit 4
output reg ATR5 //Tilemap attribute bit 5
`ifdef MISTER_HISCORE
//MiSTer high score system I/O (to be used only with Iron Horse)
,
input [11:0] hs_address,
input [7:0] hs_data_in,
output [7:0] hs_data_out,
input hs_write_enable,
input hs_access_read,
input hs_access_write
`endif
);
//------------------------------------------------------- Signal outputs -------------------------------------------------------//
//Reset line passthrough
assign NRES = NEXR;
//Generate NIOC output (active low)
assign NIOC = ~(~NXCS & (A[13:11] == 3'b001));
//TODO: The timing of the NRMW output is currently unknown - set to 1 for now
assign NRMW = 1;
//Output bits 4 and 5 of tilemap attributes for graphics ROM addressing
/*
assign ATR4 = tile_ctrl[2] ? tile_attrib_D[4] : tile0_attrib_D[4];
assign ATR5 = tile_ctrl[2] ? tile_attrib_D[5] : tile0_attrib_D[5];
*/
//Data output to CPU
assign DBo = (ram_cs & ~NRD) ? ram_Dout:
(zram0_cs & ~NRD) ? zram0_Dout:
(zram1_cs & ~NRD) ? zram1_Dout:
(zram2_cs & ~NRD) ? zram2_Dout:
(tile_attrib_cs & ~NRD) ? tile0_attrib_Dout:
(tile_cs & ~NRD) ? tile0_Dout:
(tile1_attrib_cs & ~NRD) ? tile1_attrib_Dout:
(tile1_cs & ~NRD) ? tile1_Dout:
(spriteram_cs & ~NRD) ? spriteram_Dout:
8'hFF;
//------------------------------------------------------- Clock division -------------------------------------------------------//
//Divide the incoming 49.152MHz clock to 6.144MHz and 3.072MHz
reg [3:0] div = 4'd0;
always_ff @(posedge CK49) begin
div <= div + 4'd1;
end
wire cen_6m = !div[2:0];
wire cen_3m = !div;
assign NCK2 = div[2];
assign H1O = div[3];
//The MC6809E requires two identical clocks with a 90-degree offset - assign these here
reg mc6809e_E = 0;
reg mc6809e_Q = 0;
always_ff @(posedge CK49) begin
reg [1:0] clk_phase = 0;
if(cen_6m) begin
clk_phase <= clk_phase + 1'd1;
case(clk_phase)
2'b00: mc6809e_E <= 0;
2'b01: mc6809e_Q <= 1;
2'b10: mc6809e_E <= 1;
2'b11: mc6809e_Q <= 0;
endcase
end
end
assign NCPQ = mc6809e_Q;
assign NCPE = mc6809e_E;
//Output NEQ combines NCPE and NCPQ together via an AND gate - assign this here
assign NEQ = NCPE & NCPQ;
//-------------------------------------------------------- Video timings -------------------------------------------------------//
//The 005885's video output has 384 horziontal lines and 262 vertical lines with an active resolution of 240x224. Declare both
//counters as 9-bit registers.
reg [8:0] h_cnt = 9'd0;
reg [8:0] v_cnt = 9'd0;
//Increment horizontal counter on every falling edge of the pixel clock and increment vertical counter when horizontal counter
//rolls over
reg hblank = 0;
reg vblank = 0;
reg frame_odd_even = 0;
//Add an extra 10 lines to the vertical counter if a bootleg Iron Horse ROM set is loaded or remove 9 lines from the vertical
//counter if a bootleg Jackal ROM set is loaded
reg [8:0] vcnt_end = 0;
always_ff @(posedge CK49) begin
if(cen_6m) begin
if(BTLG == 2'b01)
vcnt_end <= 9'd252;
else if(BTLG == 2'b10)
vcnt_end <= 9'd271;
else
vcnt_end <= 9'd261;
end
end
//Reposition HSync and VSync if a bootleg Iron Horse or Jackal ROM set is loaded
reg [8:0] hsync_start = 9'd0;
reg [8:0] hsync_end = 9'd0;
reg [8:0] vsync_start = 9'd0;
reg [8:0] vsync_end = 9'd0;
always_ff @(posedge CK49) begin
if(BTLG == 2'b01) begin
hsync_start <= HCTR[3] ? 9'd287 : 9'd295;
hsync_end <= HCTR[3] ? 9'd318 : 9'd326;
vsync_start <= 9'd244;
vsync_end <= 9'd251;
end
else if(BTLG == 2'b10) begin
hsync_start <= HCTR[3] ? 9'd290 : 9'd310;
hsync_end <= HCTR[3] ? 9'd321 : 9'd341;
vsync_start <= 9'd255;
vsync_end <= 9'd262;
end
else if(tile_ctrl[2]) begin
hsync_start <= HCTR[3] ? 9'd312 : 9'd320;
hsync_end <= HCTR[3] ? 9'd343 : 9'd351;
vsync_start <= 9'd254;
vsync_end <= 9'd261;
end
else begin
hsync_start <= HCTR[3] ? 9'd288 : 9'd296;
hsync_end <= HCTR[3] ? 9'd319 : 9'd327;
vsync_start <= 9'd254;
vsync_end <= 9'd261;
end
end
always_ff @(posedge CK49) begin
if(cen_6m) begin
case(h_cnt)
//HBlank ends two lines earlier than normal on bootleg Jackal PCBs
10: begin
if(BTLG == 2'b01)
hblank <= 0;
h_cnt <= h_cnt + 9'd1;
end
12: begin
if(BTLG != 2'b01)
hblank <= 0;
h_cnt <= h_cnt + 9'd1;
end
//Shift the start of HBlank two lines earlier when bootleg Jackal ROMs are loaded
250: begin
if(BTLG == 2'b01 && !tile_ctrl[2])
hblank <= 1;
h_cnt <= h_cnt + 9'd1;
end
252: begin
if(BTLG != 2'b01 && !tile_ctrl[2])
hblank <= 1;
h_cnt <= h_cnt + 9'd1;
end
//Shift the start of HBlank 40 lines later when using the wider 280x224 video mode
292: begin
if(tile_ctrl[2])
hblank <= 1;
h_cnt <= h_cnt + 9'd1;
end
383: begin
h_cnt <= 0;
case(v_cnt)
15: begin
vblank <= 0;
v_cnt <= v_cnt + 9'd1;
end
239: begin
vblank <= 1;
frame_odd_even <= ~frame_odd_even;
v_cnt <= v_cnt + 9'd1;
end
vcnt_end: begin
v_cnt <= 9'd0;
end
default: v_cnt <= v_cnt + 9'd1;
endcase
end
default: h_cnt <= h_cnt + 9'd1;
endcase
end
end
//Output HBlank and VBlank (both active high)
assign HBLK = hblank;
assign VBLK = vblank;
//Generate horizontal sync and vertical sync (both active low)
assign NHSY = HCTR[3] ? ~(h_cnt >= hsync_start - ~HCTR[2:0] && h_cnt <= hsync_end - ~HCTR[2:0]):
~(h_cnt >= hsync_start + HCTR[2:0] && h_cnt <= hsync_end + HCTR[2:0]);
assign NVSY = ~(v_cnt >= vsync_start - VCTR && v_cnt <= vsync_end - VCTR);
assign NCSY = NHSY ^ NVSY;
//------------------------------------------------------------- IRQs -----------------------------------------------------------//
//Edge detection for VBlank and vertical counter bits 4 and 5 for IRQ generation
reg old_vblank, old_vcnt4, old_vcnt5;
always_ff @(posedge CK49) begin
old_vcnt4 <= v_cnt[4];
old_vcnt5 <= v_cnt[5];
old_vblank <= vblank;
end
//IRQ (triggers every VBlank)
reg vblank_irq = 1;
always_ff @(posedge CK49) begin
if(!NEXR || !irq_mask)
vblank_irq <= 1;
else if(!old_vblank && vblank)
vblank_irq <= 0;
end
assign NIRQ = vblank_irq;
//NMI (triggers on the falling edge of vertical counter bits 4 or 5 based on the state of tile control register bit 2)
reg nmi = 1;
always_ff @(posedge CK49) begin
if(!NEXR || !nmi_mask)
nmi <= 1;
else begin
if(tile_ctrl[2]) begin
if(old_vcnt4 && !v_cnt[4])
nmi <= 0;
end
else begin
if(old_vcnt5 && !v_cnt[5])
nmi <= 0;
end
end
end
assign NNMI = nmi;
//FIRQ (triggers every second VBlank)
reg firq = 1;
always_ff @(posedge CK49) begin
if(!NEXR || !firq_mask)
firq <= 1;
else begin
if(frame_odd_even && !old_vblank && vblank)
firq <= 0;
end
end
assign NFIR = firq;
//----------------------------------------------------- Internal registers -----------------------------------------------------//
//The 005885 has five 8-bit registers set up as follows according to information in konamiic.txt found in MAME's source code:
/*
control registers
000: scroll y
001: scroll x (low 8 bits)
002: -------x scroll x (high bit)
----xxx- row/colscroll control
000 = solid scroll (finalizr, ddribble bg)
100 = solid scroll (jackal)
001 = ? (ddribble fg)
011 = colscroll (jackal high scores)
101 = rowscroll (ironhors, jackal map)
003: ------xx high bits of the tile code
-----x-- unknown (finalizr)
----x--- selects sprite buffer (and makes a copy to a private buffer?)
--x----- unknown (ironhors)
-x------ unknown (ironhors)
x------- unknown (ironhors, jackal)
004: -------x nmi enable
------x- irq enable
-----x-- firq enable
----x--- flip screen
*/
wire regs_cs = ~NXCS & (A[13:11] == 2'b00) & (A[6:3] == 4'd0);
reg [7:0] scroll_y, scroll_x, scroll_ctrl, tile_ctrl;
reg nmi_mask = 0;
reg irq_mask = 0;
reg firq_mask = 0;
reg flipscreen = 0;
//Write to the appropriate register
always_ff @(posedge CK49) begin
reg rightD, leftD, upD;
if(cen_3m) begin
if(regs_cs && NRD)
case(A[2:0])
3'b000: scroll_y <= DBi;
3'b001: scroll_x <= DBi;
3'b010: scroll_ctrl <= DBi;
3'b011: tile_ctrl <= DBi;
3'b100: begin
nmi_mask <= DBi[0];
irq_mask <= DBi[1];
firq_mask <= DBi[2];
flipscreen <= DBi[3];
end
default;
endcase
end
end
//--------------------------------------------------------- Unknown RAM --------------------------------------------------------//
wire ram_cs = ~NXCS & (A >= 14'h0005 && A <= 14'h001F);
wire [7:0] ram_Dout;
spram #(8, 5) RAM
(
.clk(CK49),
.we(ram_cs & NRD),
.addr(A[4:0]),
.data(DBi),
.q(ram_Dout)
);
//-------------------------------------------------------- Internal ZRAM -------------------------------------------------------//
wire zram0_cs = ~NXCS & (A >= 16'h0020 && A <= 16'h003F);
wire zram1_cs = ~NXCS & (A >= 16'h0040 && A <= 16'h005F);
wire zram2_cs = ~NXCS & (A >= 16'h0060 && A <= 16'h00DF);
//The 005885 addresses ZRAM with either horizontal or vertical position bits depending on whether its scroll mode is set to
//line scroll or column scroll - use vertical position bits for line scroll and horizontal position bits for column scroll,
//otherwise don't address it
wire [4:0] zram_A = (scroll_ctrl[3:1] == 3'b101) ? tilemap_vpos[7:3]:
(scroll_ctrl[3:1] == 3'b011) ? tilemap_hpos[7:3]:
5'h00;
wire [7:0] zram0_D, zram1_D, zram2_D, zram0_Dout, zram1_Dout, zram2_Dout;
dpram_dc #(.widthad_a(5)) ZRAM0
(
.clock_a(CK49),
.address_a(A[4:0]),
.data_a(DBi),
.q_a(zram0_Dout),
.wren_a(zram0_cs & NRD),
.clock_b(CK49),
.address_b(zram_A),
.q_b(zram0_D)
);
spram #(8, 5) ZRAM1
(
.clk(CK49),
.we(zram1_cs & NRD),
.addr(A[4:0]),
.data(DBi),
.q(zram1_Dout)
);
spram #(8, 5) ZRAM2
(
.clk(CK49),
.we(zram2_cs & NRD),
.addr(A[4:0]),
.data(DBi),
.q(zram2_Dout)
);
//------------------------------------------------------------ VRAM ------------------------------------------------------------//
//VRAM is external to the 005885 and combines multiple banks into a single 8KB RAM chip for tile attributes and data (two layers),
//and two sprite banks. For simplicity, this RAM has been made internal to the 005885 implementation and split into its
//constituent components.
wire tile_attrib_cs = ~NXCS & (A[13:10] == 4'b1000);
wire tile_cs = ~NXCS & (A[13:10] == 4'b1001);
wire tile1_attrib_cs = ~NXCS & (A[13:10] == 4'b1010);
wire tile1_cs = ~NXCS & (A[13:10] == 4'b1011);
wire spriteram_cs = ~NXCS & (A[13:12] == 2'b11);
wire [7:0] tile0_attrib_Dout, tile0_Dout, tile1_attrib_Dout, tile1_Dout, spriteram_Dout;
wire [7:0] tile0_attrib_D, tile0_D, tile1_attrib_D, tile1_D, spriteram_D;
//Tilemap layer 0
dpram_dc #(.widthad_a(10)) VRAM_TILEATTRIB0
(
.clock_a(CK49),
.address_a(A[9:0]),
.data_a(DBi),
.q_a(tile0_attrib_Dout),
.wren_a(tile_attrib_cs & NRD),
.clock_b(CK49),
.address_b(vram_A),
.q_b(tile0_attrib_D)
);
dpram_dc #(.widthad_a(10)) VRAM_TILECODE0
(
.clock_a(CK49),
.address_a(A[9:0]),
.data_a(DBi),
.q_a(tile0_Dout),
.wren_a(tile_cs & NRD),
.clock_b(CK49),
.address_b(vram_A),
.q_b(tile0_D)
);
//Tilemap layer 1
dpram_dc #(.widthad_a(10)) VRAM_TILEATTRIB1
(
.clock_a(CK49),
.address_a(A[9:0]),
.data_a(DBi),
.q_a(tile1_attrib_Dout),
.wren_a(tile1_attrib_cs & NRD),
.clock_b(CK49),
.address_b(vram_A),
.q_b(tile1_attrib_D)
);
dpram_dc #(.widthad_a(10)) VRAM_TILECODE1
(
.clock_a(CK49),
.address_a(A[9:0]),
.data_a(DBi),
.q_a(tile1_Dout),
.wren_a(tile1_cs & NRD),
.clock_b(CK49),
.address_b(vram_A),
.q_b(tile1_D)
);
`ifndef MISTER_HISCORE
//Sprites
dpram_dc #(.widthad_a(12)) VRAM_SPR
(
.clock_a(CK49),
.address_a(A[11:0]),
.data_a(DBi),
.q_a(spriteram_Dout),
.wren_a(spriteram_cs & NRD),
.clock_b(~CK49),
.address_b(spriteram_A),
.q_b(spriteram_D)
);
`else
// Hiscore mux (this is only to be used with Iron Horse as its high scores are stored in sprite RAM)
// - Mirrored sprite RAM used to protect against corruption while retrieving highscore data
wire [11:0] VRAM_SPR_AD = hs_access_write ? hs_address : A[11:0];
wire [7:0] VRAM_SPR_DIN = hs_access_write ? hs_data_in : DBi;
wire VRAM_SPR_WE = hs_access_write ? hs_write_enable : (spriteram_cs & NRD);
//Sprites
dpram_dc #(.widthad_a(12)) VRAM_SPR
(
.clock_a(CK49),
.address_a(VRAM_SPR_AD),
.data_a(VRAM_SPR_DIN),
.q_a(spriteram_Dout),
.wren_a(VRAM_SPR_WE),
.clock_b(~CK49),
.address_b(spriteram_A),
.q_b(spriteram_D)
);
//Sprite RAM shadow for highscore read access
dpram_dc #(.widthad_a(12)) VRAM_SPR_SHADOW
(
.clock_a(CK49),
.address_a(VRAM_SPR_AD),
.data_a(VRAM_SPR_DIN),
.wren_a(VRAM_SPR_WE),
.clock_b(CK49),
.address_b(hs_address),
.q_b(hs_data_out)
);
`endif
//-------------------------------------------------------- Tilemap layer -------------------------------------------------------//
//The Konami 005885 contains two tilemap layers. Finalizer - Super Transformation uses the second layer to draw the HUD at the
//top of the screen. Latch tilemap data out of bank 0 or bank 1 of the tilemap section of VRAM based on how far the game has
//drawn the tilemap layer when tile control bit 2 is set, otherwise grab tilemap data from bank 0 of the tilemap section of VRAM
//at all times
//Loosely based on TimePilot 84's schematics
reg [7:0] tile_attrib_D, tile_D;
wire tile1_en = flipscreen ? h_cnt > 9'd243 : h_cnt < 9'd40;
wire [5:0] tile_hoffset = tile_ctrl[2] ? (~tile1_en ? (flipscreen ? 6'd4 : 6'd32) : 6'd0) : (flipscreen ? 6'd4 : 6'd0);
always_ff @(posedge CK49) begin
if (cen_6m) begin
if(h_cnt[1:0] == 2'b01) begin // posedge of h_cnt[1]
if(tile_ctrl[2] && tile1_en) begin
tile_D <= tile1_D;
tile_attrib_D <= tile1_attrib_D;
end
else begin
tile_D <= tile0_D;
tile_attrib_D <= tile0_attrib_D;
end
end
end
end
//XOR horizontal and vertical counter bits with flipscreen bit
wire [8:0] hcnt_x = h_cnt ^ {9{flipscreen}};
wire [8:0] vcnt_x = v_cnt ^ {9{flipscreen}};
//Generate tilemap position by summing the XORed counter bits with their respective scroll registers or ZRAM bank 0 based on
//whether row scroll or column scroll is enabled (do not allow scrolling when drawing Finalizer - Super Transformation's HUD
//and offset the tilemap layer with this game)
wire [8:0] row_scroll = (tile_ctrl[2] & !flipscreen & tile1_en) ? 9'd0:
(tile_ctrl[2] & flipscreen & tile1_en) ? 9'd28:
(scroll_ctrl[3:1] == 3'b101) ? zram0_D : {scroll_ctrl[0], scroll_x};
wire [8:0] col_scroll = (scroll_ctrl[3:1] == 3'b011) ? zram0_D : scroll_y;
wire [7:2] tilemap_hpos = hcnt_x[7:2] + row_scroll[7:2] - tile_hoffset[5:2] + {!tile_ctrl[2] & !flipscreen, 1'b0}/* synthesis keep */;
wire [8:0] tilemap_vpos = vcnt_x + col_scroll;
//Address output to tilemap section of VRAM
wire [9:0] vram_A = {tilemap_vpos[7:3], tilemap_hpos[7:3]};
//Assign tile index as bits 5 and 6 of tilemap attributes and the tile code
wire [9:0] tile_index = {tile_attrib_D[7:6], tile_D} /* synthesis keep */;
//XOR tile H/V flip bits with the flipscreen bit
wire tile_hflip = tile_attrib_D[4];
wire tile_vflip = tile_attrib_D[5];
//Latch tile data from graphics ROMs, tile colors and tile H flip bit from VRAM on the falling edge of tilemap horizontal position
//bit 1 (direct for Finalizer)
reg [15:0] RD_lat = 16'd0;
reg [3:0] tile_color, tile_color_r;
reg tile_hflip_lat, tile_hflip_lat_r;
reg tile_vflip_lat;
reg hpos2_lat;
reg [2:0] yscroll_lat;
reg [1:0] xscroll_lat, xscroll_lat_r, xscroll_lat_rr;
always_ff @(posedge CK49) begin
if (cen_6m) begin
if(h_cnt[1:0] == 2'b11) begin // negedge of h_cnt[1]
hpos2_lat <= tilemap_hpos[2];
xscroll_lat <= row_scroll[1:0];
xscroll_lat_r <= xscroll_lat;
yscroll_lat <= tilemap_vpos[2:0];
tile_color <= tile_attrib_D[3:0];
tile_color_r <= tile_color;
tile_hflip_lat <= tile_hflip;
tile_hflip_lat_r <= tile_hflip_lat;
tile_vflip_lat <= tile_vflip;
//Address output to graphics ROMs
R[15:4] <= {tile_ctrl[1:0], tile_index};
//Latch graphics ROM output
RD_lat <= {RDU, RDL};
//Output bits 4 and 5 of tilemap attributes for graphics ROM addressing
ATR4 <= tile_attrib_D[4];
ATR5 <= tile_attrib_D[5];
end
xscroll_lat_rr <= xscroll_lat_r;
end
end
assign R[3:0] = {yscroll_lat[2:0] ^ {3{tile_vflip_lat}}, hpos2_lat ^ tile_hflip_lat};
reg [3:0] tile_pixel /* synthesis keep */;
always @(*) begin
case (hcnt_x[1:0] ^ {2{tile_hflip_lat_r}})
2'b00: tile_pixel = RD_lat[15:12];
2'b01: tile_pixel = RD_lat[11: 8];
2'b10: tile_pixel = RD_lat[ 7: 4];
2'b11: tile_pixel = RD_lat[ 3: 0];
default: ;
endcase
end
//Address output to tilemap LUT PROM
assign VCF = tile_color_r;
assign VCB = tile_pixel;
// latch pixel data, and generate 4 shifted pixel positions for fine scroll
reg [3:0] pix0, pix1, pix2, pix3;
always_ff @(posedge CK49) begin
if (cen_6m) begin
pix0 <= VCD;
pix1 <= pix0;
pix2 <= pix1;
pix3 <= pix2;
end
end
// select the appropriate shifted pixel according to scroll value
reg [3:0] tilemap_D /* synthesis keep */;
wire hud_left = !flipscreen && tile_ctrl[2] && h_cnt < 52;
wire hud_right = flipscreen && tile_ctrl[2] && h_cnt > 252;
always @(*) begin
case ({2{flipscreen}} ^ xscroll_lat_rr)
2'b00: tilemap_D = pix3;
2'b01: tilemap_D = pix2;
2'b10: tilemap_D = pix1;
2'b11: tilemap_D = pix0;
default: ;
endcase
if (hud_left ) tilemap_D = pix3;
if (hud_right) tilemap_D = pix0;
end
//Retrieve tilemap select bit from bit 1 of the tile control register XORed with bit 5 of the same register
wire tile_sel = tile_ctrl[1] ^ tile_ctrl[5];
//Prioritize the tilemap layer when using the extended 280x224 mode for Finalizer in the score display area, otherwise give priority
//to sprites
wire tilemap_en = tile_ctrl[2] ? (hud_left | hud_right) : tile_sel;
//-------------------------------------------------------- Sprite layer --------------------------------------------------------//
//The following code is an adaptation of the sprite renderer from MiSTer-X's Green Beret core tweaked for the 005885's sprite format
reg [8:0] sprite_hpos = 9'd0;
reg [8:0] sprite_vpos = 9'd0;
always_ff @(posedge CK49) begin
if(cen_6m) begin
sprite_hpos <= h_cnt;
//If a bootleg Iron Horse ROM set is loaded, apply a vertical offset of 65 lines (66 when flipped) to recreate the
//bootleg hardware's 1-line downward vertical offset between the sprite and tilemap layers, otherwise apply a
//vertical offset of 66 lines (65 lines when flipped)
if(BTLG == 2'b10)
if(flipscreen)
sprite_vpos <= v_cnt + 9'd66;
else
sprite_vpos <= v_cnt + 9'd65;
else
if(flipscreen)
sprite_vpos <= v_cnt + 9'd65;
else
sprite_vpos <= v_cnt + 9'd66;
end
end
//Sprite state machine
reg [8:0] sprite_index;
reg [2:0] sprite_offset;
reg [2:0] sprite_fsm_state;
reg [11:0] sprite_code;
reg [8:0] sprite_limit;
reg [8:0] sprite_x;
reg [7:0] sprite_y;
reg [5:0] sprite_width;
reg [3:0] sprite_color;
reg [2:0] sprite_size;
reg sprite_hflip, sprite_vflip, sprite_x8_sel, sprite_x8_vram;
wire [8:0] sprite_fsm_reset = tile_ctrl[2] ? 9'd40 : 9'd0;
always_ff @(posedge CK49) begin
//Bootleg Iron Horse PCBs have a lower-than-normal sprite limit causing noticeable sprite flickering - reduce the sprite limit
//to 32 sprites (0 - 155 in increments of 5) if one such ROM set is loaded (render 96 sprites at once, 0 - 485 in increments of
//5, otherwise)
sprite_limit <= (BTLG == 2'b10) ? 9'd155 : 9'd485;
//Reset the sprite state machine whenever the sprite horizontal postion, and in turn the horziontal counter, returns to 0
//Also hold the sprite state machine in this initial state for the first line while drawing sprites for bootleg Iron Horse
//ROM sets to prevent graphical garbage from occurring on the top-most line
if(sprite_hpos == sprite_fsm_reset || (BTLG == 2'b10 && (!flipscreen && sprite_vpos <= 9'd80) || (flipscreen && sprite_vpos >= 9'd304))) begin
sprite_width <= 0;
sprite_index <= 0;
sprite_offset <= 3'd4;
sprite_fsm_state <= 1;
end
else
case(sprite_fsm_state)
0: /* empty */ ;
1: begin
//If the sprite limit is reached, hold the state machine in an empty state, otherwise latch the sprite H/V flip
//bits, sprite size, bit 8 of the sprite X position and its select bit
if(sprite_index > sprite_limit)
sprite_fsm_state <= 0;
else begin
sprite_vflip <= spriteram_D[6] ^ ~flipscreen;
sprite_hflip <= spriteram_D[5] ^ flipscreen;
sprite_size <= spriteram_D[4:2];
sprite_x8_sel <= spriteram_D[1];
sprite_x8_vram <= spriteram_D[0];
sprite_offset <= 3'd3;
sprite_fsm_state <= sprite_fsm_state + 3'd1;
end
end
2: begin
//Latch sprite X position and set the 9th bit as either the one latched previously from VRAM or the AND of position
//bits [7:3] based on the state of the select bit
if(sprite_x8_sel)
sprite_x[8] <= sprite_x8_vram ^ flipscreen;
else
sprite_x[8] <= (&spriteram_D[7:3]) ^ flipscreen;
sprite_x[7:0] <= spriteram_D ^ {8{flipscreen}};
sprite_offset <= 3'd2;
sprite_fsm_state <= sprite_fsm_state + 3'd1;
end
3: begin
//Latch sprite Y position
sprite_y <= spriteram_D;
sprite_offset <= 3'd1;
sprite_fsm_state <= sprite_fsm_state + 3'd1;
end
4: begin
//Skip the current sprite if it's inactive, otherwise latch sprite color and the upper/lower 2 bits of the sprite
//code, and continue scanning out the rest of the sprite attributes
if(sprite_active) begin
sprite_color <= spriteram_D[7:4];
sprite_code[1:0] <= spriteram_D[3:2];
sprite_code[11:10] <= spriteram_D[1:0];
sprite_offset <= 3'd0;
sprite_fsm_state <= sprite_fsm_state + 3'd1;
end
else begin
sprite_index <= sprite_index + 9'd5;
sprite_offset <= 3'd4;
sprite_fsm_state <= 3'd1;
end
end
5: begin
//Latch bits [9:2] of the sprite code and set up the sprite width based on the sprite size
sprite_code[9:2] <= spriteram_D;
sprite_offset <= 3'd4;
sprite_index <= sprite_index + 9'd5;
case(sprite_size)
3'b000: sprite_width <= 6'b110000 + (BTLG == 2'b01 && flipscreen);
3'b001: sprite_width <= 6'b110000 + (BTLG == 2'b01 && flipscreen);
3'b010: sprite_width <= 6'b111000 + (BTLG == 2'b01 && flipscreen);
3'b011: sprite_width <= 6'b111000 + (BTLG == 2'b01 && flipscreen);
default: sprite_width <= 6'b100000 + (BTLG == 2'b01 && flipscreen);
endcase
sprite_fsm_state <= sprite_fsm_state + 3'd1;
S_req <= !S_req;
end
6: if (S_req == S_ack) begin
//Skip the last line of a sprite if a bootleg Jackal ROM set is loaded (the hardware on such bootlegs fails
//to render the last line of sprites), otherwise write sprites as normal
if(BTLG == 2'b01 && !flipscreen)
if(sprite_width == 6'b111110)
sprite_width <= sprite_width + 6'd2;
else
sprite_width <= sprite_width + 6'd1;
else
sprite_width <= sprite_width + 6'd1;
sprite_fsm_state <= wre ? sprite_fsm_state : 3'd1;
S_req <= (wre & sprite_width[1:0] == 2'b11) ? !S_req : S_req;
end
default:;
endcase
end
//Adjust sprite code based on sprite size
wire [11:0] sprite_code_sized = sprite_size == 3'b000 ? {sprite_code[11:2], ly[3], lx[3]}: //16x16
sprite_size == 3'b001 ? {sprite_code[11:1], lx[3]}: //16x8
sprite_size == 3'b010 ? {sprite_code[11:2], ly[3], sprite_code[0]}: //8x16
sprite_size == 3'b011 ? sprite_code: //8x8
{sprite_code[11:2] + {ly[4], lx[4]}, ly[3], lx[3]}; //32x32
//Subtract vertical sprite position from sprite Y parameter to obtain sprite height
wire [8:0] sprite_height = {(sprite_y[7:4] == 4'hF), sprite_y ^ {8{flipscreen}}} - sprite_vpos;
//Set when a sprite is active depending on whether it is 8, 16 or 32 pixels tall
reg sprite_active;
always @(*) begin
case(sprite_size)
3'b000: sprite_active = (sprite_height[8:7] == 2'b11) & (sprite_height[6] ^ ~flipscreen) & (sprite_height[5] ^ flipscreen)
& (sprite_height[4] ^ flipscreen);
3'b001: sprite_active = (sprite_height[8:7] == 2'b11) & (sprite_height[6] ^ ~flipscreen) & (sprite_height[5] ^ flipscreen)
& (sprite_height[4] ^ flipscreen) & (sprite_height[3] ^ flipscreen);
3'b010: sprite_active = (sprite_height[8:7] == 2'b11) & (sprite_height[6] ^ ~flipscreen) & (sprite_height[5] ^ flipscreen)
& (sprite_height[4] ^ flipscreen);
3'b011: sprite_active = (sprite_height[8:7] == 2'b11) & (sprite_height[6] ^ ~flipscreen) & (sprite_height[5] ^ flipscreen)
& (sprite_height[4] ^ flipscreen) & (sprite_height[3] ^ flipscreen);
3'b100: sprite_active = (sprite_height[8:7] == 2'b11) & (sprite_height[6] ^ ~flipscreen) & (sprite_height[5] ^ flipscreen);
default: sprite_active = (sprite_height[8:7] == 2'b11) & (sprite_height[6] ^ ~flipscreen) & (sprite_height[5] ^ flipscreen);
endcase
end
wire [4:0] lx = sprite_width[4:0] ^ {5{sprite_hflip}};
wire [4:0] ly = sprite_height[4:0] ^ {5{sprite_vflip}};
//Assign address outputs to sprite ROMs
assign S = {sprite_code_sized, ly[2:0], lx[2]};
//Multiplex sprite ROM data down from 16 bits to 8 using bit 1 of the horizontal position
wire [7:0] SD = lx[1] ? SDL : SDU;
//Further multiplex sprite ROM data down from 8 bits to 4 using bit 0 of the horizontal position
wire [3:0] sprite_pixel = lx[0] ? SD[3:0] : SD[7:4];
//Sum the sprite index with the sprite offset and address sprite RAM with it along with tile control register bit 3
wire [8:0] sprite_address = (sprite_index + sprite_offset);
reg sprite_bank = 0;
reg old_vsync;
//Normally, the 005885 latches the sprite bank from bit 3 of the tile control register on the rising edge of VSync, though this causes
//jerky scrolling with sprites for bootleg Jackal ROM sets - bypass this latch if such ROM sets are loaded
//Finalizer - Super Transformation only reads sprite information from the lower sprite bank
always_ff @(posedge CK49) begin
old_vsync <= NVSY;
if(!NEXR)
sprite_bank <= 0;
else if(!old_vsync && NVSY)
sprite_bank <= tile_ctrl[3];
end
wire [11:0] spriteram_A = {(BTLG == 2'b01) ? tile_ctrl[3] : sprite_bank, 2'b00, sprite_address};
//Address output to sprite LUT PROM
assign OCF = sprite_color;
assign OCB = sprite_pixel;
//----------------------------------------------------- Sprite line buffer -----------------------------------------------------//
//The sprite line buffer is external to the 005885 and consists of two 4464 DRAM chips. For simplicity, both the logic for the
//sprite line buffer and the sprite line buffer itself are internal to the 005885 implementation.
//Enable writing to sprite line buffer when bit 5 of the sprite width is 1
wire wre = sprite_width[5];
//Set sprite line buffer bank as bit 0 of the sprite vertical position
wire sprite_lbuff_bank = sprite_vpos[0];
//Sum sprite X position with the following bits of the sprite width to address the sprite line buffer based on sprite size:
//32 pixels wide: bits [4:0]
//16 pixels wide: bits [3:0]
//8 pixels wide: bits [2:0]
//XOR the upper bits for screen flipping on 16 pixel and 8 pixel wide sprites
reg [4:0] final_sprite_width;
always @(*) begin
case(sprite_size)
3'b000: final_sprite_width = {sprite_width[4] ^ ~flipscreen, sprite_width[3:0]};
3'b001: final_sprite_width = {sprite_width[4] ^ ~flipscreen, sprite_width[3:0]};
3'b010: final_sprite_width = {sprite_width[4:3] ^ {2{~flipscreen}}, sprite_width[2:0]};
3'b011: final_sprite_width = {sprite_width[4:3] ^ {2{~flipscreen}}, sprite_width[2:0]};
3'b100: final_sprite_width = sprite_width[4:0];
default: final_sprite_width = sprite_width[4:0];
endcase
end
wire [8:0] wpx = sprite_x + final_sprite_width;
//Generate sprite line buffer write addresses
reg [9:0] lbuff_A;
reg lbuff_we;
wire [3:0] lbuff_Din = OCD;
always_ff @(posedge CK49) begin
lbuff_A <= {~sprite_lbuff_bank, wpx};
lbuff_we <= wre & S_req == S_ack;
end
//Generate read address for sprite line buffer on the rising edge of the pixel clock (apply a -225 offset when the screen
//is flipped)
reg [9:0] radr0 = 10'd0;
reg [9:0] radr1 = 10'd1;
always_ff @(posedge CK49) begin
if(cen_6m)
radr0 <= {sprite_lbuff_bank, flipscreen ? sprite_hpos - 9'd225 : tile_ctrl[2] ? sprite_hpos - 9'd40 : sprite_hpos};
end
//Sprite line buffer
wire [3:0] lbuff_Dout;
dpram_dc #(.widthad_a(10)) LBUFF
(
.clock_a(CK49),
.address_a(lbuff_A),
.data_a({4'd0, lbuff_Din}),
.wren_a(lbuff_we & (lbuff_Din != 0)),
.clock_b(CK49),
.address_b(radr0),
.data_b(8'h0),
.wren_b(radr0 == radr1),
.q_b({4'bZZZZ, lbuff_Dout})
);
//Latch sprite data from the sprite line buffer
wire lbuff_read_en = (div[2:0] == 3'b100);
reg [3:0] lbuff_read = 4'd0;
always_ff @(posedge CK49) begin
if(lbuff_read_en) begin
if(radr0 != radr1)
lbuff_read <= lbuff_Dout;
radr1 <= radr0;
end
end
//Delay sprite layer by 2 horizontal lines (1 line if a bootleg Jackal ROM set is loaded and the screen is flipped)
reg [7:0] sprite_dly = 8'd0;
always_ff @(posedge CK49) begin
if(cen_6m) begin
if(BTLG == 2'b01 && flipscreen)
sprite_dly <= {4'd0, lbuff_read};
else
sprite_dly <= {lbuff_read, sprite_dly[7:4]};
end
end
//Jackal bootlegs fail to render the last two vertical lines of the sprite layer - model this behavior here
wire [3:0] sprite_D = (BTLG == 2'b01 && ((h_cnt >= 244 && ~flipscreen) || (h_cnt >= 248 && flipscreen))) ? 4'd0 : sprite_dly[3:0];
//--------------------------------------------------------- Color mixer --------------------------------------------------------//
//Multiplex tile and sprite data, then output the final result
wire tile_sprite_sel = (tilemap_en | ~(|sprite_D));
wire [3:0] tile_sprite_D = tile_sprite_sel ? tilemap_D : sprite_D;
//Latch and output pixel data
reg [4:0] pixel_D;
always_ff @(posedge CK49) begin
if(cen_6m)
pixel_D <= {tile_sprite_sel, tile_sprite_D};
end
assign COL = (BTLG == 2'b01 && ((h_cnt >= 247 && ~flipscreen) || (h_cnt <= 14 && flipscreen))) ||
(BTLG == 2'b10 && ((h_cnt <= 20 && ~flipscreen) || ((h_cnt <= 18 || h_cnt >= 251) && flipscreen))) ? 5'd0 : pixel_D;
//The above condition blacks out the last 4 lines on the right side of the screen (left when flipped) when a bootleg Jackal ROM set
//is loaded and blacks out the left-most 8 lines (7 when flipped plus an extra 2 lines on the right side) when a bootleg Iron Horse
//ROM set is loaded - this simulates the earlier-than-normal start of HBlank for Jackal bootlegs and later-than-normal end of
//HBlank for Iron Horse bootlegs while maintaining the usual 240x224 display area
endmodule

4
Arcade_MiST/Konami Finalizer/rtl/pll.qip Normal file
View File

@@ -0,0 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

348
Arcade_MiST/Konami Finalizer/rtl/pll.v Normal file
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@@ -0,0 +1,348 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 105,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 382,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 105,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 191,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "105"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "105"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "98.228569"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "49.114285"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "382"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "191"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "49.15200000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.31818000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "105"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "382"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "105"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "191"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

433
Arcade_MiST/Konami Finalizer/rtl/rom_loader.sv Normal file
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@@ -0,0 +1,433 @@
//============================================================================
//
// SD card ROM loader and ROM selector for MISTer.
// Copyright (C) 2019, 2020 Kitrinx (aka Rysha)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
// Rom layout for Finalizer:
// 0x0000 - 0x3FFF = eprom_1
// 0x4000 - 0x7FFF = eprom_2
// 0x8000 - 0xBFFF = eprom_3
// 0xC000 - 0xFFFF = eprom_4
// 0x10000 - 0x13FFF = eprom_5
// 0x14000 - 0x17FFF = eprom_6
// 0x18000 - 0x1BFFF = eprom_7
// 0x1C000 - 0x1FFFF = eprom_8
// 0x20000 - 0x23FFF = eprom_9
// 0x24000 - 0x247FF = snd01
// 0x24800 - 0x248FF = prom_1
// 0x24900 - 0x249FF = prom_2
// 0x24A00 - 0x24A1F = prom_3
// 0x24A20 - 0x24A3F = prom_4
module selector
(
input logic [24:0] ioctl_addr,
output logic ep1_cs, ep2_cs, ep3_cs, ep4_cs, ep5_cs, ep6_cs, ep7_cs, ep8_cs, ep9_cs, snd01_cs,
prom1_cs, prom2_cs, prom3_cs, prom4_cs
);
always_comb begin
{ep1_cs, ep2_cs, ep3_cs, ep4_cs, ep5_cs, ep6_cs, ep7_cs, ep8_cs, ep9_cs, snd01_cs,
prom1_cs, prom2_cs, prom3_cs, prom4_cs} = 0;
if(ioctl_addr < 'h4000)
ep1_cs = 1; // 0x4000 14
else if(ioctl_addr < 'h8000)
ep2_cs = 1; // 0x4000 14
else if(ioctl_addr < 'hC000)
ep3_cs = 1; // 0x4000 14
else if(ioctl_addr < 'h10000)
ep4_cs = 1; // 0x4000 14
else if(ioctl_addr < 'h14000)
ep5_cs = 1; // 0x4000 14
else if(ioctl_addr < 'h18000)
ep6_cs = 1; // 0x4000 14
else if(ioctl_addr < 'h1C000)
ep7_cs = 1; // 0x4000 14
else if(ioctl_addr < 'h20000)
ep8_cs = 1; // 0x4000 14
else if(ioctl_addr < 'h24000)
ep9_cs = 1; // 0x4000 14
else if(ioctl_addr < 'h24800)
snd01_cs = 1; // 0x800 11
else if(ioctl_addr < 'h24900)
prom1_cs = 1; // 0x100 8
else if(ioctl_addr < 'h24A00)
prom2_cs = 1; // 0x100 8
else if(ioctl_addr < 'h24A20)
prom3_cs = 1; // 0x20 5
else
prom4_cs = 1; // 0x20 5
end
endmodule
////////////
// EPROMS //
////////////
module eprom_1
(
input logic CLK,
input logic CLK_DL,
input logic [13:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATA
);
dpram_dc #(.widthad_a(14)) eprom_1
(
.clock_a(CLK),
.address_a(ADDR[13:0]),
.q_a(DATA[7:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[13:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule
module eprom_2
(
input logic CLK,
input logic CLK_DL,
input logic [13:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATA
);
dpram_dc #(.widthad_a(14)) eprom_2
(
.clock_a(CLK),
.address_a(ADDR[13:0]),
.q_a(DATA[7:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[13:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule
module eprom_3
(
input logic CLK,
input logic CLK_DL,
input logic [13:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATA
);
dpram_dc #(.widthad_a(14)) eprom_3
(
.clock_a(CLK),
.address_a(ADDR[13:0]),
.q_a(DATA[7:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[13:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule
module eprom_4
(
input logic CLK_A,
input logic CLK_B,
input logic [13:0] ADDR_A,
input logic [24:0] ADDR_B,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATAOUT_A,
output logic [7:0] DATAOUT_B
);
dpram_dc #(.widthad_a(14)) eprom_4
(
.clock_a(CLK_A),
.address_a(ADDR_A[13:0]),
.q_a(DATAOUT_A[7:0]),
.clock_b(CLK_B),
.address_b(ADDR_B[13:0]),
.data_b(DATA_IN),
.q_b(DATAOUT_B[7:0]),
.wren_b(WR & CS_DL)
);
endmodule
module eprom_5
(
input logic CLK_A,
input logic CLK_B,
input logic [13:0] ADDR_A,
input logic [24:0] ADDR_B,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATAOUT_A,
output logic [7:0] DATAOUT_B
);
dpram_dc #(.widthad_a(14)) eprom_5
(
.clock_a(CLK_A),
.address_a(ADDR_A[13:0]),
.q_a(DATAOUT_A[7:0]),
.clock_b(CLK_B),
.address_b(ADDR_B[13:0]),
.data_b(DATA_IN),
.q_b(DATAOUT_B[7:0]),
.wren_b(WR & CS_DL)
);
endmodule
module eprom_6
(
input logic CLK,
input logic CLK_DL,
input logic [13:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATA
);
dpram_dc #(.widthad_a(14)) eprom_6
(
.clock_a(CLK),
.address_a(ADDR[13:0]),
.q_a(DATA[7:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[13:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule
module eprom_7
(
input logic CLK,
input logic CLK_DL,
input logic [13:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATA
);
dpram_dc #(.widthad_a(14)) eprom_7
(
.clock_a(CLK),
.address_a(ADDR[13:0]),
.q_a(DATA[7:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[13:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule
module eprom_8
(
input logic CLK,
input logic CLK_DL,
input logic [13:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATA
);
dpram_dc #(.widthad_a(14)) eprom_8
(
.clock_a(CLK),
.address_a(ADDR[13:0]),
.q_a(DATA[7:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[13:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule
module eprom_9
(
input logic CLK,
input logic CLK_DL,
input logic [13:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATA
);
dpram_dc #(.widthad_a(14)) eprom_9
(
.clock_a(CLK),
.address_a(ADDR[13:0]),
.q_a(DATA[7:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[13:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule
///////////////////
// EMBEDDED ROMS //
///////////////////
module kSND01_ROM
(
input logic CLK,
input logic CLK_DL,
input logic [10:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATA
);
dpram_dc #(.widthad_a(11)) kSND01_ROM
(
.clock_a(CLK),
.address_a(ADDR[10:0]),
.q_a(DATA[7:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[10:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule
///////////
// PROMS //
///////////
module prom_1
(
input logic CLK,
input logic CLK_DL,
input logic [7:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [3:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [3:0] DATA
);
dpram_dc #(.widthad_a(8)) prom_1
(
.clock_a(CLK),
.address_a(ADDR),
.q_a(DATA[3:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[7:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule
module prom_2
(
input logic CLK,
input logic CLK_DL,
input logic [7:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [3:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [3:0] DATA
);
dpram_dc #(.widthad_a(8)) prom_2
(
.clock_a(CLK),
.address_a(ADDR),
.q_a(DATA[3:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[7:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule
module prom_3
(
input logic CLK,
input logic CLK_DL,
input logic [4:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATA
);
dpram_dc #(.widthad_a(5)) prom_3
(
.clock_a(CLK),
.address_a(ADDR),
.q_a(DATA[7:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[7:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule
module prom_4
(
input logic CLK,
input logic CLK_DL,
input logic [4:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATA
);
dpram_dc #(.widthad_a(5)) prom_4
(
.clock_a(CLK),
.address_a(ADDR),
.q_a(DATA[7:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[7:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule

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//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output reg [15:0] port1_q,
input [15:1] cpu1_addr,
output reg [15:0] cpu1_q,
input port2_req,
output reg port2_ack,
input port2_we,
input [23:1] port2_a,
input [1:0] port2_ds,
input [15:0] port2_d,
output reg [15:0] port2_q,
input [16:1] ch1_addr,
output reg [15:0] ch1_q,
input sp1_req,
input [16:1] sp1_addr,
output reg [15:0] sp1_q,
output reg sp1_ack
);
parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us
localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
/*
SDRAM state machine for 2 bank interleaved access
1 word burst, CL2
cmd issued registered
0 RAS0 cas1
1 ras0
2 data1 returned
3 CAS0
4 RAS1 cas0
5 ras1
6 CAS1 data0 returned
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
localparam STATE_READ1 = 3'd3;
localparam STATE_LAST = 3'd6;
reg [2:0] t;
always @(posedge clk) begin
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[2];
reg [24:1] addr_latch_next[2];
reg [15:1] addr_last[4];
reg [16:1] addr_last2[4];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
reg [1:0] we_latch;
reg [1:0] ds[2];
reg port1_state;
reg port2_state;
localparam PORT_NONE = 2'd0;
localparam PORT_CPU1 = 2'd1;
localparam PORT_CH1 = 2'd1;
localparam PORT_SP1 = 2'd2;
localparam PORT_REQ = 2'd3;
reg [1:0] next_port[2];
reg [1:0] port[2];
reg refresh;
reg [10:0] refresh_cnt;
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
// PORT1: bank 0,1
always @(*) begin
if (refresh) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end else if (port1_req ^ port1_state) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
next_port[0] = PORT_CPU1;
addr_latch_next[0] = { 9'd0, cpu1_addr };
end else begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end
end
// PORT1: bank 2,3
always @(*) begin
if (port2_req ^ port2_state) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (ch1_addr != addr_last2[PORT_CH1]) begin
next_port[1] = PORT_CH1;
addr_latch_next[1] = { 1'b1, 5'd0, 2'b00, ch1_addr };
end else if (sp1_req != sp1_ack) begin
next_port[1] = PORT_SP1;
addr_latch_next[1] = { 1'b1, 5'd0, 2'b00, sp1_addr };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
end
end
always @(posedge clk) begin
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
if(init) begin
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
end
end else begin
// RAS phase
// bank 0,1
if(t == STATE_RAS0) begin
addr_latch[0] <= addr_latch_next[0];
port[0] <= next_port[0];
{ oe_latch[0], we_latch[0] } <= 2'b00;
if (next_port[0] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
addr_last[next_port[0]] <= addr_latch_next[0][15:1];
if (next_port[0] == PORT_REQ) begin
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
ds[0] <= port1_ds;
din_latch[0] <= port1_d;
port1_state <= port1_req;
end else begin
{ oe_latch[0], we_latch[0] } <= 2'b10;
ds[0] <= 2'b11;
end
end
end
// bank 2,3
if(t == STATE_RAS1) begin
refresh <= 1'b0;
addr_latch[1] <= addr_latch_next[1];
{ oe_latch[1], we_latch[1] } <= 2'b00;
port[1] <= next_port[1];
if (next_port[1] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[1][22:10];
SDRAM_BA <= addr_latch_next[1][24:23];
addr_last2[next_port[1]] <= addr_latch_next[1][16:1];
if (next_port[1] == PORT_REQ) begin
{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
port2_state <= port2_req;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
end
end
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
refresh <= 1'b1;
refresh_cnt <= 0;
sd_cmd <= CMD_AUTO_REFRESH;
end
end
// CAS phase
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
if (we_latch[0]) begin
SDRAM_DQ <= din_latch[0];
port1_ack <= port1_req;
end
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[0][24:23];
end
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if (we_latch[1]) begin
SDRAM_DQ <= din_latch[1];
port2_ack <= port2_req;
end
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[1][24:23];
end
// Data returned
if(t == STATE_READ0 && oe_latch[0]) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; end
default: ;
endcase;
end
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end
PORT_CH1 : ch1_q <= sd_din;
PORT_SP1 : begin sp1_q <= sd_din; sp1_ack <= sp1_req; end
default: ;
endcase;
end
end
end
endmodule

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library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
entity spram is
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 10
);
port
(
clk : in std_logic;
addr : in std_logic_vector((ADDR_WIDTH - 1) downto 0);
data : in std_logic_vector((DATA_WIDTH - 1) downto 0);
q : out std_logic_vector((DATA_WIDTH - 1) downto 0);
we : in std_logic := '0'
);
end spram;
architecture rtl of spram is
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
shared variable ram : memory_t;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(we = '1') then
ram(to_integer(unsigned(addr))) := data;
q <= data;
else
q <= ram(to_integer(unsigned(addr)));
end if;
end if;
end process;
end rtl;

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-------------------------------------------------------------------------------
--
-- T8048 Microcontroller System
-- 8048 toplevel without tri-states
--
-- $Id: t8048_notri.vhd,v 1.7 2006/07/14 01:13:32 arniml Exp $
-- $Name: $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t8049_notri is
generic (
gate_port_input_g : integer := 1
);
port (
xtal_i : in std_logic;
xtal_en_i : in std_logic;
reset_n_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2l_low_imp_o : out std_logic;
p2h_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic;
--Extra inputs for MiSTer ROM loader to load embedded ROM
ADDR_DL : in std_logic_vector(24 downto 0);
CLK_DL : in std_logic;
CS_DL : in std_logic;
DATA_IN : in std_logic_vector( 7 downto 0);
WR : in std_logic
);
end t8049_notri;
library ieee;
use ieee.numeric_std.all;
use work.t48_core_comp_pack.t48_core;
--use work.t48_core_comp_pack.kSND01_ROM;
use work.t48_core_comp_pack.generic_ram_ena;
architecture struct of t8049_notri is
component kSND01_ROM
port (
CLK : in std_logic;
CLK_DL : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
ADDR_DL : in std_logic_vector(24 downto 0);
DATA_IN : in std_logic_vector( 7 downto 0);
CS_DL : in std_logic;
WR : in std_logic;
DATA : out std_logic_vector( 7 downto 0)
);
end component;
-- Address width of internal ROM
constant rom_addr_width_c : natural := 11;
signal xtal3_s : std_logic;
signal dmem_addr_s : std_logic_vector( 7 downto 0);
signal dmem_we_s : std_logic;
signal dmem_data_from_s : std_logic_vector( 7 downto 0);
signal dmem_data_to_s : std_logic_vector( 7 downto 0);
signal pmem_addr_s : std_logic_vector(11 downto 0);
signal pmem_data_s : std_logic_vector( 7 downto 0);
signal ea_s : std_logic;
signal p1_in_s,
p1_out_s : std_logic_vector( 7 downto 0);
signal p2_in_s,
p2_out_s : std_logic_vector( 7 downto 0);
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- Check generics for valid values.
-----------------------------------------------------------------------------
-- pragma translate_off
assert gate_port_input_g = 0 or gate_port_input_g = 1
report "gate_port_input_g must be either 1 or 0!"
severity failure;
-- pragma translate_on
t48_core_b : t48_core
generic map (
xtal_div_3_g => 1,
register_mnemonic_g => 1,
include_port1_g => 1,
include_port2_g => 1,
include_bus_g => 1,
include_timer_g => 1,
sample_t1_state_g => 4
)
port map (
xtal_i => xtal_i,
xtal_en_i => xtal_en_i,
reset_i => reset_n_i,
t0_i => t0_i,
t0_o => t0_o,
t0_dir_o => t0_dir_o,
int_n_i => int_n_i,
ea_i => ea_s,
rd_n_o => rd_n_o,
psen_n_o => psen_n_o,
wr_n_o => wr_n_o,
ale_o => ale_o,
db_i => db_i,
db_o => db_o,
db_dir_o => db_dir_o,
t1_i => t1_i,
p2_i => p2_in_s,
p2_o => p2_out_s,
p2l_low_imp_o => p2l_low_imp_o,
p2h_low_imp_o => p2h_low_imp_o,
p1_i => p1_in_s,
p1_o => p1_out_s,
p1_low_imp_o => p1_low_imp_o,
prog_n_o => prog_n_o,
clk_i => xtal_i,
en_clk_i => xtal3_s,
xtal3_o => xtal3_s,
dmem_addr_o => dmem_addr_s,
dmem_we_o => dmem_we_s,
dmem_data_i => dmem_data_from_s,
dmem_data_o => dmem_data_to_s,
pmem_addr_o => pmem_addr_s,
pmem_data_i => pmem_data_s
);
-----------------------------------------------------------------------------
-- Gate port 1 and 2 input bus with respetive output value
-----------------------------------------------------------------------------
gate_ports: if gate_port_input_g = 1 generate
p1_in_s <= p1_i and p1_out_s;
p2_in_s <= p2_i and p2_out_s;
end generate;
pass_ports: if gate_port_input_g = 0 generate
p1_in_s <= p1_i;
p2_in_s <= p2_i;
end generate;
p1_o <= p1_out_s;
p2_o <= p2_out_s;
-----------------------------------------------------------------------------
-- Process ea
--
-- Purpose:
-- Detects access to external program memory.
-- Either by ea_i = '1' or when program memory address leaves address
-- range of internal ROM.
--
ea: process (ea_i,
pmem_addr_s)
begin
if ea_i = '1' then
-- Forced external access
ea_s <= '1';
elsif unsigned(pmem_addr_s(11 downto rom_addr_width_c)) = 0 then
-- Internal access
ea_s <= '0';
else
-- Access to program memory out of internal range
ea_s <= '1';
end if;
end process ea;
--
-----------------------------------------------------------------------------
rom_2k_b : kSND01_ROM
port map (
CLK => xtal_i,
CLK_DL => CLK_DL,
ADDR => pmem_addr_s(rom_addr_width_c-1 downto 0),
ADDR_DL => ADDR_DL,
DATA_IN => DATA_IN,
CS_DL => CS_DL,
WR => WR,
DATA => pmem_data_s
);
ram_64_b : generic_ram_ena
generic map (
addr_width_g => 7,
data_width_g => 8
)
port map (
clk_i => xtal_i,
a_i => dmem_addr_s(6 downto 0),
we_i => dmem_we_s,
ena_i => vdd_s,
d_i => dmem_data_to_s,
d_o => dmem_data_from_s
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t8048_notri.vhd,v $
-- Revision 1.7 2006/07/14 01:13:32 arniml
-- name keyword added
--
-- Revision 1.6 2006/06/21 01:02:16 arniml
-- replaced syn_rom and syn_ram with t48_rom and generic_ram_ena
--
-- Revision 1.5 2006/06/20 00:47:08 arniml
-- new input xtal_en_i
--
-- Revision 1.4 2005/11/01 21:38:48 arniml
-- wire signals for P2 low impedance marker issue
--
-- Revision 1.3 2004/12/02 22:08:42 arniml
-- introduced generic gate_port_input_g
-- forces masking of P1 and P2 input bus
--
-- Revision 1.2 2004/12/01 23:08:08 arniml
-- update
--
-------------------------------------------------------------------------------