Arcade: Galaxian HW Video Fix

Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/video_mixer.sv

@@ -97,6 +97,11 @@ wire [DWIDTH:0] G_sd;
 wire [DWIDTH:0] B_sd;
 wire hs_sd, vs_sd;
 
+//reg Rd,Gd,Bd;
+//always @(posedge ce_pix) begin
+//   {Rd,Gd,Bd} <= {R,G,B};
+//end
+
 scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
 (
 	.*,

Arcade_MiST/Galaxian Hardware/AzurianAttack_MiST/Azurian.qsf

@@ -46,42 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 
 # Pin & Location Assignments
 # ==========================
@@ -181,10 +145,46 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(Galaxian)
 # --------------------
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Azurian.sv
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Azurian.sv
+set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/keyboard.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade_MiST/Galaxian Hardware/AzurianAttack_MiST/rtl/Azurian.sv

@@ -60,17 +60,17 @@ wire        ps2_kbd_clk, ps2_kbd_data;
 
 assign LED = 1;
 
-wire clk_18, clk_12, clk_6, clk_4p5;
+wire clk_24, clk_18, clk_12, clk_6;
 wire pll_locked;
 
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_18),
-	.c1(clk_12),
-	.c2(clk_6),
-	.c3(clk_4p5)
+	.c0(clk_24),
+	.c1(clk_18),
+	.c2(clk_12),
+	.c3(clk_6)
 );
 
 wire m_up     = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
@@ -106,7 +106,7 @@ wire [7:0] audio_a, audio_b;
 wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
 
 dac dac (
-	.clk_i(clk_18),
+	.clk_i(clk_24),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
@@ -120,9 +120,9 @@ wire hblank, vblank;
 wire blankn = ~(hblank | vblank);
 video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 (
-	.clk_sys(clk_18),
-	.ce_pix(clk_4p5),
-	.ce_pix_actual(clk_4p5),
+	.clk_sys(clk_24),
+	.ce_pix(clk_6),
+	.ce_pix_actual(clk_6),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
@@ -137,8 +137,8 @@ video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
 	.scandoubler_disable(scandoubler_disable),
-	.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
-	.hq2x(status[4:3]==1),
+	.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 2'b11, status[4:3] == 2'b10, status[4:3] == 2'b01}),
+	.hq2x(1'b0),
 	.ypbpr_full(1),
 	.line_start(0),
 	.mono(0)
@@ -146,7 +146,7 @@ video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 
 mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 (
-	.clk_sys        (clk_18   	  ),
+	.clk_sys        (clk_24   	     ),
 	.conf_str       (CONF_STR       ),
 	.SPI_SCK        (SPI_SCK        ),
 	.CONF_DATA0     (CONF_DATA0     ),
@@ -165,7 +165,7 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 );
 
 keyboard keyboard(
-	.clk(clk_18),
+	.clk(clk_24),
 	.reset(),
 	.ps2_kbd_clk(ps2_kbd_clk),
 	.ps2_kbd_data(ps2_kbd_data),

Arcade_MiST/Galaxian Hardware/AzurianAttack_MiST/rtl/build_id.v

@@ -1,2 +1,2 @@
-`define BUILD_DATE "180109"
-`define BUILD_TIME "174542"
+`define BUILD_DATE "180624"
+`define BUILD_TIME "115114"

Arcade_MiST/Galaxian Hardware/AzurianAttack_MiST/rtl/pll.vhd

@@ -159,21 +159,21 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 3,
+		clk0_divide_by => 9,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 2,
+		clk0_multiply_by => 8,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 9,
+		clk1_divide_by => 3,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 4,
+		clk1_multiply_by => 2,
 		clk1_phase_shift => "0",
 		clk2_divide_by => 9,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 2,
+		clk2_multiply_by => 4,
 		clk2_phase_shift => "0",
-		clk3_divide_by => 6,
+		clk3_divide_by => 9,
 		clk3_duty_cycle => 50,
-		clk3_multiply_by => 1,
+		clk3_multiply_by => 2,
 		clk3_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -254,18 +254,18 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
 -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -294,15 +294,15 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
@@ -321,7 +321,7 @@ END SYN;
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -362,21 +362,21 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"

Arcade_MiST/Galaxian Hardware/BlackHole_MiST/BlackHole.qsf

@@ -46,44 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlackHole.sv
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 
 # Pin & Location Assignments
 # ==========================
@@ -186,5 +148,43 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(Galaxian)
 # --------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlackHole.sv
+set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/keyboard.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 set_global_assignment -name VHDL_FILE rtl/pll.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade_MiST/Galaxian Hardware/BlackHole_MiST/rtl/BlackHole.sv

@@ -60,17 +60,17 @@ wire        ps2_kbd_clk, ps2_kbd_data;
 
 assign LED = 1;
 
-wire clk_18, clk_12, clk_6, clk_4p5;
+wire clk_24, clk_18, clk_12, clk_6;
 wire pll_locked;
 
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_18),
-	.c1(clk_12),
-	.c2(clk_6),
-	.c3(clk_4p5)//for now, needs a fix
+	.c0(clk_24),
+	.c1(clk_18),
+	.c2(clk_12),
+	.c3(clk_6)
 );
 
 wire m_up     = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
@@ -106,7 +106,7 @@ wire [7:0] audio_a, audio_b;
 wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
 
 dac dac (
-	.clk_i(clk_18),
+	.clk_i(clk_24),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
@@ -120,9 +120,9 @@ wire hblank, vblank;
 wire blankn = ~(hblank | vblank);
 video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 (
-	.clk_sys(clk_18),
-	.ce_pix(clk_4p5),
-	.ce_pix_actual(clk_4p5),
+	.clk_sys(clk_24),
+	.ce_pix(clk_6),
+	.ce_pix_actual(clk_6),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
@@ -146,7 +146,7 @@ video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 
 mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 (
-	.clk_sys        (clk_18     	  ),
+	.clk_sys        (clk_24     	  ),
 	.conf_str       (CONF_STR       ),
 	.SPI_SCK        (SPI_SCK        ),
 	.CONF_DATA0     (CONF_DATA0     ),
@@ -165,7 +165,7 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 );
 
 keyboard keyboard(
-	.clk(clk_18),
+	.clk(clk_24),
 	.reset(),
 	.ps2_kbd_clk(ps2_kbd_clk),
 	.ps2_kbd_data(ps2_kbd_data),

Arcade_MiST/Galaxian Hardware/BlackHole_MiST/rtl/build_id.v

@@ -1,2 +1,2 @@
-`define BUILD_DATE "180103"
-`define BUILD_TIME "172130"
+`define BUILD_DATE "180624"
+`define BUILD_TIME "115739"

Arcade_MiST/Galaxian Hardware/BlackHole_MiST/rtl/pll.vhd

@@ -159,21 +159,21 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 3,
+		clk0_divide_by => 9,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 2,
+		clk0_multiply_by => 8,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 9,
+		clk1_divide_by => 3,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 4,
+		clk1_multiply_by => 2,
 		clk1_phase_shift => "0",
 		clk2_divide_by => 9,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 2,
+		clk2_multiply_by => 4,
 		clk2_phase_shift => "0",
-		clk3_divide_by => 6,
+		clk3_divide_by => 9,
 		clk3_duty_cycle => 50,
-		clk3_multiply_by => 1,
+		clk3_multiply_by => 2,
 		clk3_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -254,18 +254,18 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
 -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -294,15 +294,15 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
@@ -319,9 +319,9 @@ END SYN;
 -- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -362,21 +362,21 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"

Arcade_MiST/Galaxian Hardware/Catacomb_MiST/Catacomb.qsf

@@ -46,42 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 
 # Pin & Location Assignments
 # ==========================
@@ -181,10 +145,46 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(Galaxian)
 # --------------------
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Catacomb.sv
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Catacomb.sv
+set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/keyboard.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade_MiST/Galaxian Hardware/Catacomb_MiST/rtl/Catacomb.sv

@@ -60,17 +60,17 @@ wire        ps2_kbd_clk, ps2_kbd_data;
 
 assign LED = 1;
 
-wire clk_18, clk_12, clk_6, clk_4p5;
+wire clk_24, clk_18, clk_12, clk_6;
 wire pll_locked;
 
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_18),
-	.c1(clk_12),
-	.c2(clk_6),
-	.c3(clk_4p5)//for now, needs a fix
+	.c0(clk_24),
+	.c1(clk_18),
+	.c2(clk_12),
+	.c3(clk_6)
 );
 
 wire m_up     = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
@@ -106,7 +106,7 @@ wire [7:0] audio_a, audio_b;
 wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
 
 dac dac (
-	.clk_i(clk_18),
+	.clk_i(clk_24),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
@@ -117,18 +117,18 @@ assign AUDIO_R = AUDIO_L;
 wire hs, vs;
 wire [2:0] r, g, b;
 wire hblank, vblank;
-
-video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(0)) video_mixer
+wire blankn = ~(hblank | vblank);
+video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 (
-	.clk_sys(clk_18),
-	.ce_pix(clk_4p5),
-	.ce_pix_actual(clk_4p5),
+	.clk_sys(clk_24),
+	.ce_pix(clk_6),
+	.ce_pix_actual(clk_6),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({r,r}),
-	.G({g,g}),
-	.B({b,b}),
+	.R(blankn?r:"000"),
+	.G(blankn?g:"000"),
+	.B(blankn?b:"000"),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -146,7 +146,7 @@ video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(0)) video_mixer
 
 mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 (
-	.clk_sys        (clk_18   	  ),
+	.clk_sys        (clk_24   	  	  ),
 	.conf_str       (CONF_STR       ),
 	.SPI_SCK        (SPI_SCK        ),
 	.CONF_DATA0     (CONF_DATA0     ),
@@ -165,8 +165,8 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 );
 
 keyboard keyboard(
-	.clk(clk_18),
-	.reset(),
+	.clk(clk_24),
+	.reset(0),
 	.ps2_kbd_clk(ps2_kbd_clk),
 	.ps2_kbd_data(ps2_kbd_data),
 	.joystick(kbjoy)

Arcade_MiST/Galaxian Hardware/Catacomb_MiST/rtl/build_id.v

@@ -1,2 +1,2 @@
-`define BUILD_DATE "180108"
-`define BUILD_TIME "213440"
+`define BUILD_DATE "180624"
+`define BUILD_TIME "123527"

Arcade_MiST/Galaxian Hardware/Catacomb_MiST/rtl/pll.vhd

@@ -159,21 +159,21 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 3,
+		clk0_divide_by => 9,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 2,
+		clk0_multiply_by => 8,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 9,
+		clk1_divide_by => 3,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 4,
+		clk1_multiply_by => 2,
 		clk1_phase_shift => "0",
 		clk2_divide_by => 9,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 2,
+		clk2_multiply_by => 4,
 		clk2_phase_shift => "0",
-		clk3_divide_by => 6,
+		clk3_divide_by => 9,
 		clk3_duty_cycle => 50,
-		clk3_multiply_by => 1,
+		clk3_multiply_by => 2,
 		clk3_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -254,18 +254,18 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
 -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -294,15 +294,15 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
@@ -319,9 +319,9 @@ END SYN;
 -- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -362,21 +362,21 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"

Arcade_MiST/Galaxian Hardware/Galaxian_MiST/Galaxian.qsf

@@ -46,44 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Galaxian.sv
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 
 # Pin & Location Assignments
 # ==========================
@@ -128,7 +90,7 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
 # Analysis & Synthesis Assignments
 # ================================
 set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY Galaxian
+set_global_assignment -name TOP_LEVEL_ENTITY Galaxian_MiST
 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
 set_global_assignment -name SAVE_DISK_SPACE OFF
@@ -177,14 +139,52 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 		# Incremental Compilation Assignments
 		# ===================================
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
 	# end DESIGN_PARTITION(Top)
 	# -------------------------
 
 # end ENTITY(Galaxian)
 # --------------------
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Galaxian_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/keyboard.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 set_global_assignment -name VHDL_FILE rtl/pll.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade_MiST/Galaxian Hardware/Galaxian_MiST/rtl/Galaxian_MiST.sv

@@ -19,7 +19,7 @@
 //  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 //============================================================================
 
-module Galaxian
+module Galaxian_MiST
 (
 	output        LED,
 	output  [5:0] VGA_R,
@@ -43,9 +43,9 @@ module Galaxian
 localparam CONF_STR = {
 	"Galaxian;;",
 	"O2,Joystick Control,Upright,Normal;",
-	"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
+	"O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
 	"T6,Reset;",
-	"V,v1.00.",`BUILD_DATE
+	"V,v1.50.",`BUILD_DATE
 };
 
 wire [31:0] status;
@@ -60,17 +60,17 @@ wire        ps2_kbd_clk, ps2_kbd_data;
 
 assign LED = 1;
 
-wire clk_18, clk_12, clk_6, clk_4p5;
+wire clk_24, clk_18, clk_12, clk_6;
 wire pll_locked;
 
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_18),
-	.c1(clk_12),
-	.c2(clk_6),
-	.c3(clk_4p5)//for now, needs a fix
+	.c0(clk_24),
+	.c1(clk_18),
+	.c2(clk_12),
+	.c3(clk_6)
 );
 
 wire m_up     = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
@@ -83,7 +83,7 @@ wire m_start1 = kbjoy[1];
 wire m_start2 = kbjoy[2];
 wire m_coin   = kbjoy[3];
 
-galaxiant galaxiant
+galaxian galaxian
 (
 	.W_CLK_18M(clk_18),
 	.W_CLK_12M(clk_12),
@@ -106,7 +106,7 @@ wire [7:0] audio_a, audio_b;
 wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
 
 dac dac (
-	.clk_i(clk_18),
+	.clk_i(clk_24),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
@@ -118,11 +118,11 @@ wire hs, vs;
 wire [2:0] r, g, b;
 wire hblank, vblank;
 wire blankn = ~(hblank | vblank);
-video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
+video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer
 (
-	.clk_sys(clk_18),
-	.ce_pix(clk_4p5),
-	.ce_pix_actual(clk_4p5),
+	.clk_sys(clk_24),
+	.ce_pix(clk_6),
+	.ce_pix_actual(clk_6),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
@@ -137,8 +137,8 @@ video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
 	.scandoubler_disable(scandoubler_disable),
-	.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
-	.hq2x(status[4:3]==1),
+	.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 2'b11, status[4:3] == 2'b10, status[4:3] == 2'b01}),
+	.hq2x(0),
 	.ypbpr_full(1),
 	.line_start(0),
 	.mono(0)
@@ -146,7 +146,7 @@ video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 
 mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 (
-	.clk_sys        (clk_18   	  ),
+	.clk_sys        (clk_24   	     ),
 	.conf_str       (CONF_STR       ),
 	.SPI_SCK        (SPI_SCK        ),
 	.CONF_DATA0     (CONF_DATA0     ),
@@ -165,8 +165,8 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 );
 
 keyboard keyboard(
-	.clk(clk_18),
-	.reset(),
+	.clk(clk_24),
+	.reset(0),
 	.ps2_kbd_clk(ps2_kbd_clk),
 	.ps2_kbd_data(ps2_kbd_data),
 	.joystick(kbjoy)

Arcade_MiST/Galaxian Hardware/Galaxian_MiST/rtl/build_id.v

@@ -1,2 +1,2 @@
-`define BUILD_DATE "180103"
-`define BUILD_TIME "171607"
+`define BUILD_DATE "180622"
+`define BUILD_TIME "194104"

Arcade_MiST/Galaxian Hardware/Galaxian_MiST/rtl/galaxian.vhd

@@ -23,7 +23,7 @@ library ieee;
 
 --use work.pkg_galaxian.all;
 
-entity galaxiant is
+entity galaxian is
 	port(
 		W_CLK_18M  : in  std_logic;
 		W_CLK_12M  : in  std_logic;
@@ -46,7 +46,7 @@ entity galaxiant is
 	);
 end;
 
-architecture RTL of galaxiant is
+architecture RTL of galaxian is
 	--    CPU ADDRESS BUS
 	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
 	--    CPU IF

Arcade_MiST/Galaxian Hardware/Galaxian_MiST/rtl/pll.qip

@@ -1,4 +1,4 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
 set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

Arcade_MiST/Galaxian Hardware/Galaxian_MiST/rtl/pll.vhd

@@ -159,21 +159,21 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 3,
+		clk0_divide_by => 9,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 2,
+		clk0_multiply_by => 8,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 9,
+		clk1_divide_by => 3,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 4,
+		clk1_multiply_by => 2,
 		clk1_phase_shift => "0",
 		clk2_divide_by => 9,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 2,
+		clk2_multiply_by => 4,
 		clk2_phase_shift => "0",
-		clk3_divide_by => 6,
+		clk3_divide_by => 9,
 		clk3_duty_cycle => 50,
-		clk3_multiply_by => 1,
+		clk3_multiply_by => 2,
 		clk3_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -254,18 +254,18 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
 -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -294,15 +294,15 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
@@ -319,9 +319,9 @@ END SYN;
 -- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -362,21 +362,21 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"

Arcade_MiST/Galaxian Hardware/MoonCresta_MiST/MoonCresta.qsf

@@ -101,6 +101,21 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
 set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/MoonCresta.sv
+set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
 set_global_assignment -name VHDL_FILE rtl/pll.vhd
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
 set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
@@ -124,20 +139,5 @@ set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
 set_global_assignment -name VHDL_FILE rtl/spram.vhd
 set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/MoonCresta.sv
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
 set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade_MiST/Galaxian Hardware/MoonCresta_MiST/README.txt

@@ -21,5 +21,3 @@
 -- Joystick support.
 -- 
 ---------------------------------------------------------------------------------
-
-ToDo: Video Fix/Rotate

Arcade_MiST/Galaxian Hardware/MoonCresta_MiST/rtl/MoonCresta.sv

@@ -60,19 +60,18 @@ wire        ps2_kbd_clk, ps2_kbd_data;
 
 assign LED = 1;
 
-wire clk_18, clk_12, clk_6, clk_4p5;
+wire clk_24, clk_18, clk_12, clk_6;
 wire pll_locked;
 
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_18),
-	.c1(clk_12),
-	.c2(clk_6),
-	.c3(clk_4p5)//for now, needs a fix
+	.c0(clk_24),
+	.c1(clk_18),
+	.c2(clk_12),
+	.c3(clk_6)
 );
-
 wire m_up     = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[4] | joystick_0[3] | joystick_1[3];
 wire m_down   = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[5] | joystick_0[2] | joystick_1[2];
 wire m_left   = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[6] | joystick_0[1] | joystick_1[1];
@@ -106,7 +105,7 @@ wire [7:0] audio_a, audio_b;
 wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
 
 dac dac (
-	.clk_i(clk_18),
+	.clk_i(clk_24),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
@@ -120,9 +119,9 @@ wire hblank, vblank;
 wire blankn = ~(hblank | vblank);
 video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 (
-	.clk_sys(clk_18),
-	.ce_pix(clk_4p5),
-	.ce_pix_actual(clk_4p5),
+	.clk_sys(clk_24),
+	.ce_pix(clk_6),
+	.ce_pix_actual(clk_6),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
@@ -146,7 +145,7 @@ video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 
 mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 (
-	.clk_sys        (clk_18    	  ),
+	.clk_sys        (clk_24    	  ),
 	.conf_str       (CONF_STR       ),
 	.SPI_SCK        (SPI_SCK        ),
 	.CONF_DATA0     (CONF_DATA0     ),
@@ -165,8 +164,8 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 );
 
 keyboard keyboard(
-	.clk(clk_18),
-	.reset(),
+	.clk(clk_24),
+	.reset(0),
 	.ps2_kbd_clk(ps2_kbd_clk),
 	.ps2_kbd_data(ps2_kbd_data),
 	.joystick(kbjoy)

Arcade_MiST/Galaxian Hardware/MoonCresta_MiST/rtl/build_id.v

@@ -1,2 +1,2 @@
-`define BUILD_DATE "180103"
-`define BUILD_TIME "171046"
+`define BUILD_DATE "180624"
+`define BUILD_TIME "121017"

Arcade_MiST/Galaxian Hardware/MoonCresta_MiST/rtl/pll.vhd

@@ -159,21 +159,21 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 3,
+		clk0_divide_by => 9,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 2,
+		clk0_multiply_by => 8,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 9,
+		clk1_divide_by => 3,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 4,
+		clk1_multiply_by => 2,
 		clk1_phase_shift => "0",
 		clk2_divide_by => 9,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 2,
+		clk2_multiply_by => 4,
 		clk2_phase_shift => "0",
-		clk3_divide_by => 6,
+		clk3_divide_by => 9,
 		clk3_duty_cycle => 50,
-		clk3_multiply_by => 1,
+		clk3_multiply_by => 2,
 		clk3_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -254,18 +254,18 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
 -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -294,15 +294,15 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
@@ -319,9 +319,9 @@ END SYN;
 -- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -362,21 +362,21 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"

Arcade_MiST/Galaxian Hardware/MrDoNightmare_MiST/MrDoNightmare.qsf

@@ -46,44 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrDoNightmare.sv
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 
 # Pin & Location Assignments
 # ==========================
@@ -186,5 +148,43 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
 # end ENTITY(Galaxian)
 # --------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrDoNightmare.sv
+set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/keyboard.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 set_global_assignment -name VHDL_FILE rtl/pll.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade_MiST/Galaxian Hardware/MrDoNightmare_MiST/rtl/MrDoNightmare.sv

@@ -60,17 +60,17 @@ wire        ps2_kbd_clk, ps2_kbd_data;
 
 assign LED = 1;
 
-wire clk_18, clk_12, clk_6, clk_4p5;
+wire clk_24, clk_18, clk_12, clk_6;
 wire pll_locked;
 
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_18),
-	.c1(clk_12),
-	.c2(clk_6),
-	.c3(clk_4p5)//for now, needs a fix
+	.c0(clk_24),
+	.c1(clk_18),
+	.c2(clk_12),
+	.c3(clk_6)
 );
 
 wire m_up     = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
@@ -106,7 +106,7 @@ wire [7:0] audio_a, audio_b;
 wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
 
 dac dac (
-	.clk_i(clk_18),
+	.clk_i(clk_24),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
@@ -120,9 +120,9 @@ wire hblank, vblank;
 wire blankn = ~(hblank | vblank);
 video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 (
-	.clk_sys(clk_18),
-	.ce_pix(clk_4p5),
-	.ce_pix_actual(clk_4p5),
+	.clk_sys(clk_24),
+	.ce_pix(clk_6),
+	.ce_pix_actual(clk_6),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
@@ -146,7 +146,7 @@ video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 
 mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 (
-	.clk_sys        (clk_18   	     ),
+	.clk_sys        (clk_24   	     ),
 	.conf_str       (CONF_STR       ),
 	.SPI_SCK        (SPI_SCK        ),
 	.CONF_DATA0     (CONF_DATA0     ),
@@ -165,8 +165,8 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 );
 
 keyboard keyboard(
-	.clk(clk_18),
-	.reset(),
+	.clk(clk_24),
+	.reset(0),
 	.ps2_kbd_clk(ps2_kbd_clk),
 	.ps2_kbd_data(ps2_kbd_data),
 	.joystick(kbjoy)

Arcade_MiST/Galaxian Hardware/MrDoNightmare_MiST/rtl/build_id.v

@@ -1,2 +1,2 @@
-`define BUILD_DATE "180103"
-`define BUILD_TIME "170728"
+`define BUILD_DATE "180624"
+`define BUILD_TIME "121254"

Arcade_MiST/Galaxian Hardware/MrDoNightmare_MiST/rtl/pll.vhd

@@ -159,21 +159,21 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 3,
+		clk0_divide_by => 9,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 2,
+		clk0_multiply_by => 8,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 9,
+		clk1_divide_by => 3,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 4,
+		clk1_multiply_by => 2,
 		clk1_phase_shift => "0",
 		clk2_divide_by => 9,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 2,
+		clk2_multiply_by => 4,
 		clk2_phase_shift => "0",
-		clk3_divide_by => 6,
+		clk3_divide_by => 9,
 		clk3_duty_cycle => 50,
-		clk3_multiply_by => 1,
+		clk3_multiply_by => 2,
 		clk3_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -254,18 +254,18 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
 -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -294,15 +294,15 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
@@ -319,9 +319,9 @@ END SYN;
 -- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -362,21 +362,21 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"

Arcade_MiST/Galaxian Hardware/Omega_MiST/Omega.qsf

@@ -46,42 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 
 # Pin & Location Assignments
 # ==========================
@@ -181,10 +145,46 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(Galaxian)
 # --------------------
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Omega.sv
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Omega.sv
+set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/keyboard.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade_MiST/Galaxian Hardware/Omega_MiST/README.txt

@@ -21,5 +21,3 @@
 -- Joystick support.
 -- 
 ---------------------------------------------------------------------------------
-
-ToDo: Video Fix/Rotate

Arcade_MiST/Galaxian Hardware/Omega_MiST/rtl/Omega.sv

@@ -60,17 +60,17 @@ wire        ps2_kbd_clk, ps2_kbd_data;
 
 assign LED = 1;
 
-wire clk_18, clk_12, clk_6, clk_4p5;
+wire clk_24, clk_18, clk_12, clk_6;
 wire pll_locked;
 
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_18),
-	.c1(clk_12),
-	.c2(clk_6),
-	.c3(clk_4p5)//for now, needs a fix
+	.c0(clk_24),
+	.c1(clk_18),
+	.c2(clk_12),
+	.c3(clk_6)
 );
 
 wire m_up     = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[4] | joystick_0[3] | joystick_1[3];
@@ -106,7 +106,7 @@ wire [7:0] audio_a, audio_b;
 wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
 
 dac dac (
-	.clk_i(clk_18),
+	.clk_i(clk_24),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
@@ -120,9 +120,9 @@ wire hblank, vblank;
 wire blankn = ~(hblank | vblank);
 video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 (
-	.clk_sys(clk_18),
-	.ce_pix(clk_4p5),
-	.ce_pix_actual(clk_4p5),
+	.clk_sys(clk_24),
+	.ce_pix(clk_6),
+	.ce_pix_actual(clk_6),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
@@ -146,7 +146,7 @@ video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 
 mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 (
-	.clk_sys        (clk_18   	  ),
+	.clk_sys        (clk_24   	     ),
 	.conf_str       (CONF_STR       ),
 	.SPI_SCK        (SPI_SCK        ),
 	.CONF_DATA0     (CONF_DATA0     ),
@@ -165,8 +165,8 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 );
 
 keyboard keyboard(
-	.clk(clk_18),
-	.reset(),
+	.clk(clk_24),
+	.reset(0),
 	.ps2_kbd_clk(ps2_kbd_clk),
 	.ps2_kbd_data(ps2_kbd_data),
 	.joystick(kbjoy)

Arcade_MiST/Galaxian Hardware/Omega_MiST/rtl/build_id.v

@@ -1,2 +1,2 @@
-`define BUILD_DATE "180108"
-`define BUILD_TIME "213858"
+`define BUILD_DATE "180624"
+`define BUILD_TIME "121746"

Arcade_MiST/Galaxian Hardware/Omega_MiST/rtl/pll.vhd

@@ -159,21 +159,21 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 3,
+		clk0_divide_by => 9,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 2,
+		clk0_multiply_by => 8,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 9,
+		clk1_divide_by => 3,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 4,
+		clk1_multiply_by => 2,
 		clk1_phase_shift => "0",
 		clk2_divide_by => 9,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 2,
+		clk2_multiply_by => 4,
 		clk2_phase_shift => "0",
-		clk3_divide_by => 6,
+		clk3_divide_by => 9,
 		clk3_duty_cycle => 50,
-		clk3_multiply_by => 1,
+		clk3_multiply_by => 2,
 		clk3_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -254,18 +254,18 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
 -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -294,15 +294,15 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
@@ -319,9 +319,9 @@ END SYN;
 -- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -362,21 +362,21 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"

Arcade_MiST/Galaxian Hardware/Orbitron_MiST/Orbitron.qsf

@@ -46,44 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Orbitron.sv
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 
 # Pin & Location Assignments
 # ==========================
@@ -186,5 +148,43 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
 # end ENTITY(Galaxian)
 # --------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Orbitron.sv
+set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/keyboard.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 set_global_assignment -name VHDL_FILE rtl/pll.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade_MiST/Galaxian Hardware/Orbitron_MiST/README.txt

@@ -21,5 +21,3 @@
 -- Joystick support.
 -- 
 ---------------------------------------------------------------------------------
-
---Rotate and Fix Video

Arcade_MiST/Galaxian Hardware/Orbitron_MiST/rtl/Orbitron.sv

@@ -60,17 +60,17 @@ wire        ps2_kbd_clk, ps2_kbd_data;
 
 assign LED = 1;
 
-wire clk_18, clk_12, clk_6, clk_4p5;
+wire clk_24, clk_18, clk_12, clk_6;
 wire pll_locked;
 
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_18),
-	.c1(clk_12),
-	.c2(clk_6),
-	.c3(clk_4p5)//for now, needs a fix
+	.c0(clk_24),
+	.c1(clk_18),
+	.c2(clk_12),
+	.c3(clk_6)
 );
 
 wire m_up     = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[4] | joystick_0[3] | joystick_1[3];
@@ -106,7 +106,7 @@ wire [7:0] audio_a, audio_b;
 wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
 
 dac dac (
-	.clk_i(clk_18),
+	.clk_i(clk_24),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
@@ -120,9 +120,9 @@ wire hblank, vblank;
 wire blankn = ~(hblank | vblank);
 video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 (
-	.clk_sys(clk_18),
-	.ce_pix(clk_4p5),
-	.ce_pix_actual(clk_4p5),
+	.clk_sys(clk_24),
+	.ce_pix(clk_6),
+	.ce_pix_actual(clk_6),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
@@ -146,7 +146,7 @@ video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 
 mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 (
-	.clk_sys        (clk_18   	     ),
+	.clk_sys        (clk_24   	     ),
 	.conf_str       (CONF_STR       ),
 	.SPI_SCK        (SPI_SCK        ),
 	.CONF_DATA0     (CONF_DATA0     ),
@@ -165,8 +165,8 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 );
 
 keyboard keyboard(
-	.clk(clk_18),
-	.reset(),
+	.clk(clk_24),
+	.reset(0),
 	.ps2_kbd_clk(ps2_kbd_clk),
 	.ps2_kbd_data(ps2_kbd_data),
 	.joystick(kbjoy)

Arcade_MiST/Galaxian Hardware/Orbitron_MiST/rtl/build_id.v

@@ -1,2 +1,2 @@
-`define BUILD_DATE "180103"
-`define BUILD_TIME "164536"
+`define BUILD_DATE "180624"
+`define BUILD_TIME "121927"

Arcade_MiST/Galaxian Hardware/Orbitron_MiST/rtl/pll.vhd

@@ -159,21 +159,21 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 3,
+		clk0_divide_by => 9,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 2,
+		clk0_multiply_by => 8,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 9,
+		clk1_divide_by => 3,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 4,
+		clk1_multiply_by => 2,
 		clk1_phase_shift => "0",
 		clk2_divide_by => 9,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 2,
+		clk2_multiply_by => 4,
 		clk2_phase_shift => "0",
-		clk3_divide_by => 6,
+		clk3_divide_by => 9,
 		clk3_duty_cycle => 50,
-		clk3_multiply_by => 1,
+		clk3_multiply_by => 2,
 		clk3_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -254,18 +254,18 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
 -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -294,15 +294,15 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
@@ -319,9 +319,9 @@ END SYN;
 -- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -362,21 +362,21 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"

Arcade_MiST/Galaxian Hardware/Pisces_MiST/Pisces.qsf

@@ -46,42 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 
 # Pin & Location Assignments
 # ==========================
@@ -181,10 +145,46 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(Galaxian)
 # --------------------
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Pisces.sv
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Pisces.sv
+set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/keyboard.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade_MiST/Galaxian Hardware/Pisces_MiST/rtl/Pisces.sv

@@ -60,17 +60,17 @@ wire        ps2_kbd_clk, ps2_kbd_data;
 
 assign LED = 1;
 
-wire clk_18, clk_12, clk_6, clk_4p5;
+wire clk_24, clk_18, clk_12, clk_6;
 wire pll_locked;
 
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_18),
-	.c1(clk_12),
-	.c2(clk_6),
-	.c3(clk_4p5)//for now, needs a fix
+	.c0(clk_24),
+	.c1(clk_18),
+	.c2(clk_12),
+	.c3(clk_6)
 );
 
 wire m_up     = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
@@ -106,7 +106,7 @@ wire [7:0] audio_a, audio_b;
 wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
 
 dac dac (
-	.clk_i(clk_18),
+	.clk_i(clk_24),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
@@ -117,18 +117,18 @@ assign AUDIO_R = AUDIO_L;
 wire hs, vs;
 wire [2:0] r, g, b;
 wire hblank, vblank;
-
-video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(0)) video_mixer
+wire blankn = ~(hblank | vblank);
+video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 (
-	.clk_sys(clk_18),
-	.ce_pix(clk_4p5),
-	.ce_pix_actual(clk_4p5),
+	.clk_sys(clk_24),
+	.ce_pix(clk_6),
+	.ce_pix_actual(clk_6),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({r,r}),
-	.G({g,g}),
-	.B({b,b}),
+	.R(blankn?r:"000"),
+	.G(blankn?g:"000"),
+	.B(blankn?b:"000"),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -146,7 +146,7 @@ video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(0)) video_mixer
 
 mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 (
-	.clk_sys        (clk_18   	  ),
+	.clk_sys        (clk_24   	     ),
 	.conf_str       (CONF_STR       ),
 	.SPI_SCK        (SPI_SCK        ),
 	.CONF_DATA0     (CONF_DATA0     ),
@@ -165,8 +165,8 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 );
 
 keyboard keyboard(
-	.clk(clk_18),
-	.reset(),
+	.clk(clk_24),
+	.reset(0),
 	.ps2_kbd_clk(ps2_kbd_clk),
 	.ps2_kbd_data(ps2_kbd_data),
 	.joystick(kbjoy)

Arcade_MiST/Galaxian Hardware/Pisces_MiST/rtl/build_id.v

@@ -1,2 +1,2 @@
-`define BUILD_DATE "180108"
-`define BUILD_TIME "220955"
+`define BUILD_DATE "180624"
+`define BUILD_TIME "123015"

Arcade_MiST/Galaxian Hardware/Pisces_MiST/rtl/pll.vhd

@@ -159,21 +159,21 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 3,
+		clk0_divide_by => 9,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 2,
+		clk0_multiply_by => 8,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 9,
+		clk1_divide_by => 3,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 4,
+		clk1_multiply_by => 2,
 		clk1_phase_shift => "0",
 		clk2_divide_by => 9,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 2,
+		clk2_multiply_by => 4,
 		clk2_phase_shift => "0",
-		clk3_divide_by => 6,
+		clk3_divide_by => 9,
 		clk3_duty_cycle => 50,
-		clk3_multiply_by => 1,
+		clk3_multiply_by => 2,
 		clk3_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -254,18 +254,18 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
 -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -294,15 +294,15 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
@@ -319,9 +319,9 @@ END SYN;
 -- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -362,21 +362,21 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"

Arcade_MiST/Galaxian Hardware/WarOfBugs_MiST/WarOfTheBugs.qsf

@@ -46,42 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 
 # Pin & Location Assignments
 # ==========================
@@ -181,10 +145,46 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(Galaxian)
 # --------------------
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/WarOfTheBugs.sv
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/WarOfTheBugs.sv
+set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/keyboard.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade_MiST/Galaxian Hardware/WarOfBugs_MiST/rtl/WarOfTheBugs.sv

@@ -60,17 +60,17 @@ wire        ps2_kbd_clk, ps2_kbd_data;
 
 assign LED = 1;
 
-wire clk_18, clk_12, clk_6, clk_4p5;
+wire clk_24, clk_18, clk_12, clk_6;
 wire pll_locked;
 
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_18),
-	.c1(clk_12),
-	.c2(clk_6),
-	.c3(clk_4p5)//for now, needs a fix
+	.c0(clk_24),
+	.c1(clk_18),
+	.c2(clk_12),
+	.c3(clk_6)
 );
 
 wire m_up     = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
@@ -106,7 +106,7 @@ wire [7:0] audio_a, audio_b;
 wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
 
 dac dac (
-	.clk_i(clk_18),
+	.clk_i(clk_24),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
@@ -120,9 +120,9 @@ wire hblank, vblank;
 wire blankn = ~(hblank | vblank);
 video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 (
-	.clk_sys(clk_18),
-	.ce_pix(clk_4p5),
-	.ce_pix_actual(clk_4p5),
+	.clk_sys(clk_24),
+	.ce_pix(clk_6),
+	.ce_pix_actual(clk_6),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
@@ -146,7 +146,7 @@ video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
 
 mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 (
-	.clk_sys        (clk_18   	  ),
+	.clk_sys        (clk_24   	     ),
 	.conf_str       (CONF_STR       ),
 	.SPI_SCK        (SPI_SCK        ),
 	.CONF_DATA0     (CONF_DATA0     ),
@@ -165,8 +165,8 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 );
 
 keyboard keyboard(
-	.clk(clk_18),
-	.reset(),
+	.clk(clk_24),
+	.reset(0),
 	.ps2_kbd_clk(ps2_kbd_clk),
 	.ps2_kbd_data(ps2_kbd_data),
 	.joystick(kbjoy)

Arcade_MiST/Galaxian Hardware/WarOfBugs_MiST/rtl/build_id.v

@@ -1,2 +1,2 @@
-`define BUILD_DATE "180103"
-`define BUILD_TIME "163543"
+`define BUILD_DATE "180624"
+`define BUILD_TIME "122526"

Arcade_MiST/Galaxian Hardware/WarOfBugs_MiST/rtl/pll.vhd

@@ -159,21 +159,21 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 3,
+		clk0_divide_by => 9,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 2,
+		clk0_multiply_by => 8,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 9,
+		clk1_divide_by => 3,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 4,
+		clk1_multiply_by => 2,
 		clk1_phase_shift => "0",
 		clk2_divide_by => 9,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 2,
+		clk2_multiply_by => 4,
 		clk2_phase_shift => "0",
-		clk3_divide_by => 6,
+		clk3_divide_by => 9,
 		clk3_duty_cycle => 50,
-		clk3_multiply_by => 1,
+		clk3_multiply_by => 2,
 		clk3_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -254,18 +254,18 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
 -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -294,15 +294,15 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
@@ -319,9 +319,9 @@ END SYN;
 -- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -362,21 +362,21 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"

GCE - Vectrex_MiST/rtl/YM2149_linmix_sep.vhd

@@ -0,0 +1,574 @@
+-- changes for seperate audio outputs and enable now enables cpu access as well
+--
+-- A simulation model of YM2149 (AY-3-8910 with bells on)
+
+-- Copyright (c) MikeJ - Jan 2005
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
+--
+-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
+-- vol 15 .. 0
+-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
+-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
+-- to produced all the required values.
+-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
+--
+-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
+-- accurate for designs where the outputs are buffered and not simply wired together.
+-- The ouput level is more complex in that case and requires a larger table.
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_arith.all;
+  use ieee.std_logic_unsigned.all;
+
+entity YM2149 is
+  port (
+  -- data bus
+  I_DA                : in  std_logic_vector(7 downto 0);
+  O_DA                : out std_logic_vector(7 downto 0);
+  O_DA_OE_L           : out std_logic;
+  -- control
+  I_A9_L              : in  std_logic;
+  I_A8                : in  std_logic;
+  I_BDIR              : in  std_logic;
+  I_BC2               : in  std_logic;
+  I_BC1               : in  std_logic;
+  I_SEL_L             : in  std_logic;
+
+  O_AUDIO             : out std_logic_vector(7 downto 0);
+  O_CHAN              : out std_logic_vector(1 downto 0);
+  -- port a
+  I_IOA               : in  std_logic_vector(7 downto 0);
+  O_IOA               : out std_logic_vector(7 downto 0);
+  O_IOA_OE_L          : out std_logic;
+  -- port b
+  I_IOB               : in  std_logic_vector(7 downto 0);
+  O_IOB               : out std_logic_vector(7 downto 0);
+  O_IOB_OE_L          : out std_logic;
+
+  ENA                 : in  std_logic; -- clock enable for higher speed operation
+  RESET_L             : in  std_logic;
+  CLK                 : in  std_logic  -- note 6 Mhz
+  );
+end;
+
+architecture RTL of YM2149 is
+  type  array_16x8   is array (0 to 15) of std_logic_vector( 7 downto 0);
+  type  array_3x12   is array (1 to  3) of std_logic_vector(11 downto 0);
+
+  signal cnt_div              : std_logic_vector(3 downto 0) := (others => '0');
+  signal cnt_div_t1           : std_logic_vector(3 downto 0);
+  signal noise_div            : std_logic := '0';
+  signal ena_div              : std_logic;
+  signal ena_div_noise        : std_logic;
+  signal poly17               : std_logic_vector(16 downto 0) := (others => '0');
+
+  -- registers
+  signal addr                 : std_logic_vector(7 downto 0);
+  signal busctrl_addr         : std_logic;
+  signal busctrl_we           : std_logic;
+  signal busctrl_re           : std_logic;
+
+  signal reg                  : array_16x8;
+  signal env_reset            : std_logic;
+  signal ioa_inreg            : std_logic_vector(7 downto 0);
+  signal iob_inreg            : std_logic_vector(7 downto 0);
+
+  signal noise_gen_cnt        : std_logic_vector(4 downto 0);
+  signal noise_gen_op         : std_logic;
+  signal tone_gen_cnt         : array_3x12 := (others => (others => '0'));
+  signal tone_gen_op          : std_logic_vector(3 downto 1) := "000";
+
+  signal env_gen_cnt          : std_logic_vector(15 downto 0);
+  signal env_ena              : std_logic;
+  signal env_hold             : std_logic;
+  signal env_inc              : std_logic;
+  signal env_vol              : std_logic_vector(4 downto 0);
+
+  signal tone_ena_l           : std_logic;
+  signal tone_src             : std_logic;
+  signal noise_ena_l          : std_logic;
+  signal chan_vol             : std_logic_vector(4 downto 0);
+
+  signal dac_amp              : std_logic_vector(7 downto 0);
+begin
+  -- cpu i/f
+  p_busdecode            : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
+    variable cs : std_logic;
+    variable sel : std_logic_vector(2 downto 0);
+  begin
+    -- BDIR BC2 BC1 MODE
+    --   0   0   0  inactive
+    --   0   0   1  address
+    --   0   1   0  inactive
+    --   0   1   1  read
+    --   1   0   0  address
+    --   1   0   1  inactive
+    --   1   1   0  write
+    --   1   1   1  read
+    busctrl_addr <= '0';
+    busctrl_we <= '0';
+    busctrl_re <= '0';
+
+    cs := '0';
+    if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
+      cs := '1';
+    end if;
+
+    sel := (I_BDIR & I_BC2 & I_BC1);
+    case sel is
+      when "000" => null;
+      when "001" => busctrl_addr <= '1';
+      when "010" => null;
+      when "011" => busctrl_re   <= cs;
+      when "100" => busctrl_addr <= '1';
+      when "101" => null;
+      when "110" => busctrl_we   <= cs;
+      when "111" => busctrl_addr <= '1';
+      when others => null;
+    end case;
+  end process;
+
+  p_oe                   : process(busctrl_re)
+  begin
+    -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
+    O_DA_OE_L <= not (busctrl_re);
+  end process;
+
+  --
+  -- CLOCKED
+  --
+  p_waddr                : process(RESET_L, CLK)
+  begin
+    -- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+    if (RESET_L = '0') then
+      addr <= (others => '0');
+    elsif rising_edge(CLK) then
+      if (ENA = '1') then
+        if (busctrl_addr = '1') then
+          addr <= I_DA;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_wdata                : process(RESET_L, CLK)
+  begin
+    if (RESET_L = '0') then
+      reg <= (others => (others => '0'));
+      env_reset <= '1';
+    elsif rising_edge(CLK) then
+      if (ENA = '1') then
+        env_reset <= '0';
+        if (busctrl_we = '1') then
+          case addr(3 downto 0) is
+            when x"0" => reg(0)  <= I_DA;
+            when x"1" => reg(1)  <= I_DA;
+            when x"2" => reg(2)  <= I_DA;
+            when x"3" => reg(3)  <= I_DA;
+            when x"4" => reg(4)  <= I_DA;
+            when x"5" => reg(5)  <= I_DA;
+            when x"6" => reg(6)  <= I_DA;
+            when x"7" => reg(7)  <= I_DA;
+            when x"8" => reg(8)  <= I_DA;
+            when x"9" => reg(9)  <= I_DA;
+            when x"A" => reg(10) <= I_DA;
+            when x"B" => reg(11) <= I_DA;
+            when x"C" => reg(12) <= I_DA;
+            when x"D" => reg(13) <= I_DA; env_reset <= '1';
+            when x"E" => reg(14) <= I_DA;
+            when x"F" => reg(15) <= I_DA;
+            when others => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_rdata                : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg)
+  begin
+    O_DA <= (others => '0'); -- 'X'
+    if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
+      case addr(3 downto 0) is
+        when x"0" => O_DA <= reg(0) ;
+        when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
+        when x"2" => O_DA <= reg(2) ;
+        when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
+        when x"4" => O_DA <= reg(4) ;
+        when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
+        when x"6" => O_DA <= "000"  & reg(6)(4 downto 0) ;
+        when x"7" => O_DA <= reg(7) ;
+        when x"8" => O_DA <= "000"  & reg(8)(4 downto 0) ;
+        when x"9" => O_DA <= "000"  & reg(9)(4 downto 0) ;
+        when x"A" => O_DA <= "000"  & reg(10)(4 downto 0) ;
+        when x"B" => O_DA <= reg(11);
+        when x"C" => O_DA <= reg(12);
+        when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
+        when x"E" => if (reg(7)(6) = '0') then -- input
+                       O_DA <= ioa_inreg;
+                     else
+                       O_DA <= reg(14); -- read output reg
+                     end if;
+        when x"F" => if (Reg(7)(7) = '0') then
+                       O_DA <= iob_inreg;
+                     else
+                       O_DA <= reg(15);
+                     end if;
+        when others => null;
+      end case;
+    end if;
+  end process;
+  --
+  p_divider              : process
+  begin
+    wait until rising_edge(CLK);
+    -- / 8 when SEL is high and /16 when SEL is low
+    if (ENA = '1') then
+      ena_div <= '0';
+      ena_div_noise <= '0';
+      if (cnt_div = "0000") then
+        cnt_div <= (not I_SEL_L) & "111";
+        ena_div <= '1';
+
+        noise_div <= not noise_div;
+        if (noise_div = '1') then
+          ena_div_noise <= '1';
+        end if;
+      else
+        cnt_div <= cnt_div - "1";
+      end if;
+    end if;
+  end process;
+
+  p_noise_gen            : process
+    variable noise_gen_comp : std_logic_vector(4 downto 0);
+    variable poly17_zero : std_logic;
+  begin
+    wait until rising_edge(CLK);
+    if (reg(6)(4 downto 0) = "00000") then
+      noise_gen_comp := "00000";
+    else
+      noise_gen_comp := (reg(6)(4 downto 0) - "1");
+    end if;
+
+    poly17_zero := '0';
+    if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
+
+    if (ENA = '1') then
+      if (ena_div_noise = '1') then -- divider ena
+
+        if (noise_gen_cnt >= noise_gen_comp) then
+          noise_gen_cnt <= "00000";
+          poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
+        else
+          noise_gen_cnt <= (noise_gen_cnt + "1");
+        end if;
+      end if;
+    end if;
+  end process;
+  noise_gen_op <= poly17(0);
+
+  p_tone_gens            : process
+    variable tone_gen_freq : array_3x12;
+    variable tone_gen_comp : array_3x12;
+  begin
+    wait until rising_edge(CLK);
+    -- looks like real chips count up - we need to get the Exact behaviour ..
+    tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
+    tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
+    tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
+    -- period 0 = period 1
+    for i in 1 to 3 loop
+      if (tone_gen_freq(i) = x"000") then
+        tone_gen_comp(i) := x"000";
+      else
+        tone_gen_comp(i) := (tone_gen_freq(i) - "1");
+      end if;
+    end loop;
+
+    if (ENA = '1') then
+      for i in 1 to 3 loop
+        if (ena_div = '1') then -- divider ena
+
+          if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
+            tone_gen_cnt(i) <= x"000";
+            tone_gen_op(i) <= not tone_gen_op(i);
+          else
+            tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
+          end if;
+        end if;
+      end loop;
+    end if;
+  end process;
+
+  p_envelope_freq        : process
+    variable env_gen_freq : std_logic_vector(15 downto 0);
+    variable env_gen_comp : std_logic_vector(15 downto 0);
+  begin
+    wait until rising_edge(CLK);
+    env_gen_freq := reg(12) & reg(11);
+    -- envelope freqs 1 and 0 are the same.
+    if (env_gen_freq = x"0000") then
+      env_gen_comp := x"0000";
+    else
+      env_gen_comp := (env_gen_freq - "1");
+    end if;
+
+    if (ENA = '1') then
+      env_ena <= '0';
+      if (ena_div = '1') then -- divider ena
+        if (env_gen_cnt >= env_gen_comp) then
+          env_gen_cnt <= x"0000";
+          env_ena <= '1';
+        else
+          env_gen_cnt <= (env_gen_cnt + "1");
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_envelope_shape       : process(env_reset, reg, CLK)
+    variable is_bot    : boolean;
+    variable is_bot_p1 : boolean;
+    variable is_top_m1 : boolean;
+    variable is_top    : boolean;
+  begin
+        -- envelope shapes
+        -- C AtAlH
+        -- 0 0 x x  \___
+        --
+        -- 0 1 x x  /___
+        --
+        -- 1 0 0 0  \\\\
+        --
+        -- 1 0 0 1  \___
+        --
+        -- 1 0 1 0  \/\/
+        --           ___
+        -- 1 0 1 1  \
+        --
+        -- 1 1 0 0  ////
+        --           ___
+        -- 1 1 0 1  /
+        --
+        -- 1 1 1 0  /\/\
+        --
+        -- 1 1 1 1  /___
+    if (env_reset = '1') then
+      -- load initial state
+      if (reg(13)(2) = '0') then -- attack
+        env_vol <= "11111";
+        env_inc <= '0'; -- -1
+      else
+        env_vol <= "00000";
+        env_inc <= '1'; -- +1
+      end if;
+      env_hold <= '0';
+
+    elsif rising_edge(CLK) then
+      is_bot    := (env_vol = "00000");
+      is_bot_p1 := (env_vol = "00001");
+      is_top_m1 := (env_vol = "11110");
+      is_top    := (env_vol = "11111");
+
+      if (ENA = '1') then
+        if (env_ena = '1') then
+          if (env_hold = '0') then
+            if (env_inc = '1') then
+              env_vol <= (env_vol + "00001");
+            else
+              env_vol <= (env_vol + "11111");
+            end if;
+          end if;
+
+          -- envelope shape control.
+          if (reg(13)(3) = '0') then
+            if (env_inc = '0') then -- down
+              if is_bot_p1 then env_hold <= '1'; end if;
+            else
+              if is_top then env_hold <= '1'; end if;
+            end if;
+          else
+            if (reg(13)(0) = '1') then -- hold = 1
+              if (env_inc = '0') then -- down
+                if (reg(13)(1) = '1') then -- alt
+                  if is_bot    then env_hold <= '1'; end if;
+                else
+                  if is_bot_p1 then env_hold <= '1'; end if;
+                end if;
+              else
+                if (reg(13)(1) = '1') then -- alt
+                  if is_top    then env_hold <= '1'; end if;
+                else
+                  if is_top_m1 then env_hold <= '1'; end if;
+                end if;
+              end if;
+
+            elsif (reg(13)(1) = '1') then -- alternate
+              if (env_inc = '0') then -- down
+                if is_bot_p1 then env_hold <= '1'; end if;
+                if is_bot    then env_hold <= '0'; env_inc <= '1'; end if;
+              else
+                if is_top_m1 then env_hold <= '1'; end if;
+                if is_top    then env_hold <= '0'; env_inc <= '0'; end if;
+              end if;
+            end if;
+
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_chan_mixer           : process(cnt_div, reg, tone_gen_op)
+  begin
+    tone_ena_l  <= '1'; tone_src <= '1';
+    noise_ena_l <= '1'; chan_vol <= "00000";
+    case cnt_div(1 downto 0) is
+      when "00" =>
+        tone_ena_l  <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
+        noise_ena_l <= reg(7)(3);
+      when "01" =>
+        tone_ena_l  <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
+        noise_ena_l <= reg(7)(4);
+      when "10" =>
+        tone_ena_l  <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
+        noise_ena_l <= reg(7)(5);
+      when "11" => null; -- tone gen outputs become valid on this clock
+      when others => null;
+    end case;
+  end process;
+
+  p_op_mixer             : process
+    variable chan_mixed : std_logic;
+    variable chan_amp : std_logic_vector(4 downto 0);
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then
+
+      chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
+
+      chan_amp := (others => '0');
+      if (chan_mixed = '1') then
+        if (chan_vol(4) = '0') then
+          if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
+            chan_amp := "00000";
+          else
+            chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
+          end if;
+        else
+          chan_amp := env_vol(4 downto 0);
+        end if;
+      end if;
+
+      dac_amp <= x"00";
+      case chan_amp is
+        when "11111" => dac_amp <= x"FF";
+        when "11110" => dac_amp <= x"D9";
+        when "11101" => dac_amp <= x"BA";
+        when "11100" => dac_amp <= x"9F";
+        when "11011" => dac_amp <= x"88";
+        when "11010" => dac_amp <= x"74";
+        when "11001" => dac_amp <= x"63";
+        when "11000" => dac_amp <= x"54";
+        when "10111" => dac_amp <= x"48";
+        when "10110" => dac_amp <= x"3D";
+        when "10101" => dac_amp <= x"34";
+        when "10100" => dac_amp <= x"2C";
+        when "10011" => dac_amp <= x"25";
+        when "10010" => dac_amp <= x"1F";
+        when "10001" => dac_amp <= x"1A";
+        when "10000" => dac_amp <= x"16";
+        when "01111" => dac_amp <= x"13";
+        when "01110" => dac_amp <= x"10";
+        when "01101" => dac_amp <= x"0D";
+        when "01100" => dac_amp <= x"0B";
+        when "01011" => dac_amp <= x"09";
+        when "01010" => dac_amp <= x"08";
+        when "01001" => dac_amp <= x"07";
+        when "01000" => dac_amp <= x"06";
+        when "00111" => dac_amp <= x"05";
+        when "00110" => dac_amp <= x"04";
+        when "00101" => dac_amp <= x"03";
+        when "00100" => dac_amp <= x"03";
+        when "00011" => dac_amp <= x"02";
+        when "00010" => dac_amp <= x"02";
+        when "00001" => dac_amp <= x"01";
+        when "00000" => dac_amp <= x"00";
+        when others => null;
+      end case;
+
+      cnt_div_t1 <= cnt_div;
+    end if;
+  end process;
+
+  p_audio_output         : process(RESET_L, CLK)
+  begin
+    if (RESET_L = '0') then
+      O_AUDIO <= (others => '0');
+      O_CHAN  <= (others => '0');
+    elsif rising_edge(CLK) then
+
+      if (ENA = '1') then
+        O_AUDIO <= dac_amp(7 downto 0);
+        O_CHAN  <= cnt_div_t1(1 downto 0);
+      end if;
+    end if;
+  end process;
+
+  p_io_ports             : process(reg)
+  begin
+    O_IOA      <= reg(14);
+    O_IOA_OE_L <= not reg(7)(6);
+    O_IOB      <= reg(15);
+    O_IOB_OE_L <= not reg(7)(7);
+  end process;
+
+  p_io_ports_inreg       : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then -- resync
+      ioa_inreg <= I_IOA;
+      iob_inreg <= I_IOB;
+    end if;
+  end process;
+end architecture RTL;

GCE - Vectrex_MiST/rtl/build_id.v

@@ -1,2 +1,2 @@
-`define BUILD_DATE "180429"
-`define BUILD_TIME "150128"
+`define BUILD_DATE "180624"
+`define BUILD_TIME "125342"

GCE - Vectrex_MiST/rtl/sp0256.vhd

@@ -0,0 +1,427 @@
+---------------------------------------------------------------------------------
+-- sp0256 by Dar (darfpga@aol.fr) (14/04/2018)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+--
+-- SP0256-al2 prom decoding scheme and speech synthesis algorithm are from :
+--
+-- Copyright Joseph Zbiciak, all rights reserved.
+-- Copyright tim lindner, all rights reserved.
+--
+-- See C source code and license in sp0256.c from MAME source
+--
+-- VHDL code is by Dar.
+--
+---------------------------------------------------------------------------------
+--
+--	 One allophone is made of N parts (called here after lines), each part has a
+--  16 bytes descriptor. One descriptor (for one part) contains one repeat value
+--  one amplitude value, one period value and 2x6 filtering coefficients.
+--
+--  for line_cnt from 0 to nb_line-1 (part)
+--		for line_rpt from 0 to line_rpt-1 (repeat)
+--			for per_cnt from 0 to line_per-1 (period) 
+--				produce 1 sample
+--
+--  One sample is the output of the 6 stages filter. Each filter stage is fed by
+--  the output of the previous stage, the first stage is fed by the source sample
+--
+--  when line_per != 0 source sample is set to amplitude value only once at the
+--  begin of each repeat (per_cnt==0) then source sample is set to 0
+--
+--  when line_per == 0 source sample is set to amplitude value only at the begin 
+--  of each repeat (per_cnt==0) then source sample sign is toggled (+/-) when then
+--  random noise generator lsb equal 1. In that case actual line_per is set to 64
+--
+--  
+--  Sound sample frequency is 10kHz. I make a 25 stages linear state machine 
+--  running at 250kHz that produce one sound sample per cycle.
+--
+--  As long as one allophones is available the state machine runs permanently and
+--  there is zero latency between allophones.
+--
+--  During one (each) cycle the state machine:
+--
+--    - fetch new allophone or go on with current one if not finished
+--    - get allophone first line descriptor address from rom entry table
+--    - get allophone nb_line from rom entry table and jump to first line address
+--    - get allophone line_rpt from rom current line descriptor
+--    - get allophone amplitude from rom current line descriptor
+--         manage source amplitude, reset filter if needed
+--    - get allophone line_per from rom current line descriptor
+--    - address filter coefficients F/B within rom current line descriptor,
+--         feed filter input, update filter state with computation output 
+--    - rescale last filter stage output to audio output 
+--    - manage per_cnt, rpt_cnt, line_cnt and random noise generator
+--
+--  Filter computation:
+--
+--	   Filter coefficients F or B index is get from rom current line descriptor
+--    (address managed by state machine), value is converted thru coeff_array
+--    table. Coefficient index has a sign bit to be managed:
+--
+--      if index sign bit = 0, filter coefficient <= -coeff_array(index)
+--      if index sign bit = 1, filter coefficient <= coeff_array(-index)
+--
+--    During one state machine cycle each filter is updated once.
+--    One filter update require two state machine steps:
+--	
+--      step 1
+-- 			sum_in1 <= filter input
+--          sum_in2 <= filter coefficient F * filter state z1 / 256
+--          sum_out <= sum_in1 + sum_in2
+--      step 2
+-- 			sum_in1 <= sum_out
+--          sum_in2 <= filter coefficient B * filter state z2 / 512
+--          sum_out <= sum_in1 + sum_in2
+--          filter state z1 <= sum_in1 + sum_in2 
+--          filter state z2 <= filter state z1 
+--
+--		(sum_out will be limited to -32768/+32767)
+--
+--  Audio output scaling to 10bits unsigned:
+--
+--    what :
+--      Last filter output is limited to -8192/+8191
+--      Then divided by 16 => -512/+511
+--      Then offset by 512 => 0/1023
+--
+--    how: 
+--      if    X >  8191, Y <= 1023
+--      elsif X < -8192, Y <= 0
+--      else             Y <= (X/16)+512
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity sp0256 is
+port
+(
+	clock_250k   : in std_logic;
+	reset        : in std_logic;
+
+	input_rdy      : out std_logic;
+	allophone      : in  std_logic_vector(5 downto 0);
+	trig_allophone : in  std_logic;
+	
+	audio_out    : out std_logic_vector(9 downto 0)
+);
+end sp0256;
+
+architecture syn of sp0256 is
+  
+ signal clock_250k_n : std_logic;
+ signal rom_addr : std_logic_vector(11 downto 0);
+ signal rom_do   : std_logic_vector( 7 downto 0);
+
+ signal stage : integer range 0 to 24; -- stage counter 0-24;
+ 
+ signal allo_entry                   : std_logic_vector(7 downto 0);
+ signal allo_addr_lsb, allo_addr_msb : std_logic_vector(7 downto 0);
+ signal allo_nb_line                 : std_logic_vector(7 downto 0);
+ signal line_rpt, line_per           : std_logic_vector(7 downto 0);
+ signal line_amp_lsb, line_amp_msb   : std_logic_vector(7 downto 0);
+ 
+ signal amp, filter, coeff : signed(15 downto 0); 
+ signal sum_in2            : signed(31 downto 0);
+ signal sum_in1,sum_out_ul : signed(15 downto 0);
+ signal sum_out            : signed(15 downto 0);
+ signal divider            : std_logic;
+ signal audio              : signed(15 downto 0);
+
+ signal is_noise  : std_logic;
+ signal noise_rng : std_logic_vector(15 downto 0) := X"0001";
+ 
+ signal f0_z1,f0_z2 : signed(15 downto 0);
+ signal f1_z1,f1_z2 : signed(15 downto 0);
+ signal f2_z1,f2_z2 : signed(15 downto 0);
+ signal f3_z1,f3_z2 : signed(15 downto 0);
+ signal f4_z1,f4_z2 : signed(15 downto 0);
+ signal f5_z1,f5_z2 : signed(15 downto 0);
+  
+ signal input_rdy_in     : std_logic;
+ signal sound_on         : std_logic := '0';
+ signal trig_allophone_r : std_logic;
+ signal line_cnt, rpt_cnt, per_cnt : std_logic_vector(7 downto 0);
+ 
+ signal coeff_idx : std_logic_vector(6 downto 0);
+ 
+ type coeff_array_t is array(0 to  127) of integer range 0 to 511;
+ signal coeff_array : coeff_array_t := (
+    0,      9,      17,     25,     33,     41,     49,     57,
+    65,     73,     81,     89,     97,     105,    113,    121,
+    129,    137,    145,    153,    161,    169,    177,    185,
+    193,    201,    209,    217,    225,    233,    241,    249,
+    257,    265,    273,    281,    289,    297,    301,    305,
+    309,    313,    317,    321,    325,    329,    333,    337,
+    341,    345,    349,    353,    357,    361,    365,    369,
+    373,    377,    381,    385,    389,    393,    397,    401,
+    405,    409,    413,    417,    421,    425,    427,    429,
+    431,    433,    435,    437,    439,    441,    443,    445,
+    447,    449,    451,    453,    455,    457,    459,    461,
+    463,    465,    467,    469,    471,    473,    475,    477,
+    479,    481,    482,    483,    484,    485,    486,    487,
+    488,    489,    490,    491,    492,    493,    494,    495,
+    496,    497,    498,    499,    500,    501,    502,    503,
+    504,    505,    506,    507,    508,    509,    510,    511);
+
+begin
+
+input_rdy <= input_rdy_in;
+clock_250k_n <= not clock_250k;
+
+-- stage counter : Fs=250k/25 = 10kHz
+process (clock_250k, reset)
+  begin
+	if reset='1' then
+		stage <= 0;
+	else
+      if rising_edge(clock_250k) then
+			if stage >= 24 then 
+				stage <= 0;
+			else
+				stage <= stage + 1;
+			end if;
+		end if;
+	end if;
+end process;
+
+process (clock_250k, reset)
+  begin
+	if reset='1' then
+		input_rdy_in <= '1';
+		sound_on  <= '0';
+		noise_rng <= X"0001";
+	else
+      if rising_edge(clock_250k) then
+			
+			trig_allophone_r <= trig_allophone;
+			if trig_allophone = '1' and trig_allophone_r = '0' then
+				input_rdy_in <= '0';
+			end if;
+			
+			if sound_on = '0' then
+			
+				if stage = 0 and input_rdy_in = '0' then
+					allo_entry <=       allophone*"11";
+					rom_addr   <= X"0"&(allophone*"11");
+					line_cnt   <= (others => '0');
+					rpt_cnt    <= (others => '0');
+					per_cnt    <= (others => '0');
+					sound_on   <= '1';
+					input_rdy_in <= '1';
+				end if;
+				
+			else -- sound is on	
+					
+				case stage is
+					when 0 =>
+						rom_addr <= X"0"&allo_entry;						
+					when 1 =>
+						allo_addr_msb <= rom_do;
+						rom_addr <= rom_addr + '1';
+					when 2 =>
+						allo_addr_lsb <= rom_do;
+						rom_addr <= rom_addr + '1';
+					when 3 =>
+						allo_nb_line <= rom_do - '1';
+						rom_addr <= (allo_addr_lsb +line_cnt) & X"0";
+					when 4 =>
+						line_rpt <= rom_do - '1';
+						rom_addr <= rom_addr + '1';
+					when 5 =>
+						line_amp_msb <= rom_do;
+						rom_addr <= rom_addr + '1';
+					when 6 =>
+						
+						if per_cnt = X"00" then
+							amp <= signed(line_amp_msb & rom_do);
+						else
+							if is_noise = '1' then
+								if noise_rng(0) = '1' then
+									amp <= -amp;
+								end if;
+							else
+								amp <= (others => '0');
+							end if;
+						end if;
+						
+						if per_cnt = X"00"then
+							f0_z1 <= (others => '0'); f0_z2 <= (others => '0');
+							f1_z1 <= (others => '0'); f1_z2 <= (others => '0');
+							f2_z1 <= (others => '0'); f2_z2 <= (others => '0');
+							f3_z1 <= (others => '0'); f3_z2 <= (others => '0');
+							f4_z1 <= (others => '0'); f4_z2 <= (others => '0');
+							f5_z1 <= (others => '0'); f5_z2 <= (others => '0');
+						end if;
+							
+						rom_addr <= rom_addr + '1';
+						
+					when 7 =>
+						if rom_do = X"00" then 
+							line_per <= X"40";
+							is_noise <= '1';
+						else
+							line_per <= rom_do - '1';
+							is_noise <= '0';
+						end if;
+						sum_in1  <= amp;
+						filter   <= f0_z1;
+						divider  <= '0';
+						rom_addr <= rom_addr + '1';
+					when 8 =>
+						sum_in1  <= sum_out;
+						filter   <= f0_z2;
+						divider  <= '1';
+						rom_addr <= rom_addr + '1';
+						
+					when 9 =>
+						f0_z1    <= sum_out;
+						f0_z2    <= f0_z1;
+						sum_in1  <= sum_out;
+						filter   <= f1_z1;
+						divider  <= '0';
+						rom_addr <= rom_addr + '1';
+					when 10 =>
+						sum_in1  <= sum_out;
+						filter   <= f1_z2;
+						divider  <= '1';
+						rom_addr <= rom_addr + '1';
+						
+					when 11 =>
+						f1_z1    <= sum_out;
+						f1_z2    <= f1_z1;
+						sum_in1  <= sum_out;
+						filter   <= f2_z1;
+						divider  <= '0';
+						rom_addr <= rom_addr + '1';
+					when 12 =>
+						sum_in1  <= sum_out;
+						filter   <= f2_z2;
+						divider  <= '1';
+						rom_addr <= rom_addr + '1';
+						
+					when 13 =>
+						f2_z1    <= sum_out;
+						f2_z2    <= f2_z1;
+						sum_in1  <= sum_out;
+						filter   <= f3_z1;
+						divider  <= '0';
+						rom_addr <= rom_addr + '1';
+					when 14 =>
+						sum_in1  <= sum_out;
+						filter   <= f3_z2;
+						divider  <= '1';
+						rom_addr <= rom_addr + '1';
+
+					when 15 =>
+						f3_z1    <= sum_out;
+						f3_z2    <= f3_z1;
+						sum_in1  <= sum_out;
+						filter   <= f4_z1;
+						divider  <= '0';
+						rom_addr <= rom_addr + '1';
+					when 16 =>
+						sum_in1  <= sum_out;
+						filter   <= f4_z2;
+						divider  <= '1';
+						rom_addr <= rom_addr + '1';
+
+					when 17 =>
+						f4_z1    <= sum_out;
+						f4_z2    <= f4_z1;
+						sum_in1  <= sum_out;
+						filter   <= f5_z1;
+						divider  <= '0';
+						rom_addr <= rom_addr + '1';
+					when 18 =>
+						sum_in1  <= sum_out;
+						filter   <= f5_z2;
+						divider  <= '1';
+						rom_addr <= rom_addr + '1';
+						
+					when 19 =>
+						f5_z1    <= sum_out;
+						f5_z2    <= f5_z1;
+						
+						if sum_out > 510*16 then
+							audio <= to_signed(1023,16);
+						elsif sum_out < -510*16 then
+							audio <= to_signed(0,16);
+						else
+							audio <= (sum_out/16)+X"0200";						
+						end if;
+					
+					when 20 =>					
+						if per_cnt >= line_per then
+							per_cnt <= (others => '0');
+							if rpt_cnt >= line_rpt then
+								rpt_cnt <= (others => '0');
+								if line_cnt >= allo_nb_line then
+									line_cnt <= (others => '0');
+									sound_on <= '0';
+								else
+									line_cnt <= line_cnt + '1';
+								end if;
+								is_noise <= '0';
+							else
+								rpt_cnt <= rpt_cnt + '1';
+							end if;
+						else
+							per_cnt <= per_cnt + '1';
+						end if;
+						
+						if noise_rng(0) = '1' then
+							noise_rng <= ('0' & noise_rng(15 downto 1) ) xor X"4001";
+						else
+							noise_rng <=  '0' & noise_rng(15 downto 1);
+						end if;
+
+					when others => null;
+				end case;
+			
+			end if;
+	
+		end if;
+	end if;
+end process;
+
+
+audio_out <= std_logic_vector(unsigned(audio(9 downto 0)));
+
+-- filter computation
+coeff_idx <= rom_do(6 downto 0) when rom_do(7)='0' else
+				 not(rom_do(6 downto 0)) + '1';
+
+coeff <= -to_signed(coeff_array(to_integer(unsigned(coeff_idx))),16) when  rom_do(7)='0' else
+			 to_signed(coeff_array(to_integer(unsigned(coeff_idx))),16);
+
+sum_in2 <= (filter * coeff) / 256 when divider = '0' else 
+           (filter * coeff) / 512 ;
+
+sum_out_ul <= sum_in1 + sum_in2(15 downto 0);
+
+sum_out <= to_signed( 32767,16) when sum_out_ul >  32767 else
+			  to_signed(-32768,16) when sum_out_ul < -32768 else
+			  sum_out_ul;
+			  
+
+-- sp0256-al2 prom (decoded)
+sp0256_al2_decoded : entity work.sp0256_al2_decoded
+port map(
+ clk  => clock_250k_n,
+ addr => rom_addr,
+ data => rom_do  
+);
+
+
+end syn;

GCE - Vectrex_MiST/rtl/sp0256_al2_decoded.vhd

@@ -0,0 +1,373 @@
+---------------------------------------------------------------------------------
+-- sp0256 by Dar (darfpga@aol.fr) (14/04/2018)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+--
+-- SP0256-al2 prom decoding scheme and speech synthesis algorithm are from :
+--
+-- Copyright Joseph Zbiciak, all rights reserved.
+-- Copyright tim lindner, all rights reserved.
+--
+-- See C source code and license in sp0256.c from MAME source
+--
+-- VHDL code is by Dar.
+--
+---------------------------------------------------------------------------------
+-- Original sp0256 prom is bit compressed. I used sp0256.c from MAME to produce
+-- an uncompressed and more easy format to be used in FPGA.
+--
+-- Original prom is 2K, uncompressed prom is 4k.
+--
+-- Uncompressed format is :
+--
+--   64 entries table of 3 bytes/entry : adr_msb, adr_lsb, nb_line (nb parts)
+--   (1 entry per allophone)
+--
+--   Each allophone is made of #nb_line parts
+--
+--   Each part is described by 16 bytes (one line) : 
+--  
+--    rpt              : repeat nb 
+--    amp_msb, amp_lsb : amplitude
+--    per              : periode (number of sample to be produced for each rpt)
+--    F0|B0|F1|B1|F2|B2|F3|B3|F4|B4|F5|B5 : filtering coefficients
+--
+---------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity sp0256_al2_decoded is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(11 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of sp0256_al2_decoded is
+	type rom is array(0 to  4095) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+-- adr_msb|adr_lsb|nb_line
+X"00",X"0C",X"01", -- #00 : 000-002
+X"00",X"0D",X"01", -- #01 : 003-005
+X"00",X"0E",X"01", -- #02 : 006-008
+X"00",X"0F",X"01", -- #03 : 009-00B
+X"00",X"10",X"01", -- #04 : 00C-00E
+X"00",X"11",X"0A", -- #05 : 00F-011
+X"00",X"1B",X"0A", -- #06 : 012-014
+X"00",X"25",X"01", -- #07 : 015-017
+X"00",X"26",X"03", -- #08 : 018-01A
+X"00",X"29",X"03", -- #09 : 01B-01D
+X"00",X"2C",X"03", -- #0A : 01E-020
+X"00",X"2F",X"03", -- #0B : 021-023
+X"00",X"32",X"01", -- #0C : 024-026
+X"00",X"33",X"04", -- #0D : 027-029
+X"00",X"37",X"06", -- #0E : 02A-02C
+X"00",X"3D",X"01", -- #0F : 02D-02F
+X"00",X"3E",X"04", -- #10 : 030-032
+X"00",X"42",X"03", -- #11 : 033-035
+X"00",X"45",X"02", -- #12 : 036-038
+X"00",X"47",X"06", -- #13 : 039-03B
+X"00",X"4D",X"08", -- #14 : 03C-03E
+X"00",X"55",X"02", -- #15 : 03F-041
+X"00",X"57",X"03", -- #16 : 042-044
+X"00",X"5A",X"01", -- #17 : 045-047
+X"00",X"5B",X"03", -- #18 : 048-04A
+X"00",X"5E",X"06", -- #19 : 04B-04D
+X"00",X"64",X"01", -- #1A : 04E-050
+X"00",X"65",X"03", -- #1B : 051-053
+X"00",X"68",X"02", -- #1C : 054-056
+X"00",X"6A",X"01", -- #1D : 057-059
+X"00",X"6B",X"01", -- #1E : 05A-05C
+X"00",X"6C",X"03", -- #1F : 05D-05F
+X"00",X"6F",X"05", -- #20 : 060-062
+X"00",X"74",X"03", -- #21 : 063-065
+X"00",X"77",X"03", -- #22 : 066-068
+X"00",X"7A",X"03", -- #23 : 069-06B
+X"00",X"7D",X"03", -- #24 : 06C-06E
+X"00",X"80",X"04", -- #25 : 06F-071
+X"00",X"84",X"02", -- #26 : 072-074
+X"00",X"86",X"03", -- #27 : 075-077
+X"00",X"89",X"01", -- #28 : 078-07A
+X"00",X"8A",X"03", -- #29 : 07B-07D
+X"00",X"8D",X"04", -- #2A : 07E-080
+X"00",X"91",X"03", -- #2B : 081-083
+X"00",X"94",X"04", -- #2C : 084-086
+X"00",X"98",X"03", -- #2D : 087-089
+X"00",X"9B",X"03", -- #2E : 08A-08C
+X"00",X"9E",X"0D", -- #2F : 08D-08F
+X"00",X"AB",X"04", -- #30 : 090-092
+X"00",X"AF",X"04", -- #31 : 093-095
+X"00",X"B3",X"03", -- #32 : 096-098
+X"00",X"B6",X"09", -- #33 : 099-09B
+X"00",X"BF",X"0A", -- #34 : 09C-09E
+X"00",X"C9",X"06", -- #35 : 09F-0A1
+X"00",X"CF",X"02", -- #36 : 0A2-0A4
+X"00",X"D1",X"01", -- #37 : 0A5-0A7
+X"00",X"D2",X"06", -- #38 : 0A8-0AA
+X"00",X"D8",X"02", -- #39 : 0AB-0AD
+X"00",X"DA",X"09", -- #3A : 0AE-0B0
+X"00",X"E3",X"09", -- #3B : 0B1-0B3
+X"00",X"EC",X"08", -- #3C : 0B4-0B6
+X"00",X"F4",X"03", -- #3D : 0B7-0B9
+X"00",X"F7",X"03", -- #3E : 0BA-0BC
+X"00",X"FA",X"03", -- #3F : 0BD-0BF
+-- rpt|amp_msb mp_lsb|per|F0|B0|F1|B1|F2|B2|F3|B3|F4|B4|F5|B5
+X"01",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #00.0 : 0C0-0CF
+X"04",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #01.0 : 0D0-0DF
+X"07",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #02.0 : 0E0-0EF
+X"0F",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #03.0 : 0F0-0FF
+X"1F",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #04.0 : 100-10F
+X"03",X"01",X"40",X"5B",X"A0",X"60",X"B8",X"60",X"F8",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #05.0 : 110-11F
+X"03",X"00",X"C0",X"5B",X"A0",X"60",X"B0",X"60",X"F8",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #05.1 : 120-12F
+X"01",X"00",X"50",X"5B",X"A0",X"60",X"A8",X"60",X"F8",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #05.2 : 130-13F
+X"03",X"00",X"80",X"5B",X"A0",X"60",X"B0",X"60",X"F8",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #05.3 : 140-14F
+X"01",X"00",X"70",X"5B",X"A0",X"60",X"B0",X"60",X"F8",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #05.4 : 150-15F
+X"04",X"00",X"A0",X"5B",X"A0",X"60",X"B8",X"60",X"F8",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #05.5 : 160-16F
+X"02",X"01",X"C0",X"5B",X"A8",X"60",X"C0",X"60",X"F8",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #05.6 : 170-17F
+X"04",X"02",X"80",X"5B",X"A8",X"60",X"D0",X"60",X"F8",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #05.7 : 180-18F
+X"02",X"02",X"80",X"5B",X"A8",X"60",X"E0",X"60",X"F8",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #05.8 : 190-19F
+X"09",X"01",X"00",X"5B",X"A0",X"60",X"E8",X"60",X"F8",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #05.9 : 1A0-1AF
+X"01",X"03",X"00",X"5B",X"B0",X"70",X"C8",X"70",X"F8",X"60",X"18",X"50",X"3C",X"44",X"00",X"00", -- #06.0 : 1B0-1BF
+X"01",X"02",X"80",X"5B",X"C8",X"70",X"B0",X"70",X"F8",X"60",X"18",X"50",X"3C",X"44",X"00",X"00", -- #06.1 : 1C0-1CF
+X"02",X"03",X"00",X"5B",X"C8",X"70",X"B0",X"70",X"F8",X"60",X"18",X"50",X"3C",X"44",X"00",X"00", -- #06.2 : 1D0-1DF
+X"02",X"02",X"80",X"5B",X"B0",X"70",X"C8",X"70",X"F8",X"60",X"18",X"50",X"3C",X"44",X"00",X"00", -- #06.3 : 1E0-1EF
+X"02",X"02",X"00",X"5B",X"C8",X"70",X"F8",X"70",X"B8",X"60",X"18",X"50",X"3C",X"44",X"00",X"00", -- #06.4 : 1F0-1FF
+X"02",X"02",X"80",X"5B",X"B0",X"70",X"D0",X"70",X"F8",X"60",X"18",X"50",X"3C",X"44",X"00",X"00", -- #06.5 : 200-20F
+X"03",X"03",X"80",X"5B",X"B0",X"70",X"F8",X"70",X"E0",X"60",X"18",X"50",X"3C",X"44",X"00",X"00", -- #06.6 : 210-21F
+X"01",X"03",X"00",X"5B",X"A8",X"70",X"E0",X"70",X"F8",X"60",X"18",X"50",X"3C",X"44",X"00",X"00", -- #06.7 : 220-22F
+X"03",X"02",X"80",X"5B",X"A0",X"70",X"E8",X"70",X"00",X"60",X"18",X"50",X"3C",X"44",X"00",X"00", -- #06.8 : 230-23F
+X"02",X"01",X"00",X"5B",X"A0",X"70",X"F0",X"70",X"00",X"60",X"18",X"50",X"3C",X"44",X"00",X"00", -- #06.9 : 240-24F
+X"06",X"06",X"00",X"5B",X"00",X"50",X"28",X"50",X"40",X"50",X"F8",X"10",X"E8",X"58",X"AA",X"64", -- #07.0 : 250-25F
+X"04",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #08.0 : 260-26F
+X"03",X"00",X"28",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"40",X"FC",X"04",X"CB",X"68", -- #08.1 : 270-27F
+X"05",X"00",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"18",X"20",X"40",X"C5",X"62", -- #08.2 : 280-28F
+X"0D",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #09.0 : 290-29F
+X"04",X"00",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"28",X"40",X"F4",X"2C",X"BF",X"3B", -- #09.1 : 2A0-2AF
+X"06",X"00",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"28",X"50",X"F8",X"44",X"CF",X"3A", -- #09.2 : 2B0-2BF
+X"04",X"00",X"50",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"28",X"20",X"18",X"42",X"FA",X"30", -- #0A.0 : 2C0-2CF
+X"04",X"01",X"C0",X"5B",X"18",X"60",X"30",X"50",X"38",X"20",X"00",X"10",X"00",X"60",X"E6",X"38", -- #0A.1 : 2D0-2DF
+X"04",X"01",X"40",X"5B",X"18",X"50",X"28",X"40",X"40",X"30",X"FC",X"68",X"E8",X"52",X"DD",X"16", -- #0A.2 : 2E0-2EF
+X"07",X"00",X"38",X"5B",X"00",X"30",X"18",X"20",X"38",X"40",X"FC",X"60",X"E0",X"2A",X"A1",X"54", -- #0B.0 : 2F0-2FF
+X"03",X"00",X"50",X"5B",X"08",X"30",X"20",X"30",X"20",X"10",X"FC",X"68",X"E8",X"1C",X"A2",X"50", -- #0B.1 : 300-30F
+X"09",X"00",X"60",X"5B",X"08",X"30",X"20",X"40",X"20",X"10",X"FC",X"68",X"E0",X"24",X"9B",X"5B", -- #0B.2 : 310-31F
+X"05",X"06",X"00",X"5B",X"00",X"50",X"10",X"20",X"30",X"50",X"E8",X"60",X"34",X"1E",X"A0",X"6E", -- #0C.0 : 320-32F
+X"05",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #0D.0 : 330-33F
+X"03",X"00",X"A0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"34",X"28",X"1C",X"4E",X"F4",X"21", -- #0D.1 : 340-34F
+X"04",X"00",X"50",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"20",X"1C",X"44",X"EA",X"53", -- #0D.2 : 350-35F
+X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"24",X"18",X"1C",X"46",X"E7",X"5A", -- #0D.3 : 360-36F
+X"05",X"00",X"1C",X"5B",X"98",X"60",X"C0",X"60",X"E0",X"50",X"0C",X"40",X"20",X"3C",X"32",X"2B", -- #0E.0 : 370-37F
+X"03",X"00",X"50",X"5B",X"98",X"60",X"C0",X"60",X"E8",X"50",X"0C",X"40",X"20",X"3C",X"32",X"2B", -- #0E.1 : 380-38F
+X"01",X"00",X"C0",X"5B",X"98",X"60",X"C0",X"60",X"E8",X"50",X"0C",X"40",X"20",X"3C",X"32",X"2B", -- #0E.2 : 390-39F
+X"02",X"02",X"80",X"5B",X"A0",X"60",X"C0",X"60",X"F0",X"50",X"0C",X"40",X"20",X"3C",X"32",X"2B", -- #0E.3 : 3A0-3AF
+X"01",X"01",X"C0",X"5B",X"A0",X"60",X"B8",X"60",X"F0",X"50",X"0C",X"40",X"20",X"3C",X"32",X"2B", -- #0E.4 : 3B0-3BF
+X"02",X"02",X"00",X"5B",X"A0",X"60",X"B8",X"60",X"F0",X"50",X"0C",X"40",X"20",X"3C",X"32",X"2B", -- #0E.5 : 3C0-3CF
+X"06",X"06",X"00",X"5B",X"F0",X"50",X"18",X"20",X"28",X"60",X"D0",X"60",X"28",X"18",X"A8",X"61", -- #0F.0 : 3D0-3DF
+X"06",X"00",X"A0",X"5B",X"F0",X"50",X"C0",X"30",X"E0",X"20",X"00",X"10",X"20",X"44",X"00",X"00", -- #10.0 : 3E0-3EF
+X"05",X"00",X"C0",X"5B",X"F0",X"50",X"C0",X"30",X"E0",X"20",X"00",X"10",X"20",X"44",X"00",X"00", -- #10.1 : 3F0-3FF
+X"05",X"00",X"E0",X"5B",X"F0",X"50",X"E0",X"30",X"C8",X"20",X"00",X"10",X"20",X"44",X"00",X"00", -- #10.2 : 400-40F
+X"04",X"01",X"40",X"5B",X"F0",X"50",X"E0",X"30",X"C8",X"20",X"00",X"10",X"20",X"44",X"00",X"00", -- #10.3 : 410-41F
+X"06",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #11.0 : 420-42F
+X"01",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"48",X"10",X"40",X"DF",X"3F", -- #11.1 : 430-43F
+X"05",X"00",X"28",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"24",X"18",X"28",X"40",X"E8",X"3F", -- #11.2 : 440-44F
+X"0C",X"00",X"A0",X"5B",X"08",X"30",X"18",X"30",X"38",X"40",X"EC",X"30",X"D4",X"2E",X"CB",X"20", -- #12.0 : 450-45F
+X"03",X"02",X"80",X"5B",X"00",X"60",X"18",X"50",X"38",X"50",X"F4",X"08",X"DC",X"5E",X"A1",X"5C", -- #12.1 : 460-46F
+X"03",X"06",X"00",X"5B",X"08",X"00",X"28",X"40",X"38",X"40",X"04",X"60",X"F0",X"66",X"A1",X"5A", -- #13.0 : 470-47F
+X"03",X"06",X"00",X"5B",X"28",X"40",X"38",X"40",X"08",X"00",X"04",X"50",X"F4",X"62",X"A4",X"57", -- #13.1 : 480-48F
+X"02",X"06",X"00",X"5B",X"08",X"10",X"28",X"50",X"38",X"40",X"04",X"48",X"F4",X"64",X"9A",X"62", -- #13.2 : 490-49F
+X"03",X"06",X"00",X"5B",X"08",X"20",X"28",X"50",X"38",X"40",X"04",X"38",X"F8",X"60",X"96",X"66", -- #13.3 : 4A0-4AF
+X"04",X"04",X"00",X"5B",X"08",X"30",X"28",X"50",X"38",X"50",X"FC",X"20",X"F8",X"62",X"92",X"6E", -- #13.4 : 4B0-4BF
+X"04",X"01",X"40",X"5B",X"08",X"40",X"28",X"40",X"38",X"40",X"F8",X"60",X"F4",X"0C",X"90",X"71", -- #13.5 : 4C0-4CF
+X"03",X"03",X"00",X"5B",X"A0",X"70",X"E8",X"60",X"00",X"20",X"04",X"30",X"28",X"52",X"00",X"00", -- #14.0 : 4D0-4DF
+X"01",X"03",X"00",X"5B",X"A0",X"70",X"F0",X"60",X"00",X"20",X"04",X"30",X"28",X"52",X"00",X"00", -- #14.1 : 4E0-4EF
+X"03",X"02",X"80",X"5B",X"A0",X"70",X"F0",X"60",X"00",X"20",X"04",X"30",X"28",X"52",X"00",X"00", -- #14.2 : 4F0-4FF
+X"01",X"01",X"C0",X"5B",X"98",X"70",X"F8",X"60",X"F8",X"20",X"04",X"30",X"28",X"52",X"00",X"00", -- #14.3 : 500-50F
+X"05",X"01",X"C0",X"5B",X"98",X"70",X"F8",X"60",X"00",X"20",X"04",X"30",X"28",X"52",X"00",X"00", -- #14.4 : 510-51F
+X"01",X"01",X"C0",X"5B",X"98",X"70",X"F8",X"60",X"00",X"20",X"04",X"30",X"28",X"52",X"00",X"00", -- #14.5 : 520-52F
+X"06",X"00",X"A0",X"5B",X"90",X"70",X"F8",X"60",X"00",X"20",X"04",X"30",X"28",X"52",X"00",X"00", -- #14.6 : 530-53F
+X"02",X"00",X"70",X"5B",X"90",X"70",X"F8",X"60",X"F8",X"20",X"04",X"30",X"28",X"52",X"00",X"00", -- #14.7 : 540-54F
+X"03",X"02",X"80",X"5B",X"90",X"70",X"E0",X"70",X"00",X"60",X"10",X"10",X"1C",X"56",X"3A",X"49", -- #15.0 : 550-55F
+X"02",X"02",X"00",X"5B",X"98",X"70",X"E0",X"70",X"00",X"60",X"10",X"10",X"1C",X"56",X"3A",X"49", -- #15.1 : 560-56F
+X"03",X"05",X"00",X"5B",X"98",X"60",X"F0",X"60",X"D8",X"60",X"1C",X"58",X"24",X"4E",X"39",X"2C", -- #16.0 : 570-57F
+X"02",X"05",X"00",X"5B",X"D0",X"60",X"F0",X"60",X"A0",X"60",X"1C",X"58",X"24",X"4E",X"39",X"2C", -- #16.1 : 580-58F
+X"02",X"04",X"00",X"5B",X"F0",X"60",X"C8",X"60",X"A0",X"60",X"1C",X"58",X"24",X"4E",X"39",X"2C", -- #16.2 : 590-59F
+X"08",X"04",X"00",X"5B",X"20",X"50",X"18",X"20",X"40",X"30",X"F8",X"60",X"C0",X"60",X"B2",X"5A", -- #17.0 : 5A0-5AF
+X"03",X"05",X"00",X"5B",X"C8",X"60",X"B8",X"60",X"F8",X"60",X"14",X"28",X"1C",X"36",X"44",X"41", -- #18.0 : 5B0-5BF
+X"02",X"05",X"00",X"5B",X"C8",X"60",X"B8",X"60",X"F8",X"60",X"14",X"28",X"1C",X"36",X"44",X"41", -- #18.1 : 5C0-5CF
+X"02",X"05",X"00",X"5B",X"B8",X"60",X"C8",X"60",X"F8",X"60",X"14",X"28",X"1C",X"36",X"44",X"41", -- #18.2 : 5D0-5DF
+X"03",X"01",X"C0",X"5B",X"10",X"50",X"28",X"40",X"30",X"30",X"08",X"30",X"F0",X"64",X"8E",X"70", -- #19.0 : 5E0-5EF
+X"02",X"01",X"80",X"5B",X"10",X"50",X"28",X"50",X"38",X"30",X"04",X"28",X"F4",X"5E",X"8C",X"76", -- #19.1 : 5F0-5FF
+X"04",X"02",X"80",X"5B",X"08",X"30",X"28",X"40",X"30",X"20",X"08",X"40",X"F4",X"5C",X"90",X"70", -- #19.2 : 600-60F
+X"01",X"04",X"00",X"5B",X"10",X"30",X"20",X"50",X"38",X"40",X"00",X"38",X"F0",X"5A",X"95",X"69", -- #19.3 : 610-61F
+X"03",X"07",X"00",X"5B",X"20",X"40",X"28",X"40",X"18",X"10",X"00",X"48",X"F0",X"60",X"98",X"69", -- #19.4 : 620-62F
+X"01",X"06",X"00",X"5B",X"18",X"30",X"28",X"40",X"20",X"10",X"00",X"48",X"F0",X"5E",X"9C",X"68", -- #19.5 : 630-63F
+X"09",X"03",X"00",X"5B",X"F8",X"40",X"20",X"50",X"30",X"50",X"F0",X"20",X"DC",X"4C",X"AE",X"66", -- #1A.0 : 640-64F
+X"06",X"00",X"1C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"24",X"28",X"08",X"4E",X"EB",X"0C", -- #1B.0 : 650-65F
+X"06",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"34",X"38",X"0C",X"3E",X"F1",X"1A", -- #1B.1 : 660-66F
+X"02",X"00",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"30",X"E8",X"F2",X"03",X"3F", -- #1B.2 : 670-67F
+X"03",X"00",X"04",X"5B",X"F8",X"30",X"18",X"40",X"40",X"30",X"E4",X"20",X"18",X"04",X"88",X"76", -- #1C.0 : 680-68F
+X"01",X"03",X"00",X"5B",X"20",X"50",X"18",X"10",X"30",X"40",X"F8",X"78",X"E0",X"74",X"98",X"6C", -- #1C.1 : 690-69F
+X"14",X"00",X"28",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"30",X"10",X"24",X"E5",X"3B", -- #1D.0 : 6A0-6AF
+X"08",X"02",X"80",X"5B",X"F8",X"70",X"20",X"50",X"28",X"50",X"C0",X"68",X"18",X"06",X"A4",X"5E", -- #1E.0 : 6B0-6BF
+X"08",X"02",X"80",X"5B",X"F0",X"60",X"18",X"60",X"20",X"40",X"D8",X"60",X"20",X"0C",X"9D",X"61", -- #1F.0 : 6C0-6CF
+X"04",X"03",X"00",X"5B",X"18",X"50",X"20",X"50",X"38",X"30",X"F0",X"60",X"D0",X"66",X"A6",X"53", -- #1F.1 : 6D0-6DF
+X"07",X"02",X"00",X"5B",X"18",X"60",X"28",X"50",X"40",X"40",X"F0",X"60",X"C8",X"62",X"9D",X"61", -- #1F.2 : 6E0-6EF
+X"08",X"01",X"C0",X"5B",X"B8",X"60",X"D0",X"60",X"F8",X"50",X"0C",X"20",X"20",X"44",X"00",X"00", -- #20.0 : 6F0-6FF
+X"05",X"01",X"00",X"5B",X"B0",X"60",X"C8",X"60",X"F8",X"50",X"0C",X"20",X"20",X"44",X"00",X"00", -- #20.1 : 700-70F
+X"04",X"00",X"A0",X"5B",X"B0",X"60",X"C0",X"60",X"F8",X"50",X"0C",X"20",X"20",X"44",X"00",X"00", -- #20.2 : 710-71F
+X"04",X"00",X"80",X"5B",X"A8",X"60",X"C0",X"60",X"00",X"50",X"0C",X"20",X"20",X"44",X"00",X"00", -- #20.3 : 720-72F
+X"07",X"00",X"28",X"5B",X"A0",X"60",X"B8",X"60",X"00",X"50",X"0C",X"20",X"20",X"44",X"00",X"00", -- #20.4 : 730-73F
+X"04",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #21.0 : 740-74F
+X"03",X"00",X"38",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"28",X"20",X"14",X"32",X"E7",X"23", -- #21.1 : 750-75F
+X"03",X"06",X"00",X"5B",X"18",X"50",X"20",X"50",X"40",X"30",X"F8",X"60",X"E4",X"72",X"9D",X"5D", -- #21.2 : 760-76F
+X"08",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #22.0 : 770-77F
+X"05",X"00",X"38",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"48",X"F4",X"42",X"EA",X"2A", -- #22.1 : 780-78F
+X"03",X"01",X"40",X"5B",X"20",X"30",X"30",X"50",X"18",X"10",X"F8",X"68",X"E8",X"58",X"9C",X"68", -- #22.2 : 790-79F
+X"06",X"00",X"20",X"5B",X"08",X"30",X"28",X"50",X"50",X"40",X"F0",X"48",X"C8",X"68",X"A8",X"47", -- #23.0 : 7A0-7AF
+X"06",X"00",X"E0",X"5B",X"10",X"40",X"28",X"40",X"50",X"50",X"F0",X"40",X"D0",X"1A",X"DE",X"3A", -- #23.1 : 7B0-7BF
+X"02",X"01",X"40",X"5B",X"F0",X"60",X"18",X"40",X"20",X"40",X"D0",X"68",X"2C",X"18",X"C7",X"25", -- #23.2 : 7C0-7CF
+X"04",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #24.0 : 7D0-7DF
+X"03",X"00",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"14",X"30",X"FC",X"F0",X"FB",X"41", -- #24.1 : 7E0-7EF
+X"03",X"03",X"80",X"5B",X"10",X"40",X"20",X"60",X"38",X"30",X"F8",X"30",X"F4",X"5E",X"A1",X"5C", -- #24.2 : 7F0-7FF
+X"06",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1C",X"50",X"0C",X"0E",X"FB",X"5C", -- #25.0 : 800-80F
+X"03",X"00",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"24",X"18",X"18",X"42",X"FA",X"56", -- #25.1 : 810-81F
+X"12",X"00",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"18",X"18",X"4A",X"FC",X"5B", -- #25.2 : 820-82F
+X"04",X"00",X"50",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"24",X"18",X"10",X"2E",X"F8",X"4C", -- #25.3 : 830-83F
+X"07",X"01",X"40",X"5B",X"C0",X"30",X"E0",X"40",X"F8",X"60",X"14",X"58",X"24",X"48",X"00",X"00", -- #26.0 : 840-84F
+X"0B",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"42",X"FE",X"3F", -- #26.1 : 850-85F
+X"02",X"00",X"38",X"5B",X"08",X"40",X"20",X"30",X"38",X"30",X"DC",X"48",X"BC",X"58",X"A4",X"54", -- #27.0 : 860-86F
+X"03",X"00",X"60",X"5B",X"D0",X"60",X"10",X"70",X"20",X"30",X"BC",X"60",X"1C",X"08",X"A1",X"5D", -- #27.1 : 870-87F
+X"04",X"00",X"A0",X"5B",X"D0",X"50",X"10",X"60",X"18",X"50",X"BC",X"60",X"20",X"0E",X"A3",X"5C", -- #27.2 : 880-88F
+X"11",X"00",X"38",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"28",X"38",X"04",X"28",X"E3",X"27", -- #28.0 : 890-89F
+X"12",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #29.0 : 8A0-8AF
+X"01",X"00",X"38",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"34",X"30",X"04",X"12",X"DE",X"56", -- #29.1 : 8B0-8BF
+X"02",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"2C",X"28",X"F4",X"1E",X"DC",X"49", -- #29.2 : 8C0-8CF
+X"07",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #2A.0 : 8D0-8DF
+X"01",X"00",X"A0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"38",X"0C",X"62",X"E2",X"37", -- #2A.1 : 8E0-8EF
+X"01",X"00",X"1C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"2C",X"20",X"10",X"36",X"F9",X"44", -- #2A.2 : 8F0-8FF
+X"09",X"00",X"50",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"2C",X"28",X"0C",X"44",X"E7",X"1B", -- #2A.3 : 900-90F
+X"06",X"04",X"00",X"5B",X"20",X"50",X"40",X"60",X"58",X"50",X"00",X"58",X"DC",X"54",X"A7",X"4D", -- #2B.0 : 910-91F
+X"09",X"00",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"44",X"58",X"EC",X"00",X"21",X"30", -- #2B.1 : 920-92F
+X"04",X"05",X"00",X"5B",X"20",X"50",X"40",X"50",X"48",X"40",X"00",X"40",X"DC",X"60",X"B9",X"37", -- #2B.2 : 930-93F
+X"05",X"03",X"80",X"5B",X"D8",X"40",X"B8",X"40",X"F8",X"40",X"04",X"58",X"2C",X"3C",X"55",X"5A", -- #2C.0 : 940-94F
+X"03",X"02",X"00",X"5B",X"F0",X"40",X"B0",X"40",X"D8",X"40",X"04",X"58",X"2C",X"3C",X"55",X"5A", -- #2C.1 : 950-95F
+X"06",X"01",X"C0",X"5B",X"B0",X"40",X"F0",X"40",X"D8",X"40",X"04",X"58",X"2C",X"3C",X"55",X"5A", -- #2C.2 : 960-96F
+X"08",X"01",X"40",X"5B",X"F0",X"40",X"B0",X"40",X"D0",X"40",X"04",X"58",X"2C",X"3C",X"55",X"5A", -- #2C.3 : 970-97F
+X"03",X"00",X"C0",X"5B",X"98",X"60",X"C8",X"60",X"08",X"40",X"18",X"30",X"28",X"44",X"2E",X"25", -- #2D.0 : 980-98F
+X"03",X"02",X"80",X"5B",X"A0",X"60",X"C8",X"60",X"08",X"40",X"18",X"30",X"28",X"44",X"2E",X"25", -- #2D.1 : 990-99F
+X"03",X"02",X"00",X"5B",X"A0",X"60",X"C0",X"60",X"00",X"40",X"18",X"30",X"28",X"44",X"2E",X"25", -- #2D.2 : 9A0-9AF
+X"05",X"00",X"28",X"5B",X"F8",X"20",X"18",X"40",X"28",X"30",X"C0",X"38",X"10",X"F8",X"A0",X"5A", -- #2E.0 : 9B0-9BF
+X"05",X"00",X"38",X"5B",X"08",X"30",X"20",X"60",X"38",X"40",X"FC",X"08",X"B0",X"50",X"9E",X"5F", -- #2E.1 : 9C0-9CF
+X"06",X"00",X"50",X"5B",X"00",X"50",X"18",X"60",X"20",X"50",X"A8",X"70",X"14",X"02",X"93",X"72", -- #2E.2 : 9D0-9DF
+X"03",X"02",X"80",X"5B",X"A0",X"60",X"E8",X"60",X"F8",X"60",X"00",X"10",X"1C",X"52",X"42",X"59", -- #2F.0 : 9E0-9EF
+X"02",X"02",X"80",X"5B",X"A0",X"60",X"E8",X"60",X"F8",X"60",X"00",X"10",X"1C",X"52",X"42",X"59", -- #2F.1 : 9F0-9FF
+X"02",X"01",X"C0",X"5B",X"A0",X"60",X"E8",X"60",X"F0",X"60",X"00",X"10",X"1C",X"52",X"42",X"59", -- #2F.2 : A00-A0F
+X"02",X"02",X"80",X"5B",X"A0",X"60",X"E0",X"60",X"F0",X"60",X"00",X"10",X"1C",X"52",X"42",X"59", -- #2F.3 : A10-A1F
+X"02",X"03",X"00",X"5B",X"A8",X"60",X"E0",X"60",X"F0",X"60",X"00",X"10",X"1C",X"52",X"42",X"59", -- #2F.4 : A20-A2F
+X"02",X"02",X"80",X"5B",X"A8",X"60",X"D8",X"60",X"E8",X"60",X"00",X"10",X"1C",X"52",X"42",X"59", -- #2F.5 : A30-A3F
+X"03",X"02",X"00",X"5B",X"A8",X"60",X"D8",X"60",X"E8",X"60",X"00",X"10",X"1C",X"52",X"42",X"59", -- #2F.6 : A40-A4F
+X"01",X"01",X"C0",X"5B",X"A8",X"60",X"D8",X"60",X"E8",X"60",X"00",X"10",X"1C",X"52",X"42",X"59", -- #2F.7 : A50-A5F
+X"03",X"00",X"E0",X"5B",X"A8",X"60",X"D0",X"60",X"E0",X"60",X"00",X"10",X"1C",X"52",X"42",X"59", -- #2F.8 : A60-A6F
+X"01",X"00",X"80",X"5B",X"A0",X"60",X"D0",X"60",X"E0",X"60",X"00",X"10",X"1C",X"52",X"42",X"59", -- #2F.9 : A70-A7F
+X"02",X"00",X"C0",X"5B",X"A8",X"60",X"D0",X"60",X"E8",X"60",X"00",X"10",X"1C",X"52",X"42",X"59", -- #2F.A : A80-A8F
+X"01",X"00",X"70",X"5B",X"A8",X"60",X"D0",X"60",X"E8",X"60",X"00",X"10",X"1C",X"52",X"42",X"59", -- #2F.B : A90-A9F
+X"03",X"00",X"50",X"5B",X"A8",X"60",X"D8",X"60",X"E8",X"60",X"00",X"10",X"1C",X"52",X"42",X"59", -- #2F.C : AA0-AAF
+X"06",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"20",X"FC",X"1C",X"D2",X"28", -- #30.0 : AB0-ABF
+X"0B",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"24",X"38",X"04",X"18",X"B4",X"55", -- #30.1 : AC0-ACF
+X"02",X"00",X"C0",X"5B",X"F8",X"40",X"30",X"70",X"20",X"20",X"C4",X"38",X"10",X"FC",X"A3",X"5D", -- #30.2 : AD0-ADF
+X"02",X"01",X"40",X"5B",X"F8",X"60",X"28",X"50",X"28",X"50",X"B0",X"68",X"1C",X"06",X"A3",X"58", -- #30.3 : AE0-AEF
+X"03",X"01",X"C0",X"5B",X"10",X"50",X"28",X"40",X"30",X"30",X"08",X"30",X"F0",X"64",X"8E",X"70", -- #31.0 : AF0-AFF
+X"02",X"01",X"80",X"5B",X"10",X"50",X"28",X"50",X"38",X"30",X"04",X"28",X"F4",X"5E",X"8C",X"76", -- #31.1 : B00-B0F
+X"04",X"02",X"80",X"5B",X"08",X"30",X"28",X"40",X"30",X"20",X"08",X"40",X"F4",X"5C",X"90",X"70", -- #31.2 : B10-B1F
+X"01",X"04",X"00",X"5B",X"10",X"30",X"20",X"50",X"38",X"40",X"00",X"38",X"F0",X"5A",X"95",X"69", -- #31.3 : B20-B2F
+X"05",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #32.0 : B30-B3F
+X"05",X"00",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"28",X"40",X"08",X"4E",X"E4",X"19", -- #32.1 : B40-B4F
+X"0D",X"00",X"50",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"34",X"50",X"10",X"66",X"F6",X"49", -- #32.2 : B50-B5F
+X"01",X"02",X"80",X"5B",X"18",X"40",X"20",X"40",X"30",X"20",X"E4",X"60",X"CC",X"68",X"A5",X"5F", -- #33.0 : B60-B6F
+X"02",X"02",X"80",X"5B",X"18",X"40",X"20",X"40",X"28",X"10",X"E4",X"58",X"D0",X"60",X"A5",X"5F", -- #33.1 : B70-B7F
+X"01",X"02",X"80",X"5B",X"E0",X"60",X"18",X"40",X"20",X"40",X"D0",X"60",X"24",X"12",X"A8",X"5B", -- #33.2 : B80-B8F
+X"01",X"02",X"00",X"5B",X"E0",X"60",X"18",X"50",X"28",X"40",X"D0",X"60",X"20",X"0A",X"A3",X"63", -- #33.3 : B90-B9F
+X"01",X"01",X"C0",X"5B",X"E0",X"60",X"18",X"60",X"28",X"40",X"D0",X"68",X"20",X"0A",X"A5",X"61", -- #33.4 : BA0-BAF
+X"02",X"02",X"00",X"5B",X"E0",X"60",X"18",X"50",X"28",X"40",X"D0",X"60",X"24",X"12",X"A2",X"69", -- #33.5 : BB0-BBF
+X"01",X"01",X"40",X"5B",X"E0",X"60",X"18",X"60",X"28",X"40",X"D4",X"68",X"1C",X"0A",X"A0",X"6E", -- #33.6 : BC0-BCF
+X"02",X"00",X"E0",X"5B",X"18",X"60",X"20",X"20",X"20",X"10",X"E0",X"60",X"D4",X"68",X"A0",X"6E", -- #33.7 : BD0-BDF
+X"01",X"01",X"00",X"5B",X"18",X"60",X"18",X"20",X"30",X"20",X"E4",X"60",X"D4",X"6A",X"A3",X"63", -- #33.8 : BE0-BEF
+X"02",X"02",X"80",X"5B",X"18",X"40",X"20",X"40",X"30",X"20",X"E4",X"60",X"CC",X"68",X"A5",X"5F", -- #34.0 : BF0-BFF
+X"02",X"02",X"80",X"5B",X"18",X"40",X"20",X"40",X"28",X"10",X"E4",X"58",X"D0",X"60",X"A5",X"5F", -- #34.1 : C00-C0F
+X"02",X"02",X"00",X"5B",X"E0",X"60",X"18",X"40",X"28",X"40",X"D0",X"60",X"24",X"10",X"A9",X"59", -- #34.2 : C10-C1F
+X"02",X"02",X"00",X"5B",X"E0",X"60",X"18",X"40",X"20",X"40",X"D0",X"60",X"24",X"12",X"A8",X"5B", -- #34.3 : C20-C2F
+X"02",X"01",X"C0",X"5B",X"E0",X"60",X"18",X"50",X"28",X"40",X"D0",X"60",X"20",X"0A",X"A3",X"63", -- #34.4 : C30-C3F
+X"02",X"01",X"C0",X"5B",X"E0",X"60",X"18",X"60",X"28",X"40",X"D0",X"68",X"20",X"0A",X"A5",X"61", -- #34.5 : C40-C4F
+X"02",X"01",X"C0",X"5B",X"E0",X"60",X"18",X"50",X"28",X"40",X"D0",X"60",X"24",X"12",X"A2",X"69", -- #34.6 : C50-C5F
+X"03",X"01",X"40",X"5B",X"E0",X"60",X"18",X"60",X"28",X"40",X"D4",X"68",X"1C",X"0A",X"A0",X"6E", -- #34.7 : C60-C6F
+X"03",X"00",X"C0",X"5B",X"18",X"60",X"20",X"20",X"20",X"10",X"E0",X"60",X"D4",X"68",X"A0",X"6E", -- #34.8 : C70-C7F
+X"03",X"00",X"E0",X"5B",X"18",X"60",X"18",X"20",X"30",X"20",X"E4",X"60",X"D4",X"6A",X"A3",X"63", -- #34.9 : C80-C8F
+X"03",X"02",X"80",X"5B",X"A8",X"60",X"C0",X"60",X"F8",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #35.0 : C90-C9F
+X"03",X"02",X"00",X"5B",X"A8",X"60",X"C0",X"60",X"00",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #35.1 : CA0-CAF
+X"01",X"01",X"C0",X"5B",X"A8",X"60",X"C0",X"60",X"00",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #35.2 : CB0-CBF
+X"05",X"00",X"C0",X"5B",X"A0",X"60",X"B8",X"60",X"00",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #35.3 : CC0-CCF
+X"01",X"00",X"C0",X"5B",X"A0",X"60",X"B8",X"60",X"00",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #35.4 : CD0-CDF
+X"06",X"00",X"70",X"5B",X"A0",X"60",X"B8",X"60",X"00",X"60",X"40",X"60",X"24",X"60",X"00",X"00", -- #35.5 : CE0-CEF
+X"11",X"00",X"A0",X"5B",X"08",X"30",X"18",X"30",X"38",X"40",X"EC",X"30",X"D4",X"2E",X"CB",X"20", -- #36.0 : CF0-CFF
+X"03",X"02",X"80",X"5B",X"00",X"60",X"18",X"50",X"38",X"50",X"F4",X"08",X"DC",X"5E",X"A1",X"5C", -- #36.1 : D00-D0F
+X"0A",X"00",X"70",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"48",X"40",X"20",X"38",X"E3",X"29", -- #37.0 : D10-D1F
+X"04",X"00",X"A0",X"5B",X"00",X"30",X"18",X"20",X"38",X"40",X"FC",X"60",X"E0",X"2A",X"A1",X"54", -- #38.0 : D20-D2F
+X"02",X"00",X"C0",X"5B",X"08",X"30",X"20",X"30",X"20",X"10",X"FC",X"68",X"E8",X"1C",X"A2",X"50", -- #38.1 : D30-D3F
+X"02",X"00",X"C0",X"5B",X"08",X"30",X"20",X"40",X"20",X"10",X"FC",X"68",X"E0",X"24",X"9B",X"5B", -- #38.2 : D40-D4F
+X"03",X"06",X"00",X"5B",X"10",X"40",X"18",X"40",X"30",X"30",X"F8",X"68",X"DC",X"62",X"A8",X"50", -- #38.3 : D50-D5F
+X"01",X"06",X"00",X"5B",X"10",X"20",X"18",X"40",X"30",X"40",X"F8",X"68",X"D4",X"6E",X"AC",X"55", -- #38.4 : D60-D6F
+X"03",X"06",X"00",X"5B",X"20",X"50",X"18",X"10",X"30",X"40",X"F8",X"70",X"D0",X"6A",X"AC",X"58", -- #38.5 : D70-D7F
+X"0E",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"30",X"00",X"1E",X"C1",X"48", -- #39.0 : D80-D8F
+X"04",X"00",X"C0",X"5B",X"00",X"40",X"20",X"60",X"38",X"50",X"E8",X"18",X"E0",X"0A",X"C2",X"49", -- #39.1 : D90-D9F
+X"02",X"00",X"60",X"5B",X"A0",X"60",X"A8",X"60",X"F8",X"60",X"10",X"20",X"20",X"60",X"37",X"57", -- #3A.0 : DA0-DAF
+X"01",X"00",X"40",X"5B",X"A0",X"60",X"A8",X"60",X"F0",X"60",X"10",X"20",X"20",X"60",X"37",X"57", -- #3A.1 : DB0-DBF
+X"03",X"00",X"50",X"5B",X"A0",X"60",X"A8",X"60",X"F0",X"60",X"10",X"20",X"20",X"60",X"37",X"57", -- #3A.2 : DC0-DCF
+X"03",X"00",X"E0",X"5B",X"A0",X"60",X"B0",X"60",X"F0",X"60",X"10",X"20",X"20",X"60",X"37",X"57", -- #3A.3 : DD0-DDF
+X"05",X"01",X"40",X"5B",X"A0",X"60",X"C0",X"60",X"E8",X"60",X"10",X"20",X"20",X"60",X"37",X"57", -- #3A.4 : DE0-DEF
+X"04",X"01",X"C0",X"5B",X"A8",X"60",X"C8",X"60",X"E0",X"60",X"10",X"20",X"20",X"60",X"37",X"57", -- #3A.5 : DF0-DFF
+X"04",X"01",X"C0",X"5B",X"A8",X"60",X"D0",X"60",X"E0",X"60",X"10",X"20",X"20",X"60",X"37",X"57", -- #3A.6 : E00-E0F
+X"01",X"00",X"E0",X"5B",X"A0",X"60",X"D0",X"60",X"E0",X"60",X"10",X"20",X"20",X"60",X"37",X"57", -- #3A.7 : E10-E1F
+X"03",X"00",X"60",X"5B",X"A0",X"60",X"D0",X"60",X"E0",X"60",X"10",X"20",X"20",X"60",X"37",X"57", -- #3A.8 : E20-E2F
+X"02",X"01",X"00",X"5B",X"18",X"60",X"28",X"40",X"10",X"00",X"F0",X"48",X"BC",X"64",X"AC",X"59", -- #3B.0 : E30-E3F
+X"02",X"01",X"40",X"5B",X"10",X"60",X"20",X"40",X"18",X"10",X"F0",X"48",X"BC",X"62",X"AF",X"56", -- #3B.1 : E40-E4F
+X"02",X"01",X"80",X"5B",X"10",X"50",X"20",X"30",X"20",X"10",X"EC",X"48",X"C0",X"5E",X"B0",X"56", -- #3B.2 : E50-E5F
+X"02",X"01",X"40",X"5B",X"F0",X"50",X"10",X"60",X"20",X"50",X"C0",X"60",X"10",X"02",X"B6",X"51", -- #3B.3 : E60-E6F
+X"02",X"01",X"40",X"5B",X"E8",X"60",X"18",X"60",X"28",X"50",X"C4",X"60",X"04",X"00",X"B8",X"4A", -- #3B.4 : E70-E7F
+X"03",X"01",X"40",X"5B",X"18",X"60",X"10",X"00",X"20",X"30",X"E8",X"58",X"C8",X"62",X"B5",X"54", -- #3B.5 : E80-E8F
+X"03",X"00",X"E0",X"5B",X"00",X"00",X"18",X"60",X"30",X"50",X"E4",X"60",X"CC",X"58",X"B5",X"56", -- #3B.6 : E90-E9F
+X"03",X"00",X"C0",X"5B",X"00",X"00",X"18",X"60",X"28",X"40",X"E4",X"60",X"D0",X"5C",X"B2",X"59", -- #3B.7 : EA0-EAF
+X"03",X"00",X"80",X"5B",X"E8",X"60",X"10",X"60",X"20",X"20",X"CC",X"60",X"04",X"FC",X"B2",X"55", -- #3B.8 : EB0-EBF
+X"03",X"03",X"80",X"5B",X"90",X"70",X"F0",X"50",X"00",X"30",X"04",X"18",X"28",X"4E",X"39",X"41", -- #3C.0 : EC0-ECF
+X"02",X"04",X"00",X"5B",X"90",X"70",X"F8",X"50",X"00",X"30",X"04",X"18",X"28",X"4E",X"39",X"41", -- #3C.1 : ED0-EDF
+X"03",X"05",X"00",X"5B",X"90",X"70",X"F8",X"50",X"00",X"30",X"04",X"18",X"28",X"4E",X"39",X"41", -- #3C.2 : EE0-EEF
+X"02",X"02",X"80",X"5B",X"90",X"70",X"F0",X"50",X"00",X"30",X"04",X"18",X"28",X"4E",X"39",X"41", -- #3C.3 : EF0-EFF
+X"03",X"02",X"80",X"5B",X"98",X"70",X"E8",X"50",X"F8",X"30",X"04",X"18",X"28",X"4E",X"39",X"41", -- #3C.4 : F00-F0F
+X"04",X"01",X"80",X"5B",X"A0",X"70",X"E0",X"50",X"F0",X"30",X"04",X"18",X"28",X"4E",X"39",X"41", -- #3C.5 : F10-F1F
+X"05",X"01",X"80",X"5B",X"A0",X"70",X"D8",X"50",X"F0",X"30",X"04",X"18",X"28",X"4E",X"39",X"41", -- #3C.6 : F20-F2F
+X"05",X"01",X"40",X"5B",X"A0",X"70",X"D8",X"50",X"F0",X"30",X"04",X"18",X"28",X"4E",X"39",X"41", -- #3C.7 : F30-F3F
+X"04",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #3D.0 : F40-F4F
+X"04",X"00",X"1C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"38",X"E0",X"40",X"E6",X"1C", -- #3D.1 : F50-F5F
+X"02",X"01",X"80",X"5B",X"F8",X"40",X"18",X"60",X"38",X"50",X"F8",X"18",X"D8",X"5C",X"A1",X"70", -- #3D.2 : F60-F6F
+X"05",X"03",X"00",X"5B",X"18",X"40",X"28",X"50",X"20",X"20",X"FC",X"68",X"C4",X"60",X"A3",X"64", -- #3E.0 : F70-F7F
+X"03",X"01",X"80",X"5B",X"10",X"10",X"28",X"60",X"38",X"40",X"FC",X"60",X"C0",X"62",X"A3",X"60", -- #3E.1 : F80-F8F
+X"07",X"01",X"00",X"5B",X"28",X"60",X"18",X"10",X"30",X"30",X"00",X"60",X"C0",X"60",X"A0",X"68", -- #3E.2 : F90-F9F
+X"04",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -- #3F.0 : FA0-FAF
+X"01",X"00",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"30",X"FC",X"24",X"DE",X"43", -- #3F.1 : FB0-FBF
+X"02",X"05",X"00",X"5B",X"20",X"50",X"30",X"40",X"18",X"10",X"F8",X"68",X"E0",X"6E",X"99",X"6C", -- #3F.2 : FC0-FCF
+X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", --       : FD0-FDF
+X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", --       : FE0-FEF
+X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"  --       : FF0-FFF
+);
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;

GCE - Vectrex_MiST/rtl/vectrex.vhd

@@ -7,6 +7,29 @@
 -- Do not redistribute roms whatever the form
 -- Use at your own risk
 ---------------------------------------------------------------------------------
+--  
+-- Vectrex releases
+--
+-- Release 0.2 - 12/06/2018 - Dar
+--	delays ramp related signals w.r.t. blank signal 
+--	result is not perfect but clean sweep maze is much more correct and playable
+--
+-- Release 0.1 - 05/05/2018 - Dar
+--	add sp0256-al2 VHDL speech simulation
+--	add speakjet interface (speech IC)
+--
+-- Release 0.0 - 10/02/2018 - Dar
+--	initial release
+--
+---------------------------------------------------------------------------------
+-- SP0256-al2 prom decoding scheme and speech synthesis algorithm are from :
+--
+-- Copyright Joseph Zbiciak, all rights reserved.
+-- Copyright tim lindner, all rights reserved.
+--
+-- See C source code and license in sp0256.c from MAME source
+--
+-- VHDL code is by Dar.
 ---------------------------------------------------------------------------------
 -- gen_ram.vhd & io_ps2_keyboard
 -- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
@@ -103,6 +126,7 @@
 --		pixel is displayed upper bits intensity as long as lower bits value not equal to 0
 --
 ---------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.ALL;
 use ieee.std_logic_unsigned.all;
@@ -114,7 +138,7 @@ port
 	clock_24     : in std_logic;
 	clock_12     : in std_logic;
 	reset        : in std_logic;
-	cpu_clock_o	 : out std_logic;
+
 	 
 	video_r      : out std_logic_vector(3 downto 0);
 	video_g      : out std_logic_vector(3 downto 0);
@@ -122,9 +146,13 @@ port
 
 	video_hs     : out std_logic;
 	video_vs     : out std_logic;
-	video_blankn : out std_logic;
+	video_hblank : out std_logic;
+	video_vblank : out std_logic;
+
+	speech_mode  : in  std_logic;
 	video_csync  : out std_logic;
 	frame		    : out std_logic;
+	
 	audio_out    : out std_logic_vector(9 downto 0);
 	cart_addr    : out std_logic_vector(13 downto 0);
 	cart_do      : in std_logic_vector( 7 downto 0);
@@ -141,6 +169,10 @@ port
 	btn24        : in std_logic;
 	pot_x_2      : in signed(7 downto 0);
 	pot_y_2      : in signed(7 downto 0);
+	speakjet_cmd : out std_logic;
+	speakjet_rdy : in  std_logic;
+	speakjet_pwm : in  std_logic;
+	external_speech_mode : in std_logic_vector(1 downto 0);
 	leds 			 : out std_logic_vector(9 downto 0);	
 	dbg_cpu_addr : out std_logic_vector(15 downto 0)
   );
@@ -185,6 +217,8 @@ architecture syn of vectrex is
  
  signal clock_24n : std_logic;
  signal clock_div : std_logic_vector(2 downto 0);
+ signal clock_div2: std_logic_vector(6 downto 0);
+ signal clock_250k: std_logic;
  signal reset_n   : std_logic;
 
  signal cpu_clock  : std_logic;
@@ -194,6 +228,7 @@ architecture syn of vectrex is
  signal cpu_rw     : std_logic;
  signal cpu_irq    : std_logic;
  signal cpu_firq   : std_logic;
+ signal cpu_ifetch : std_logic;
  signal cpu_fetch  : std_logic;
 
  signal ram_cs   : std_logic;
@@ -218,6 +253,15 @@ architecture syn of vectrex is
  signal via_irq_n : std_logic;
  signal via_en_4  : std_logic;
  
+  type delay_buffer_t is array(0 to 255) of std_logic_vector(17 downto 0);
+ signal delay_buffer : delay_buffer_t;
+
+ signal via_ca2_o_d : std_logic;
+ signal via_cb2_o_d : std_logic;
+ signal via_pa_o_d  : std_logic_vector(7 downto 0);
+ signal via_pb_o_d  : std_logic_vector(7 downto 0);
+
+ 
  signal sh_dac  : std_logic;
  signal dac_mux : std_logic_vector(2 downto 1);
  signal zero_integrator_n : std_logic;
@@ -296,45 +340,40 @@ architecture syn of vectrex is
  signal ay_chan_a      : std_logic_vector(7 downto 0);
  signal ay_chan_b      : std_logic_vector(7 downto 0);
  signal ay_chan_c      : std_logic_vector(7 downto 0);
+ signal ay_ioa_oe      : std_logic;
  
  signal pot     : signed(7 downto 0);
  signal compare : std_logic;
  signal players_switches : std_logic_vector(7 downto 0);
  
- component ym2149 is port
-(
-	CLK       : in  std_logic;
-	CE        : in  std_logic;
-	RESET     : in  std_logic;
-	BDIR      : in  std_logic;
-	BC        : in  std_logic;
-	DI        : in  std_logic_vector(7 downto 0);
-	DO        : out std_logic_vector(7 downto 0);
-	CHANNEL_A : out std_logic_vector(7 downto 0);
-	CHANNEL_B : out std_logic_vector(7 downto 0);
-	CHANNEL_C : out std_logic_vector(7 downto 0);
-	SEL       : in  std_logic;
-	MODE      : in  std_logic;
-	IOA_in    : in  std_logic_vector(7 downto 0);
-	IOA_out   : out std_logic_vector(7 downto 0);
-	IOB_in    : in  std_logic_vector(7 downto 0);
-	IOB_out   : out std_logic_vector(7 downto 0)
-);
-end component ym2149;
+ signal vectrex_bd_rate_div       : std_logic_vector(7 downto 0) := X"00";
+ signal vectrex_serial_bit_in     : std_logic;
+ signal vectrex_serial_bit_in_d   : std_logic;
+ signal vectrex_serial_data_shift : std_logic_vector(7 downto 0) := X"00";
+ signal vectrex_serial_bit_cnt    : std_logic_vector(3 downto 0) := X"0";
+ signal vectrex_serial_byte_rdy   : std_logic;
+ signal vectrex_serial_byte_out   : std_logic_vector(7 downto 0) := X"00";
+ 
+ signal audio_1        : std_logic_vector(9 downto 0);
+ signal audio_speech   : std_logic_vector(9 downto 0);
+ --signal speech_mode    : std_logic_vector(1 downto 0);
+ signal speech_rdy     : std_logic;
+ signal sp0256_rdy     : std_logic;
+
+
  
 begin
 
 -- debug
-process (clock_12, cpu_fetch)
+process (clock_12)
 begin 
-	if rising_edge(clock_12) then
-		dbg_cpu_addr <= cpu_addr;
+	if rising_edge(clock_12) then		
+		if cpu_ifetch = '1' then
+			dbg_cpu_addr <=  cpu_addr;
+		end if;
 	end if;		
 end process;
 
-leds(7 downto 0) <= dac_sound; 
---------------------
-
 -- clocks
 reset_n <= not reset;
 clock_24n <= not clock_24;
@@ -356,7 +395,24 @@ end process;
 
 via_en_4  <= clock_div(0);
 cpu_clock <= clock_div(2);
-cpu_clock_o <= clock_div(2);
+
+process (clock_24, reset)
+begin
+	if reset='1' then
+		clock_div2 <= (others=>'0');
+	else 		
+		if rising_edge(clock_24) then
+			if clock_div2 >= 99 then
+				clock_div2 <= (others=>'0');
+			else
+				clock_div2 <= clock_div2 + '1';
+			end if;		
+		end if;
+	end if;	
+end process;
+
+clock_250k <= clock_div2(6);
+
 
 --static ADDRESS_MAP_START(vectrex_map, AS_PROGRAM, 8, vectrex_state )
 --	AM_RANGE(0x0000, 0x7fff) AM_NOP // cart area, handled at machine_start
@@ -388,27 +444,51 @@ via_pa_i <= ay_do;
 via_pb_i <= "00"&compare&"00000";
 
 -- players controls
-players_switches <= not(btn24&btn23&btn22&btn21&btn14&btn13&btn12&btn11);
+players_switches <= not(btn24&btn23&btn22&btn21&btn14&btn13&btn12&btn11) when speech_mode = '0' 
+							else speech_rdy&speech_rdy&speech_rdy&speech_rdy & not(btn14&btn13&btn12&btn11);
 
-with dac_mux select
+with via_pb_o(2 downto 1) select  -- dac_mux but not delayed
 pot <= pot_x_1 when "00",
 		 pot_y_1 when "01",
 		 pot_x_2 when "10",
 		 pot_y_2 when others;
 
-compare <= '1' when (pot(7)&pot) > dac else '0';
+compare <= '1' when (pot(7)&pot) > signed(via_pa_o(7)&via_pa_o) else '0'; -- dac but not delayed
 
 -- beam control
-sh_dac            <= via_pb_o(0);
-dac_mux           <= via_pb_o(2 downto 1);
-zero_integrator_n <= via_ca2_o;
-ramp_integrator_n <= via_pb_o(7);
-beam_blank_n      <= via_cb2_o;
-			 			 
-dac <= signed(via_pa_o(7)&via_pa_o); -- must ensure sign extension for 0x80 value to be used in integrator equation
+
+-- integrator related signals have to be delayed with respect to blank signal
+-- tuned value : ~94 @ clock_12
+-- (port A, port B, CA2 and CB2 are declared to be delayed. Unsued delayed signals/buffers
+-- will be removed automaticaly by compiler so no ressources will be wasted)
+
+process (clock_12)
+begin
+	if rising_edge(clock_12) then
+	
+		delay_buffer(0) <= via_cb2_o & via_ca2_o & via_pb_o & via_pa_o;
+		for i in 255 downto 1 loop
+			delay_buffer(i) <= delay_buffer(i-1) ;
+		end loop;
+		
+		via_pa_o_d  <= delay_buffer(94)( 7 downto 0);
+		via_pb_o_d  <= delay_buffer(94)(15 downto 8);
+		via_ca2_o_d <= delay_buffer(94)(16);
+		via_cb2_o_d <= delay_buffer(94)(17);
+		
+	end if;
+end process;	
+
+sh_dac            <= via_pb_o_d(0);
+dac_mux           <= via_pb_o_d(2 downto 1);
+zero_integrator_n <= via_ca2_o_d;
+ramp_integrator_n <= via_pb_o_d(7);
+beam_blank_n      <= via_cb2_o;      -- blank is not delayed
+	 			 
+dac <= signed(via_pa_o_d(7)&via_pa_o_d); -- must ensure sign extension for 0x80 value to be used in integrator equation
 
 z_level <=  "11" when dac_z > 128 else 
-				"10" when dac_Z >  64 else
+				"10" when dac_z >  64 else
 				"01" when dac_z >   0 else 
 				"00";
 
@@ -419,12 +499,13 @@ begin
 		null;
 	else
       if rising_edge(clock_12) then
+				
 			if sh_dac = '0' then
 				case dac_mux is
 				when "00"   => dac_y     <= dac;
 				when "01"   => ref_level <= dac;
-				when "10"   => dac_z     <= unsigned(via_pa_o);
-				when others => dac_sound <= via_pa_o;
+				when "10"   => dac_z     <= unsigned(via_pa_o_d);
+				when others => dac_sound <= via_pa_o_d;
 				end case;
 			end if;
 
@@ -567,6 +648,7 @@ begin
 	end if;
 end process;
 
+
 -- uncomment when vram_width is 4
 --
 --video_pixel <= pixel(3 downto 2)&"00" when (pixel(1 downto 0) > "00") and (hblank = '0') else "0000";
@@ -654,9 +736,27 @@ begin
 	end if;
 end process;
 
-video_blankn <= not (hblank or vblank);
-
+video_hblank <= hblank;
+video_vblank <= vblank;
 scan_video_addr <= vcnt_video * std_logic_vector(to_unsigned(max_h,10)) + hcnt_video;
+		
+-- sound	
+process (cpu_clock)
+begin
+	if rising_edge(cpu_clock) then
+		if ay_audio_chan = "00" then ay_chan_a <= ay_audio_muxed; end if;
+		if ay_audio_chan = "01" then ay_chan_b <= ay_audio_muxed; end if;
+		if ay_audio_chan = "10" then ay_chan_c <= ay_audio_muxed; end if;
+	end if;	
+end process;
+
+audio_1  <= 	("00"&ay_chan_a) +
+					("00"&ay_chan_b) +
+					("00"&ay_chan_c) +
+					("00"&dac_sound);
+
+audio_out <=  "000"&audio_1(9 downto 3) + audio_speech;
+
 	
 frame <= frame_line;	
 ---------------------------
@@ -779,28 +879,76 @@ port map(
 
 
 -- AY-3-8910
-ym2149_inst : ym2149
-port map
-(
-	CLK       => cpu_clock,
-	CE        => '1',
-	RESET     => reset,
-	BDIR      => via_pb_o(4),
-	BC        => via_pb_o(3),
-	DI        => via_pa_o,
-	DO        => ay_do,
-	CHANNEL_A => ay_chan_a,
-	CHANNEL_B => ay_chan_b,
-	CHANNEL_C => ay_chan_c,
-	SEL       => '0',
-	MODE      => '0',
-	IOA_in    => players_switches,
-	IOB_in    => (others => '0')
+ay_3_8910_2 : entity work.YM2149
+port map(
+  -- data bus
+  I_DA       => via_pa_o,    -- in  std_logic_vector(7 downto 0);
+  O_DA       => ay_do,     -- out std_logic_vector(7 downto 0);
+  O_DA_OE_L  => open,      -- out std_logic;
+  -- control
+  I_A9_L     => '0',       -- in  std_logic;
+  I_A8       => '1',       -- in  std_logic;
+  I_BDIR     => via_pb_o(4),  -- in  std_logic;
+  I_BC2      => '1',       -- in  std_logic;
+  I_BC1      => via_pb_o(3),   -- in  std_logic;
+  I_SEL_L    => '0',       -- in  std_logic;
+
+  O_AUDIO    => ay_audio_muxed, -- out std_logic_vector(7 downto 0);
+  O_CHAN     => ay_audio_chan,  -- out std_logic_vector(1 downto 0);
+  
+  -- port a
+  I_IOA      => players_switches, -- in  std_logic_vector(7 downto 0);
+  O_IOA      => open,             -- out std_logic_vector(7 downto 0);
+  O_IOA_OE_L => ay_ioa_oe,        -- out std_logic;
+  -- port b
+  I_IOB      => (others => '0'), -- in  std_logic_vector(7 downto 0);
+  O_IOB      => open,            -- out std_logic_vector(7 downto 0);
+  O_IOB_OE_L => open,            -- out std_logic;
+
+  ENA        => '1', --cpu_ena,  -- in  std_logic; -- clock enable for higher speed operation
+  RESET_L    => reset_n,         -- in  std_logic;
+  CLK        => cpu_clock        -- in  std_logic  -- note 6 Mhz
 );
 
-audio_out <= 	("00"&ay_chan_a) +
-					("00"&ay_chan_b) +
-					("00"&ay_chan_c) +
-					("00"&dac_sound);
+-- select hardware speakjet or VHDL sp0256
 
+-- hardware speakjet chip interface
+--speech_rdy <= speakjet_rdy;
+--
+--speakjet : entity work.vectrex_speakjet
+--port map(	
+--	cpu_clock    => cpu_clock,
+--	clock_25     => clock_24,
+--	reset        => reset,
+--	
+--	mode         => speech_mode,        -- "01" for sp0256, else for speakjet
+--		
+--	vectrex_serial_byte_out => vectrex_serial_byte_out,
+--	vectrex_serial_byte_rdy => vectrex_serial_byte_rdy,
+--	
+--	speakjet_cmd => speakjet_cmd,       -- serial data to speakjet chip
+--	speakjet_rdy => speakjet_rdy,       -- speakjet chip is ready to receive a new cmd
+--	speakjet_pwm => speakjet_pwm,       -- speakjet chip audio output
+--	
+--	audio_out    => audio_speech
+--
+--);
+
+-- sp0256 VHDL simulation
+speech_rdy <= not sp0256_rdy;
+ 
+sp0256 : entity work.sp0256
+port map(
+ clock_250k  => clock_250k,  
+ reset       => reset,
+ 
+ input_rdy      => sp0256_rdy,
+ allophone      => vectrex_serial_byte_out(5 downto 0),
+ trig_allophone => vectrex_serial_byte_rdy,
+ 
+ audio_out      => audio_speech
+  
+);
+
+ 
 end SYN;

GCE - Vectrex_MiST/rtl/vectrex_mist.sv

@@ -21,14 +21,14 @@ module vectrex_mist
 
 localparam CONF_STR = {
 	"Vectrex;BINVECROM;",
-	"O2,Show Frame,No,Yes;",
-   "O3,Skip Logo,No,Yes;",		
+	"O2,Show Frame,Yes,No;",
+   "O3,Skip Logo,Yes,No;",
+	"O4,Second Joystick, Player 2, Player 1;",	
+//	"O5,Speech Mode,No,Yes;",
 //	"O23,Phosphor persistance,1,2,3,4;",
-//	"O8,Overburn,No,Yes;",
-	
-	
+//	"O8,Overburn,No,Yes;",	
 	"T6,Reset;",
-	"V,v1.00.",`BUILD_DATE
+	"V,v1.50.",`BUILD_DATE
 };
 
 wire [31:0] status;
@@ -44,7 +44,8 @@ wire  [7:0]	pot_y_1, pot_y_2;
 wire  [9:0] audio;
 wire 			hs, vs, cs;
 wire  [3:0] r, g, b;
-wire       	blankn;
+wire 			hb, vb;
+wire       	blankn = ~(hb | vb);
 wire 			cart_rd;
 wire [13:0] cart_addr;
 wire  [7:0] cart_do;
@@ -60,7 +61,7 @@ assign LED = !ioctl_downl;
 wire 			clk_24, clk_12, clk_6;
 wire 			pll_locked;
 
-always @(clk_6)begin
+always @(clk_12)begin
 	pot_x_1 = 8'h00;
 	pot_y_1 = 8'h00;
 	pot_x_2 = 8'h00;
@@ -121,7 +122,9 @@ vectrex vectrex (
 	.video_g			( gg				),
 	.video_b			( bb				),
 	.video_csync	( cs				),
-	.video_blankn	( blankn			),
+	.video_hblank	( hb				),
+	.video_vblank	( vb				),
+//	.speech_mode   ( status[5]		),
 	.video_hs		( hs				),
 	.video_vs		( vs				),
 	.frame			( frame_line	),
@@ -129,16 +132,16 @@ vectrex vectrex (
 	.cart_addr		( cart_addr		),
 	.cart_do			( cart_do		),
 	.cart_rd			( cart_rd		),	
-	.btn11			( joystick_0[4] | kbjoy[4]),
-	.btn12			( joystick_0[5] | kbjoy[5]),
-	.btn13			( joystick_0[6] | kbjoy[6]),
-	.btn14			( joystick_0[7] | kbjoy[7]),
+	.btn11			( joystick_0[4] | kbjoy[4] | status[4] ? joystick_1[4] : 1'b0),
+	.btn12			( joystick_0[5] | kbjoy[5] | status[4] ? joystick_1[5] : 1'b0),
+	.btn13			( joystick_0[6] | kbjoy[6] | status[4] ? joystick_1[6] : 1'b0),
+	.btn14			( joystick_0[7] | kbjoy[7] | status[4] ? joystick_1[7] : 1'b0),
 	.pot_x_1			( pot_x_1			),
 	.pot_y_1			( pot_y_1			),
-	.btn21			( joystick_1[4] | kbjoy[12]),
-	.btn22			( joystick_1[5] | kbjoy[13]),
-	.btn23			( joystick_1[6] | kbjoy[14]),
-	.btn24			( joystick_1[7] | kbjoy[15]),
+	.btn21			( kbjoy[12] | ~status[4] ? joystick_1[4] : 1'b0),
+	.btn22			( kbjoy[13] | ~status[4] ? joystick_1[5] : 1'b0),
+	.btn23			( kbjoy[14] | ~status[4] ? joystick_1[6] : 1'b0),
+	.btn24			( kbjoy[15] | ~status[4] ? joystick_1[7] : 1'b0),
 	.pot_x_2			( pot_x_2			),
 	.pot_y_2			( pot_y_2			),
 	.leds				(					),
@@ -178,7 +181,7 @@ video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer (
 	.G					(  blankn ? g : "0000"),
 	.B					(  blankn ? b : "0000"),
 	.HSync			( hs				),
-	.VSync			( vs				),
+	.VSync			( vs			   ),
 	.VGA_R			( VGA_R			),
 	.VGA_G			( VGA_G			),
 	.VGA_B			( VGA_B			),
@@ -215,7 +218,7 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io (
 
 keyboard keyboard (
 	.clk				( clk_24			),
-	.reset			(					),
+	.reset			( 0				),
 	.ps2_kbd_clk	( ps2_kbd_clk	),
 	.ps2_kbd_data	( ps2_kbd_data	),
 	.joystick		( kbjoy			)

GCE - Vectrex_MiST/rtl/vectrex_speakjet.vhd

@@ -0,0 +1,173 @@
+---------------------------------------------------------------------------------
+-- Vectrex_speakjet by Dar (darfpga@aol.fr) (14/04/2018)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+-- Get vectrex serial data out that is sligtly too fast to be send directly to
+-- speakjet chip (due to cpu09 running faster than original cpu). 
+--
+-- Retransmit vectrex serial data at 9600bd to speakjet chip.
+--
+-- Get back speakjet pwm bit output and convert it to numeric value
+--
+-- You have to fill correctly sp0256_to_speakjet array to convert sp0256 code to
+-- speakjet code, then you can use sp0256 mode with speakjet chip
+--
+-- (code are not delivered due to eventual property right and since such a 
+-- product is currently commercialised)
+---------------------------------------------------------------------------------
+-- Speakjet wiring
+--
+--  /!\ pwm and rdy can be directly connected FPGA 3.3V input *only* if VCC = 3.3V
+--
+--
+--                            VCC (3.3v)
+--                             |
+--                    +-----+--+
+--	      pwm      rdy |     |  | cmd
+--	       |        |  | GND |  |  |
+--	       ^  x  x  ^  |  |  |  |  v
+--        |  |  |  |  |  |  |  |  |  
+--     +--'--'--'--'--'--'--'--'--'--+
+--     | 18 17 16 15 14 13 12 11 10  |
+--     |                             |
+--      >         SPEAKJET IC        |
+--     |                             |
+--     |  1  2  3  4  5  6  7  8  9  |
+--     +--,--,--,--,--,--,--,--,--,--+
+--        |  |  |  |  |  |  |  |  |
+--        +--+--+--+--+--+--+--+--+
+--                                |
+--                               GND
+--
+---------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity vectrex_speakjet is
+port
+(
+	cpu_clock    : in std_logic;
+	clock_25     : in std_logic;
+	reset        : in std_logic;
+
+	mode         : in std_logic_vector(1 downto 0); -- "01" for sp0256, else for speakjet
+	
+	vectrex_serial_byte_out : in std_logic_vector(7 downto 0);
+	vectrex_serial_byte_rdy : in std_logic;
+				
+	speakjet_cmd : out std_logic;  -- serial data to speakjet chip
+	speakjet_rdy : in  std_logic;  -- speakjet chip is ready to receive a new cmd
+	speakjet_pwm : in  std_logic;  -- speakjet chip audio output
+	
+	audio_out    : out std_logic_vector(9 downto 0)
+);
+end vectrex_speakjet;
+
+architecture syn of vectrex_speakjet is
+  
+ signal speakjet_bd_rate_div     : std_logic_vector( 7 downto 0);
+ signal speakjet_serial_bit_cnt  : std_logic_vector( 3 downto 0) := X"0";
+ signal speakjet_serial_data_out : std_logic_vector(11 downto 0);
+
+ type array_64_bytes is array(0 to  63) of std_logic_vector(7 downto 0);
+
+ signal sp0256_to_speakjet: array_64_bytes := (
+ X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+ X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+ X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+ X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+ 
+ 
+ signal speakjet_pwm_d   : std_logic;
+ signal speakjet_pwm_dd  : std_logic;
+ signal speakjet_pwm_cnt : std_logic_vector(9 downto 0);
+	
+begin
+
+-- send serial data to speakjet
+process (cpu_clock, vectrex_serial_byte_rdy)
+begin
+	if vectrex_serial_byte_rdy ='0' then
+		speakjet_bd_rate_div <= (others => '0');
+		speakjet_serial_bit_cnt <= (others => '0');
+	else 
+		if rising_edge(cpu_clock) then
+			if speakjet_bd_rate_div = X"A3" then
+				speakjet_bd_rate_div <= (others => '0');
+				if speakjet_serial_bit_cnt < X"B" then
+					speakjet_serial_bit_cnt <= speakjet_serial_bit_cnt + '1';
+				end if;
+			else
+				speakjet_bd_rate_div <= speakjet_bd_rate_div + '1';
+			end if;
+		end if;
+	end if;
+end process;
+
+speakjet_serial_data_out <= 
+	  "11"&sp0256_to_speakjet(to_integer(unsigned(vectrex_serial_byte_out(5 downto 0))))&"01" when mode = "01"
+else "11"&vectrex_serial_byte_out&"01";
+
+speakjet_cmd <= speakjet_serial_data_out(to_integer(unsigned(speakjet_serial_bit_cnt)));
+
+-- convert speakjet pwm
+--
+-- ---     --------------
+--    |    |||||||||||   |
+--     ---------------    ---
+--    <----  T=32us ---->  constant
+--            (800)
+--
+--  Max count = 32e-6*25e6 = 800
+--
+-- 
+-- No sound
+-- ---           --------
+--    |         |        |
+--     ---------          ---
+--    <- 16us -><- 16us ->
+--      (400)     (400)
+--
+-- Let's assume min is 400-250, max is 400+250
+-- (Observed with oscilloscope)
+
+process (clock_25)
+begin
+	if falling_edge(clock_25) then
+		speakjet_pwm_d <= speakjet_pwm;
+		speakjet_pwm_dd <= speakjet_pwm_d;
+		
+		if speakjet_pwm_dd = '1' and speakjet_pwm_d = '0' then
+		
+			speakjet_pwm_cnt <= (others => '0');
+		
+			-- limit audio_out between 0 and 650
+			if (speakjet_pwm_cnt > 150) and (speakjet_pwm_cnt < 650) then
+				audio_out <= speakjet_pwm_cnt-150;
+			else
+				if (speakjet_pwm_cnt > 150) then
+					audio_out <= std_logic_vector(to_unsigned(650,10));
+				else
+					audio_out <= (others => '0');
+				end if;
+			end if;
+				
+		else
+			
+			if (speakjet_pwm_cnt < ("11"&X"FF")) and (speakjet_pwm = '0') then
+				speakjet_pwm_cnt <= speakjet_pwm_cnt + '1';
+			end if;
+			
+		end if;
+		
+	end if;
+end process;	
+
+end syn;

GCE - Vectrex_MiST/rtl/ym2149.sv

@@ -1,304 +0,0 @@
-
-
-module ym2149
-(
-   input        CLK,		   // Global clock
-   input        CE,        // PSG Clock enable
-   input        RESET,	   // Chip RESET (set all Registers to '0', active hi)
-   input        BDIR,	   // Bus Direction (0 - read , 1 - write)
-   input        BC,		   // Bus control
-   input  [7:0] DI,	      // Data In
-   output [7:0] DO,	      // Data Out
-   output [7:0] CHANNEL_A, // PSG Output channel A
-   output [7:0] CHANNEL_B, // PSG Output channel B
-   output [7:0] CHANNEL_C, // PSG Output channel C
-
-   input        SEL,
-   input        MODE,
-   output [5:0] ACTIVE,
-
-   input  [7:0] IOA_in,
-   output [7:0] IOA_out,
-
-   input  [7:0] IOB_in,
-   output [7:0] IOB_out
-);
-
-assign ACTIVE = ~ymreg[7][5:0];
-
-assign     IOA_out = ymreg[14];
-assign     IOB_out = ymreg[15];
-
-reg        ena_div;
-reg        ena_div_noise;
-reg [3:0]  addr;
-reg [7:0]  ymreg[16];
-reg        env_ena;
-reg [4:0]  env_vol;
-
-wire [7:0] volTableAy[16] = 
-       '{8'h00, 8'h03, 8'h04, 8'h06, 
-		   8'h0a, 8'h0f, 8'h15, 8'h22, 
-		   8'h28, 8'h41, 8'h5b, 8'h72, 
-		   8'h90, 8'hb5, 8'hd7, 8'hff
-		 };
-
-wire [7:0] volTableYm[32] = 
-		'{8'h00, 8'h01, 8'h01, 8'h02, 
-		  8'h02, 8'h03, 8'h03, 8'h04, 
-		  8'h06, 8'h07, 8'h09, 8'h0a, 
-		  8'h0c, 8'h0e, 8'h11, 8'h13, 
-		  8'h17, 8'h1b, 8'h20, 8'h25, 
-		  8'h2c, 8'h35, 8'h3e, 8'h47, 
-		  8'h54, 8'h66, 8'h77, 8'h88, 
-		  8'ha1, 8'hc0, 8'he0, 8'hff
-		};
-
-// Read from AY
-assign DO = dout;
-reg [7:0] dout;
-always_comb begin
-	case(addr)
-		 0: dout = ymreg[0];
-		 1: dout = {4'b0000, ymreg[1][3:0]};
-		 2: dout = ymreg[2];
-		 3: dout = {4'b0000, ymreg[3][3:0]};
-		 4: dout = ymreg[4];
-		 5: dout = {4'b0000, ymreg[5][3:0]};
-		 6: dout = {3'b000,  ymreg[6][4:0]};
-		 7: dout = ymreg[7];
-		 8: dout = {3'b000,  ymreg[8][4:0]};
-		 9: dout = {3'b000,  ymreg[9][4:0]};
-		10: dout = {3'b000,  ymreg[10][4:0]};
-		11: dout = ymreg[11];
-		12: dout = ymreg[12];
-		13: dout = {4'b0000, ymreg[13][3:0]};
-		14: dout = (ymreg[7][6] ? ymreg[14] : IOA_in);
-		15: dout = (ymreg[7][7] ? ymreg[15] : IOB_in);
-	endcase
-end
-
-//  p_divider
-always @(posedge CLK) begin
-	reg [3:0]  cnt_div;
-	reg        noise_div;
-
-	if(CE) begin
-		ena_div <= 0;
-		ena_div_noise <= 0;
-		if(!cnt_div) begin
-			cnt_div <= {SEL, 3'b111};
-			ena_div <= 1;
-            
-			noise_div <= (~noise_div);
-			if (noise_div) ena_div_noise <= 1;
-		end else begin
-			cnt_div <= cnt_div - 1'b1;
-		end
-	end
-end
-
-
-reg noise_gen_op;
-
-//  p_noise_gen
-always @(posedge CLK) begin
-	reg [16:0] poly17;
-	reg [4:0]  noise_gen_cnt;
-
-	if(CE) begin
-		if (ena_div_noise) begin
-			if(ymreg[6][4:0]) begin
-				if (noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin
-					noise_gen_cnt <= 0;
-					poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]};
-				end else begin
-					noise_gen_cnt <= noise_gen_cnt + 1'd1;
-				end
-				noise_gen_op <= poly17[0];
-			end else begin
-				noise_gen_op <= 0;
-				noise_gen_cnt <= 0;
-			end
-		end
-	end
-end
-
-wire [11:0] tone_gen_freq[1:3];
-assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]};
-assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]};
-assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]};
-
-reg [3:1] tone_gen_op;
-
-//p_tone_gens
-always @(posedge CLK) begin
-	integer i;
-	reg [11:0] tone_gen_cnt[1:3];
-
-	if(CE) begin
-		// looks like real chips count up - we need to get the Exact behaviour ..
-	
-		for (i = 1; i <= 3; i = i + 1) begin
-			if(ena_div) begin
-				if (tone_gen_freq[i]) begin
-					if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin
-						tone_gen_cnt[i] <= 0;
-						tone_gen_op[i]  <= ~tone_gen_op[i];
-					end else begin
-						tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1;
-					end
-				end else begin
-					tone_gen_op[i] <= 0;
-					tone_gen_cnt[i] <= 0;
-				end
-			end
-		end
-	end
-end
-
-wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0;
-
-//p_envelope_freq
-always @(posedge CLK) begin
-	reg [15:0] env_gen_cnt;
-
-	if(CE) begin
-		env_ena <= 0;
-		if(ena_div) begin
-			if (env_gen_cnt >= env_gen_comp) begin
-				env_gen_cnt <= 0;
-				env_ena <= 1;
-			end else begin
-				env_gen_cnt <= (env_gen_cnt + 1'd1);
-			end
-		end
-	end
-end
-
-wire is_bot    = (env_vol == 5'b00000);
-wire is_bot_p1 = (env_vol == 5'b00001);
-wire is_top_m1 = (env_vol == 5'b11110);
-wire is_top    = (env_vol == 5'b11111);
-
-always @(posedge CLK) begin
-	reg old_BDIR;
-	reg env_reset;
-	reg env_hold;
-	reg env_inc;
-
-	// envelope shapes
-	// C AtAlH
-	// 0 0 x x  \___
-	//
-	// 0 1 x x  /___
-	//
-	// 1 0 0 0  \\\\
-	//
-	// 1 0 0 1  \___
-	//
-	// 1 0 1 0  \/\/
-	//           ___
-	// 1 0 1 1  \
-	//
-	// 1 1 0 0  ////
-	//           ___
-	// 1 1 0 1  /
-	//
-	// 1 1 1 0  /\/\
-	//
-	// 1 1 1 1  /___
-
-	if(RESET) begin
-		ymreg[0]  <= 0;
-		ymreg[1]  <= 0;
-		ymreg[2]  <= 0;
-		ymreg[3]  <= 0;
-		ymreg[4]  <= 0;
-		ymreg[5]  <= 0;
-		ymreg[6]  <= 0;
-		ymreg[7]  <= 255;
-		ymreg[8]  <= 0;
-		ymreg[9]  <= 0;
-		ymreg[10] <= 0;
-		ymreg[11] <= 0;
-		ymreg[12] <= 0;
-		ymreg[13] <= 0;
-		ymreg[14] <= 0;
-		ymreg[15] <= 0;
-		addr      <= 0;
-		env_vol   <= 0;
-	end else begin
-		old_BDIR <= BDIR;
-		if(~old_BDIR & BDIR) begin
-			if(BC) addr <= DI[3:0];
-			else begin 
-				ymreg[addr] <= DI;
-				env_reset <= (addr == 13);
-			end
-		end
-	end
-
-	if(CE) begin
-		if(env_reset) begin
-			env_reset <= 0;
-			// load initial state
-			if(!ymreg[13][2]) begin		// attack
-				env_vol <= 5'b11111;
-				env_inc <= 0;		// -1
-			end else begin
-				env_vol <= 5'b00000;
-				env_inc <= 1;		// +1
-			end
-			env_hold <= 0;
-		end else begin
-
-			if (env_ena) begin
-				if (!env_hold) begin
-					if (env_inc) env_vol <= (env_vol + 5'b00001);
-						else env_vol <= (env_vol + 5'b11111);
-				end
-
-				// envelope shape control.
-				if(!ymreg[13][3]) begin
-					if(!env_inc) begin	// down
-						if(is_bot_p1) env_hold <= 1;
-					end else if (is_top) env_hold <= 1;
-				end else if(ymreg[13][0]) begin		// hold = 1
-					if(!env_inc) begin	// down
-						if(ymreg[13][1]) begin		// alt
-							if(is_bot) env_hold <= 1;
-						end else if(is_bot_p1) env_hold <= 1;
-					end else if(ymreg[13][1]) begin	// alt
-						if(is_top) env_hold <= 1;
-					end else if(is_top_m1) env_hold <= 1;
-				end else if(ymreg[13][1]) begin		// alternate
-					if(env_inc == 1'b0) begin		// down
-						if(is_bot_p1) env_hold <= 1;
-						if(is_bot) begin
-							env_hold <= 0;
-							env_inc  <= 1;
-						end
-					end else begin
-						if(is_top_m1) env_hold <= 1;
-						if(is_top) begin
-							env_hold <= 0;
-							env_inc  <= 0;
-						end
-					end
-				end
-			end
-		end
-	end
-end
-
-wire [4:0] A = ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op)) ? 5'd0 : ymreg[8][4]  ? env_vol[4:0] : { ymreg[8][3:0],  ymreg[8][3]};
-wire [4:0] B = ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op)) ? 5'd0 : ymreg[9][4]  ? env_vol[4:0] : { ymreg[9][3:0],  ymreg[9][3]};
-wire [4:0] C = ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op)) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]};
-
-assign CHANNEL_A = MODE ? volTableAy[A[4:1]] : volTableYm[A];
-assign CHANNEL_B = MODE ? volTableAy[B[4:1]] : volTableYm[B];
-assign CHANNEL_C = MODE ? volTableAy[C[4:1]] : volTableYm[C];
-
-
-endmodule

GCE - Vectrex_MiST/vectrex_MiST.out.sdc

@@ -0,0 +1,176 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {CLOCK_27} -period 37.037 -waveform { 0.000 18.518 } [get_ports {CLOCK_27}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+create_generated_clock -name {pll|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 9 -master_clock {CLOCK_27} [get_pins {pll|altpll_component|auto_generated|pll1|clk[0]}] 
+create_generated_clock -name {pll|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -divide_by 9 -master_clock {CLOCK_27} [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] 
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_27}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_27}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_27}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_27}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_27}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_27}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_27}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_27}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020  
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {SPI_SS3}]
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_B[0]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_B[1]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_B[2]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_B[3]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_B[4]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_B[5]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_G[0]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_G[1]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_G[2]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_G[3]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_G[4]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_G[5]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_HS}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_R[0]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_R[1]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_R[2]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_R[3]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_R[4]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_R[5]}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {VGA_VS}]
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+

GCE - Vectrex_MiST/vectrex_MiST.qsf

@@ -43,22 +43,7 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016"
 set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name VHDL_FILE rtl/vectrex.vhd
-set_global_assignment -name VHDL_FILE rtl/m6522a.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu09l_128a.vhd
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name QIP_FILE rtl/pll.qip
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/vectrex_mist.sv
-set_global_assignment -name VHDL_FILE rtl/vectrex_exec_prom.vhd
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name QIP_FILE rtl/card.qip
 
 # Pin & Location Assignments
 # ==========================
@@ -92,45 +77,6 @@ set_location_assignment PIN_126 -to SPI_SCK
 set_location_assignment PIN_127 -to SPI_SS2
 set_location_assignment PIN_91 -to SPI_SS3
 set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PIN_49 -to SDRAM_A[0]
-set_location_assignment PIN_44 -to SDRAM_A[1]
-set_location_assignment PIN_42 -to SDRAM_A[2]
-set_location_assignment PIN_39 -to SDRAM_A[3]
-set_location_assignment PIN_4 -to SDRAM_A[4]
-set_location_assignment PIN_6 -to SDRAM_A[5]
-set_location_assignment PIN_8 -to SDRAM_A[6]
-set_location_assignment PIN_10 -to SDRAM_A[7]
-set_location_assignment PIN_11 -to SDRAM_A[8]
-set_location_assignment PIN_28 -to SDRAM_A[9]
-set_location_assignment PIN_50 -to SDRAM_A[10]
-set_location_assignment PIN_30 -to SDRAM_A[11]
-set_location_assignment PIN_32 -to SDRAM_A[12]
-set_location_assignment PIN_83 -to SDRAM_DQ[0]
-set_location_assignment PIN_79 -to SDRAM_DQ[1]
-set_location_assignment PIN_77 -to SDRAM_DQ[2]
-set_location_assignment PIN_76 -to SDRAM_DQ[3]
-set_location_assignment PIN_72 -to SDRAM_DQ[4]
-set_location_assignment PIN_71 -to SDRAM_DQ[5]
-set_location_assignment PIN_69 -to SDRAM_DQ[6]
-set_location_assignment PIN_68 -to SDRAM_DQ[7]
-set_location_assignment PIN_86 -to SDRAM_DQ[8]
-set_location_assignment PIN_87 -to SDRAM_DQ[9]
-set_location_assignment PIN_98 -to SDRAM_DQ[10]
-set_location_assignment PIN_99 -to SDRAM_DQ[11]
-set_location_assignment PIN_100 -to SDRAM_DQ[12]
-set_location_assignment PIN_101 -to SDRAM_DQ[13]
-set_location_assignment PIN_103 -to SDRAM_DQ[14]
-set_location_assignment PIN_104 -to SDRAM_DQ[15]
-set_location_assignment PIN_58 -to SDRAM_BA[0]
-set_location_assignment PIN_51 -to SDRAM_BA[1]
-set_location_assignment PIN_85 -to SDRAM_DQMH
-set_location_assignment PIN_67 -to SDRAM_DQML
-set_location_assignment PIN_60 -to SDRAM_nRAS
-set_location_assignment PIN_64 -to SDRAM_nCAS
-set_location_assignment PIN_66 -to SDRAM_nWE
-set_location_assignment PIN_59 -to SDRAM_nCS
-set_location_assignment PIN_33 -to SDRAM_CKE
-set_location_assignment PIN_43 -to SDRAM_CLK
 set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
 
 # Analysis & Synthesis Assignments
@@ -219,7 +165,56 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
 set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA
 set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
 set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CONF_DATA0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_R
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_L
+set_global_assignment -name SDC_FILE vectrex_MiST.out.sdc
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/vectrex_mist.sv
+set_global_assignment -name VHDL_FILE rtl/vectrex.vhd
+set_global_assignment -name VHDL_FILE rtl/vectrex_exec_prom.vhd
+set_global_assignment -name VHDL_FILE rtl/m6522a.vhd
+set_global_assignment -name QIP_FILE rtl/card.qip
+set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu09l_128a.vhd
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VERILOG_FILE rtl/keyboard.v
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VERILOG_FILE rtl/pll.v
 set_global_assignment -name VERILOG_FILE rtl/mc6809is.v
 set_global_assignment -name VERILOG_FILE rtl/mc6809.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/ym2149.sv
+set_global_assignment -name VHDL_FILE rtl/sp0256.vhd
+set_global_assignment -name VHDL_FILE rtl/sp0256_al2_decoded.vhd
+set_global_assignment -name VHDL_FILE rtl/vectrex_speakjet.vhd
+set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Oric Atmos_MiST/Oric_Mist.qpf

@@ -20,4 +20,4 @@ DATE = "20:32:23  January 19, 2009"
 
 # Revisions
 
-PROJECT_REVISION = "Extender"
+PROJECT_REVISION = "Oric_Mist"

Oric Atmos_MiST/Oric_Mist.qsf

@@ -45,31 +45,6 @@ set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name MISC_FILE "C:/_fpga/_cone/C1Extender/SYMB_CPC/Extender.dpf"
-set_global_assignment -name VHDL_FILE rtl/oricatmos.vhd
-set_global_assignment -name VHDL_FILE rtl/STOP_WATCH.vhd
-set_global_assignment -name VHDL_FILE rtl/t65_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/t65.vhd
-set_global_assignment -name VHDL_FILE rtl/t65_alu.vhd
-set_global_assignment -name VHDL_FILE rtl/pack_t65.vhd
-set_global_assignment -name VHDL_FILE rtl/ula.vhd
-set_global_assignment -name VHDL_FILE rtl/pack_ula.vhd
-set_global_assignment -name VHDL_FILE rtl/m6522.vhd
-set_global_assignment -name VHDL_FILE rtl/vag.vhd
-set_global_assignment -name VHDL_FILE rtl/video.vhd
-set_global_assignment -name VHDL_FILE rtl/keyboard.vhd
-set_global_assignment -name VHDL_FILE rtl/iodecode.vhd
-set_global_assignment -name VHDL_FILE rtl/addmemux.vhd
-set_global_assignment -name VHDL_FILE rtl/memmap.vhd
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/ps2key.vhd
-set_global_assignment -name VHDL_FILE rtl/ctrlseq.vhd
-set_global_assignment -name VHDL_FILE rtl/ay3819x.vhd
-set_global_assignment -name VHDL_FILE rtl/tone_generator.vhd
-set_global_assignment -name VHDL_FILE rtl/noise_generator.vhd
-set_global_assignment -name VHDL_FILE rtl/GEN_CLK.vhd
-set_global_assignment -name VHDL_FILE rtl/MIXER.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_env.vhd
-set_global_assignment -name VHDL_FILE rtl/manage_amplitude.vhd
 
 # Pin & Location Assignments
 # ==========================
@@ -263,6 +238,31 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name VHDL_FILE rtl/oricatmos.vhd
+set_global_assignment -name VHDL_FILE rtl/STOP_WATCH.vhd
+set_global_assignment -name VHDL_FILE rtl/t65_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/t65.vhd
+set_global_assignment -name VHDL_FILE rtl/t65_alu.vhd
+set_global_assignment -name VHDL_FILE rtl/pack_t65.vhd
+set_global_assignment -name VHDL_FILE rtl/ula.vhd
+set_global_assignment -name VHDL_FILE rtl/pack_ula.vhd
+set_global_assignment -name VHDL_FILE rtl/m6522.vhd
+set_global_assignment -name VHDL_FILE rtl/vag.vhd
+set_global_assignment -name VHDL_FILE rtl/video.vhd
+set_global_assignment -name VHDL_FILE rtl/keyboard.vhd
+set_global_assignment -name VHDL_FILE rtl/iodecode.vhd
+set_global_assignment -name VHDL_FILE rtl/addmemux.vhd
+set_global_assignment -name VHDL_FILE rtl/memmap.vhd
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/ps2key.vhd
+set_global_assignment -name VHDL_FILE rtl/ctrlseq.vhd
+set_global_assignment -name VHDL_FILE rtl/ay3819x.vhd
+set_global_assignment -name VHDL_FILE rtl/tone_generator.vhd
+set_global_assignment -name VHDL_FILE rtl/noise_generator.vhd
+set_global_assignment -name VHDL_FILE rtl/GEN_CLK.vhd
+set_global_assignment -name VHDL_FILE rtl/MIXER.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_env.vhd
+set_global_assignment -name VHDL_FILE rtl/manage_amplitude.vhd
 set_global_assignment -name QIP_FILE rtl/pll.qip
 set_global_assignment -name VHDL_FILE rtl/ram48k.vhd
 set_global_assignment -name VHDL_FILE rtl/scan_converter.vhd
@@ -280,6 +280,5 @@ set_global_assignment -name VHDL_FILE rtl/spram.vhd
 set_global_assignment -name VHDL_FILE rtl/sprom.vhd
 set_global_assignment -name QIP_FILE rtl/HC4051.qip
 set_global_assignment -name QIP_FILE rtl/rrom.qip
-set_global_assignment -name QIP_FILE rtl/RAM16X1D.qip
-set_global_assignment -name VHDL_FILE rtl/keyboardX.vhd
+set_global_assignment -name QIP_FILE rtl/RAM8X1D.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Oric Atmos_MiST/rtl/RAM8X1D.qip

@@ -1,3 +1,3 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
 set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "RAM16X1D.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "RAM8X1D.vhd"]

Oric Atmos_MiST/rtl/RAM8X1D.vhd

@@ -4,7 +4,7 @@
 -- MODULE: altsyncram 
 
 -- ============================================================
--- File Name: RAM16X1D.vhd
+-- File Name: RAM8X1D.vhd
 -- Megafunction Name(s):
 -- 			altsyncram
 --
@@ -39,70 +39,60 @@ USE ieee.std_logic_1164.all;
 LIBRARY altera_mf;
 USE altera_mf.altera_mf_components.all;
 
-ENTITY RAM16X1D IS
+ENTITY RAM8X1D IS
 	PORT
 	(
-		address_a		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
-		address_b		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
 		clock		: IN STD_LOGIC  := '1';
-		data_a		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
-		q_b		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
+		data		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+		enable		: IN STD_LOGIC  := '1';
+		rdaddress		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		rden		: IN STD_LOGIC  := '1';
+		wraddress		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		wren		: IN STD_LOGIC  := '0';
+		q		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
 	);
-END RAM16X1D;
+END RAM8X1D;
 
 
-ARCHITECTURE SYN OF ram16x1d IS
+ARCHITECTURE SYN OF ram8x1d IS
 
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 BEGIN
-	q_a    <= sub_wire0(0 DOWNTO 0);
-	q_b    <= sub_wire1(0 DOWNTO 0);
+	q    <= sub_wire0(0 DOWNTO 0);
 
 	altsyncram_component : altsyncram
 	GENERIC MAP (
+		address_aclr_b => "NONE",
 		address_reg_b => "CLOCK0",
-		clock_enable_input_a => "BYPASS",
-		clock_enable_input_b => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK0",
+		clock_enable_input_a => "NORMAL",
+		clock_enable_input_b => "NORMAL",
+		clock_enable_output_b => "NORMAL",
 		intended_device_family => "Cyclone III",
 		lpm_type => "altsyncram",
-		numwords_a => 16,
-		numwords_b => 16,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
+		numwords_a => 8,
+		numwords_b => 8,
+		operation_mode => "DUAL_PORT",
 		outdata_aclr_b => "NONE",
-		outdata_reg_a => "CLOCK0",
 		outdata_reg_b => "CLOCK0",
 		power_up_uninitialized => "FALSE",
+		rdcontrol_reg_b => "CLOCK0",
 		read_during_write_mode_mixed_ports => "DONT_CARE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => 4,
-		widthad_b => 4,
+		widthad_a => 3,
+		widthad_b => 3,
 		width_a => 1,
 		width_b => 1,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK0"
+		width_byteena_a => 1
 	)
 	PORT MAP (
+		address_a => wraddress,
 		clock0 => clock,
-		wren_a => wren_a,
-		address_b => address_b,
-		data_b => data_b,
-		wren_b => wren_b,
-		address_a => address_a,
-		data_a => data_a,
-		q_a => sub_wire0,
-		q_b => sub_wire1
+		data_a => data,
+		rden_b => rden,
+		wren_a => wren,
+		address_b => rdaddress,
+		clocken0 => enable,
+		q_b => sub_wire0
 	);
 
 
@@ -120,10 +110,10 @@ END SYN;
 -- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
 -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
 -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
 -- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
 -- Retrieval info: PRIVATE: CLRq NUMERIC "0"
 -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
@@ -135,17 +125,17 @@ END SYN;
 -- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
 -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
 -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
--- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
--- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
 -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
 -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8"
 -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
 -- Retrieval info: PRIVATE: MIFfilename STRING ""
--- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
 -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
 -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
 -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
@@ -154,8 +144,8 @@ END SYN;
 -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
 -- Retrieval info: PRIVATE: REGdata NUMERIC "1"
 -- Retrieval info: PRIVATE: REGq NUMERIC "1"
--- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
--- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
 -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
 -- Retrieval info: PRIVATE: REGwren NUMERIC "1"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
@@ -167,58 +157,50 @@ END SYN;
 -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "1"
 -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "1"
 -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
--- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
 -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
--- Retrieval info: PRIVATE: enable NUMERIC "0"
--- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "1"
+-- Retrieval info: PRIVATE: rden NUMERIC "1"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
 -- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
--- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "NORMAL"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
--- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
--- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
 -- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
--- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
 -- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
 -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
 -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
--- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
--- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
--- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "3"
 -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
 -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "1"
 -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
--- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
--- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL "address_a[3..0]"
--- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL "address_b[3..0]"
 -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
--- Retrieval info: USED_PORT: data_a 0 0 1 0 INPUT NODEFVAL "data_a[0..0]"
--- Retrieval info: USED_PORT: data_b 0 0 1 0 INPUT NODEFVAL "data_b[0..0]"
--- Retrieval info: USED_PORT: q_a 0 0 1 0 OUTPUT NODEFVAL "q_a[0..0]"
--- Retrieval info: USED_PORT: q_b 0 0 1 0 OUTPUT NODEFVAL "q_b[0..0]"
--- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
--- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
--- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0
--- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0
+-- Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL "data[0..0]"
+-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT VCC "enable"
+-- Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
+-- Retrieval info: USED_PORT: rdaddress 0 0 3 0 INPUT NODEFVAL "rdaddress[2..0]"
+-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+-- Retrieval info: USED_PORT: wraddress 0 0 3 0 INPUT NODEFVAL "wraddress[2..0]"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 3 0 wraddress 0 0 3 0
+-- Retrieval info: CONNECT: @address_b 0 0 3 0 rdaddress 0 0 3 0
 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @data_a 0 0 1 0 data_a 0 0 1 0
--- Retrieval info: CONNECT: @data_b 0 0 1 0 data_b 0 0 1 0
--- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
--- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
--- Retrieval info: CONNECT: q_a 0 0 1 0 @q_a 0 0 1 0
--- Retrieval info: CONNECT: q_b 0 0 1 0 @q_b 0 0 1 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL RAM16X1D.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL RAM16X1D.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL RAM16X1D.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL RAM16X1D.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL RAM16X1D_inst.vhd FALSE
+-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 1 0 data 0 0 1 0
+-- Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 1 0 @q_b 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: altera_mf

Oric Atmos_MiST/rtl/build_id.v

@@ -1,2 +1,2 @@
-`define BUILD_DATE "180506"
-`define BUILD_TIME "191822"
+`define BUILD_DATE "180624"
+`define BUILD_TIME "130024"

Oric Atmos_MiST/rtl/greybox_tmp/cbx_args.txt

@@ -0,0 +1,29 @@
+ADDRESS_ACLR_B=NONE
+ADDRESS_REG_B=CLOCK0
+CLOCK_ENABLE_INPUT_A=NORMAL
+CLOCK_ENABLE_INPUT_B=NORMAL
+CLOCK_ENABLE_OUTPUT_B=NORMAL
+INTENDED_DEVICE_FAMILY="Cyclone III"
+LPM_TYPE=altsyncram
+NUMWORDS_A=8
+NUMWORDS_B=8
+OPERATION_MODE=DUAL_PORT
+OUTDATA_ACLR_B=NONE
+OUTDATA_REG_B=CLOCK0
+POWER_UP_UNINITIALIZED=FALSE
+RDCONTROL_REG_B=CLOCK0
+READ_DURING_WRITE_MODE_MIXED_PORTS=DONT_CARE
+WIDTHAD_A=3
+WIDTHAD_B=3
+WIDTH_A=1
+WIDTH_B=1
+WIDTH_BYTEENA_A=1
+DEVICE_FAMILY="Cyclone III"
+address_a
+address_b
+clock0
+clocken0
+data_a
+rden_b
+wren_a
+q_b

Oric Atmos_MiST/rtl/keymatrix.vhd

@@ -41,28 +41,62 @@ WEi(7) <= WE when wEN = '1' and wROW = "111" else '0';
 --      INIT => X"FFFF")
 --   port map (
 
---      D => wVAL,           -- Write 1-bit data input
+--      D => wVAL,           -- Write 1-bit data input---------------------------data
 
 --      SPO => SPOi(i),     	-- R/W 1-bit data output for A0-A3
---      A0 => wCOL(0),       -- R/W address[0] input bit
+
+--      A0 => wCOL(0),       -- R/W address[0] input bit--------------------------waddress
 --      A1 => wCOL(1),       -- R/W address[1] input bit
 --      A2 => wCOL(2),       -- R/W address[2] input bit
 --      A3 => '0',           -- R/W ddress[3] input bit
 
 
---      DPO => rROWBit(i),   -- Read-only 1-bit data output for DPRA
---      DPRA0 => rCOL(0),    -- Read-only address[0] input bit
+--      DPO => rROWBit(i),   -- Read-only 1-bit data output for DPRA--------------q
+
+
+--      DPRA0 => rCOL(0),    -- Read-only address[0] input bit--------------------------raddress
 --      DPRA1 => rCOL(1),    -- Read-only address[1] input bit
 --      DPRA2 => rCOL(2),    -- Read-only address[2] input bit
 --      DPRA3 => '0',        -- Read-only address[3] input bit
 
 
 
---      WCLK => CLK,         -- Write clock input
- --     WE => WEi(i)         -- Write enable input
+--      WCLK => CLK,         -- Write clock input-----------------------------------clock
+ --     WE => WEi(i)         -- Write enable input----------------------------------wren
  --  );
 --end generate;
 
+ROWBit : for i in 0 to 7 generate
+   RAM16X1D_ROWBit : entity work.RAM8X1D
+--   generic map (
+--      INIT => X"FFFF")
+   port map (
+
+      data(0) => wVAL,           -- Write 1-bit data input---------------------------data
+
+      enable => SPOi(i),     	-- R/W 1-bit data output for A0-A3
+		wraddress => wCOL,
+--      A0 => wCOL(0),       -- R/W address[0] input bit--------------------------waddress
+--      A1 => wCOL(1),       -- R/W address[1] input bit
+--      A2 => wCOL(2),       -- R/W address[2] input bit
+--      A3 => '0',           -- R/W ddress[3] input bit
+
+
+--      rden => rROWBit(i),   -- Read-only 1-bit data output for DPRA--------------q
+
+		rdaddress => rCOL,
+--      DPRA0 => rCOL(0),    -- Read-only address[0] input bit--------------------------raddress
+--      DPRA1 => rCOL(1),    -- Read-only address[1] input bit
+--      DPRA2 => rCOL(2),    -- Read-only address[2] input bit
+--      DPRA3 => '0',        -- Read-only address[3] input bit
+
+
+		clock => CLK,
+--      WCLK => CLK,         -- Write clock input-----------------------------------clock
+      wren => WEi(i)         -- Write enable input----------------------------------wren
+   );
+end generate;
+
 
 end arch;