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https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-31 05:41:56 +00:00
Right char colours
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@@ -39,14 +39,12 @@ wire oHB = (PH>=290) & (PH<492);
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assign VB = (PV==224);
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reg [4:0] PALT_A;
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wire [7:0] PALT_D;
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wire [7:0] CLT0_A;
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wire [3:0] CLT0_D;
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wire [11:0] BGCH_A;
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wire [7:0] BGCH_D;
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@@ -64,7 +62,7 @@ always @(posedge VCLKx8) if (PH == 290) BGVSCR <= SCROLL;
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reg [7:0] BGPN;
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reg BGH;
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reg [5:0] COL, ROW, ROW2;
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reg [5:0] COL, ROW;
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wire [7:0] CHRC = VRAM_D[7:0];
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wire [5:0] BGPL = VRAM_D[13:8];
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@@ -72,7 +70,7 @@ wire [5:0] BGPL = VRAM_D[13:8];
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wire [8:0] HP = HPOS;
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wire [8:0] VP = COL[5] ? VPOS : BGVPOS;
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wire [11:0] CHRA = { CHRC, ~HP[2], VP[2:0] };
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wire [7:0] CHRO = BGCH_D;
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wire [7:0] CHRO = BGCH_D; // Char pixel data
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reg [10:0] VRAMADRS;
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always @ ( posedge VCLKx8 ) begin
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@@ -86,17 +84,15 @@ always @ ( posedge VCLKx8 ) begin
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end
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assign CLT0_A = BGPN;
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assign BGCH_A = CHRA;
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assign CLT0_A = BGPN ^ ( MODEL==SUPERPAC ? 8'h0 : 8'h03 );
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assign VRAM_A = VRAMADRS & ( MODEL==SUPERPAC ? 11'h3FF : 11'h7FF );
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wire BGHI = BGH & (CLT0_D!=4'd15);
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wire [4:0] BGCOL = { 1'b1, CLT0_D };
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wire [4:0] BGCOL = { 1'b1, (MODEL==SUPERPAC ? ~CLT0_D :CLT0_D) };
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always @(*) begin
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COL = HPOS[8:3];
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ROW = VPOS[8:3];
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ROW2 = ROW + 6'h02;
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if( MODEL==SUPERPAC ) begin
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ROW = ROW + 6'h2;
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@@ -104,9 +100,10 @@ always @(*) begin
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COL[5] ? {COL[4:0], ROW[4:0]} :
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{ROW[4:0], COL[4:0]}
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};
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end else
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VRAMADRS = COL[5] ? { 4'b1111, COL[1:0], ROW[4], ROW2[3:0] } :
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end else begin
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VRAMADRS = COL[5] ? { 4'b1111, COL[1:0], ROW[4], ROW[3:0]+4'h2 } :
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{ VP[8:3], HP[7:3] };
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end
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end
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//----------------------------------------
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@@ -126,25 +123,48 @@ DRUAGA_SPRITE spr
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//----------------------------------------
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// Color mixer & Final output
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//----------------------------------------
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always @(posedge VCLKx8) if (VCLK_EN) PALT_A <= BGHI ? BGCOL : ((SPCOL[3:0]==4'd15) ? BGCOL : SPCOL );
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assign POUT = oHB ? 8'd0 : PALT_D;
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assign PCLK = VCLK;
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always @(posedge VCLKx8) if (VCLK_EN) begin
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PALT_A <= BGHI ? BGCOL : ((SPCOL[3:0]==4'd15) ? BGCOL : SPCOL );
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end
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assign POUT = oHB ? 8'd0 : PALT_D;
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assign PCLK = VCLK;
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assign PCLK_EN = VCLK_EN;
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//----------------------------------------
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// ROMs
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//----------------------------------------
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wire [7:0] chr_data = MODEL==SUPERPAC ? ~ROMDT : ROMDT;
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dpram #(8,12) bgchr(.clk_a(VCLKx8), .addr_a(BGCH_A), .q_a(BGCH_D),
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.clk_b(VCLKx8), .addr_b(ROMAD[11:0]),
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.we_b(ROMEN & (ROMAD[16:12]=={1'b1,4'h2})),
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.d_b(chr_data)
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// Char Tiles
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dpram #(8,12) bgchr(.clk_a ( VCLKx8 ),
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.addr_a( CHRA ),
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.q_a ( BGCH_D ),
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// ROM download
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.clk_b ( VCLKx8 ),
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.addr_b( ROMAD[11:0] ),
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.we_b ( ROMEN & (ROMAD[16:12]=={1'b1,4'h2}) ),
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.d_b ( ROMDT )
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);
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// Char palette LUT
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dpram #(4,8) clut0( .clk_a ( VCLKx8 ),
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.addr_a( CLT0_A ),
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.q_a ( CLT0_D ),
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// ROM download
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.clk_b ( VCLKx8 ),
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.addr_b( ROMAD[7:0] ),
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.we_b ( ROMEN & (ROMAD[16:8]=={1'b1,8'h34}) ),
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.d_b ( ROMDT[3:0] )
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);
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dpram #(4,8) clut0(.clk_a(VCLKx8), .addr_a(CLT0_A^8'h03), .q_a(CLT0_D),
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.clk_b(VCLKx8), .addr_b(ROMAD[7:0]), .we_b(ROMEN & (ROMAD[16:8]=={1'b1,8'h34})), .d_b(ROMDT[3:0]));
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// Colour PROM
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dpram #(8,5) pelet(.clk_a(VCLKx8), .addr_a(PALT_A), .q_a(PALT_D),
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.clk_b(VCLKx8), .addr_b(ROMAD[4:0]),
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.we_b(ROMEN & (ROMAD[16:5]=={1'b1,8'h36,3'b000})), .d_b(ROMDT));
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dpram #(8,5) pelet(.clk_a ( VCLKx8 ),
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.addr_a( PALT_A ),
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.q_a ( PALT_D ),
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// ROM download
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.clk_b ( VCLKx8 ),
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.addr_b( ROMAD[4:0] ),
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.we_b ( ROMEN & (ROMAD[16:5]=={1'b1,8'h36,3'b000}) ),
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.d_b ( ROMDT )
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);
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endmodule
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