mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-03-06 02:58:52 +00:00
Sync
This commit is contained in:
Marcel
@@ -1,29 +0,0 @@
|
||||
inst_via : entity work.M6522
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||||
port map (
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I_RS => cpu_ad(3 downto 0),
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I_DATA => cpu_do(7 downto 0),
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O_DATA => VIA_DO,
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I_RW_L => cpu_rw,
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||||
I_CS1 => ula_CSIO,
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||||
I_CS2_L => ula_IOCONTROL,
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||||
O_IRQ_L => cpu_irq, -- note, not open drain
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||||
I_CA1 => '1', -- PRT_ACK
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||||
I_CA2 => '1', -- psg_bdir
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O_CA2 => psg_bdir, -- via_ca2_out
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I_PA => via_pa_in,
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O_PA => via_pa_out,
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-- O_PA_OE_L => via_pa_out_oe,
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I_CB1 => K7_TAPEIN,
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-- O_CB1 => via_cb1_out,
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-- O_CB1_OE_L => via_cb1_oe_l,
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I_CB2 => '1',
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O_CB2 => via_cb2_out,
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-- O_CB2_OE_L => via_cb2_oe_l,
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I_PB => via_in,
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O_PB => via_out,
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-- O_PB_OE_L => via_oe_l,
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RESET_L => RESETn,
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I_P2_H => ula_phi2,
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ENA_4 => '1',
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CLK => ula_CLK_4
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);
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@@ -217,5 +217,4 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
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# --------------------------
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
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set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
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set_global_assignment -name VERILOG_FILE ../../common/IO/via6522.v
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@@ -293,16 +293,17 @@ inst_key : keyboard
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swrst => break
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);
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||||
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via_in <= x"F7" when (KEY_ROW or via_pa_out) = x"FF" else x"FF";
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via_in <= x"F7" when (KEY_ROW or via_pa_out) = x"FF-" else x"FF";
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K7_TAPEOUT <= via_out(7);
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K7_REMOTE <= via_out(6);
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ula_IOCONTROL <= '0'; -- ula_IOCONTROL <= IOCONTROL;
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process begin
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wait until rising_edge(clk_in);
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if cpu_rw = '1' and ula_IOCONTROL = '1' and ula_CSIOn = '0' then
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cpu_di <= SRAM_DO;-- expansion port
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elsif cpu_rw = '1' and ula_IOCONTROL = '0' and ula_CSIOn = '0' and ula_LATCH_SRAM = '0' then
|
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-- if cpu_rw = '1' and ula_IOCONTROL = '1' and ula_CSIOn = '0' then
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||||
-- cpu_di <= EXP_DO;-- expansion port
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-- els
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||||
if cpu_rw = '1' and ula_IOCONTROL = '0' and ula_CSIOn = '0' and ula_LATCH_SRAM = '0' then
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cpu_di <= VIA_DO;-- Via
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elsif cpu_rw = '1' and ula_IOCONTROL = '0' and ula_CSROMn = '0' then
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cpu_di <= ROM_DO; -- ROM
|
||||
|
||||
@@ -38,21 +38,34 @@
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||||
// synopsys translate_on
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module pll (
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||||
inclk0,
|
||||
c0);
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||||
c0,
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c1,
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c2,
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||||
locked);
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||||
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input inclk0;
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output c0;
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output c1;
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output c2;
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output locked;
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wire [4:0] sub_wire0;
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wire [0:0] sub_wire4 = 1'h0;
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wire [0:0] sub_wire1 = sub_wire0[0:0];
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wire c0 = sub_wire1;
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||||
wire sub_wire2 = inclk0;
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||||
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
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||||
wire sub_wire2;
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wire [0:0] sub_wire7 = 1'h0;
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wire [2:2] sub_wire4 = sub_wire0[2:2];
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||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
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wire [1:1] sub_wire1 = sub_wire0[1:1];
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wire c1 = sub_wire1;
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wire locked = sub_wire2;
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wire c0 = sub_wire3;
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wire c2 = sub_wire4;
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wire sub_wire5 = inclk0;
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wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
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altpll altpll_component (
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.inclk (sub_wire3),
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.inclk (sub_wire6),
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.clk (sub_wire0),
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.locked (sub_wire2),
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.activeclock (),
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.areset (1'b0),
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.clkbad (),
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@@ -69,7 +82,6 @@ module pll (
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||||
.fbout (),
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||||
.fref (),
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.icdrclk (),
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||||
.locked (),
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.pfdena (1'b1),
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.phasecounterselect ({4{1'b1}}),
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.phasedone (),
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@@ -94,6 +106,14 @@ module pll (
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altpll_component.clk0_duty_cycle = 50,
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altpll_component.clk0_multiply_by = 8,
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altpll_component.clk0_phase_shift = "0",
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altpll_component.clk1_divide_by = 9,
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altpll_component.clk1_duty_cycle = 50,
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altpll_component.clk1_multiply_by = 16,
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altpll_component.clk1_phase_shift = "0",
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altpll_component.clk2_divide_by = 9,
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altpll_component.clk2_duty_cycle = 50,
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altpll_component.clk2_multiply_by = 16,
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altpll_component.clk2_phase_shift = "-2500",
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altpll_component.compensate_clock = "CLK0",
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altpll_component.inclk0_input_frequency = 37037,
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altpll_component.intended_device_family = "Cyclone III",
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@@ -111,7 +131,7 @@ module pll (
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altpll_component.port_fbin = "PORT_UNUSED",
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altpll_component.port_inclk0 = "PORT_USED",
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altpll_component.port_inclk1 = "PORT_UNUSED",
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altpll_component.port_locked = "PORT_UNUSED",
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altpll_component.port_locked = "PORT_USED",
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altpll_component.port_pfdena = "PORT_UNUSED",
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altpll_component.port_phasecounterselect = "PORT_UNUSED",
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altpll_component.port_phasedone = "PORT_UNUSED",
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@@ -127,8 +147,8 @@ module pll (
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||||
altpll_component.port_scanread = "PORT_UNUSED",
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altpll_component.port_scanwrite = "PORT_UNUSED",
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altpll_component.port_clk0 = "PORT_USED",
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altpll_component.port_clk1 = "PORT_UNUSED",
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altpll_component.port_clk2 = "PORT_UNUSED",
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altpll_component.port_clk1 = "PORT_USED",
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altpll_component.port_clk2 = "PORT_USED",
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altpll_component.port_clk3 = "PORT_UNUSED",
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altpll_component.port_clk4 = "PORT_UNUSED",
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altpll_component.port_clk5 = "PORT_UNUSED",
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@@ -142,6 +162,7 @@ module pll (
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altpll_component.port_extclk1 = "PORT_UNUSED",
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altpll_component.port_extclk2 = "PORT_UNUSED",
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altpll_component.port_extclk3 = "PORT_UNUSED",
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altpll_component.self_reset_on_loss_lock = "OFF",
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||||
altpll_component.width_clock = 5;
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||||
|
||||
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||||
@@ -167,8 +188,14 @@ endmodule
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||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
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// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
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||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
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||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
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||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
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||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
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||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
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||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
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||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
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||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "48.000000"
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||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "48.000000"
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||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
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||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
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||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
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@@ -184,23 +211,39 @@ endmodule
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||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
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// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
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||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
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||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
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||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
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||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
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||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
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||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
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||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
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||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
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||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
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||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
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||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
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||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
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||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "48.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "48.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2500.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
@@ -223,11 +266,17 @@ endmodule
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
@@ -236,6 +285,14 @@ endmodule
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2500"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
@@ -252,7 +309,7 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
@@ -268,8 +325,8 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
@@ -283,13 +340,20 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
|
||||
30
Console_MiST/APF_TV_Fun/APF_TV_Fun.qpf
Normal file
30
Console_MiST/APF_TV_Fun/APF_TV_Fun.qpf
Normal file
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
|
||||
# Date created = 14:32:28 October 06, 2018
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "14:32:28 October 06, 2018"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "APF_TV_Fun"
|
||||
277
Console_MiST/APF_TV_Fun/APF_TV_Fun.qsf
Normal file
277
Console_MiST/APF_TV_Fun/APF_TV_Fun.qsf
Normal file
@@ -0,0 +1,277 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
# Date created = 02:08:17 July 22, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# Oric_MiST_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:11:53 MARCH 09, 2017"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
|
||||
set_location_assignment PIN_54 -to CLOCK_27
|
||||
set_location_assignment PIN_144 -to VGA_R[5]
|
||||
set_location_assignment PIN_143 -to VGA_R[4]
|
||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
||||
set_location_assignment PIN_137 -to VGA_R[1]
|
||||
set_location_assignment PIN_135 -to VGA_R[0]
|
||||
set_location_assignment PIN_133 -to VGA_B[5]
|
||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_4 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_6 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_8 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_10 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_11 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_28 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_50 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_30 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_32 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PIN_31 -to UART_RXD
|
||||
set_location_assignment PIN_46 -to UART_TXD
|
||||
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name SEARCH_PATH roms/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/MC6522/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/RAM/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/T6502/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/ps2kybrd/ -tag from_archive
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY APF_TV_Fun_MiST
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
|
||||
# EDA Netlist Writer Assignments
|
||||
# ==============================
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
# start EDA_TOOL_SETTINGS(eda_simulation)
|
||||
# ---------------------------------------
|
||||
|
||||
# EDA Netlist Writer Assignments
|
||||
# ==============================
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
|
||||
|
||||
# end EDA_TOOL_SETTINGS(eda_simulation)
|
||||
# -------------------------------------
|
||||
|
||||
# ----------------------------
|
||||
# start ENTITY(OricAtmos_MiST)
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(OricAtmos_MiST)
|
||||
# --------------------------
|
||||
set_global_assignment -name VERILOG_FILE rtl/ay_3_8500NTSC.v
|
||||
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/APF_TV_Fun_MiST.sv
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name VERILOG_FILE rtl/pll.v
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to UART_TXD
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CLOCK_27
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DI
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_SCK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_SS2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_SS3
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_HS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_VS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to UART_RXD
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
21
Console_MiST/APF_TV_Fun/APF_TV_Fun.srf
Normal file
21
Console_MiST/APF_TV_Fun/APF_TV_Fun.srf
Normal file
@@ -0,0 +1,21 @@
|
||||
{ "" "" "" "Verilog HDL macro warning at hq2x.sv(26): overriding existing definition for macro \"BITS_TO_FIT\", which was defined in \"rtl/scandoubler.v\", line 109" { } { } 0 10274 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL information at scandoubler.v(102): always construct contains both blocking and non-blocking assignments" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL warning at hq2x.sv(247): extended using \"x\" or \"z\"" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL or VHDL warning at t65.vhd(101): object \"D\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL or VHDL warning at keymatrix.vhd(24): object \"SPOi\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "VHDL warning at spram.vhd(10): ignored assignment of value to null range" { } { } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "VHDL warning at spram.vhd(66): ignored assignment of value to null range" { } { } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "VHDL warning at t65.vhd(186): comparison between unequal length operands always returns TRUE" { } { } 0 10620 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "VHDL warning at m6522.vhd(338): sensitivity list already contains r_ira" { } { } 0 10812 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Output port \"UART_TXD\" at OricAtmos_MiST.sv(10) has no driver" { } { } 0 10034 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Design contains 2 input pin(s) that do not drive logic" { } { } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "PLL \"pll:pll\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK\[1\] is not connected" { } { } 0 15899 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Output pins are stuck at VCC or GND" { } { } 0 13024 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Inferred dual-clock RAM node \"video_mixer:video_mixer\|osd:osd\|osd_buffer_rtl_0\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Design contains 1 input pin(s) that do not drive logic" { } { } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Ignored locations or region assignments to the following nodes" { } { } 0 15705 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "7 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
37
Console_MiST/APF_TV_Fun/clean.bat
Normal file
37
Console_MiST/APF_TV_Fun/clean.bat
Normal file
@@ -0,0 +1,37 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
del /s *~
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
rmdir /s /q hc_output
|
||||
rmdir /s /q .qsys_edit
|
||||
rmdir /s /q hps_isw_handoff
|
||||
rmdir /s /q sys\.qsys_edit
|
||||
rmdir /s /q sys\vip
|
||||
cd sys
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
cd ..
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
del build_id.v
|
||||
del c5_pin_model_dump.txt
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del /s *.qws
|
||||
del /s *.ppf
|
||||
del /s *.ddb
|
||||
del /s *.csv
|
||||
del /s *.cmp
|
||||
del /s *.sip
|
||||
del /s *.spd
|
||||
del /s *.bsf
|
||||
del /s *.f
|
||||
del /s *.sopcinfo
|
||||
del /s *.xml
|
||||
del /s new_rtl_netlist
|
||||
del /s old_rtl_netlist
|
||||
|
||||
pause
|
||||
187
Console_MiST/APF_TV_Fun/rtl/APF_TV_Fun_MiST.sv
Normal file
187
Console_MiST/APF_TV_Fun/rtl/APF_TV_Fun_MiST.sv
Normal file
@@ -0,0 +1,187 @@
|
||||
module APF_TV_Fun_MiST
|
||||
(
|
||||
input CLOCK_27,
|
||||
output LED,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input CONF_DATA0
|
||||
);
|
||||
|
||||
`include "rtl\build_id.v"
|
||||
|
||||
localparam CONF_STR = {
|
||||
"APF_TV_fun;;",
|
||||
// "O1,Sound ,On,Off;",
|
||||
"O23,Game ,Tennis,Soccer,Squash,Practice;",
|
||||
// "O13,Game ,Hidden,Tennis,Soccer,Squash,Practice,gameRifle1,gameRifle2;",
|
||||
"O4,Serve ,Auto,Manual;",
|
||||
"O5,Ball Angle ,20deg,40deg;", //check
|
||||
"O6,Bat Size ,Small,Big;", //check
|
||||
"O7,Ball Speed ,Fast,Slow;",
|
||||
"T8,Start;",
|
||||
|
||||
"T9,Reset;",
|
||||
"V,v1.00.",`BUILD_DATE
|
||||
};
|
||||
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
assign LED = 1'b1;
|
||||
|
||||
wire clk_16, clk_2;
|
||||
pll pll(
|
||||
.inclk0 ( CLOCK_27 ),
|
||||
.areset ( 0 ),
|
||||
.c0 ( clk_16 ),
|
||||
.c1 ( clk_2 )
|
||||
);
|
||||
|
||||
wire [31:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [15:0] kbjoy;
|
||||
wire [10:0] ps2_key;
|
||||
wire [7:0] joystick_0;
|
||||
wire [7:0] joystick_1;
|
||||
wire scandoubler_disable;
|
||||
wire ypbpr;
|
||||
wire ps2_kbd_clk, ps2_kbd_data;
|
||||
wire audio;
|
||||
wire hs, vs;
|
||||
wire vid_play, vid_RP, vid_LP, vid_Ball;
|
||||
wire video = vid_play | vid_RP | vid_LP | vid_Ball;
|
||||
wire gameTennis;
|
||||
wire gameSoccer;
|
||||
wire gameSquash;
|
||||
wire gamePractice;
|
||||
wire gameRifle1;
|
||||
wire gameRifle2;
|
||||
wire m_left, m_right;
|
||||
wire LPin, RPin, Rifle1, Rifle2;
|
||||
|
||||
always @(clk_16)
|
||||
begin
|
||||
if (RPin) begin
|
||||
if (joystick_0[2]) m_right = 1'b1; else
|
||||
if (joystick_0[3]) m_right = 1'b0;
|
||||
end else m_right = 1'bz;
|
||||
|
||||
if (LPin) begin
|
||||
if (joystick_1[2]) m_left = 1'b1; else
|
||||
if (joystick_1[3]) m_left = 1'b0;
|
||||
end else m_left = 1'bz;
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
case (status[3:2])
|
||||
// 3'b001 : begin gameTennis <= 0; gameSoccer <= 1; gameSquash <= 1; gamePractice <= 1; gameRifle1 <= 1; gameRifle2 <= 1; end
|
||||
// 3'b010 : begin gameTennis <= 1; gameSoccer <= 0; gameSquash <= 1; gamePractice <= 1; gameRifle1 <= 1; gameRifle2 <= 1; end
|
||||
// 3'b011 : begin gameTennis <= 1; gameSoccer <= 1; gameSquash <= 0; gamePractice <= 1; gameRifle1 <= 1; gameRifle2 <= 1; end
|
||||
// 3'b100 : begin gameTennis <= 1; gameSoccer <= 1; gameSquash <= 1; gamePractice <= 0; gameRifle1 <= 1; gameRifle2 <= 1; end
|
||||
// 3'b101 : begin gameTennis <= 1; gameSoccer <= 1; gameSquash <= 1; gamePractice <= 1; gameRifle1 <= 0; gameRifle2 <= 1; end
|
||||
// 3'b111 : begin gameTennis <= 1; gameSoccer <= 1; gameSquash <= 1; gamePractice <= 1; gameRifle1 <= 1; gameRifle2 <= 0; end
|
||||
// default : begin gameTennis <= 1; gameSoccer <= 1; gameSquash <= 1; gamePractice <= 1; gameRifle1 <= 1; gameRifle2 <= 1; end
|
||||
|
||||
2'b01 : begin gameTennis <= 1; gameSoccer <= 0; gameSquash <= 1; gamePractice <= 1; gameRifle1 <= 1; gameRifle2 <= 1; end
|
||||
2'b10 : begin gameTennis <= 1; gameSoccer <= 1; gameSquash <= 0; gamePractice <= 1; gameRifle1 <= 1; gameRifle2 <= 1; end
|
||||
2'b11 : begin gameTennis <= 1; gameSoccer <= 1; gameSquash <= 1; gamePractice <= 0; gameRifle1 <= 1; gameRifle2 <= 1; end
|
||||
default : begin gameTennis <= 0; gameSoccer <= 1; gameSquash <= 1; gamePractice <= 1; gameRifle1 <= 1; gameRifle2 <= 1; end
|
||||
endcase
|
||||
end
|
||||
|
||||
ay38500NTSC ay38500NTSC(
|
||||
.clk(clk_2),
|
||||
.reset(~(buttons[1] | status[0] | status[9])),
|
||||
.pinSound(audio),
|
||||
//Video
|
||||
.pinBallOut(vid_Ball),
|
||||
.pinRPout(vid_RP),
|
||||
.pinLPout(vid_LP),
|
||||
.pinSFout(vid_play),
|
||||
.vsync(vs),
|
||||
.hsync(hs),
|
||||
//Menu Items
|
||||
.pinManualServe(status[4] | joystick_0[4] | joystick_1[4]),
|
||||
.pinBallAngle(status[5]),
|
||||
.pinBatSize(status[6]),
|
||||
.pinBallSpeed(status[7]),
|
||||
//Game Select
|
||||
.pinRifle1(1'b1),// ?
|
||||
.pinRifle2(1'b1),// ?
|
||||
.pinTennis(gameTennis),
|
||||
.pinSoccer(gameSoccer),
|
||||
.pinSquash(gameSquash),
|
||||
.pinPractice(gamePractice),
|
||||
|
||||
.pinShotIn(1'b1),// todo
|
||||
.pinHitIn(1'b0),// todo
|
||||
.pinRifle1_DWN(Rifle1),// ?
|
||||
.pinTennis_DWN(Rifle2),// ?
|
||||
.pinRPin_DWN(RPin),
|
||||
.pinLPin_DWN(LPin),
|
||||
.pinRPin(m_right),// todo
|
||||
.pinLPin(m_left)// todo
|
||||
);
|
||||
|
||||
dac #(
|
||||
.c_bits(8))
|
||||
dac (
|
||||
.clk_i (clk_16 ),
|
||||
.res_n_i (1 ),
|
||||
.dac_i ({8{audio}} ),
|
||||
.dac_o (AUDIO_L )
|
||||
);
|
||||
|
||||
mist_video #(
|
||||
.SD_HCNT_WIDTH(10),//wrong
|
||||
.COLOR_DEPTH(1))
|
||||
mist_video(
|
||||
.clk_sys(clk_16),
|
||||
.SPI_DI(SPI_DI),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_SS3(SPI_SS3),
|
||||
.scandoubler_disable(scandoubler_disable),
|
||||
.ypbpr(ypbpr),
|
||||
.HSync(~hs),
|
||||
.VSync(~vs),
|
||||
.R(video),
|
||||
.G(video),
|
||||
.B(video),
|
||||
.VGA_HS(VGA_HS),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B)
|
||||
);
|
||||
|
||||
user_io #(.STRLEN(($size(CONF_STR)>>3))) user_io (
|
||||
.clk_sys ( clk_16 ),
|
||||
.conf_str ( CONF_STR ),
|
||||
.SPI_CLK ( SPI_SCK ),
|
||||
.SPI_SS_IO ( CONF_DATA0 ),
|
||||
.SPI_MISO ( SPI_DO ),
|
||||
.SPI_MOSI ( SPI_DI ),
|
||||
.buttons ( buttons ),
|
||||
.switches ( switches ),
|
||||
.ypbpr ( ypbpr ),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.scandoubler_disable(scandoubler_disable),
|
||||
.joystick_0 ( joystick_0 ),
|
||||
.joystick_1 ( joystick_1 ),
|
||||
.status ( status )
|
||||
);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
852
Console_MiST/APF_TV_Fun/rtl/ay_3_8500NTSC.v
Normal file
852
Console_MiST/APF_TV_Fun/rtl/ay_3_8500NTSC.v
Normal file
@@ -0,0 +1,852 @@
|
||||
/*
|
||||
* Release 1 7/3/2019
|
||||
* Verilog description of the AY-3-8500 (NTSC varient)
|
||||
* Generated from a transistor-level netlist by DLAET
|
||||
* Some manual patches have been made (marked by comments)
|
||||
*
|
||||
* Thanks to Sean Riddle for decapping the speciman
|
||||
* and to: Suverman, Erika, Ewen McNeill, and Dylan Lipsitz
|
||||
* for supporting me on Patreon
|
||||
*/
|
||||
|
||||
/*verilator lint_off UNOPTFLAT */
|
||||
module ay38500NTSC(
|
||||
output pinRPout,
|
||||
output pinLPout,
|
||||
output pinBallOut,
|
||||
input pinManualServe,
|
||||
output pinRPin_DWN,
|
||||
input pinRPin,
|
||||
input pinBallAngle,
|
||||
output pinLPin_DWN,
|
||||
input pinLPin,
|
||||
input pinBatSize,
|
||||
input pinBallSpeed,
|
||||
output pinSyncOut,
|
||||
output pinSound,
|
||||
input clk,
|
||||
input pinHitIn,
|
||||
output pinRifle1_DWN,
|
||||
input pinRifle1,
|
||||
input pinRifle2,
|
||||
input pinShotIn,
|
||||
output pinTennis_DWN,
|
||||
input pinTennis,
|
||||
output pinSFout,
|
||||
input pinSoccer,
|
||||
input pinSquash,
|
||||
input pinPractice,
|
||||
input reset,
|
||||
output vsync,
|
||||
output hsync);
|
||||
|
||||
assign vsync = flop6;
|
||||
assign hsync= !flop7;
|
||||
|
||||
assign pinRPout = !or28;
|
||||
assign pinLPout = !or38;
|
||||
assign pinBallOut = !or2;
|
||||
assign pinRPin_DWN = flop6;//MC: The ORs were bypassed
|
||||
assign pinLPin_DWN = flop6;
|
||||
assign pinSyncOut = !or56;
|
||||
assign pinSound = or69;
|
||||
assign pinRifle1_DWN = !or150;
|
||||
assign pinTennis_DWN = !or211;
|
||||
assign pinSFout = or212;
|
||||
wire pulser0 = flop6;
|
||||
wire pulser1 = (!or170 | pulser1_delay);
|
||||
reg pulser1_delay = 0;
|
||||
always @(negedge clk) begin
|
||||
pulser1_delay <= or170;
|
||||
end
|
||||
reg flop0 = 0;
|
||||
always @(posedge clk) begin
|
||||
flop0 <= flop2;
|
||||
end
|
||||
reg flop1 = 0;
|
||||
wire flop1_reset = !or213 | counter5_2268;
|
||||
wire flop1_set = !or3 | !or6;
|
||||
always @(posedge flop1_reset or posedge flop1_set) begin
|
||||
if(flop1_reset)
|
||||
flop1 <= 0;
|
||||
else
|
||||
flop1 <= 1;
|
||||
end
|
||||
reg flop2 = 0;
|
||||
wire flop2_reset = !or213 | counter4_2130;
|
||||
wire flop2_set = !or18 | !or19;
|
||||
always @(posedge flop2_reset or posedge flop2_set) begin
|
||||
if(flop2_reset)
|
||||
flop2 <= 0;
|
||||
else
|
||||
flop2 <= 1;
|
||||
end
|
||||
reg flop3 = 0;
|
||||
wire flop3_reset = !or4;
|
||||
wire flop3_set = !pinManualServe & reset;//MC: set/reset priority have been reversed + reset added to flop3_set's OR
|
||||
always @(posedge flop3_set or posedge flop3_reset) begin
|
||||
if(flop3_set)
|
||||
flop3 <= 0;
|
||||
else
|
||||
flop3 <= 1;
|
||||
end
|
||||
reg flop4 = 0;
|
||||
wire flop4_reset = !or16 | or24 | or27 | !or213;
|
||||
wire flop4_set = !or15 | or23 | or22;
|
||||
always @(posedge flop4_reset or posedge flop4_set) begin
|
||||
if(flop4_reset)
|
||||
flop4 <= 0;
|
||||
else
|
||||
flop4 <= 1;
|
||||
end
|
||||
reg flop5 = 0;
|
||||
wire flop5_reset = or27 | or22;
|
||||
wire flop5_set = or24 | or23 | !or213;
|
||||
always @(posedge flop5_reset or posedge flop5_set) begin
|
||||
if(flop5_reset)
|
||||
flop5 <= 0;
|
||||
else
|
||||
flop5 <= 1;
|
||||
end
|
||||
reg flop6 = 0;
|
||||
wire flop6_reset = !reset | !or88;
|
||||
wire flop6_set = !or86;
|
||||
always @(posedge flop6_reset or posedge flop6_set) begin
|
||||
if(flop6_reset)
|
||||
flop6 <= 0;
|
||||
else
|
||||
flop6 <= 1;
|
||||
end
|
||||
reg flop7 = 0;
|
||||
wire flop7_reset = !reset | !or63;
|
||||
wire flop7_set = !or74;
|
||||
always @(posedge flop7_reset or posedge flop7_set) begin
|
||||
if(flop7_reset)
|
||||
flop7 <= 0;
|
||||
else
|
||||
flop7 <= 1;
|
||||
end
|
||||
reg flop8 = 0;
|
||||
always @(negedge or8) begin
|
||||
flop8 <= or55;
|
||||
end
|
||||
reg flop9 = 0;
|
||||
always @(negedge or8) begin
|
||||
flop9 <= !or49;
|
||||
end
|
||||
reg flop10 = 0;
|
||||
always @(negedge or8) begin
|
||||
flop10 <= or66;
|
||||
end
|
||||
reg flop11 = 0;
|
||||
always @(negedge or8) begin
|
||||
flop11 <= !or51;
|
||||
end
|
||||
reg flop12 = 0;
|
||||
wire flop12_reset = !or92;
|
||||
wire flop12_set = !or90;
|
||||
always @(posedge flop12_reset or posedge flop12_set) begin
|
||||
if(flop12_reset)
|
||||
flop12 <= 0;
|
||||
else
|
||||
flop12 <= 1;
|
||||
end
|
||||
reg flop13 = 0;
|
||||
wire flop13_reset = !or169;
|
||||
wire flop13_set = !flop26 | !and18;
|
||||
always @(posedge flop13_reset or posedge flop13_set) begin
|
||||
if(flop13_reset)
|
||||
flop13 <= 0;
|
||||
else
|
||||
flop13 <= 1;
|
||||
end
|
||||
reg flop14 = 0;
|
||||
wire flop14_reset = !pulser1;
|
||||
wire flop14_set = !and18;
|
||||
always @(posedge flop14_reset or posedge flop14_set) begin
|
||||
if(flop14_reset)
|
||||
flop14 <= 0;
|
||||
else
|
||||
flop14 <= 1;
|
||||
end
|
||||
reg flop15 = 0;
|
||||
wire flop15_reset = !or135;
|
||||
wire flop15_set = !or136;
|
||||
always @(posedge flop15_reset or posedge flop15_set) begin
|
||||
if(flop15_reset)
|
||||
flop15 <= 0;
|
||||
else
|
||||
flop15 <= 1;
|
||||
end
|
||||
reg flop16 = 0;
|
||||
wire flop16_reset = or144;
|
||||
wire flop16_set = !and18;
|
||||
always @(posedge flop16_reset or posedge flop16_set) begin
|
||||
if(flop16_reset)
|
||||
flop16 <= 0;
|
||||
else
|
||||
flop16 <= 1;
|
||||
end
|
||||
reg flop17 = 0;
|
||||
wire flop17_reset = or149;
|
||||
wire flop17_set = or127 | !or153 | !or213;
|
||||
always @(posedge flop17_reset or posedge flop17_set) begin
|
||||
if(flop17_reset)
|
||||
flop17 <= 0;
|
||||
else
|
||||
flop17 <= 1;
|
||||
end
|
||||
reg flop18 = 0;
|
||||
wire flop18_reset = !reset;
|
||||
wire flop18_set = !or193 | !or200;
|
||||
always @(posedge flop18_reset or posedge flop18_set) begin
|
||||
if(flop18_reset)
|
||||
flop18 <= 0;
|
||||
else
|
||||
flop18 <= 1;
|
||||
end
|
||||
reg flop19 = 0;
|
||||
wire flop19_reset = !or155;
|
||||
wire flop19_set = !and18;
|
||||
always @(posedge flop19_reset or posedge flop19_set) begin
|
||||
if(flop19_reset)
|
||||
flop19 <= 0;
|
||||
else
|
||||
flop19 <= 1;
|
||||
end
|
||||
reg flop20 = 0;
|
||||
wire flop20_reset = !or143;
|
||||
wire flop20_set = !or142;
|
||||
always @(posedge flop20_reset or posedge flop20_set) begin
|
||||
if(flop20_reset)
|
||||
flop20 <= 0;
|
||||
else
|
||||
flop20 <= 1;
|
||||
end
|
||||
reg flop21 = 0;
|
||||
wire flop21_reset = or146;
|
||||
wire flop21_set = !or138;
|
||||
always @(posedge flop21_reset or posedge flop21_set) begin
|
||||
if(flop21_reset)
|
||||
flop21 <= 0;
|
||||
else
|
||||
flop21 <= 1;
|
||||
end
|
||||
reg flop22 = 0;
|
||||
always @(posedge or152) begin
|
||||
flop22 <= flop21;
|
||||
end
|
||||
reg flop23 = 0;
|
||||
wire flop23_reset = !or70;
|
||||
wire flop23_set = !or68;
|
||||
always @(posedge flop23_reset or posedge flop23_set) begin
|
||||
if(flop23_reset)
|
||||
flop23 <= 0;
|
||||
else
|
||||
flop23 <= 1;
|
||||
end
|
||||
reg flop24 = 0;
|
||||
wire flop24_reset = !ripple_ctr9_2;
|
||||
wire flop24_set = flop25;
|
||||
always @(posedge flop24_reset or posedge flop24_set) begin
|
||||
if(flop24_reset)
|
||||
flop24 <= 0;
|
||||
else
|
||||
flop24 <= 1;
|
||||
end
|
||||
reg flop25 = 0;
|
||||
wire flop25_reset = !ripple_ctr9_2 | flop24;
|
||||
wire flop25_set = !or141;
|
||||
always @(posedge flop25_reset or posedge flop25_set) begin
|
||||
if(flop25_reset)
|
||||
flop25 <= 0;
|
||||
else
|
||||
flop25 <= 1;
|
||||
end
|
||||
reg flop26 = 0;
|
||||
wire flop26_reset = !pinHitIn;
|
||||
wire flop26_set = !and18;
|
||||
always @(posedge flop26_reset or posedge flop26_set) begin
|
||||
if(flop26_reset)
|
||||
flop26 <= 0;
|
||||
else
|
||||
flop26 <= 1;
|
||||
end
|
||||
reg flop27 = 0;
|
||||
wire flop27_reset = !or199;
|
||||
wire flop27_set = !or166;
|
||||
always @(posedge flop27_reset or posedge flop27_set) begin
|
||||
if(flop27_reset)
|
||||
flop27 <= 0;
|
||||
else
|
||||
flop27 <= 1;
|
||||
end
|
||||
reg flop28 = 0;
|
||||
wire flop28_reset = !or124;
|
||||
wire flop28_set = !or70;
|
||||
always @(posedge flop28_reset or posedge flop28_set) begin
|
||||
if(flop28_reset)
|
||||
flop28 <= 0;
|
||||
else
|
||||
flop28 <= 1;
|
||||
end
|
||||
reg flop29 = 0;
|
||||
wire flop29_reset = !or164;
|
||||
wire flop29_set = !or199;
|
||||
always @(posedge flop29_reset or posedge flop29_set) begin
|
||||
if(flop29_reset)
|
||||
flop29 <= 0;
|
||||
else
|
||||
flop29 <= 1;
|
||||
end
|
||||
reg flop30 = 0;
|
||||
wire flop30_reset = !or199 | or205;
|
||||
wire flop30_set = !reset;
|
||||
always @(posedge flop30_reset or posedge flop30_set) begin
|
||||
if(flop30_reset)
|
||||
flop30 <= 0;
|
||||
else
|
||||
flop30 <= 1;
|
||||
end
|
||||
reg flop31 = 0;
|
||||
wire flop31_reset = !or188;
|
||||
wire flop31_set = !and18;
|
||||
always @(posedge flop31_reset or posedge flop31_set) begin
|
||||
if(flop31_reset)
|
||||
flop31 <= 0;
|
||||
else
|
||||
flop31 <= 1;
|
||||
end
|
||||
reg flop32 = 0;
|
||||
wire flop32_reset = !flop13 | !or155 | or144 | !pulser1;
|
||||
wire flop32_set = !and18;
|
||||
always @(posedge flop32_reset or posedge flop32_set) begin
|
||||
if(flop32_reset)
|
||||
flop32 <= 0;
|
||||
else
|
||||
flop32 <= 1;
|
||||
end
|
||||
reg flop33 = 0;
|
||||
wire flop33_reset = !or193 | !or200 | !or205;
|
||||
wire flop33_set = !or210;
|
||||
always @(posedge flop33_reset or posedge flop33_set) begin
|
||||
if(flop33_reset)
|
||||
flop33 <= 0;
|
||||
else
|
||||
flop33 <= 1;
|
||||
end
|
||||
reg flop34 = 0;
|
||||
wire flop34_reset = !or181;
|
||||
wire flop34_set = !or177;
|
||||
always @(posedge flop34_reset or posedge flop34_set) begin
|
||||
if(flop34_reset)
|
||||
flop34 <= 0;
|
||||
else
|
||||
flop34 <= 1;
|
||||
end
|
||||
reg flop35 = 0;
|
||||
wire flop35_reset = !or168;
|
||||
wire flop35_set = !or178;
|
||||
always @(posedge flop35_reset or posedge flop35_set) begin
|
||||
if(flop35_reset)
|
||||
flop35 <= 0;
|
||||
else
|
||||
flop35 <= 1;
|
||||
end
|
||||
wire and0 = !or26 & !or147;
|
||||
wire and1 = !or29 & or118;
|
||||
wire and2 = !or31 & !or147;
|
||||
wire and3 = !or34 & or118;
|
||||
wire and4 = !or36 & !or147;
|
||||
wire and5 = !or39 & or118;
|
||||
wire and6 = !or42 & !or147;
|
||||
wire and7 = !or43 & or118;
|
||||
wire and8 = !or117 & or0;
|
||||
wire and9 = !flop23 & ripple_ctr1_4;
|
||||
wire and10 = flop23 & ripple_ctr0_4;
|
||||
wire and11 = !flop23 & ripple_ctr1_3;
|
||||
wire and12 = flop23 & ripple_ctr0_3;
|
||||
wire and13 = !flop23 & ripple_ctr1_2;
|
||||
wire and14 = flop23 & ripple_ctr0_2;
|
||||
wire and15 = !flop23 & ripple_ctr1_5;
|
||||
wire and16 = flop23 & ripple_ctr0_5;
|
||||
wire and17 = flop4 & !or214;
|
||||
wire and18 = or1 & reset;
|
||||
wire and19 = !or214 & flop17;
|
||||
wire or0 = !or72 | !or73;
|
||||
wire or1 = ripple_ctr4_4 | ripple_ctr4_3 | ripple_ctr4_2 | ripple_ctr4_5;
|
||||
wire or2 = !or13 | or196 | pinHitIn;
|
||||
wire or3 = !or205 | !counter5_2254;
|
||||
wire or4 = !or176 | flop7;
|
||||
wire or5 = !counter5_2265 | !flop0 | !or209;
|
||||
wire or6 = or205 | !counter5_2263;
|
||||
wire or7 = !flop2 | !flop1 | !or209;
|
||||
wire or8 = !or16 | !or15 | or127 | or149 | !or213;
|
||||
wire or9 = pinBallSpeed | flop8;
|
||||
wire or10 = flop9 | pinBallSpeed;
|
||||
wire or11 = pinBallSpeed | flop11;
|
||||
wire or12 = !pinBallSpeed | flop10;
|
||||
wire or13 = !or7 | !or214;
|
||||
wire or14 = flop6 | !pinRPin;
|
||||
wire or15 = !or13 | !or195;
|
||||
wire or16 = !or13 | !or65;
|
||||
wire or17 = !or16 | !or15 | !or152 | !or67;
|
||||
wire or18 = !or205 | !counter4_2125;
|
||||
wire or19 = or205 | !counter4_2128;
|
||||
wire or20 = !ripple_ctr7_2 | !ripple_ctr7_3 | !ripple_ctr7_4 | !ripple_ctr7_5;
|
||||
wire or21 = or14 | !or54 | !or20;
|
||||
wire or22 = and6 | and7;
|
||||
wire or23 = and4 | and5;
|
||||
wire or24 = and2 | and3;
|
||||
wire or25 = !ripple_ctr8_2 | !ripple_ctr8_3 | !ripple_ctr8_4 | !ripple_ctr8_5;
|
||||
wire or26 = !ripple_ctr7_4 | !ripple_ctr7_5;
|
||||
wire or27 = and0 | and1;
|
||||
wire or28 = !or120 | flop34 | or14 | !or20 | or205;
|
||||
wire or29 = !ripple_ctr8_4 | !ripple_ctr8_5;
|
||||
wire or30 = !flop5 | !flop4;
|
||||
wire or31 = ripple_ctr7_4 | !ripple_ctr7_5;
|
||||
wire or32 = !flop17 | pinBallSpeed;
|
||||
wire or33 = !flop5 | flop4;
|
||||
wire or34 = ripple_ctr8_4 | !ripple_ctr8_5;
|
||||
wire or35 = !flop4 | flop5;
|
||||
wire or36 = !ripple_ctr7_4 | ripple_ctr7_5;
|
||||
wire or37 = !flop17 | !pinBallSpeed;
|
||||
wire or38 = !or119 | flop34 | or48 | !or25 | or205;
|
||||
wire or39 = !ripple_ctr8_4 | ripple_ctr8_5;
|
||||
wire or40 = flop17 | pinBallSpeed;
|
||||
wire or41 = flop4 | flop5;
|
||||
wire or42 = ripple_ctr7_4 | ripple_ctr7_5;
|
||||
wire or43 = ripple_ctr8_5 | ripple_ctr8_4;
|
||||
wire or44 = flop17 | !pinBallSpeed;
|
||||
wire or45 = !or25 | !or54 | or48;
|
||||
wire or46 = !pinBallAngle | or41;
|
||||
wire or47 = !pinBallAngle | or35;
|
||||
wire or48 = flop6 | !pinLPin;
|
||||
wire or49 = !or47 | !or30;
|
||||
wire or50 = !or32 | !or37 | !or40 | !or44 | !reset;
|
||||
wire or51 = !or46 | !or33;
|
||||
wire or52 = !pinBatSize | !ripple_ctr10_2;
|
||||
wire or53 = flop7 | pinBatSize;
|
||||
wire or54 = !or53 | !or52;
|
||||
wire or55 = or35 | pinBallAngle;
|
||||
wire or56 = flop6 | !flop7;
|
||||
wire or57 = !reset | !or74;
|
||||
wire or58 = !reset | !or88;
|
||||
wire or59 = !pinBallSpeed | flop9;
|
||||
wire or60 = pinBallSpeed | flop10;
|
||||
wire or61 = !pinBallSpeed | flop8;
|
||||
wire or62 = !pinBallSpeed | flop11;
|
||||
wire or63 = ripple_ctr9_2 | !counter2_2060;
|
||||
wire or64 = ripple_ctr9_2 | !counter2_2048;
|
||||
wire or65 = !or181 | !or71;
|
||||
wire or66 = or41 | pinBallAngle;
|
||||
wire or67 = or158 | !or176;
|
||||
wire or68 = ripple_ctr9_2 | !counter2_2031;
|
||||
wire or69 = !or130 | !or133;
|
||||
wire or70 = ripple_ctr9_2 | !counter2_2013;
|
||||
wire or71 = !flop7 | !counter3_2020;
|
||||
wire or72 = and11 | and12;
|
||||
wire or73 = and9 | and10;
|
||||
wire or74 = ripple_ctr9_2 | !counter2_2064;
|
||||
wire or75 = !or117 | !or112 | !or72 | !or73;
|
||||
wire or76 = or107 | or106 | or105 | !or95 | !or96 | !or97 | !or98 | or110 | or109;
|
||||
wire or77 = or107 | or106 | !or96 | !or97 | !or98 | or110 | or109 | or108;
|
||||
wire or78 = or107 | or106 | or105 | !or95 | !or96 | !or97 | !or98 | or110 | or109 | or108;
|
||||
wire or79 = or107 | or106 | or105 | !or95 | !or97 | !or98 | or108;
|
||||
wire or80 = or107 | or105 | !or95 | !or96 | !or97 | !or98 | or110 | or108;
|
||||
wire or81 = or107 | or105 | !or95 | !or97 | !or98 | or110 | or108;
|
||||
wire or82 = !or95 | !or97 | or110 | or108;
|
||||
wire or83 = or107 | or106 | or105 | !or95 | !or97 | !or98 | or110 | or108;
|
||||
wire or84 = or106 | or105 | !or95 | !or97 | !or98 | or110;
|
||||
wire or85 = or107 | or106 | or105 | !or95 | !or96 | !or97 | !or98 | or110 | or108;
|
||||
wire or86 = !or63 | !counter3_2129;
|
||||
wire or87 = !or117 | or112 | !or72 | !or73;
|
||||
wire or88 = !or63 | !counter3_2131;
|
||||
wire or89 = !or117 | !or112 | or72 | !or73;
|
||||
wire or90 = !flop7 | !counter3_2034;
|
||||
wire or91 = !or117 | or112 | or72 | !or73;
|
||||
wire or92 = !flop7 | !counter3_2022;
|
||||
wire or93 = !or117 | !or112 | or73 | !or72;
|
||||
wire or94 = !or117 | or112 | or73 | !or72;
|
||||
wire or95 = !or117 | !or112 | or73 | or72;
|
||||
wire or96 = !or117 | or112 | or73 | or72;
|
||||
wire or97 = !or112 | or117 | !or72 | !or73;
|
||||
wire or98 = or112 | or117 | !or72 | !or73;
|
||||
wire or99 = !or112 | or117 | or72 | !or73;
|
||||
wire or100 = or112 | or117 | or72 | !or73;
|
||||
wire or101 = !or112 | or117 | or73 | !or72;
|
||||
wire or102 = or112 | or117 | or73 | !or72;
|
||||
wire or103 = !or112 | or117 | or73 | or72;
|
||||
wire or104 = or112 | or117 | or73 | or72;
|
||||
wire or105 = !or94 | !or104;
|
||||
wire or106 = !or93 | !or103;
|
||||
wire or107 = !or91 | !or102;
|
||||
wire or108 = !or89 | !or101;
|
||||
wire or109 = !or87 | !or100;
|
||||
wire or110 = !or75 | !or99;
|
||||
wire or111 = counter1_2000 | counter1_2006;
|
||||
wire or112 = and13 | and14;
|
||||
wire or113 = !and8 | or111;
|
||||
wire or114 = mux2_100 | or111;
|
||||
wire or115 = mux0_100 | or111;
|
||||
wire or116 = mux1_100 | or111;
|
||||
wire or117 = and15 | and16;
|
||||
wire or118 = !or138 | !or128;
|
||||
wire or119 = !or137 | !or132;
|
||||
wire or120 = !or123 | !or122 | !or126;
|
||||
wire or121 = ripple_ctr9_2 | !counter2_2014;
|
||||
wire or122 = ripple_ctr9_2 | or204 | !counter2_2022;
|
||||
wire or123 = ripple_ctr9_2 | or206 | !counter2_2039;
|
||||
wire or124 = ripple_ctr9_2 | !counter2_2049;
|
||||
wire or125 = flop18 | or28;
|
||||
wire or126 = or202 | or64;
|
||||
wire or127 = !or148 | !or134;
|
||||
wire or128 = !or191 | or134;
|
||||
wire or129 = or38 | flop18 | !or191;
|
||||
wire or130 = !or131 | or205;
|
||||
wire or131 = !or139 | !or140 | !or151;
|
||||
wire or132 = or121 | or202;
|
||||
wire or133 = !or205 | ripple_ctr3_2 | flop13;
|
||||
wire or134 = !or176 | or129;
|
||||
wire or135 = ripple_ctr9_2 | !counter2_2029;
|
||||
wire or136 = ripple_ctr9_2 | !counter2_2024;
|
||||
wire or137 = ripple_ctr9_2 | or207 | !counter2_2040;
|
||||
wire or138 = or191 | !or176 | flop18 | or38 | !or165;
|
||||
wire or139 = flop14 | ripple_ctr3_2;
|
||||
wire or140 = flop16 | !ripple_ctr5_2;
|
||||
wire or141 = !or142 | !or136;
|
||||
wire or142 = ripple_ctr9_2 | !or189 | !counter2_2033;
|
||||
wire or143 = ripple_ctr9_2 | !counter2_2038;
|
||||
wire or144 = !or134 | !or147 | !or138;
|
||||
wire or145 = !or182 | !or172;
|
||||
wire or146 = !or147 | !reset;
|
||||
wire or147 = or125 | !or176 | !or167;
|
||||
wire or148 = or161 | !or176;
|
||||
wire or149 = !or147 | !or138 | !or67;
|
||||
wire or150 = !pinRifle1 | and17;
|
||||
wire or151 = flop19 | !ripple_ctr6_2;
|
||||
wire or152 = !or176 | or161;
|
||||
wire or153 = pinRifle2 | !pinSoccer;
|
||||
wire or154 = !flop17 | !or191;
|
||||
wire or155 = !or17 | or170;
|
||||
wire or156 = !flop21 | or191;
|
||||
wire or157 = !or154 | !or156;
|
||||
wire or158 = flop35 | or124 | or204 | !or153;
|
||||
wire or159 = flop17 | !or191;
|
||||
wire or160 = flop34 | or202 | or68;
|
||||
wire or161 = flop35 | or70 | or203;
|
||||
wire or162 = flop21 | or191;
|
||||
wire or163 = !or159 | !or162;
|
||||
wire or164 = !or163 | flop7 | !or176;
|
||||
wire or165 = !flop22 | or191;
|
||||
wire or166 = !or157 | flop7 | !or176;
|
||||
wire or167 = flop22 | or191;
|
||||
wire or168 = !flop7 | !counter3_2096;
|
||||
wire or169 = flop26 | !pinHitIn;
|
||||
wire or170 = !flop29 | flop27;
|
||||
wire or171 = !or161 | !or158;
|
||||
wire or172 = flop12 | !flop20 | ripple_ctr9_2;
|
||||
wire or173 = !flop27 | or205 | flop18;
|
||||
wire or174 = ripple_ctr10_2 | !or171 | flop34;
|
||||
wire or175 = !or124 | !or70;
|
||||
wire or176 = !or5 | !or214;
|
||||
wire or177 = !flop7 | !counter3_2117;
|
||||
wire or178 = !flop7 | or208 | !counter3_2041;
|
||||
wire or179 = !or205 | flop18 | !pinShotIn;
|
||||
wire or180 = !flop7 | !counter3_2116;
|
||||
wire or181 = !flop7 | !counter3_2021;
|
||||
wire or182 = flop12 | !flop15 | ripple_ctr9_2;
|
||||
wire or183 = flop30 | !or179 | !or173;
|
||||
wire or184 = !or160 | !or198 | !or174;
|
||||
wire or185 = !or150 | !pinSoccer;
|
||||
wire or186 = flop29 | or205 | flop18;
|
||||
wire or187 = !or184 | or205;
|
||||
wire or188 = !ripple_ctr6_2 | flop32;
|
||||
wire or189 = !pinSoccer | pinPractice;
|
||||
wire or190 = !or205 | flop18 | !pinHitIn;
|
||||
wire or191 = !pinSoccer | pinSquash;
|
||||
wire or192 = flop30 | !or186 | !or190;
|
||||
wire or193 = ripple_ctr1_4 | ripple_ctr1_3 | ripple_ctr1_2 | ripple_ctr1_5 | or183;
|
||||
wire or194 = !or180 | !or181;
|
||||
wire or195 = !or177 | !or180;
|
||||
wire or196 = flop34 | !flop28;
|
||||
wire or197 = flop12 | shift_reg0_104 | flop33;
|
||||
wire or198 = !or194 | !flop28 | ripple_ctr9_2;
|
||||
wire or199 = !or175 | !or176;
|
||||
wire or200 = ripple_ctr0_5 | ripple_ctr0_2 | ripple_ctr0_3 | ripple_ctr0_4 | or192;
|
||||
wire or201 = !pinSoccer | !or211;
|
||||
wire or202 = !or189 | !or191;
|
||||
wire or203 = !or201 | !or153;
|
||||
wire or204 = !or189 | !or191 | !or201;
|
||||
wire or205 = !or185 | !or153;
|
||||
wire or206 = !pinSoccer | !or201;
|
||||
wire or207 = !or189 | !or201;
|
||||
wire or208 = !or185 | !or189 | !or191;
|
||||
wire or209 = pinPractice | pinSoccer;
|
||||
wire or210 = reset | !or205;
|
||||
wire or211 = !pinTennis | and19;
|
||||
wire or212 = !or187 | !or197;
|
||||
wire or213 = pinSquash | pinSoccer;
|
||||
wire or214 = pinSoccer | pinRifle2;
|
||||
reg [5:0] shift_reg0 = 0;
|
||||
reg [3:0] shift_reg0_spot = 0;
|
||||
/* verilator lint_off WIDTH */
|
||||
wire shift_reg0_104 = shift_reg0[shift_reg0_spot];
|
||||
/* verilator lint_on WIDTH */
|
||||
always @(negedge or145 or posedge flop24) begin
|
||||
if(flop24) begin
|
||||
shift_reg0_spot <= 5;
|
||||
end
|
||||
else if(shift_reg0_spot!=0) begin
|
||||
shift_reg0_spot <= shift_reg0_spot - 1;
|
||||
end
|
||||
end
|
||||
//MC: This block had to be manually changed
|
||||
always @(posedge flop24) begin
|
||||
shift_reg0[0:0] <= 1;
|
||||
shift_reg0[1:1] <= or115;
|
||||
shift_reg0[2:2] <= or116;
|
||||
shift_reg0[3:3] <= or114;
|
||||
shift_reg0[4:4] <= 1;
|
||||
shift_reg0[5:5] <= or113;
|
||||
end
|
||||
//MC: All ripple counter outputs (except paddle ones) have inverted resets & outputs
|
||||
reg [4:0] ripple_ctr0 = 0;
|
||||
wire ripple_ctr0_2 = !ripple_ctr0[0:0];
|
||||
wire ripple_ctr0_3 = !ripple_ctr0[1:1];
|
||||
wire ripple_ctr0_4 = !ripple_ctr0[2:2];
|
||||
wire ripple_ctr0_5 = !ripple_ctr0[3:3];
|
||||
always @(posedge or192 or negedge reset) begin
|
||||
if(!reset)
|
||||
ripple_ctr0 <= 0;
|
||||
else
|
||||
ripple_ctr0 <= ripple_ctr0 + 1;
|
||||
end
|
||||
|
||||
reg [4:0] ripple_ctr1 = 0;
|
||||
wire ripple_ctr1_2 = !ripple_ctr1[0:0];
|
||||
wire ripple_ctr1_3 = !ripple_ctr1[1:1];
|
||||
wire ripple_ctr1_4 = !ripple_ctr1[2:2];
|
||||
wire ripple_ctr1_5 = !ripple_ctr1[3:3];
|
||||
always @(posedge or183 or negedge reset) begin
|
||||
if(!reset)
|
||||
ripple_ctr1 <= 0;
|
||||
else
|
||||
ripple_ctr1 <= ripple_ctr1 + 1;
|
||||
end
|
||||
|
||||
reg [1:0] ripple_ctr2 = 0;
|
||||
wire ripple_ctr2_2 = !ripple_ctr2[0:0];
|
||||
always @(negedge ripple_ctr10_2 or negedge or213) begin
|
||||
if(!or213)
|
||||
ripple_ctr2 <= 0;
|
||||
else
|
||||
ripple_ctr2 <= ripple_ctr2 + 1;
|
||||
end
|
||||
|
||||
reg [1:0] ripple_ctr3 = 0;
|
||||
wire ripple_ctr3_2 = !ripple_ctr3[0:0];
|
||||
always @(negedge ripple_ctr2_2 or negedge or213) begin
|
||||
if(!or213)
|
||||
ripple_ctr3 <= 0;
|
||||
else
|
||||
ripple_ctr3 <= ripple_ctr3 + 1;
|
||||
end
|
||||
|
||||
reg [4:0] ripple_ctr4 = 0;
|
||||
wire ripple_ctr4_2 = !ripple_ctr4[0:0];
|
||||
wire ripple_ctr4_3 = !ripple_ctr4[1:1];
|
||||
wire ripple_ctr4_4 = !ripple_ctr4[2:2];
|
||||
wire ripple_ctr4_5 = !ripple_ctr4[3:3];
|
||||
always @(negedge or188 or posedge flop31) begin
|
||||
if(flop31)
|
||||
ripple_ctr4 <= 0;
|
||||
else
|
||||
ripple_ctr4 <= ripple_ctr4 + 1;
|
||||
end
|
||||
|
||||
reg [1:0] ripple_ctr5 = 0;
|
||||
wire ripple_ctr5_2 = !ripple_ctr5[0:0];
|
||||
always @(negedge ripple_ctr3_2 or negedge reset) begin
|
||||
if(!reset)
|
||||
ripple_ctr5 <= 0;
|
||||
else
|
||||
ripple_ctr5 <= ripple_ctr5 + 1;
|
||||
end
|
||||
|
||||
reg [1:0] ripple_ctr6 = 0;
|
||||
wire ripple_ctr6_2 = !ripple_ctr6[0:0];
|
||||
always @(negedge ripple_ctr5_2 or negedge reset) begin
|
||||
if(!reset)
|
||||
ripple_ctr6 <= 0;
|
||||
else
|
||||
ripple_ctr6 <= ripple_ctr6 + 1;
|
||||
end
|
||||
|
||||
reg [4:0] ripple_ctr7 = 0;
|
||||
wire ripple_ctr7_2 = ripple_ctr7[0:0];
|
||||
wire ripple_ctr7_3 = ripple_ctr7[1:1];
|
||||
wire ripple_ctr7_4 = ripple_ctr7[2:2];
|
||||
wire ripple_ctr7_5 = ripple_ctr7[3:3];
|
||||
always @(negedge or21 or posedge or14) begin
|
||||
if(or14)
|
||||
ripple_ctr7 <= 0;
|
||||
else
|
||||
ripple_ctr7 <= ripple_ctr7 + 1;
|
||||
end
|
||||
|
||||
reg [4:0] ripple_ctr8 = 0;
|
||||
wire ripple_ctr8_2 = ripple_ctr8[0:0];
|
||||
wire ripple_ctr8_3 = ripple_ctr8[1:1];
|
||||
wire ripple_ctr8_4 = ripple_ctr8[2:2];
|
||||
wire ripple_ctr8_5 = ripple_ctr8[3:3];
|
||||
always @(negedge or45 or posedge or48) begin
|
||||
if(or48)
|
||||
ripple_ctr8 <= 0;
|
||||
else
|
||||
ripple_ctr8 <= ripple_ctr8 + 1;
|
||||
end
|
||||
|
||||
reg [1:0] ripple_ctr9 = 0;
|
||||
wire ripple_ctr9_2 = !ripple_ctr9[0:0];
|
||||
always @(negedge clk or negedge or213) begin
|
||||
if(!or213)
|
||||
ripple_ctr9 <= 0;
|
||||
else
|
||||
ripple_ctr9 <= ripple_ctr9 + 1;
|
||||
end
|
||||
|
||||
reg [1:0] ripple_ctr10 = 0;
|
||||
wire ripple_ctr10_2 = !ripple_ctr10[0:0];
|
||||
always @(posedge flop7 or negedge or213) begin
|
||||
if(!or213)
|
||||
ripple_ctr10 <= 0;
|
||||
else
|
||||
ripple_ctr10 <= ripple_ctr10 + 1;
|
||||
end
|
||||
|
||||
//MC: Add flop12 reset
|
||||
reg [2:0] counter0 = 0;
|
||||
wire counter0_2003 = (counter0==3);
|
||||
always @(negedge flop7 or posedge flop12) begin
|
||||
if(flop12)
|
||||
counter0 <= 0;
|
||||
else if(counter0==3)
|
||||
counter0 <= 0;
|
||||
else
|
||||
counter0 <= counter0 + 1;
|
||||
end
|
||||
reg [3:0] counter1 = 0;
|
||||
wire counter1_2005 = (counter1==5);
|
||||
wire counter1_2003 = (counter1==3);
|
||||
wire counter1_2006 = (counter1==6);
|
||||
wire counter1_2000 = (counter1==0);
|
||||
wire counter1_2001 = (counter1==1);
|
||||
wire counter1_2002 = (counter1==2);
|
||||
wire counter1_2004 = (counter1==4);
|
||||
always @(negedge counter0_2003 or posedge flop12) begin
|
||||
if(flop12)
|
||||
counter1 <= 0;
|
||||
else if(counter1==6)
|
||||
counter1 <= 0;
|
||||
else
|
||||
counter1 <= counter1 + 1;
|
||||
end
|
||||
reg [7:0] counter2 = 0;
|
||||
wire counter2_2038 = (counter2==38);
|
||||
wire counter2_2033 = (counter2==33);
|
||||
wire counter2_2029 = (counter2==29);
|
||||
wire counter2_2049 = (counter2==49);
|
||||
wire counter2_2022 = (counter2==22);
|
||||
wire counter2_2064 = (counter2==64);
|
||||
wire counter2_2048 = (counter2==48);
|
||||
wire counter2_2040 = (counter2==40);
|
||||
wire counter2_2039 = (counter2==39);
|
||||
wire counter2_2031 = (counter2==31);
|
||||
wire counter2_2024 = (counter2==24);
|
||||
wire counter2_2014 = (counter2==14);
|
||||
wire counter2_2013 = (counter2==13);
|
||||
wire counter2_2060 = (counter2==60);
|
||||
always @(posedge ripple_ctr9_2 or posedge or57) begin
|
||||
if(or57)
|
||||
counter2 <= 0;
|
||||
else if(counter2==126)
|
||||
counter2 <= 0;
|
||||
else
|
||||
counter2 <= counter2 + 1;
|
||||
end
|
||||
reg [8:0] counter3 = 0;
|
||||
wire counter3_2129 = (counter3==129);
|
||||
wire counter3_2131 = (counter3==131);
|
||||
wire counter3_2117 = (counter3==117);
|
||||
wire counter3_2096 = (counter3==96);
|
||||
wire counter3_2022 = (counter3==22);
|
||||
wire counter3_2020 = (counter3==20);
|
||||
wire counter3_2116 = (counter3==116);
|
||||
wire counter3_2041 = (counter3==41);
|
||||
wire counter3_2034 = (counter3==34);
|
||||
wire counter3_2021 = (counter3==21);
|
||||
always @(posedge ripple_ctr10_2 or posedge or58) begin
|
||||
if(or58)
|
||||
counter3 <= 0;
|
||||
else if(counter3==216)
|
||||
counter3 <= 0;
|
||||
else
|
||||
counter3 <= counter3 + 1;
|
||||
end
|
||||
//MC: Multiple changes to jumping counters
|
||||
reg [8:0] counter4 = 0;
|
||||
reg counter4_delay = 0;
|
||||
reg counter4_jump = 0;
|
||||
wire counter4_2130 = (counter4==129);
|
||||
wire counter4_2125 = (counter4==125);
|
||||
wire counter4_2128 = (counter4==128);
|
||||
always @(posedge clk) begin
|
||||
if(!reset | flop3) begin
|
||||
counter4 <= 0;
|
||||
counter4_jump <= 0;
|
||||
end
|
||||
else begin
|
||||
if(counter4==129) begin
|
||||
counter4 <= !counter4_jump ? 2 : !or32 ? 0 : !or37 ? 1 : !or40 ? 4 : !or44 ? 3 : 0;//MC: 3 & 4 changed to 4 & 5
|
||||
counter4_jump <= 0;
|
||||
end
|
||||
else begin
|
||||
counter4_delay <= pulser0;
|
||||
if(!counter4_delay && pulser0)
|
||||
counter4_jump <= 1;
|
||||
counter4 <= counter4 + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [9:0] counter5 = 0;
|
||||
reg counter5_delay = 0;
|
||||
reg counter5_jump = 0;
|
||||
wire counter5_2254 = (counter5==254);
|
||||
wire counter5_2263 = (counter5==263);
|
||||
wire counter5_2265 = (counter5==265);
|
||||
wire counter5_2268 = (counter5==267);
|
||||
always @(negedge flop7) begin
|
||||
if(!reset) begin
|
||||
counter5 <= 0;
|
||||
counter5_jump <= 0;
|
||||
end
|
||||
else begin
|
||||
if(counter5==267) begin//Values > non-jump must be increased by 4?
|
||||
counter5 <= !counter5_jump ? 6 : !or59 ? 11 : !or9 ? 15 : !or10 ? 12 : !or62 ? 5 : !or61 ? 13 : !or11 ? 4 : !or12 ? 3 : !or60 ? 1 : 0;
|
||||
counter5_jump <= 0;
|
||||
end
|
||||
else begin
|
||||
counter5_delay <= pulser0;
|
||||
if(!counter5_delay && pulser0)
|
||||
counter5_jump <= 1;
|
||||
counter5 <= counter5 + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
wire mux0_100 = (!or78 & counter1_2001) | (!or77 & counter1_2002) | (!or76 & counter1_2004);
|
||||
//MC: Some changes to this line
|
||||
wire mux1_100 = (!or81 & counter1_2005) | (!or80 & counter1_2001) | (!or79 & counter1_2003) | counter1_2002 | counter1_2004;//constants had to be added manually
|
||||
wire mux2_100 = (!or81 & counter1_2005) | (!or85 & counter1_2001) | (!or83 & counter1_2003) | (!or84 & counter1_2002) | (!or82 & counter1_2004);
|
||||
endmodule
|
||||
35
Console_MiST/APF_TV_Fun/rtl/build_id.tcl
Normal file
35
Console_MiST/APF_TV_Fun/rtl/build_id.tcl
Normal file
@@ -0,0 +1,35 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
4
Console_MiST/APF_TV_Fun/rtl/pll.qip
Normal file
4
Console_MiST/APF_TV_Fun/rtl/pll.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
||||
348
Console_MiST/APF_TV_Fun/rtl/pll.v
Normal file
348
Console_MiST/APF_TV_Fun/rtl/pll.v
Normal file
@@ -0,0 +1,348 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2014 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll (
|
||||
areset,
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
locked);
|
||||
|
||||
input areset;
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output locked;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 areset;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
|
||||
altpll altpll_component (
|
||||
.areset (areset),
|
||||
.inclk (sub_wire5),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.activeclock (),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 27,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 16,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 27,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 2,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_USED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "16.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "16.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
Reference in New Issue
Block a user