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Marcel
parent
c29a0b0144
commit
540d571150
@ -239,7 +239,6 @@ set_global_assignment -name VERILOG_FILE rtl/mario_logic.v
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set_global_assignment -name VERILOG_FILE rtl/mario_sound.v
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set_global_assignment -name VERILOG_FILE rtl/mario_sound_mixer.v
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set_global_assignment -name VERILOG_FILE rtl/mario_sound_digital.v
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set_global_assignment -name VHDL_FILE rtl/rom/snd_rom.vhd
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set_global_assignment -name VERILOG_FILE rtl/m58715ip.v
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set_global_assignment -name VERILOG_FILE rtl/mario_iir_filter.v
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set_global_assignment -name VERILOG_FILE rtl/mario_bram.v
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@ -259,4 +258,7 @@ set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/CPU/T80/T80.qip"
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set_global_assignment -name QIP_FILE ../../common/CPU/t48/T48.qip
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set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip"
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set_global_assignment -name VERILOG_FILE rtl/mario_sound_analog.v
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set_global_assignment -name VHDL_FILE rtl/rom/snd_rom.vhd
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set_global_assignment -name VERILOG_FILE rtl/mario_wav_sound.v
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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Binary file not shown.
@ -78,8 +78,8 @@ reg port1_req, port2_req;
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reg [23:0] port1_a, port2_a;
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wire [15:0] cpu_rom_addr;
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wire [15:0] cpu_rom_do;
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wire [11:0] bg_rom_addr;
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wire [15:0] bg_rom_do;
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wire [12:0] snd_rom_addr;
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wire [15:0] snd_rom_do;
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data_io #(.ROM_DIRECT_UPLOAD(0)) data_io(
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.clk_sys ( clk_sys ),
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@ -115,14 +115,14 @@ sdram sdram(
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// port2 for sound board
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.port2_req ( port2_req ),
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.port2_ack ( ),
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.port2_a ( ioctl_addr[23:1] - 17'h10000 ),
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.port2_a ( ioctl_addr[23:1] - 15'h4800 ),
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.port2_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
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.port2_we ( ioctl_downl ),
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.port2_d ( {ioctl_dout, ioctl_dout} ),
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.port2_q ( ),
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.snd_addr ( ioctl_downl ? 15'h7fff : bg_rom_addr[11:1] ),
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.snd_q ( bg_rom_do )
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.snd_addr ( ioctl_downl ? 15'h7fff : snd_rom_addr[12:1] ),
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.snd_q ( snd_rom_do )
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);
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@ -158,7 +158,6 @@ end
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mario_top mario_top(
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.I_CLK_48M(clk_sys),
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.I_RESETn(~reset),
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.I_ANLG_VOL(status[11:8]),
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.I_SW1(m_sw1),
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.I_SW2(m_sw2),
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@ -173,9 +172,8 @@ mario_top mario_top(
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.O_SOUND_DAT(audio),
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.cpu_rom_addr(cpu_rom_addr),
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.cpu_rom_do(cpu_rom_addr[0] ? cpu_rom_do[15:8] : cpu_rom_do[7:0]),
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.bg_rom_addr(bg_rom_addr),
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.bg_rom_do(bg_rom_do)
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.snd_rom_addr(snd_rom_addr),
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.snd_rom_do(snd_rom_do)
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);
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mist_video #(.COLOR_DEPTH(3),.SD_HCNT_WIDTH(11)) mist_video(
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@ -16,7 +16,9 @@ module mario_sound
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input [9:0]I_SND_CTRL,
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input [3:0]I_ANLG_VOL,
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input [3:0]I_H_CNT,
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output signed [15:0]O_SND_DAT
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output signed [15:0]O_SND_DAT,
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output [12:0] snd_rom_addr,
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input [15:0] snd_rom_do
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);
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//------------------------------------------------
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@ -34,7 +36,6 @@ mario_sound_digital digital_sound
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.I_RST(I_RESETn),
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.I_SND_DATA(I_SND_DATA),
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.I_SND_CTRL(I_SND_CTRL[6:0]),
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.O_SND_OUT(W_D_S_DATA)
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);
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@ -45,23 +46,20 @@ mario_sound_digital digital_sound
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wire signed [15:0]W_WAVROM_DS[0:2];
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//mario_sound_analog analog_sound
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//(
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// .I_CLK_48M(I_CLK_48M),
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// .I_RESETn(I_RESETn),
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//
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// .I_SND_CTRL(I_SND_CTRL[9:7]),
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// .I_ANLG_VOL(I_ANLG_VOL),
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// .I_H_CNT(I_H_CNT),
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//
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// .I_DLADDR(I_DLADDR),
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// .I_DLDATA(I_DLDATA),
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// .I_DLWR(I_DLWR),
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//
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// .O_WAVROM_DS0(W_WAVROM_DS[0]),
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// .O_WAVROM_DS1(W_WAVROM_DS[1]),
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// .O_WAVROM_DS2(W_WAVROM_DS[2])
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//);
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mario_sound_analog analog_sound
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(
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.I_CLK_48M(I_CLK_48M),
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.I_RESETn(I_RESETn),
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.I_SND_CTRL(I_SND_CTRL[9:7]),
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.I_ANLG_VOL(I_ANLG_VOL),
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.I_H_CNT(I_H_CNT),
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.O_WAVROM_DS0(W_WAVROM_DS[0]),
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.O_WAVROM_DS1(W_WAVROM_DS[1]),
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.O_WAVROM_DS2(W_WAVROM_DS[2]),
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.snd_rom_addr(snd_rom_addr),
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.snd_rom_do(snd_rom_do)
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);
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//----------------------------------
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// Sound Mixer (Analogue & Digital)
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137
Arcade_MiST/Nintendo Mario Bros/rtl/mario_sound_analog.v
Normal file
137
Arcade_MiST/Nintendo Mario Bros/rtl/mario_sound_analog.v
Normal file
@ -0,0 +1,137 @@
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//----------------------------------------------------------------------------
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// Mario Bros Arcade
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//
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// Author: gaz68 (https://github.com/gaz68) June 2020
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//
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// Analogue sounds (samples).
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// Mario run, Luigi run and skid sounds.
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//----------------------------------------------------------------------------
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module mario_sound_analog
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(
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input I_CLK_48M,
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input I_RESETn,
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input [2:0]I_SND_CTRL,
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input [3:0]I_ANLG_VOL,
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input [3:0]I_H_CNT,
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input [16:0]I_DLADDR,
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input [7:0]I_DLDATA,
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input I_DLWR,
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output signed [15:0]O_WAVROM_DS0,
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output signed [15:0]O_WAVROM_DS1,
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output signed [15:0]O_WAVROM_DS2,
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output [12:0] snd_rom_addr,
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input [15:0] snd_rom_do
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);
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//-----------------------
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// Extra ROM for samples
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//-----------------------
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reg [12:0]WAVROM_ADDR;
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wire [15:0]W_WAVROM_DO;
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//WAV_ROM wavrom(I_CLK_48M, WAVROM_ADDR, W_WAVROM_DO,
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// I_CLK_48M, I_DLADDR, I_DLDATA, I_DLWR);
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assign snd_rom_addr = WAVROM_ADDR;
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assign W_WAVROM_DO = snd_rom_do;
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wire signed [15:0]W_WAVROM_DS[0:3];
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wire [12:0]W_WAVROM_A[0:3];
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//------------
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// Skid sound
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//------------
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mario_wav_sound skid_sound
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(
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.I_CLK(I_CLK_48M),
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.I_RSTn(I_RESETn),
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.I_H_CNT(I_H_CNT[3:0]),
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.I_DIV(12'd2176), // 48Mhz / 2176 = 22,050Hz
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.I_VOL(I_ANLG_VOL),
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.I_DMA_TRIG(~I_SND_CTRL[0]),
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.I_DMA_STOP(1'b0),
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.I_RETRIG_EN(1'b1),
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.I_DMA_CHAN(3'd0),
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.I_DMA_ADDR(16'h0000),
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.I_DMA_LEN(16'h0800),
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.I_DMA_DATA(W_WAVROM_DO), // Sample data from wave ROM.
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.O_DMA_ADDR(W_WAVROM_A[0]), // Wave ROM address.
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.O_SND(W_WAVROM_DS[0])
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);
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assign O_WAVROM_DS0 = W_WAVROM_DS[0];
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//-----------------
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// Mario run sound
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//-----------------
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mario_wav_sound mario_run_sound
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(
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.I_CLK(I_CLK_48M),
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.I_RSTn(I_RESETn),
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.I_H_CNT(I_H_CNT[3:0]),
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.I_DIV(12'd2176),
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.I_VOL(I_ANLG_VOL),
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.I_DMA_TRIG(~I_SND_CTRL[1]),
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.I_DMA_STOP(1'b0),
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.I_RETRIG_EN(1'b0),
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.I_DMA_CHAN(3'd1),
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.I_DMA_ADDR(16'h0800),
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.I_DMA_LEN(16'h0800),
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.I_DMA_DATA(W_WAVROM_DO),
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.O_DMA_ADDR(W_WAVROM_A[1]),
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.O_SND(W_WAVROM_DS[1])
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);
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assign O_WAVROM_DS1 = W_WAVROM_DS[1];
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//-----------------
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// Luigi run sound
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//-----------------
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mario_wav_sound luigi_run_sound
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(
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.I_CLK(I_CLK_48M),
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.I_RSTn(I_RESETn),
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.I_H_CNT(I_H_CNT[3:0]),
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.I_DIV(12'd2176),
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.I_VOL(I_ANLG_VOL),
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.I_DMA_TRIG(~I_SND_CTRL[2]),
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.I_DMA_STOP(1'b0),
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.I_RETRIG_EN(1'b0),
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.I_DMA_CHAN(3'd2),
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.I_DMA_ADDR(16'h1000),
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.I_DMA_LEN(16'h0800),
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.I_DMA_DATA(W_WAVROM_DO),
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.O_DMA_ADDR(W_WAVROM_A[2]),
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.O_SND(W_WAVROM_DS[2])
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);
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assign O_WAVROM_DS2 = W_WAVROM_DS[2];
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//--------------------------------
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// Sample ROM address bus sharing
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//--------------------------------
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always @(posedge I_CLK_48M or negedge I_RESETn)
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begin
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if(! I_RESETn)begin
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WAVROM_ADDR <= 0;
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end else begin
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case(I_H_CNT[3:0])
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0: WAVROM_ADDR <= W_WAVROM_A[0];
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2: WAVROM_ADDR <= W_WAVROM_A[1];
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4: WAVROM_ADDR <= W_WAVROM_A[2];
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default:;
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endcase
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end
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end
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endmodule
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@ -21,6 +21,7 @@ module mario_sound_digital
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output signed [15:0]O_SND_DAC,
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output signed [15:0]O_SND_OUT
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);
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//----------------
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@ -100,6 +101,7 @@ wire [7:0]S_PROG_D ;
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//SUB_EXT_ROM srom5k(I_CLK_48M, S_ROM_A, 1'b0, S_ROM_OE, S_PROG_D,
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// I_CLK_48M, I_DLADDR, I_DLDATA, I_DLWR);
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snd_rom snd_rom(
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.clk(I_CLK_48M),
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.addr(S_ROM_A),
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@ -107,7 +109,6 @@ snd_rom snd_rom(
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);
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// M58715 Data Bus
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wire [7:0]M58715_DO = S_7J_OC == 1'b0 ? I_SND_DATA : S_PROG_D;
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@ -18,8 +18,8 @@ module mario_top
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output [15:0] cpu_rom_addr,
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input [7:0] cpu_rom_do,
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output [11:0] bg_rom_addr,
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input [15:0] bg_rom_do,
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output [12:0] snd_rom_addr,
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input [15:0] snd_rom_do,
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output [2:0] O_VGA_R,
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output [2:0] O_VGA_G,
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@ -29,7 +29,6 @@ module mario_top
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output O_VGA_HSYNCn,
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output O_VGA_VSYNCn,
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output O_PIX,
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output signed [15:0] O_SOUND_DAT
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);
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@ -216,8 +215,6 @@ mario_video vid
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.I_OBJDMA_A(W_DMAD_A),
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.I_OBJDMA_D(W_DMAD_D),
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.I_OBJDMA_CE(W_DMAD_CE),
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.bg_rom_addr(bg_rom_addr),
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.bg_rom_do(bg_rom_do),
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.O_VRAM_DB(W_VRAM_DB),
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.O_VRAMBUSYn(W_VRAMBUSYn),
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.O_FLIP_HV(W_FLIP_HV),
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@ -242,7 +239,9 @@ mario_sound sound
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.I_SND_CTRL({W_4C_Q[1:0],W_7M_Q}),
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.I_ANLG_VOL(I_ANLG_VOL),
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.I_H_CNT(W_H_CNT[3:0]),
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.O_SND_DAT(O_SOUND_DAT)
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.O_SND_DAT(O_SOUND_DAT),
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.snd_rom_addr(snd_rom_addr),
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.snd_rom_do(snd_rom_do)
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);
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@ -34,9 +34,7 @@ module mario_video
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output [7:0]O_OBJ_DB,
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output [2:0]O_VGA_RED,
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output [2:0]O_VGA_GRN,
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output [1:0]O_VGA_BLU,
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output [15:0]bg_rom_addr,
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input [15:0]bg_rom_do
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output [1:0]O_VGA_BLU
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);
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//------------------
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@ -69,9 +67,7 @@ mario_vram vram
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.O_DB(W_VRAM_DB),
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.O_COL(W_VRAM_COL),
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.O_VID(W_VRAM_VID),
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.O_VRAMBUSYn(W_VRAMBUSYn),
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.bg_rom_addr(bg_rom_addr),
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.bg_rom_do(bg_rom_do)
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.O_VRAMBUSYn(W_VRAMBUSYn)
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);
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wire [6:0]W_VRAM_DAT = {W_VRAM_COL[3:0],1'b0,W_VRAM_VID[1:0]};
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@ -37,9 +37,7 @@ module mario_vram(
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output [7:0]O_DB,
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output reg [3:0]O_COL,
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output [1:0]O_VID,
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output O_VRAMBUSYn,
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output [15:0]bg_rom_addr,
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input [15:0]bg_rom_do
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output O_VRAMBUSYn
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);
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//---------------------------------------------------
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@ -142,9 +140,6 @@ gfx_3j gfx_3j(
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.data(W_3FJ_DO[7:0])
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);
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//assign bg_rom_addr = W_VROM_AB;
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//assign W_3FJ_DO = bg_rom_do;
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//-------------------
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// Shift register 2H
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//-------------------
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116
Arcade_MiST/Nintendo Mario Bros/rtl/mario_wav_sound.v
Normal file
116
Arcade_MiST/Nintendo Mario Bros/rtl/mario_wav_sound.v
Normal file
@ -0,0 +1,116 @@
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//----------------------------------------------------------------------------
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// Mario Bros Arcade
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//
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// Author: gaz68 (https://github.com/gaz68) June 2020
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//
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// Sound sample player.
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// Up to 8 channels. 16-bit signed samples.
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// This version supports re-triggerable samples.
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// Workaround for Mario Bros analogue sounds.
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// TO DO: Proper synthesis/simulation of analogue sounds.
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//----------------------------------------------------------------------------
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module mario_wav_sound
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(
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input I_CLK,
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input I_RSTn,
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input [3:0]I_H_CNT,
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input [11:0]I_DIV,
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input [3:0]I_VOL,
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input I_DMA_TRIG,
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input I_DMA_STOP,
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input I_RETRIG_EN, // Allow sample to be retriggered during playback
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input [2:0]I_DMA_CHAN, // 8 channels
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input [15:0]I_DMA_ADDR,
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input [15:0]I_DMA_LEN,
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input signed [15:0]I_DMA_DATA, // Data coming back from wave ROM
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output [15:0]O_DMA_ADDR, // Output address to wave ROM
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output signed [15:0]O_SND
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);
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reg [15:0]W_DMA_ADDR;
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reg signed [23:0]W_DMA_DATA;
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reg [15:0]W_DMA_CNT;
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reg W_DMA_EN = 1'b0;
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reg [11:0]sample;
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reg W_DMA_TRIG;
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reg signed [15:0]W_SAMPL;
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reg signed [8:0]W_VOL;
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always@(posedge I_CLK or negedge I_RSTn)
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begin
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if(! I_RSTn)begin
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W_DMA_EN <= 1'b0;
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W_DMA_CNT <= 0;
|
||||
W_DMA_DATA <= 0;
|
||||
W_DMA_ADDR <= 0;
|
||||
W_DMA_TRIG <= 0;
|
||||
W_VOL <= 0;
|
||||
sample <= 0;
|
||||
|
||||
end else begin
|
||||
|
||||
// Check for DMA trigger and enable DMA.
|
||||
W_DMA_TRIG <= I_DMA_TRIG;
|
||||
|
||||
if(~W_DMA_TRIG & I_DMA_TRIG) begin
|
||||
|
||||
if (W_DMA_EN==1'b0 || (W_DMA_EN==1'b1 & I_RETRIG_EN)) begin
|
||||
|
||||
W_DMA_ADDR <= I_DMA_ADDR;
|
||||
W_DMA_CNT <= 0;
|
||||
W_DMA_EN <= 1'b1;
|
||||
W_DMA_DATA <= 0;
|
||||
sample <= 0;
|
||||
|
||||
end
|
||||
|
||||
end else if (W_DMA_EN == 1'b1) begin
|
||||
|
||||
case(I_VOL)
|
||||
0: W_VOL <= 9'sd255; // 100%
|
||||
1: W_VOL <= 9'sd0; // OFF
|
||||
2: W_VOL <= 9'sd26; // 10%
|
||||
3: W_VOL <= 9'sd52; // 20%
|
||||
4: W_VOL <= 9'sd79; // 30%
|
||||
5: W_VOL <= 9'sd104; // 40%
|
||||
6: W_VOL <= 9'sd130; // 50%
|
||||
7: W_VOL <= 9'sd156; // 60%
|
||||
8: W_VOL <= 9'sd182; // 70%
|
||||
9: W_VOL <= 9'sd208; // 80%
|
||||
10: W_VOL <= 9'sd234; // 90%
|
||||
default: W_VOL <= 9'sd255;
|
||||
endcase
|
||||
|
||||
// Prefetch sample.
|
||||
if (I_H_CNT == {I_DMA_CHAN,1'b1}) begin
|
||||
W_DMA_DATA <= I_DMA_DATA * W_VOL;
|
||||
end
|
||||
|
||||
sample <= (sample == I_DIV-1) ? 1'b0 : sample + 1'b1;
|
||||
|
||||
if (sample == I_DIV-1) begin
|
||||
W_SAMPL <= W_DMA_DATA[23:8];
|
||||
W_DMA_ADDR <= W_DMA_ADDR + 1'd1;
|
||||
W_DMA_CNT <= W_DMA_CNT + 1'd1;
|
||||
W_DMA_EN <= (W_DMA_CNT==I_DMA_LEN) || I_DMA_STOP ? 1'b0 : 1'b1;
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
W_DMA_ADDR <= 0;
|
||||
W_SAMPL <= 0;
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
assign O_DMA_ADDR = W_DMA_ADDR;
|
||||
assign O_SND = W_SAMPL;
|
||||
|
||||
endmodule
|
||||
BIN
Arcade_MiST/Nintendo Mario Bros/rtl/rom/samp.bin
Normal file
BIN
Arcade_MiST/Nintendo Mario Bros/rtl/rom/samp.bin
Normal file
Binary file not shown.
@ -232,10 +232,11 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(MrDo_mist)
|
||||
# ---------------------
|
||||
# ---------------------
|
||||
set_global_assignment -name SDC_FILE MrDo.sdc
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
136
Arcade_MiST/Universal MrDo/MrDo.sdc
Normal file
136
Arcade_MiST/Universal MrDo/MrDo.sdc
Normal file
@ -0,0 +1,136 @@
|
||||
## Generated SDC file "vectrex_MiST.out.sdc"
|
||||
|
||||
## Copyright (C) 1991-2013 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
|
||||
|
||||
## DATE "Sun Jun 24 12:53:00 2018"
|
||||
|
||||
##
|
||||
## DEVICE "EP3C25E144C8"
|
||||
##
|
||||
|
||||
# Clock constraints
|
||||
|
||||
# Automatically constrain PLL and other generated clocks
|
||||
derive_pll_clocks -create_base_clocks
|
||||
|
||||
# Automatically calculate clock uncertainty to jitter and other effects.
|
||||
derive_clock_uncertainty
|
||||
|
||||
# tsu/th constraints
|
||||
|
||||
# tco constraints
|
||||
|
||||
# tpd constraints
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
|
||||
|
||||
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
|
||||
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
|
||||
set clk_10M "pll|altpll_component|auto_generated|pll1|clk[1]"
|
||||
set clk_8M "pll|altpll_component|auto_generated|pll1|clk[2]"
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
create_generated_clock -name clk_5M -source $clk_10M -divide_by 2 [get_registers clk_5M]
|
||||
create_generated_clock -name clk_4M -source $clk_8M -divide_by 2 [get_registers clk_4M]
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
|
||||
|
||||
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
|
||||
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
|
||||
|
||||
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
set_multicycle_path -to {VGA_*[*]} -setup 2
|
||||
set_multicycle_path -to {VGA_*[*]} -hold 1
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
Binary file not shown.
@ -31,7 +31,7 @@ module MrDo_mist (
|
||||
`include "rtl\build_id.v"
|
||||
|
||||
localparam CONF_STR = {
|
||||
"MRDO;;",
|
||||
"MRDO;rom;",
|
||||
"O2,Rotate Controls,Off,On;",
|
||||
"O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
|
||||
"O5,Blend,Off,On;",
|
||||
@ -59,17 +59,19 @@ wire [1:0] Lives = status[13:12];
|
||||
|
||||
assign LED = ~ioctl_downl;
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
assign SDRAM_CLK = ~clock_49;
|
||||
assign SDRAM_CLK = sys_clk;
|
||||
assign SDRAM_CKE = 1;
|
||||
|
||||
wire clock_98, clock_49, pll_locked;
|
||||
pll pll(
|
||||
wire sys_clk, clk_10M, clk_8M, pll_locked;
|
||||
|
||||
pll pll(
|
||||
.inclk0(CLOCK_27),
|
||||
.c0(clock_98),
|
||||
.c1(clock_49),
|
||||
.c0(sys_clk),
|
||||
.c1(clk_10M),
|
||||
.c2(clk_8M),
|
||||
.locked(pll_locked)
|
||||
);
|
||||
|
||||
|
||||
wire [31:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
@ -94,7 +96,7 @@ wire key_pressed;
|
||||
wire [7:0] key_code;
|
||||
|
||||
data_io data_io(
|
||||
.clk_sys ( clock_49 ),
|
||||
.clk_sys ( sys_clk ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS2 ( SPI_SS2 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
@ -110,7 +112,7 @@ reg port1_req;
|
||||
sdram #(.MHZ(49)) sdram(
|
||||
.*,
|
||||
.init_n ( pll_locked ),
|
||||
.clk ( clock_49 ),
|
||||
.clk ( sys_clk ),
|
||||
|
||||
// ROM upload
|
||||
.port1_req ( port1_req ),
|
||||
@ -126,7 +128,7 @@ sdram #(.MHZ(49)) sdram(
|
||||
.cpu1_q ( rom_do )
|
||||
);
|
||||
|
||||
always @(posedge clock_49) begin
|
||||
always @(posedge sys_clk) begin
|
||||
reg ioctl_wr_last = 0;
|
||||
|
||||
ioctl_wr_last <= ioctl_wr;
|
||||
@ -137,7 +139,7 @@ end
|
||||
|
||||
reg reset = 1;
|
||||
reg rom_loaded = 0;
|
||||
always @(posedge clock_49) begin
|
||||
always @(posedge sys_clk) begin
|
||||
reg ioctl_downlD;
|
||||
ioctl_downlD <= ioctl_downl;
|
||||
|
||||
@ -146,9 +148,8 @@ always @(posedge clock_49) begin
|
||||
end
|
||||
|
||||
MrDo_top MrDo_top(
|
||||
.clk_98M(clock_98),
|
||||
.clk_20M(),
|
||||
.clk_8M(),
|
||||
.clk_10M(clk_10M),
|
||||
.clk_8M(clk_8M),
|
||||
.reset(reset),
|
||||
.red(r),
|
||||
.green(g),
|
||||
@ -169,7 +170,7 @@ MrDo_top MrDo_top(
|
||||
|
||||
|
||||
mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(11)) mist_video(
|
||||
.clk_sys ( clock_49 ),
|
||||
.clk_sys ( sys_clk ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS3 ( SPI_SS3 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
@ -192,7 +193,7 @@ mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(11)) mist_video(
|
||||
);
|
||||
|
||||
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
|
||||
.clk_sys (clock_49 ),
|
||||
.clk_sys (sys_clk ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
@ -211,7 +212,7 @@ user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
|
||||
);
|
||||
|
||||
dac #(.C_bits(16))dac(
|
||||
.clk_i(clock_49),
|
||||
.clk_i(sys_clk),
|
||||
.res_n_i(1),
|
||||
.dac_i({audio1, audio2}),
|
||||
.dac_o(AUDIO_L)
|
||||
@ -222,7 +223,7 @@ wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D,
|
||||
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
|
||||
|
||||
arcade_inputs inputs (
|
||||
.clk ( clock_49 ),
|
||||
.clk ( sys_clk ),
|
||||
.key_strobe ( key_strobe ),
|
||||
.key_pressed ( key_pressed ),
|
||||
.key_code ( key_code ),
|
||||
|
||||
@ -1,9 +1,6 @@
|
||||
module MrDo_top(
|
||||
input clk_98M,
|
||||
|
||||
//input clk_20M,
|
||||
//input clk_8M,
|
||||
|
||||
input clk_10M,
|
||||
input clk_8M,
|
||||
input reset,
|
||||
output [3:0] red,
|
||||
output [3:0] green,
|
||||
@ -22,70 +19,36 @@ output [14:0] rom_addr,
|
||||
input [7:0] rom_do
|
||||
);
|
||||
|
||||
//divider_by2 gen10(
|
||||
// .out_clk(clk_10M),
|
||||
// .clk(clk_20M),
|
||||
// .rst(reset)
|
||||
//);
|
||||
//
|
||||
//divider_by2 gen5(
|
||||
// .out_clk(clk_5M),
|
||||
// .clk(clk_10M),
|
||||
// .rst(reset)
|
||||
//);
|
||||
//
|
||||
|
||||
always @(posedge clk_10M)
|
||||
begin
|
||||
if (reset)
|
||||
clk_5M <= 1'b0;
|
||||
else
|
||||
clk_5M <= ~clk_5M;
|
||||
end
|
||||
|
||||
//divider_by2 gen4(
|
||||
// .out_clk(clk_4M),
|
||||
// .clk(clk_8M),
|
||||
// .rst(reset)
|
||||
//);
|
||||
|
||||
//fg_ram0 is driven by 5mhz instead of 4mhz??? check schematics!!!
|
||||
|
||||
wire clk_4M, clk_5M, clk_8M, clk_10M;
|
||||
reg [5:0] clk10_count;
|
||||
reg [5:0] clk5_count;
|
||||
reg [5:0] clk8_count;
|
||||
reg [5:0] clk4_count;
|
||||
|
||||
always @ (posedge clk_98M) begin
|
||||
if ( reset == 1 ) begin
|
||||
clk10_count <= 0;
|
||||
clk8_count <= 0;
|
||||
clk5_count <= 0;
|
||||
clk4_count <= 0;
|
||||
|
||||
end else begin
|
||||
if ( clk10_count == 4 ) begin
|
||||
clk10_count <= 0;
|
||||
clk_10M <= ~ clk_10M ;
|
||||
end else begin
|
||||
clk10_count <= clk10_count + 1;
|
||||
end
|
||||
|
||||
if ( clk8_count == 5 ) begin
|
||||
clk8_count <= 0;
|
||||
clk_8M <= ~ clk_8M ;
|
||||
end else begin
|
||||
clk8_count <= clk8_count + 1;
|
||||
end
|
||||
|
||||
if ( clk5_count == 9 ) begin
|
||||
clk5_count <= 0;
|
||||
clk_5M <= ~ clk_5M ;
|
||||
end else begin
|
||||
clk5_count <= clk5_count + 1;
|
||||
end
|
||||
|
||||
if ( clk4_count == 11 ) begin
|
||||
clk4_count <= 0;
|
||||
clk_4M <= ~ clk_4M ;
|
||||
end else begin
|
||||
clk4_count <= clk4_count + 1;
|
||||
end
|
||||
end
|
||||
always @(posedge clk_8M)
|
||||
begin
|
||||
if (reset)
|
||||
clk_4M <= 1'b0;
|
||||
else
|
||||
clk_4M <= ~clk_4M;
|
||||
end
|
||||
|
||||
reg clk_4M, clk_5M;
|
||||
|
||||
wire hff;
|
||||
reg [7:0]v;
|
||||
reg [7:0]h;
|
||||
@ -702,7 +665,7 @@ always @ (posedge clk_4M ) begin
|
||||
// cpu tries to read val from 0x9803 which is state machine pal
|
||||
// written to on all tile ram access. should try converting pal logic to verilog.
|
||||
cpu_din <= 0;
|
||||
else*/ if ( cpu_addr >= 16'h0000 && cpu_addr < 16'h8000 )
|
||||
else */if ( cpu_addr >= 16'h0000 && cpu_addr < 16'h8000 )
|
||||
cpu_din <= rom_do;
|
||||
else if ( cpu_addr >= 16'h8000 && cpu_addr < 16'h8400 )
|
||||
cpu_din <= bg_ram0_data;
|
||||
@ -846,7 +809,7 @@ cpu_ram cpu_ram_inst (
|
||||
|
||||
// foreground tile attributes
|
||||
ram_dp_1k gfx_fg_ram0_inst (
|
||||
.clock_a ( ~clk_5M ),
|
||||
.clock_a ( ~clk_4M ),
|
||||
.address_a ( cpu_addr[9:0] ),
|
||||
.data_a ( cpu_dout ),
|
||||
.wren_a ( gfx_fg_ram0_wr ),
|
||||
@ -929,13 +892,13 @@ ram_dp_1k spr_ram (
|
||||
|
||||
// FG Roms
|
||||
fg1_rom fg1_rom(
|
||||
.clk(~clk_10M),
|
||||
.clk(clk_10M),
|
||||
.addr(fg_bitmap_addr),
|
||||
.data(s8_data)
|
||||
);
|
||||
|
||||
fg2_rom fg2_rom(
|
||||
.clk(~clk_10M),
|
||||
.clk(clk_10M),
|
||||
.addr(fg_bitmap_addr),
|
||||
.data(u8_data)
|
||||
);
|
||||
|
||||
4
Arcade_MiST/Universal MrDo/rtl/pll.qip
Normal file
4
Arcade_MiST/Universal MrDo/rtl/pll.qip
Normal file
@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
||||
@ -40,26 +40,30 @@ module pll (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
locked);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output c2;
|
||||
output locked;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire [0:0] sub_wire7 = 1'h0;
|
||||
wire [2:2] sub_wire4 = sub_wire0[2:2];
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
wire c2 = sub_wire4;
|
||||
wire sub_wire5 = inclk0;
|
||||
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire5),
|
||||
.inclk (sub_wire6),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.activeclock (),
|
||||
@ -100,12 +104,16 @@ module pll (
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 27,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 98,
|
||||
altpll_component.clk0_multiply_by = 40,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 27,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 49,
|
||||
altpll_component.clk1_multiply_by = 10,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.clk2_divide_by = 27,
|
||||
altpll_component.clk2_duty_cycle = 50,
|
||||
altpll_component.clk2_multiply_by = 8,
|
||||
altpll_component.clk2_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
@ -140,7 +148,7 @@ module pll (
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk2 = "PORT_USED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
@ -181,10 +189,13 @@ endmodule
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "98.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "49.000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "10.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "8.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
@ -206,25 +217,33 @@ endmodule
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "98"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "49"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "40"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "10"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "98.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "49.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "10.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "8.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
@ -248,25 +267,32 @@ endmodule
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "98"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "40"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "49"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "10"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
@ -300,7 +326,7 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
@ -319,12 +345,14 @@ endmodule
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user