github.com/Gehstock.Mist_FPGA
1
0
Fork 0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-20 17:47:33 +00:00
Code Issues Releases Wiki Activity

Qbert: gate bgram write

Browse Source
This commit is contained in:
Gyorgy Szombathelyi 2022-01-29 21:02:52 +01:00
parent 9e0511234c
commit 58aacfd5fc
2 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Arcade_MiST/Gottlieb Qbert/rtl/Qbert_MiST.sv
View File

@ -453,6 +453,7 @@ mylstar_board mylstar_board
.rom_init_address(ioctl_addr),
.rom_init_data(ioctl_dout),
.nvram_data(ioctl_din),
.bgram(core_mod == mod_krull),
.vflip(flip),
.hflip(flip),

3
Arcade_MiST/Gottlieb Qbert/rtl/mylstar_board.v
View File

@ -34,6 +34,7 @@ module mylstar_board
input [17:0] rom_init_address,
input [7:0] rom_init_data,
output [7:0] nvram_data,
input bgram, // E11-12 writeable
input vflip,
input hflip,
@ -722,7 +723,7 @@ dpram #(.addr_width(13),.data_width(8)) E11_12 (
.ce(1'b0),
//.ce(L10_Q1),
.oe(1'b0),
.we(rom_init ? rom_init_address < 18'h10000 : ~nBOJRWR),
.we(rom_init ? rom_init_address < 18'h10000 : bgram & ~nBOJRWR),
.waddr(rom_init ? rom_init_address : addr[12:0]),
.wdata(rom_init ? rom_init_data : cpu_dout),
.doutb(BGRAMROM_Q)