github.com/Gehstock.Mist_FPGA
1
0
Fork 0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-18 00:52:09 +00:00
Code Issues Releases Wiki Activity

MiST: simplify data_io a bit

Browse Source
This commit is contained in:
Gyorgy Szombathelyi 2020-12-11 01:08:21 +01:00
parent bec9ee23f9
commit 5b8795a621
1 changed files with 46 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

92
common/mist/data_io.v
View File

@ -73,19 +73,17 @@ always@(negedge SPI_SCK or posedge SPI_SS2) begin : SPI_TRANSMITTER
if(SPI_SS2) begin
SPI_DO <= 1'bZ;
end else begin
if (cnt == 15) dout_r <= ioctl_din;
SPI_DO <= dout_r[~cnt[2:0]];
{SPI_DO, dout_r} <= (cnt == 15) ? {dout_r[7], ioctl_din} : {dout_r, 1'b0};
end
end
reg [7:0] cmd;
reg [3:0] cnt;
reg [5:0] bytecnt;
always@(posedge SPI_SCK, posedge SPI_SS2) begin : SPI_RECEIVER
reg [6:0] sbuf;
reg [24:0] addr;
reg [7:0] cmd;
reg [5:0] bytecnt;
if(SPI_SS2) begin
bytecnt <= 0;
@ -102,52 +100,53 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin : SPI_RECEIVER
// finished command byte
if(cnt == 7) cmd <= {sbuf, SPI_DI};
// prepare/end transmission
if((cmd == DIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
addr_reset <= ~addr_reset;
downloading_reg <= 1;
end else begin
downloading_reg <= 0;
if(cnt == 15) begin
case (cmd)
// prepare/end transmission
DIO_FILE_TX: begin
// prepare
if(SPI_DI) begin
addr_reset <= ~addr_reset;
downloading_reg <= 1;
end else begin
downloading_reg <= 0;
end
end
end
if((cmd == DIO_FILE_RX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
addr_reset <= ~addr_reset;
uploading_reg <= 1;
end else begin
uploading_reg <= 0;
DIO_FILE_RX: begin
// prepare
if(SPI_DI) begin
addr_reset <= ~addr_reset;
uploading_reg <= 1;
end else begin
uploading_reg <= 0;
end
end
end
// command 0x54: UIO_FILE_TX
if((cmd == DIO_FILE_TX_DAT) && (cnt == 15)) begin
data_w <= {sbuf, SPI_DI};
rclk <= ~rclk;
end
// command 0x57: DIO_FILE_RX_DAT
// command 0x54: DIO_FILE_TX_DAT
DIO_FILE_RX_DAT,
DIO_FILE_TX_DAT: begin
data_w <= {sbuf, SPI_DI};
rclk <= ~rclk;
end
// command 0x57: UIO_FILE_RX
if((cmd == DIO_FILE_RX_DAT) && (cnt == 15)) begin
rclk <= ~rclk;
end
// expose file (menu) index
DIO_FILE_INDEX: ioctl_index <= {sbuf, SPI_DI};
// expose file (menu) index
if((cmd == DIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
// receiving FAT directory entry (mist-firmware/fat.h - DIRENTRY)
if((cmd == DIO_FILE_INFO) && (cnt == 15)) begin
bytecnt <= bytecnt + 1'd1;
case (bytecnt)
8'h08: ioctl_fileext[23:16] <= {sbuf, SPI_DI};
8'h09: ioctl_fileext[15: 8] <= {sbuf, SPI_DI};
8'h0A: ioctl_fileext[ 7: 0] <= {sbuf, SPI_DI};
8'h1C: ioctl_filesize[ 7: 0] <= {sbuf, SPI_DI};
8'h1D: ioctl_filesize[15: 8] <= {sbuf, SPI_DI};
8'h1E: ioctl_filesize[23:16] <= {sbuf, SPI_DI};
8'h1F: ioctl_filesize[31:24] <= {sbuf, SPI_DI};
// receiving FAT directory entry (mist-firmware/fat.h - DIRENTRY)
DIO_FILE_INFO: begin
bytecnt <= bytecnt + 1'd1;
case (bytecnt)
8'h08: ioctl_fileext[23:16] <= {sbuf, SPI_DI};
8'h09: ioctl_fileext[15: 8] <= {sbuf, SPI_DI};
8'h0A: ioctl_fileext[ 7: 0] <= {sbuf, SPI_DI};
8'h1C: ioctl_filesize[ 7: 0] <= {sbuf, SPI_DI};
8'h1D: ioctl_filesize[15: 8] <= {sbuf, SPI_DI};
8'h1E: ioctl_filesize[23:16] <= {sbuf, SPI_DI};
8'h1F: ioctl_filesize[31:24] <= {sbuf, SPI_DI};
endcase
end
endcase
end
end
@ -244,8 +243,9 @@ always@(posedge clk_sys) begin : DATA_OUT
// detect new byte from the SPI receiver
if (rclkD ^ rclkD2) begin
wr_int <= downloading_reg;
if (uploading_reg) rd_int <= uploading_reg;
rd_int <= uploading_reg;
end
// direct transfer receiver
if (rclk2D ^ rclk2D2 && filepos != ioctl_filesize) begin
filepos <= filepos + 1'd1;
wr_int_direct <= 1;