mirror of
https://github.com/Gehstock/Mist_FPGA.git
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Merge pull request #108 from gyurco/master
DK: Radar Scope + Pest Place
This commit is contained in:
Marcel
GitHub
commit
6023966acb
@ -230,7 +230,7 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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# end ENTITY(dkong_MiST)
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# ----------------------
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/dl.stp
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/stars.stp
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/dkong_MiST.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
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set_global_assignment -name VERILOG_FILE rtl/dkong_top.v
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@ -247,10 +247,12 @@ set_global_assignment -name VERILOG_FILE rtl/dkong_hv_count.v
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set_global_assignment -name VERILOG_FILE rtl/dkong_col_pal.v
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set_global_assignment -name VERILOG_FILE rtl/dkong_bram.v
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set_global_assignment -name VERILOG_FILE rtl/dkong_adec.v
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set_global_assignment -name VERILOG_FILE rtl/radarscp_stars.v
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name QIP_FILE ../../../common/CPU/t48/T48.qip
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set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
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set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
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set_global_assignment -name SIGNALTAP_FILE output_files/dkong.stp
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set_global_assignment -name SIGNALTAP_FILE output_files/dl.stp
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set_global_assignment -name SIGNALTAP_FILE output_files/stars.stp
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -0,0 +1,33 @@
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---------------------------------------------------------------------------------
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--
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-- Arcade: Donkey Kong port to MiST
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-- Jan 2021
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--
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-- Usage:
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-- - Create ROM and ARC files from the MRA files using the MRA utility.
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-- Example: mra -A -z /path/to/mame/roms "Donkey Kong.mra"
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-- - Copy the ROM files to the root of the SD Card
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-- - Copy the RBF and ARC files to the same folder on the SD Card
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--
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-- Bugs/limitations:
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-- - Some sounds are missing in some games
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-- - Grid drawing delay is not implemented in Radar Scope
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--
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---------------------------------------------------------------------------------
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-- Based on:
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-- FPGA DONKEY KONG TOP
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-- Version : 4.00
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-- Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
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---------------------------------------------------------------------------------
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--
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--
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-- Keyboard inputs :
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--
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-- ESC,5 : Coin
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-- F2,2 : Start 2 players
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-- F1,1 : Start 1 player
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-- UP,DOWN,LEFT,RIGHT arrows : Movements
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-- CTRL : Jump/Fire
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-- Joystick support.
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---------------------------------------------------------------------------------
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@ -0,0 +1,51 @@
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<misterromdescription>
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<name>Pest Place</name>
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<mameversion>0217</mameversion>
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<setname>pestplce</setname>
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<mratimestamp>201912300000</mratimestamp>
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<year>1982</year>
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<manufacturer>Nintendo of America</manufacturer>
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<category>Maze / Monkeys</category>
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<category>Platform</category>
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<category>Platform / Mario Bros.</category>
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<rbf>dkong</rbf>
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<buttons names="Jump,Start 1P,Start 2P,Coin" default="A,Start,Select,R" />
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<switches default="80" base="8">
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<dip bits="0,1" name="Lives" ids="3,4,5,6"/>
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<dip bits="2,3" name="Bonus" ids="10k,15k,20k,25k"/>
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<dip bits="4,6" name="Coins" ids="1C1P,2C1P,1C1P,3C1P,1C1P,4C1P,1C1P,5C1P,1C1P"/>
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<dip bits="7" name="Lives" ids="Cocktail,Upright"/>
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</switches>
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<rom index="1"><part>09</part></rom>
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<rom index="0" zip="pestplce.zip" md5="48576fcf2767241441d662768cc53899" type="merged|nonmerged">
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<!-- Main CPU 32k-->
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<part name="pest.1p"/>
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<part name="pest.2p"/>
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<part name="pest.3p"/>
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<part name="pest.0"/>
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<part name="pest.0"/>
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<!-- GFX1 8k-->
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<part name="pest.o"/>
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<part name="pest.k"/>
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<!-- GFX2 16k-->
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<part name="pest.b"/>
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<part name="pest.a"/>
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<part name="pest.d"/>
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<part name="pest.c"/>
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<!-- Sound CPU 4k-->
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<part name="pest.4"/>
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<!-- LUTs -->
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<part name="n82s129a.bin"/>
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<part name="n82s129a.bin"/>
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<part name="n82s129b.bin"/>
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<part name="n82s129b.bin"/>
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<part repeat="3072">00</part>
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</rom>
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</misterromdescription>
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File diff suppressed because it is too large
Load Diff
@ -44,6 +44,8 @@ wire rotate = status[2];
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wire [1:0] scanlines = status[4:3];
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wire blend = status[5];
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wire landscape = core_mod[3];
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assign LED = ~ioctl_downl;
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assign AUDIO_R = AUDIO_L;
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assign SDRAM_CLK = clock_24;
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@ -160,6 +162,8 @@ dkong_top dkong(
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.I_DIP_SW(status[15:8]),
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.I_DKJR(core_mod[0]),
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.I_DK3B(core_mod[1]),
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.I_RADARSCP(core_mod[2]),
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.I_PESTPLCE(core_mod[3]),
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.O_SOUND_DAT(audio),
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.O_VGA_R(r),
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.O_VGA_G(g),
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@ -262,7 +266,7 @@ arcade_inputs inputs (
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.joystick_0 ( joystick_0 ),
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.joystick_1 ( joystick_1 ),
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.rotate ( rotate ),
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.orientation ( 2'b11 ),
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.orientation ( {1'b1, ~landscape} ),
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.joyswap ( 1'b0 ),
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.oneplayer ( 1'b1 ),
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.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
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@ -25,6 +25,7 @@ I_CLK_EN_N,
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I_RESET_n,
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I_DKJR,
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I_DK3B,
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I_PESTPLCE,
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I_AB,
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I_DB,
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I_MREQ_n,
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@ -55,7 +56,8 @@ O_DIP_OE_n,
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O_4H_Q,
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O_5H_Q,
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O_6H_Q,
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O_3D_Q
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O_3D_Q,
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O_AREF
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);
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@ -65,6 +67,7 @@ input I_CLK_EN_N;
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input I_RESET_n;
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input I_DKJR;
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input I_DK3B;
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input I_PESTPLCE;
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input [15:0]I_AB;
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input [3:0]I_DB;
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input I_MREQ_n;
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@ -94,6 +97,7 @@ output [1:0]O_4H_Q; // GFX (Characters) bank switch, sound
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output [7:0]O_5H_Q; // FLIP,
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output [7:0]O_6H_Q; // sound
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output [4:0]O_3D_Q; // sound
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output [2:0]O_AREF; // 7C80 H Radar Scope grid color (W)
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output O_WAIT_n;
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output O_NMI_n;
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@ -152,7 +156,7 @@ logic_74xx138 U_4D(
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);
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assign O_ROM_CS_n = I_DKJR ? (&W_4D_Q[5:0] & (!I_DK3B | !(I_AB[15:12] == 4'h9 | I_AB[15:12] == 4'hD))) : &W_4D_Q[3:0];
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assign O_ROM_CS_n = I_DKJR ? (&W_4D_Q[5:0] & (!I_PESTPLCE | I_AB[15:12] != 4'hB) & (!I_DK3B | !(I_AB[15:12] == 4'h9 | I_AB[15:12] == 4'hD))) : &W_4D_Q[3:0];
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// ADDR DEC 7000H - 7FFFH
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@ -321,16 +325,24 @@ assign O_6H_Q = W_6H_Q;
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// Parts 3D
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reg [4:0]O_3D_Q;
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reg [2:0]W_AREF;
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assign O_AREF = W_AREF;
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always@(posedge I_CLK24M or negedge I_RESET_n)
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begin
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reg W_1C_Q0_D;
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if(! I_RESET_n) O_3D_Q <= 0;
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else begin
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reg W_1C_Q0_D, W_1C_Q1_D;
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if(! I_RESET_n) begin
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O_3D_Q <= 0;
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W_AREF <= 0;
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end else begin
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W_1C_Q0_D <= W_1C_Q[0];
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W_1C_Q1_D <= W_1C_Q[1];
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if (!W_1C_Q0_D & W_1C_Q[0]) begin
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O_3D_Q <= I_DB;
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end
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if (!W_1C_Q1_D & W_1C_Q[1]) begin
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W_AREF <= I_DB[2:0];
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end
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end
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end
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@ -18,6 +18,7 @@ module dkong_col_pal(
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input CLK_24M,
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input CLK_6M_EN,
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input I_DK3B,
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input I_PESTPLCE,
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input I_PALBNK,
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input [5:0]I_VRAM_D,
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input [5:0]I_OBJ_D,
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@ -86,8 +87,8 @@ dpram #(9,8) col2 (
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);
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//assign {O_R, O_G, O_B} = I_DK3B ? {W_2F_DO, W_2E_DO} : ~{W_2F_DO[3:1], W_2F_DO[3], ~W_2E_DO};
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assign O_R = I_DK3B ? W_2F_DO[7:4] : ~{W_2F_DO[3:1], W_2F_DO[3]};
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assign O_G = I_DK3B ? W_2F_DO[3:0] : ~{W_2F_DO[0], W_2E_DO[3:2], W_2F_DO[0]};
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assign O_B = I_DK3B ? W_2E_DO[3:0] : ~{W_2E_DO[1:0], W_2E_DO[1:0]};
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assign O_R = I_DK3B ? W_2F_DO[7:4] : {4{I_PESTPLCE}} ^ ~{W_2F_DO[3:1], W_2F_DO[3]};
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assign O_G = I_DK3B ? W_2F_DO[3:0] : {4{I_PESTPLCE}} ^ ~{W_2F_DO[0], W_2E_DO[3:2], W_2F_DO[0]};
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assign O_B = I_DK3B ? W_2E_DO[3:0] : {4{I_PESTPLCE}} ^ ~{W_2E_DO[1:0], W_2E_DO[1:0]};
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endmodule
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@ -31,6 +31,7 @@ module dkong_obj(
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input CLK_24M,
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input CLK_12M,
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input CLK_12M_EN,
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input I_PESTPLCE,
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input [9:0] I_AB,
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// input [7:0] I_DB,
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input [7:0] I_OBJ_D,
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@ -170,8 +171,9 @@ always@(posedge W_5F2_Q[0]) W_8H_Q <= W_8H_D;
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reg [7:0]W_6J_Q;
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always@(posedge W_5F2_Q[2]) W_6J_Q <= W_HD[7:0];
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wire [7:0]W_6K_D = {W_6J_Q[7],I_CMPBLKn,~I_H_CNT[9],
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~(I_H_CNT[9]|W_FLIP_2),W_6J_Q[3:0]};
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wire [7:0]W_6K_D = !I_PESTPLCE ?
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{W_6J_Q[7],I_CMPBLKn,~I_H_CNT[9],~(I_H_CNT[9]|W_FLIP_2),W_6J_Q[3:0]} :
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{W_6H_Q[7],I_CMPBLKn,~I_H_CNT[9],~(I_H_CNT[9]|W_FLIP_2),W_6H_Q[3:0]};
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reg [7:0]W_6K_Q;
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always@(posedge CLK_24M)
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@ -309,8 +311,9 @@ begin
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O_OBJ_DO <= O_OBJ_DO ;
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end
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wire [11:0]W_ROM_OBJ_AB = {W_6J_Q[6],W_6H_Q[6:0],W_8H_Q[3:0]^{W_6H_Q[7],W_6H_Q[7],W_6H_Q[7],W_6H_Q[7]}};
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wire [11:0]W_ROM_OBJ_AB = !I_PESTPLCE ?
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{W_6J_Q[6],W_6H_Q[6:0],W_8H_Q[3:0]^{{4{W_6H_Q[7]}}}} :
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{W_6J_Q[7:0],W_8H_Q[3:0]^{4{W_6H_Q[6]}}};
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wire [7:0]W_OBJ_DO_7C,W_OBJ_DO_7D,W_OBJ_DO_7E,W_OBJ_DO_7F;
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@ -10,6 +10,7 @@ module dkong_soundboard(
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input [1:0] W_4H_Q,
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input [4:0] W_3D_Q,
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output [15:0] O_SOUND_DAT,
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output O_SACK,
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output [11:0] ROM_A,
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input [7:0] ROM_D,
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output [18:0] WAV_ROM_A,
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@ -60,6 +61,7 @@ I8035IP SOUND_CPU
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.I_P2(I8035_PBO),
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.O_P2(I8035_PBI)
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);
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assign O_SACK = I8035_PBI[4];
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//-------------------------------------------------
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dkong_sound Digtal_sound
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@ -37,6 +37,8 @@ module dkong_top
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input [7:0] I_DIP_SW,
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input I_DKJR,
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input I_DK3B,
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input I_RADARSCP,
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input I_PESTPLCE,
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// VGA (VIDEO) IF
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output [3:0]O_VGA_R,
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@ -96,7 +98,7 @@ wire W_SW2_OEn ;
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wire W_SW3_OEn ;
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wire W_DIP_OEn ;
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wire [1:0]W_4H_Q;
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wire [2:0]W_4H_Q;
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wire [7:0]W_5H_Q;
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wire [7:0]W_6H_Q;
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wire [4:0]W_3D_Q;
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@ -187,6 +189,9 @@ always @(*) begin
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6'h07: MAIN_CPU_A = {5'h03,W_CPU_A[10:0]}; // 0x3800-0x3FFF -> 0x1800-0x1FFF in ROM file
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6'h09: MAIN_CPU_A = {5'h05,W_CPU_A[10:0]}; // 0x4800-0x4FFF -> 0x2800-0x2FFF in ROM file
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6'h0B: MAIN_CPU_A = {5'h07,W_CPU_A[10:0]}; // 0x5800-0x5FFF -> 0x3800-0x3FFF in ROM file
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//pestplace
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6'h16: MAIN_CPU_A = {5'h0C,W_CPU_A[10:0]}; // 0xB000-0xB7FF -> 0x6000-0x6FFF in ROM file
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6'h17: MAIN_CPU_A = {5'h0D,W_CPU_A[10:0]}; // 0xB800-0xBFFF -> 0x6000-0x6FFF in ROM file
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// dkong3b
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6'h12: MAIN_CPU_A = {5'h0C,W_CPU_A[10:0]}; // 0x9000-0x97FF -> 0x6000-0x6FFF in ROM file
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6'h13: MAIN_CPU_A = {5'h0D,W_CPU_A[10:0]}; // 0x9800-0x9FFF -> 0x6000-0x6FFF in ROM file
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@ -294,9 +299,10 @@ ram_1024_8_8 U_6PR
|
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);
|
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|
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//=========== SW Interface ========================================================
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wire W_SACK;
|
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wire [7:0]W_SW1 = W_SW1_OEn ? 8'h00: ~{1'b1,1'b1,1'b1,I_J1,I_D1,I_U1,I_L1,I_R1};
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wire [7:0]W_SW2 = W_SW2_OEn ? 8'h00: ~{1'b1,1'b1,1'b1,I_J2,I_D2,I_U2,I_L2,I_R2};
|
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wire [7:0]W_SW3 = W_SW3_OEn ? 8'h00: ~{I_C1,1'b1,1'b1,1'b1,I_S2,I_S1,1'b1,1'b1};
|
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wire [7:0]W_SW3 = W_SW3_OEn ? 8'h00: ~{I_C1,~I_RADARSCP | W_SACK,1'b1,1'b1,I_S2,I_S1,1'b1,1'b1};
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wire [7:0]W_DIP = W_DIP_OEn ? 8'h00: I_DIP_SW;
|
||||
|
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|
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@ -312,6 +318,7 @@ dkong_adec adec
|
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.I_RESET_n(W_RESETn),
|
||||
.I_DKJR(I_DKJR),
|
||||
.I_DK3B(I_DK3B),
|
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.I_PESTPLCE(I_PESTPLCE),
|
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.I_AB(W_CPU_A),
|
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.I_DB(WI_D),
|
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.I_MREQ_n(W_CPU_MREQn),
|
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@ -341,10 +348,12 @@ dkong_adec adec
|
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.O_4H_Q(W_4H_Q),
|
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.O_5H_Q(W_5H_Q),
|
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.O_6H_Q(W_6H_Q),
|
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.O_3D_Q(W_3D_Q)
|
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.O_3D_Q(W_3D_Q),
|
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.O_AREF(W_AREF)
|
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);
|
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|
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wire W_FLIPn = W_5H_Q[2];
|
||||
wire W_DISPLAY = W_5H_Q[1]; // radar enable
|
||||
wire W_FLIPn = I_PESTPLCE ^ W_5H_Q[2];
|
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wire W_2PSL = W_5H_Q[3];
|
||||
wire W_DREQ = W_5H_Q[5]; // DMA Trigger
|
||||
|
||||
@ -387,6 +396,7 @@ dkong_obj obj
|
||||
.CLK_24M(W_CLK_24576M),
|
||||
.CLK_12M(WB_CLK_12288M),
|
||||
.CLK_12M_EN(W_CLK_12288M_EN),
|
||||
.I_PESTPLCE(I_PESTPLCE),
|
||||
.I_AB(),
|
||||
.I_DB(/*W_2N_DO*/),
|
||||
.I_OBJ_D(W_OBJ_DI),
|
||||
@ -435,7 +445,44 @@ dkong_vram vram
|
||||
.DL_DATA(DL_DATA)
|
||||
);
|
||||
|
||||
wire W_RADARn;
|
||||
wire W_STARn;
|
||||
wire W_NOISE;
|
||||
wire W_DISPLAY_O;
|
||||
|
||||
radarscp_stars rstars
|
||||
(
|
||||
.CLK_24M(W_CLK_24576M),
|
||||
.CLK_EN(W_CLK_12288M),
|
||||
.RESETn(W_RESETn),
|
||||
.O_RADARn(W_RADARn),
|
||||
.O_STARn(W_STARn),
|
||||
.O_NOISE(W_NOISE),
|
||||
.O_DISPLAY(W_DISPLAY_O),
|
||||
.I_DISPLAY(W_DISPLAY),
|
||||
.I_VBLKn(W_V_BLANKn),
|
||||
.I_H_CNT(W_H_CNT),
|
||||
.I_FLIPn(W_FLIPn),
|
||||
.I_SOU2(W_6H_Q[2]),
|
||||
|
||||
.DL_ADDR(DL_ADDR),
|
||||
.DL_WR(DL_WR),
|
||||
.DL_DATA(DL_DATA)
|
||||
);
|
||||
|
||||
assign O_PIX = W_H_CNT[0];
|
||||
wire [3:0] W_RED;
|
||||
wire [3:0] W_GREEN;
|
||||
wire [3:0] W_BLUE;
|
||||
wire [2:0] W_AREF;
|
||||
wire [2:0] W_GRID = {3{W_L_CMPBLKn & W_DISPLAY_O & ~W_RADARn & I_RADARSCP}} & W_AREF;
|
||||
wire W_STAR = W_L_CMPBLKn & W_NOISE & ~W_STARn & I_RADARSCP;
|
||||
wire [4:0] W_RED_TOTAL = W_RED + {W_GRID[0] | W_STAR, 3'b000};
|
||||
wire [4:0] W_GREEN_TOTAL = W_GREEN + {W_GRID[1] & ~W_STAR, 3'b000};
|
||||
wire [4:0] W_BLUE_TOTAL = W_BLUE + {W_GRID[2] & ~W_STAR, I_RADARSCP & W_L_CMPBLKn, I_RADARSCP & W_L_CMPBLKn, 1'b0};
|
||||
assign O_VGA_R = W_RED_TOTAL[4] ? 4'hF : W_RED_TOTAL[3:0];
|
||||
assign O_VGA_G = W_GREEN_TOTAL[4] ? 4'hF : W_GREEN_TOTAL[3:0];
|
||||
assign O_VGA_B = W_BLUE_TOTAL[4] ? 4'hF : W_BLUE_TOTAL[3:0];
|
||||
|
||||
dkong_col_pal cpal
|
||||
(
|
||||
@ -443,14 +490,15 @@ dkong_col_pal cpal
|
||||
.CLK_24M(W_CLK_24576M),
|
||||
.CLK_6M_EN(W_CLK_12288M & !W_H_CNT[0]),
|
||||
.I_DK3B(I_DK3B),
|
||||
.I_PESTPLCE(I_PESTPLCE),
|
||||
.I_VRAM_D({W_VRAM_COL[3:0],W_VRAM_VID[1:0]}),
|
||||
.I_OBJ_D(W_OBJ_DAT),
|
||||
.I_CMPBLKn(W_L_CMPBLKn),
|
||||
.I_5H_Q6(W_5H_Q[6]),
|
||||
.I_5H_Q7(W_5H_Q[7]),
|
||||
.O_R(O_VGA_R),
|
||||
.O_G(O_VGA_G),
|
||||
.O_B(O_VGA_B),
|
||||
.O_R(W_RED),
|
||||
.O_G(W_GREEN),
|
||||
.O_B(W_BLUE),
|
||||
|
||||
.DL_ADDR(DL_ADDR),
|
||||
.DL_WR(DL_WR),
|
||||
@ -462,6 +510,7 @@ dkong_soundboard dkong_soundboard(
|
||||
.W_RESETn(W_RESETn),
|
||||
.I_DKJR(I_DKJR),
|
||||
.O_SOUND_DAT(O_SOUND_DAT),
|
||||
.O_SACK(W_SACK),
|
||||
.W_6H_Q(W_6H_Q),
|
||||
.W_5H_Q0(W_5H_Q[0]),
|
||||
.W_4H_Q(W_4H_Q),
|
||||
|
||||
@ -0,0 +1,110 @@
|
||||
//===============================================================================
|
||||
// FPGA DONKEY KONG Radar Scope grid/star generator
|
||||
//
|
||||
// Version : 1.00
|
||||
//
|
||||
// Copyright(c) 2021 Gyorgy Szombathelyi
|
||||
//
|
||||
// Important !
|
||||
//
|
||||
// This program is freeware for non-commercial use.
|
||||
// An author does no guarantee about this program.
|
||||
// You can use this under your own risk.
|
||||
//
|
||||
//================================================================================
|
||||
//-----------------------------------------------------------------------------------------
|
||||
// H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8],H_CNT[9]
|
||||
// 1/2 H 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H
|
||||
//-----------------------------------------------------------------------------------------
|
||||
|
||||
module radarscp_stars(
|
||||
input CLK_24M,
|
||||
input CLK_EN,
|
||||
input RESETn,
|
||||
output O_RADARn,
|
||||
output O_STARn,
|
||||
output O_NOISE,
|
||||
output O_DISPLAY,
|
||||
input I_DISPLAY,
|
||||
input I_VBLKn,
|
||||
input [9:0] I_H_CNT,
|
||||
input I_FLIPn,
|
||||
input I_SOU2,
|
||||
|
||||
input [15:0] DL_ADDR,
|
||||
input DL_WR,
|
||||
input [7:0] DL_DATA
|
||||
);
|
||||
|
||||
reg [7:0] RADAR_SHIFT;
|
||||
reg [19:0] CNT_30HZ;
|
||||
reg NOISE;
|
||||
reg [15:0] NOISE_LFSR;
|
||||
|
||||
always @(posedge CLK_24M, negedge RESETn) begin
|
||||
if (!RESETn) begin
|
||||
RADAR_SHIFT <= 0;
|
||||
CNT_30HZ <= 0;
|
||||
end else begin
|
||||
CNT_30HZ <= CNT_30HZ + 1'd1;
|
||||
if (CNT_30HZ == 20'd799999) begin
|
||||
RADAR_SHIFT <= {RADAR_SHIFT[6:0], ~^RADAR_SHIFT[7:6]};
|
||||
CNT_30HZ <= 0;
|
||||
|
||||
NOISE_LFSR <= {NOISE_LFSR[14:0], (NOISE ^ NOISE_LFSR[4])};
|
||||
NOISE <= ~NOISE_LFSR[15]; // originally generated on the sound board - used for stars dimming
|
||||
end
|
||||
end
|
||||
end
|
||||
wire W_RFLIP = (RADAR_SHIFT[5] & I_SOU2) ^ I_FLIPn; // does the radar flipping when destroyed
|
||||
|
||||
assign O_DISPLAY = I_DISPLAY; // TODO: grid slow drawing effect
|
||||
|
||||
reg [10:0] STARS_A;
|
||||
wire [7:0] STARS_DO;
|
||||
reg [3:0] W_1E_D;
|
||||
|
||||
assign O_NOISE = NOISE;
|
||||
assign O_STARn = ~(W_1E_D[2] & W_1E_D[1] & W_1E_D[0]);
|
||||
assign O_RADARn = ~(~W_1E_D[2] & W_1E_D[1] & W_1E_D[0]);
|
||||
wire [3:0] W_1E_D_next = { 1'b1, STARS_DO[7], W_1E_D[0], {1'b0, STARS_DO[6:0]} == {I_H_CNT[2], I_H_CNT[9:3]} };
|
||||
|
||||
`ifdef SIM
|
||||
always @(posedge I_H_CNT[0]) begin
|
||||
W_1E_D <= W_1E_D_next;
|
||||
end
|
||||
|
||||
wire W_1G_2E_CLK = ~&W_1E_D[1:0];
|
||||
always @(posedge W_1G_2E_CLK, negedge I_VBLKn) begin
|
||||
if (!I_VBLKn)
|
||||
STARS_A <= {W_RFLIP, 10'd0};
|
||||
else
|
||||
STARS_A <= STARS_A + 1'd1;
|
||||
end
|
||||
`else
|
||||
always @(posedge CLK_24M) begin
|
||||
if (CLK_EN & ~I_H_CNT[0])
|
||||
W_1E_D <= W_1E_D_next;
|
||||
end
|
||||
|
||||
always @(posedge CLK_24M, negedge I_VBLKn) begin
|
||||
if (!I_VBLKn)
|
||||
STARS_A <= 0;
|
||||
else if (CLK_EN) begin
|
||||
if (&W_1E_D[1:0] & ~&W_1E_D_next[1:0]) STARS_A <= {W_RFLIP, STARS_A[9:0] + 1'd1};
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
dpram #(11,8) U_3E (
|
||||
.clock_a(CLK_24M),
|
||||
.address_a(STARS_A),
|
||||
.q_a(STARS_DO),
|
||||
|
||||
.clock_b(CLK_24M),
|
||||
.address_b(DL_ADDR[10:0]),
|
||||
.wren_b(DL_WR && DL_ADDR[15:11] == {4'hF, 1'b1}),
|
||||
.data_b(DL_DATA)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user