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Code Issues Releases Wiki Activity

Demolition Derby: update CTC, common inputs

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This commit is contained in:
Gyorgy Szombathelyi
2020-01-07 07:48:19 +01:00
parent c963036524
commit 62fb051271
6 changed files with 106 additions and 475 deletions
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5
Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/DDerby.qsf
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@@ -41,7 +41,7 @@
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
@@ -225,8 +225,6 @@ set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/DDerby_MiST.sv
set_global_assignment -name VHDL_FILE rtl/dderby.vhd
set_global_assignment -name VHDL_FILE rtl/ctc_counter.vhd
set_global_assignment -name VHDL_FILE rtl/ctc_controler.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/cmos_ram.vhd
set_global_assignment -name VHDL_FILE rtl/rom/dderby_bg_bits_2.vhd
@@ -237,6 +235,7 @@ set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
set_global_assignment -name VHDL_FILE rtl/spinner.vhd
set_global_assignment -name QIP_FILE ../../../common/IO/Z80CTC/z80ctc.qip
set_global_assignment -name VHDL_FILE ../../../common/IO/pia6821.vhd
set_global_assignment -name VHDL_FILE ../../../common/CPU/MC6809/cpu09l_128a.vhd
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip

153
Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/rtl/DDerby_MiST.sv
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@@ -50,7 +50,6 @@ module DDerby_MiST(
localparam CONF_STR = {
"DDERBY;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blend,Off,On;",
"O6,Service,Off,On;",
"O7,Swap Joystick,Off,On;",
@@ -61,6 +60,10 @@ localparam CONF_STR = {
"V,v1.1.",`BUILD_DATE
};
wire rotate = status[2];
wire blend = status[5];
wire service = status[6];
wire joyswap = status[7];
wire players4 = status[8];
wire difficulty = status[9];
wire girl = status[10];
@@ -82,16 +85,20 @@ pll_mist pll(
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joy_0;
wire [7:0] joy_1;
wire [7:0] joy_2;
wire [7:0] joy_3;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire [7:0] joystick_2;
wire [7:0] joystick_3;
wire scandoublerD;
wire ypbpr;
wire [9:0] audio;
wire hs, vs, cs;
wire blankn;
wire [2:0] g, r, b;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
wire [15:0] rom_addr;
wire [15:0] rom_do;
wire [14:0] snd_addr;
@@ -164,8 +171,9 @@ always @(posedge clk_sys) begin
port2_req <= ~port2_req;
end
end
// register for better timings
cpu2_addr <= ioctl_downl ? 16'hffff : (16'h8000 + snd_addr[14:1]);
cpu2_addr <= ioctl_downl ? 16'hffff : {2'b10, snd_addr[14:1]};
end
// reset signal generation
@@ -190,8 +198,8 @@ spinner spinner1 (
.clock_40(clk_sys),
.reset(reset),
.btn_acc(),
.btn_left(m_left1),
.btn_right(m_right1),
.btn_left(m_left),
.btn_right(m_right),
.ctc_zc_to_2(vs),
.spin_angle(wheel1)
);
@@ -242,31 +250,31 @@ dderby dderby(
.tv15Khz_mode(scandoublerD),
.separate_audio(1'b0),
.audio_out(audio),
.coin1(btn_coin),
.coin2(btn_coin),
.coin3(btn_coin),
.coin4(btn_coin),
.coin1(m_coin1),
.coin2(m_coin2),
.coin3(m_coin3),
.coin4(m_coin4),
.start4(btn_four_players),
.start3(btn_three_players),
.start2(btn_two_players),
.start1(btn_one_player),
.start4(m_four_players),
.start3(m_three_players),
.start2(m_two_players),
.start1(m_one_player),
.p1_fire1(m_fire1),
.p1_fire2(m_fire1b),
.p2_fire1(m_fire2),
.p2_fire2(m_fire2b),
.p3_fire1(m_fire3),
.p3_fire2(m_fire3b),
.p4_fire1(m_fire4),
.p4_fire2(m_fire4b),
.p1_fire1(m_fireA),
.p1_fire2(m_fireB),
.p2_fire1(m_fire2A),
.p2_fire2(m_fire2B),
.p3_fire1(m_fire3A),
.p3_fire2(m_fire3B),
.p4_fire1(m_fire4A),
.p4_fire2(m_fire4B),
.wheel1(wheel1),
.wheel2(wheel2),
.wheel3(wheel3),
.wheel4(wheel4),
.service(status[6]),
.service(service),
.dipsw(~{3'b000, girl, 1'b0, difficulty, players4}), // NU, coins/credit, girl, free play, difficulty, 2player
.cpu_rom_addr ( rom_addr ),
.cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
@@ -296,12 +304,12 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.VGA_B ( VGA_B ),
.VGA_VS ( vs_out ),
.VGA_HS ( hs_out ),
.rotate ( {1'b1,status[2]} ),
.rotate ( { 1'b1, rotate } ),
.ce_divider ( 1 ),
.blend ( status[5] ),
.blend ( blend ),
.scandoubler_disable(1),//scandoublerD ),
.no_csync ( 1'b1 ),
.scanlines ( status[4:3] ),
.scanlines ( ),
.ypbpr ( ypbpr )
);
@@ -321,10 +329,10 @@ user_io(
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joy_0 ),
.joystick_1 (joy_1 ),
.joystick_2 (joy_2 ),
.joystick_3 (joy_3 ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.joystick_2 (joystick_2 ),
.joystick_3 (joystick_3 ),
.status (status )
);
@@ -336,63 +344,30 @@ dac #(10) dac(
);
assign AUDIO_R = AUDIO_L;
wire [7:0] joystick_0 = status[7] ? joy_1 : joy_0;
wire [7:0] joystick_1 = status[7] ? joy_0 : joy_1;
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B;
wire m_up3, m_down3, m_left3, m_right3, m_fire3A, m_fire3B;
wire m_up4, m_down4, m_left4, m_right4, m_fire4A, m_fire4B;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
// Rotated Normal
wire m_left1 = btn_left | joystick_0[1];
wire m_right1 = btn_right | joystick_0[0];
wire m_fire1 = btn_fire1 | joystick_0[4];
wire m_fire1b = btn_fire2 | joystick_0[5];
wire m_left2 = joystick_1[1];
wire m_right2 = joystick_1[0];
wire m_fire2 = joystick_1[4];
wire m_fire2b = joystick_1[5];
wire m_left3 = joy_2[1];
wire m_right3 = joy_2[0];
wire m_fire3 = joy_2[4];
wire m_fire3b = joy_2[5];
wire m_left4 = joy_3[1];
wire m_right4 = joy_3[0];
wire m_fire4 = joy_3[4];
wire m_fire4b = joy_3[5];
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_three_players = 0;
reg btn_four_players = 0;
reg btn_left = 0;
reg btn_right = 0;
//reg btn_down = 0;
//reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
//reg btn_fire3 = 0;
reg btn_coin = 0;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
always @(posedge clk_sys) begin
if(key_strobe) begin
case(key_code)
// 'h75: btn_up <= key_pressed; // up
// 'h72: btn_down <= key_pressed; // down
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
'h04: btn_three_players <= key_pressed; // F3
'h0C: btn_four_players <= key_pressed; // F4
// 'h14: btn_fire3 <= key_pressed; // ctrl
'h11: btn_fire2 <= key_pressed; // alt
'h29: btn_fire1 <= key_pressed; // Space
endcase
end
end
arcade_inputs inputs (
.clk ( clk_sys ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.joystick_2 ( joystick_2 ),
.joystick_3 ( joystick_3 ),
.rotate ( 1'b0 ),
.orientation ( 2'b10 ),
.joyswap ( joyswap ),
.oneplayer ( 1'b0 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ),
.player3 ( {m_fire3B, m_fire3A, m_up3, m_down3, m_left3, m_right3} ),
.player4 ( {m_fire4B, m_fire4A, m_up4, m_down4, m_left4, m_right4} )
);
endmodule

106
Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/rtl/ctc_controler.vhd
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@@ -1,106 +0,0 @@
---------------------------------------------------------------------------------
-- Z80-CTC controler by Dar (darfpga@aol.fr) (19/10/2019)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ctc_controler is
port(
clock : in std_logic;
clock_ena : in std_logic;
reset : in std_logic;
d_in : in std_logic_vector( 7 downto 0);
load_data : in std_logic;
int_ack : in std_logic;
int_pulse_0 : in std_logic;
int_pulse_1 : in std_logic;
int_pulse_2 : in std_logic;
int_pulse_3 : in std_logic;
d_out : out std_logic_vector( 7 downto 0);
int_n : out std_logic
);
end ctc_controler;
architecture struct of ctc_controler is
signal int_vector : std_logic_vector(4 downto 0);
signal wait_for_time_constant : std_logic;
signal load_data_r : std_logic; -- make sure load_data toggles to get one new data
signal int_reg_0 : std_logic;
signal int_reg_1 : std_logic;
signal int_reg_2 : std_logic;
signal int_reg_3 : std_logic;
signal int_ack_r : std_logic;
begin
int_n <= '0' when (int_reg_0 or int_reg_1 or int_reg_2 or int_reg_3) = '1' else '1';
d_out <= int_vector & "000" when int_reg_0 = '1' else
int_vector & "010" when int_reg_1 = '1' else
int_vector & "100" when int_reg_2 = '1' else
int_vector & "110" when int_reg_3 = '1' else (others => '0');
process (reset, clock)
begin
if reset = '1' then -- hardware and software reset
wait_for_time_constant <= '0';
int_reg_0 <= '0';
int_reg_1 <= '0';
int_reg_2 <= '0';
int_reg_3 <= '0';
load_data_r <= load_data;
int_vector <= (others => '0');
else
if rising_edge(clock) then
if clock_ena = '1' then
load_data_r <= load_data;
int_ack_r <= int_ack;
if load_data = '1' and load_data_r = '0' then
if wait_for_time_constant = '1' then
wait_for_time_constant <= '0';
else
if d_in(0) = '1' then -- check if its a control world
wait_for_time_constant <= d_in(2);
-- if d_in(1) = '1' then -- software reset
-- wait_for_time_constant <= '0';
-- end if;
else -- its an interrupt vector
int_vector <= d_in(7 downto 3);
end if;
end if;
end if;
if int_pulse_0 = '1' then int_reg_0 <= '1'; end if;
if int_pulse_1 = '1' then int_reg_1 <= '1'; end if;
if int_pulse_2 = '1' then int_reg_2 <= '1'; end if;
if int_pulse_3 = '1' then int_reg_3 <= '1'; end if;
if int_ack_r = '1' and int_ack = '0' then
if int_reg_0 = '1' then int_reg_0 <= '0';
elsif int_reg_1 = '1' then int_reg_1 <= '0';
elsif int_reg_2 = '1' then int_reg_2 <= '0';
elsif int_reg_3 = '1' then int_reg_3 <= '0'; end if;
end if;
end if;
end if;
end if;
end process;
end struct;

152
Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/rtl/ctc_counter.vhd
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@@ -1,152 +0,0 @@
---------------------------------------------------------------------------------
-- Z80-CTC counter by Dar (darfpga@aol.fr) (19/10/2019)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ctc_counter is
port(
clock : in std_logic;
clock_ena : in std_logic;
reset : in std_logic;
d_in : in std_logic_vector( 7 downto 0);
load_data : in std_logic;
clk_trg : in std_logic;
d_out : out std_logic_vector(7 downto 0);
zc_to : out std_logic;
int_pulse : out std_logic
);
end ctc_counter;
architecture struct of ctc_counter is
signal control_word : std_logic_vector(7 downto 0);
signal wait_for_time_constant : std_logic;
signal time_constant_loaded : std_logic;
signal restart_on_next_clock : std_logic;
signal restart_on_next_trigger : std_logic;
signal prescale_max : std_logic_vector(7 downto 0);
signal prescale_in : std_logic_vector(7 downto 0) := (others => '0');
signal count_max : std_logic_vector(8 downto 0);
signal count_in : std_logic_vector(8 downto 0) := (others => '0');
signal zc_to_in : std_logic;
signal clk_trg_r : std_logic;
signal trigger : std_logic;
signal count_ena : std_logic;
signal load_data_r : std_logic; -- make sure load_data toggles to get one new data
begin
prescale_max <=
(others => '0') when control_word(6) = '1' else -- counter mode (prescale max = 0)
X"0F" when control_word(6 downto 5) = "00" else -- timer mode prescale 16
X"FF"; -- timer mode prescale 256
trigger <=
'1' when (clk_trg = '0' and clk_trg_r = '1' and control_word(4) = '0') or -- falling edge
(clk_trg = '1' and clk_trg_r = '0' and control_word(4) = '1') else '0'; -- rising edge
d_out <= count_in(7 downto 0);
zc_to <= zc_to_in;
int_pulse <= zc_to_in when control_word(7) = '1' else '0';
process (reset, clock)
begin
if reset = '1' then -- hardware reset
count_ena <= '0';
wait_for_time_constant <= '0';
time_constant_loaded <= '0';
restart_on_next_clock <= '0';
restart_on_next_trigger <= '0';
count_in <= (others=> '0');
zc_to_in <= '0';
clk_trg_r <= clk_trg;
else
if rising_edge(clock) then
if clock_ena = '1' then
clk_trg_r <= clk_trg;
load_data_r <= load_data;
if (restart_on_next_trigger = '1' and trigger = '1') or (restart_on_next_clock = '1') then
restart_on_next_clock <= '0';
restart_on_next_trigger <= '0';
count_ena <= '1';
count_in <= count_max;
prescale_in <= prescale_max;
end if;
if load_data = '1' and load_data_r = '0' then
if wait_for_time_constant = '1' then
wait_for_time_constant <= '0';
time_constant_loaded <= '1';
if d_in = X"00" then
count_max <= '1'&X"00";
else
count_max <= '0'&d_in;
end if;
if control_word(6) = '0' and count_ena = '0' then -- in timer mode, if count was stooped
if control_word(3) = '0' then -- auto start when time_constant loaded
restart_on_next_clock <= '1';
else -- wait for trigger to start
restart_on_next_trigger <= '1';
end if;
end if;
else -- not waiting for time constant
if d_in(0) = '1' then -- check if its a control world
control_word <= d_in;
wait_for_time_constant <= d_in(2);
restart_on_next_clock <= '0';
restart_on_next_trigger <= '0';
if d_in(1) = '1' then -- software reset
count_ena <= '0';
time_constant_loaded <= '0';
zc_to_in <= '0';
-- zc_to_in_r <= '0';
clk_trg_r <= clk_trg;
end if;
end if;
end if;
end if; -- end load data
-- counter
zc_to_in <= '0';
if ((control_word(6) = '1' and trigger = '1' ) or
(control_word(6) = '0' and count_ena = '1') ) and time_constant_loaded = '1' then
if prescale_in = 0 then
prescale_in <= '0'&prescale_max(7 downto 1); -- test divide by 2 !
if count_in = 0 then
zc_to_in <= '1';
count_in <= count_max;
else
count_in <= count_in - '1';
end if;
else
prescale_in <= prescale_in - '1';
end if;
end if;
end if;
end if;
end if;
end process;
end struct;

157
Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/rtl/dderby.vhd
View File

@@ -211,31 +211,15 @@ architecture struct of dderby is
signal cpu_ioreq_n : std_logic;
signal cpu_irq_n : std_logic;
signal cpu_m1_n : std_logic;
signal ctc_controler_we : std_logic;
signal ctc_controler_do : std_logic_vector(7 downto 0);
signal ctc_int_ack : std_logic;
signal cpu_int_ack_n : std_logic;
signal ctc_counter_0_we : std_logic;
-- signal ctc_counter_0_trg : std_logic;
signal ctc_counter_0_do : std_logic_vector(7 downto 0);
signal ctc_counter_0_int : std_logic;
signal ctc_ce : std_logic;
signal ctc_do : std_logic_vector(7 downto 0);
signal ctc_counter_1_we : std_logic;
-- signal ctc_counter_1_trg : std_logic;
signal ctc_counter_1_do : std_logic_vector(7 downto 0);
signal ctc_counter_1_int : std_logic;
signal ctc_counter_2_we : std_logic;
-- signal ctc_counter_2_trg : std_logic;
signal ctc_counter_2_do : std_logic_vector(7 downto 0);
signal ctc_counter_2_int : std_logic;
signal ctc_counter_3_we : std_logic;
signal ctc_counter_1_trg : std_logic;
signal ctc_counter_2_trg : std_logic;
signal ctc_counter_3_trg : std_logic;
signal ctc_counter_3_do : std_logic_vector(7 downto 0);
signal ctc_counter_3_int : std_logic;
-- signal cpu_rom_do : std_logic_vector( 7 downto 0);
signal wram_we : std_logic;
@@ -421,8 +405,8 @@ begin
vcnt >= 1 and vcnt < 241 then video_blankn <= '1';end if;
if hs_cnt = 0 then hsync0 <= '0';
elsif hs_cnt = 47 then hsync0 <= '1';
if hs_cnt = 0 then hsync0 <= '0'; video_hs <= '0';
elsif hs_cnt = 47 then hsync0 <= '1'; video_hs <= '1';
end if;
if hs_cnt = 0 then hsync1 <= '0';
@@ -506,24 +490,17 @@ cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"E
wram_do when cpu_mreq_n = '0' and (cpu_addr and X"F800") = x"E000" else -- E000-E7FF
sp_ram_cache_do_r when cpu_mreq_n = '0' and (cpu_addr and x"FC00") = x"E800" else -- sprite ram E800-E9FF + mirroring 0200
bg_ram_do_r when cpu_mreq_n = '0' and (cpu_addr and x"F800") = x"F000" else -- video ram F000-F7FF
ctc_controler_do when cpu_ioreq_n = '0' and cpu_m1_n = '0' else -- ctc ctrl (interrupt vector)
ctc_do when cpu_int_ack_n = '0' or ctc_ce = '1' else -- ctc (interrupt vector or counter data)
ssio_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 5) = "000" else -- 0x00-0x1F
ctc_counter_3_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F3" else
ctc_counter_2_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F2" else
ctc_counter_1_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F1" else
ctc_counter_0_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else
X"FF";
------------------------------------------------------------------------
-- Misc registers : ctc write enable / interrupt acknowledge
------------------------------------------------------------------------
ctc_counter_3_trg <= '1' when (vcnt = 246 and tv15Khz_mode = '1') or (vcnt = 493 and tv15Khz_mode = '0')else '0';
ctc_counter_3_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F3" else '0';
ctc_counter_2_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F2" else '0';
ctc_counter_1_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F1" else '0';
ctc_counter_0_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else '0';
ctc_controler_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else '0'; -- only channel 0 receive int vector
ctc_int_ack <= '1' when cpu_ioreq_n = '0' and cpu_m1_n = '0' else '0';
cpu_int_ack_n <= cpu_ioreq_n or cpu_m1_n;
ctc_ce <= '1' when cpu_ioreq_n = '0' and cpu_addr(7 downto 4) = x"F" else '0';
ctc_counter_2_trg <= '1' when (vcnt >= 240 and vcnt <= 262 and tv15Khz_mode = '1') or (vcnt >= 480 and tv15Khz_mode = '0') else '0';
ctc_counter_3_trg <= '1' when top_frame = '1' and ((vcnt = 246 and tv15Khz_mode = '1') or (vcnt = 493 and tv15Khz_mode = '0')) else '0';
------------------------------------------
-- write enable / ram access from CPU --
@@ -754,92 +731,28 @@ port map(
DO => cpu_do
);
-- CTC interrupt controler Z80-CTC (MK3882)
ctc_controler : entity work.ctc_controler
port map(
clock => clock_vid,
clock_ena => cpu_ena,
reset => reset,
d_in => cpu_do,
load_data => ctc_controler_we,
int_ack => ctc_int_ack,
int_pulse_0 => ctc_counter_0_int,
int_pulse_1 => ctc_counter_1_int,
int_pulse_2 => ctc_counter_2_int,
int_pulse_3 => ctc_counter_3_int,
d_out => ctc_controler_do,
int_n => cpu_irq_n
);
ctc_counter_0 : entity work.ctc_counter
port map(
clock => clock_vid,
clock_ena => cpu_ena,
reset => reset,
d_in => cpu_do,
load_data => ctc_counter_0_we,
clk_trg => '0',
d_out => ctc_counter_0_do,
zc_to => open, -- zc/to #0 (pin 7) connected to clk_trg #1 (pin 22) on schematics (seems to be not used)
int_pulse => ctc_counter_0_int
);
ctc_counter_1 : entity work.ctc_counter
port map(
clock => clock_vid,
clock_ena => cpu_ena,
reset => reset,
d_in => cpu_do,
load_data => ctc_counter_1_we,
clk_trg => '0',
d_out => ctc_counter_1_do,
zc_to => open,
int_pulse => ctc_counter_1_int
);
ctc_counter_2 : entity work.ctc_counter
port map(
clock => clock_vid,
clock_ena => cpu_ena,
reset => reset,
d_in => cpu_do,
load_data => ctc_counter_2_we,
clk_trg => '0',
d_out => ctc_counter_2_do,
zc_to => open,
int_pulse => ctc_counter_2_int
);
ctc_counter_3 : entity work.ctc_counter
port map(
clock => clock_vid,
clock_ena => cpu_ena,
reset => reset,
d_in => cpu_do,
load_data => ctc_counter_3_we,
clk_trg => ctc_counter_3_trg,
d_out => ctc_counter_3_do,
zc_to => open,
int_pulse => ctc_counter_3_int
-- Z80-CTC (MK3882)
z80ctc : entity work.z80ctc_top
port map (
clock => clock_vid,
clock_ena => cpu_ena,
reset => reset,
din => cpu_do,
cpu_din => cpu_di,
dout => ctc_do,
ce_n => not ctc_ce,
cs => cpu_addr(1 downto 0),
m1_n => cpu_m1_n,
iorq_n => cpu_ioreq_n,
rd_n => cpu_rd_n,
int_n => cpu_irq_n,
trg0 => '0',
to0 => ctc_counter_1_trg,
trg1 => ctc_counter_1_trg,
to1 => open,
trg2 => ctc_counter_2_trg,
to2 => open,
trg3 => ctc_counter_3_trg
);
cpu_rom_addr <= cpu_addr(15 downto 0);

8
Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/rtl/sdram.sv
View File

@@ -63,6 +63,8 @@ module sdram (
output reg [31:0] sp_q
);
parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
@@ -72,8 +74,8 @@ localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single acc
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
localparam RFRSH_CYCLES = 10'd842;
// 64ms/8192 rows = 7.8us
localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
@@ -81,7 +83,7 @@ localparam RFRSH_CYCLES = 10'd842;
/*
SDRAM state machine for 2 bank interleaved access
1 word burst, CL2
2 words burst, CL2
cmd issued registered
0 RAS0 cas1 - data0 read burst terminated
1 ras0