github.com/Gehstock.Mist_FPGA
1
0
Fork 0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-03-08 03:29:26 +00:00
Code Issues Releases Wiki Activity

Add Flicky Project files

Browse Source
This commit is contained in:
Gehstock
2020-05-16 06:42:10 +02:00
parent c4579a939f
commit 66fc73f59d
54 changed files with 32932 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/Flicky_MiST.qpf Normal file
View File

@@ -0,0 +1,31 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 00:21:03 December 03, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "00:21:03 December 03, 2019"
# Revisions
PROJECT_REVISION = "Flicky_MiST"

247
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/Flicky_MiST.qsf Normal file
View File

@@ -0,0 +1,247 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 06:24:46 May 16, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Flicky_MiST_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Flicky_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/FPGA_FLICKY.v
set_global_assignment -name VERILOG_FILE rtl/FlickyMAIN.v
set_global_assignment -name VERILOG_FILE rtl/FlickyVIDEO.v
set_global_assignment -name VERILOG_FILE rtl/FlickySND.v
set_global_assignment -name VERILOG_FILE rtl/z80ip.v
set_global_assignment -name VERILOG_FILE rtl/FlickySPRITE.v
set_global_assignment -name VERILOG_FILE rtl/parts.v
set_global_assignment -name VERILOG_FILE rtl/hvgen.v
set_global_assignment -name VERILOG_FILE rtl/SN76496.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/pll_mist.v
set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_1B.v
set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_11B.v
set_global_assignment -name VHDL_FILE rtl/rom/dec_rom.vhd
set_global_assignment -name VHDL_FILE rtl/rom/prg_rom.vhd
set_global_assignment -name VHDL_FILE rtl/rom/snd_rom.vhd
set_global_assignment -name VHDL_FILE rtl/rom/clut.vhd
set_global_assignment -name VHDL_FILE rtl/rom/spr_rom.vhd
set_global_assignment -name VHDL_FILE rtl/rom/tile1.vhd
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name TOP_LEVEL_ENTITY Flicky_MiST
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/zaxx.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# -------------------------
# start ENTITY(Flicky_MiST)
# Pin & Location Assignments
# ==========================
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
# Fitter Assignments
# ==================
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Flicky_MiST)
# -----------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

134
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/Flicky_MiST.sdc Normal file
View File

@@ -0,0 +1,134 @@
## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

BIN
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/Snapshot/Flicky_MiST.rbf Normal file
View File

Binary file not shown.

37
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/clean.bat Normal file
View File

@@ -0,0 +1,37 @@
@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

128
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/DPRAM1024_11B.v Normal file
View File

@@ -0,0 +1,128 @@
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: DPRAM1024_11B.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module DPRAM1024_11B (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock_a;
input clock_b;
input [15:0] data_a;
input [15:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire [15:0] q_a = sub_wire0[15:0];
wire [15:0] q_b = sub_wire1[15:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule

128
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/DPRAM1024_1B.v Normal file
View File

@@ -0,0 +1,128 @@
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: DPRAM1024_1B.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module DPRAM1024_1B (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock_a;
input clock_b;
input [0:0] data_a;
input [0:0] data_b;
input wren_a;
input wren_b;
output [0:0] q_a;
output [0:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [0:0] q_a = sub_wire0[0:0];
wire [0:0] q_b = sub_wire1[0:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 1,
altsyncram_component.width_b = 1,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule

143
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/FPGA_FLICKY.v Normal file
View File

@@ -0,0 +1,143 @@
/********************************************************************
FPGA Implimentation of "FLICKY" (Top Module)
Copyright (c) 2017,19 MiSTer-X
*********************************************************************/
module FPGA_FLICKY
(
input clk48M,
input reset,
input [7:0] INP0,
input [7:0] INP1,
input [7:0] INP2,
input [7:0] DSW0,
input [7:0] DSW1,
output [2:0] video_r,
output [2:0] video_g,
output [1:0] video_b,
output video_hs,
output video_vs,
output video_hb,
output video_vb,
output [15:0] SOUT, // Sound Out (PCM)
output [14:0] cpu_rom_addr,
input [7:0] cpu_rom_do,
output [14:0] spr_rom_addr,
input [7:0] spr_rom_do,
output [12:0] snd_rom_addr,
input [7:0] snd_rom_do,
output [13:0] tile_rom_addr,
input [23:0] tile_rom_do
);
// Clocks
wire clk24M, clk12M, clk6M, clk3M, clk8M ;
CLKGEN clks( clk48M, clk24M, clk12M, clk6M, clk3M, clk8M );
// CPU
wire CPUCLn;
wire [15:0] CPUAD;
wire [7:0] CPUDO,VIDDO;
wire CPUWR,VIDCS,VBLK;
wire SNDRQ;
FlickyMAIN Main (
.RESET(reset),
.INP0(INP0),.INP1(INP1),.INP2(INP2),
.DSW0(DSW0),.DSW1(DSW1),
.CLK48M(clk48M),.CLK3M(clk3M),
.CPUCLn(CPUCLn),.CPUAD(CPUAD),.CPUDO(CPUDO),.CPUWR(CPUWR),
.VBLK(VBLK),.VIDCS(VIDCS),.VIDDO(VIDDO),
.SNDRQ(SNDRQ),
.cpu_rom_addr(cpu_rom_addr),
.cpu_rom_do(cpu_rom_do)
);
// Video
FlickyVIDEO Video (
.VCLKx8(clk48M),
.VCLKx4(clk24M),
.VCLKx2(clk12M),
.VCLK(clk6M),
.PH(HPOS),
.PV(VPOS),
.VBLK(VBLK),
.RGB8(POUT),
.PALDSW(1'b0),
.cpu_cl(CPUCLn),
.cpu_ad(CPUAD),
.cpu_wr(CPUWR),
.cpu_dw(CPUDO),
.cpu_rd(VIDCS),
.cpu_dr(VIDDO),
.spr_rom_addr(spr_rom_addr),
.spr_rom_do(spr_rom_do),
.tile_rom_addr(tile_rom_addr),
.tile_rom_do(tile_rom_do)
);
assign PCLK = clk6M;
// Sound
FlickySND Sound(
clk8M, reset, CPUDO, SNDRQ, SOUT,
snd_rom_addr, snd_rom_do
);
wire [8:0] HPOS;
wire [8:0] VPOS;
wire PCLK;
wire [7:0] POUT;
hvgen hvgen(
.HPOS(HPOS),
.VPOS(VPOS),
.PCLK(PCLK),
.iRGB(POUT),
.oRGB({video_b,video_g,video_r}),
.HBLK(video_hb),
.VBLK(video_vb),
.HSYN(video_hs),
.VSYN(video_vs)
);
endmodule
//----------------------------------
// Clock Generator
//----------------------------------
module CLKGEN
(
input clk48M,
output clk24M,
output clk12M,
output clk6M,
output clk3M,
output reg clk8M
);
reg [4:0] clkdiv;
always @( posedge clk48M ) clkdiv <= clkdiv+1;
assign clk24M = clkdiv[0];
assign clk12M = clkdiv[1];
assign clk6M = clkdiv[2];
assign clk3M = clkdiv[3];
reg [1:0] count;
always @( posedge clk48M ) begin
if (count > 2'd2) begin
count <= count - 2'd2;
clk8M <= ~clk8M;
end
else count <= count + 2'd1;
end
endmodule

167
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/FlickyMAIN.v Normal file
View File

@@ -0,0 +1,167 @@
// Copyright (c) 2017,19 MiSTer-X
module FlickyMAIN
(
input CLK48M,
input CLK3M,
input RESET,
input [7:0] INP0,
input [7:0] INP1,
input [7:0] INP2,
input [7:0] DSW0,
input [7:0] DSW1,
input VBLK,
input VIDCS,
input [7:0] VIDDO,
output CPUCLn,
output [15:0] CPUAD,
output [7:0] CPUDO,
output CPUWR,
output SNDRQ,
// input ROMCL, // Downloaded ROM image
// input [24:0] ROMAD,
// input [7:0] ROMDT,
// input ROMEN
output [14:0] cpu_rom_addr,
input [7:0] cpu_rom_do
);
wire AXSCL = CLK48M;
wire CPUCL = CLK3M;
assign CPUCLn = ~CPUCL;
wire [7:0] CPUDI;
wire CPURD;
wire cpu_cs_video;
wire [7:0] cpu_rd_video;
wire cpu_m1;
wire cpu_mreq, cpu_iorq;
wire _cpu_rd, _cpu_wr;
Z80IP maincpu(
.reset(RESET),
.clk(CPUCL),
.adr(CPUAD),
.data_in(CPUDI),
.data_out(CPUDO),
.m1(cpu_m1),
.mx(cpu_mreq),
.ix(cpu_iorq),
.rd(_cpu_rd),
.wr(_cpu_wr),
.intreq(VBLK),
.nmireq(1'b0)
);
assign CPUWR = _cpu_wr & cpu_mreq;
assign CPURD = _cpu_rd & cpu_mreq;
assign SNDRQ = (CPUAD[4:0] == 5'b1_1000) & cpu_iorq & _cpu_wr;
wire cpu_cs_port1 = (CPUAD[4:2] == 3'b0_00) & cpu_iorq;
wire cpu_cs_port2 = (CPUAD[4:2] == 3'b0_01) & cpu_iorq;
wire cpu_cs_portS = (CPUAD[4:2] == 3'b0_10) & cpu_iorq;
wire cpu_cs_portA = (CPUAD[4:2] == 3'b0_11) & ~CPUAD[0] & cpu_iorq;
wire cpu_cs_portB =(((CPUAD[4:2] == 3'b0_11) & CPUAD[0]) | (CPUAD[4:0] == 5'b1_0000)) & cpu_iorq;
wire cpu_cs_portI = (CPUAD[4:2] == 3'b1_10) & cpu_iorq;
wire [7:0] cpu_rd_port1 = INP0;
wire [7:0] cpu_rd_port2 = INP1;
wire [7:0] cpu_rd_portS = INP2;
wire [7:0] cpu_rd_portA = DSW0;
wire [7:0] cpu_rd_portB = DSW1;
wire [7:0] cpu_rd_mrom;
wire cpu_cs_mrom = (CPUAD[15] == 1'b0);
PRGROM prom(AXSCL, cpu_m1, CPUAD[14:0], cpu_rd_mrom, cpu_rom_addr,cpu_rom_do );
wire [7:0] cpu_rd_mram;
wire cpu_cs_mram = (CPUAD[15:12] == 4'b1100);
SRAM_4096 mainram(CPUCLn, CPUAD[11:0], cpu_rd_mram, cpu_cs_mram & CPUWR, CPUDO );
reg [7:0] vidmode;
always @(posedge CPUCLn) begin
if ((CPUAD[4:0] == 5'b1_1001) & cpu_iorq & _cpu_wr) begin
vidmode <= CPUDO;
end
end
dataselector8 mcpudisel(
CPUDI,
VIDCS, VIDDO,
cpu_cs_port1, cpu_rd_port1,
cpu_cs_port2, cpu_rd_port2,
cpu_cs_portS, cpu_rd_portS,
cpu_cs_portA, cpu_rd_portA,
cpu_cs_portB, cpu_rd_portB,
cpu_cs_mram, cpu_rd_mram,
cpu_cs_mrom, cpu_rd_mrom,
8'hFF
);
endmodule
//----------------------------------
// Program ROM with Decryptor
//----------------------------------
module PRGROM
(
input clk,
input mrom_m1,
input [14:0] mrom_ad,
output reg [7:0] mrom_dt,
output [14:0] cpu_rom_addr,
input [7:0] cpu_rom_do
// input ROMCL, // Downloaded ROM image
// input [24:0] ROMAD,
// input [7:0] ROMDT,
// input ROMEN
);
reg [15:0] madr;
wire [7:0] mdat;
wire f = mdat[7];
wire [7:0] xorv = { f, 1'b0, f, 1'b0, f, 3'b000 };
wire [7:0] andv = ~(8'hA8);
wire [1:0] decidx0 = { mdat[5], mdat[3] } ^ { f, f };
wire [6:0] decidx = { madr[12], madr[8], madr[4], madr[0], ~madr[15], decidx0 };
wire [7:0] dectbl;
wire [7:0] mdec = ( mdat & andv ) | ( dectbl ^ xorv );
//DLROM #( 7,8) decrom( clk, decidx, dectbl, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16: 7]==10'b1_1110_0001_0) ); // $1E100-$1E17F
dec_rom dec_rom(
.clk(clk),
.addr(decidx),
.data(dectbl)
);
//DLROM #(15,8) mainir( clk, madr[14:0], mdat, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b0_0) ); // $00000-$07FFF
//prg_rom pgr_rom(
// .clk(clk),
// .addr(madr[14:0]),
// .data(mdat)
//);
assign cpu_rom_addr = madr[14:0];
assign mdat = cpu_rom_do;
reg phase = 1'b0;
always @( negedge clk ) begin
if ( phase ) mrom_dt <= mdec;
else madr <= { mrom_m1, mrom_ad };
phase <= ~phase;
end
endmodule

214
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/FlickySND.v Normal file
View File

@@ -0,0 +1,214 @@
// Copyright (c) 2017,19 MiSTer-X
module FlickySND
(
input clk8M,
input reset,
input [7:0] sndno,
input sndstart,
output [15:0] sndout,
output [12:0] snd_rom_addr,
input [7:0] snd_rom_do
);
//----------------------------------
// ClockGen
//----------------------------------
wire clk4M,clk2M;
SndClkGen clkgen(clk8M,clk4M,clk2M);
wire cpuclkx2 = clk8M;
wire cpu_clk = clk4M;
//----------------------------------
// Z80 (1.5625MHz)
//----------------------------------
wire [15:0] cpu_ad;
wire [7:0] cpu_di, cpu_do;
wire cpu_mreq, cpu_iorq, cpu_rd, cpu_wr;
wire cpu_irq, cpu_nmi;
wire cpu_irqa, cpu_nmia;
wire cpu_mw, cpu_cs_rom, cpu_cs_ram, cpu_wr_ram, cpu_cs_psg0, cpu_cs_psg1, cpu_cs_com;
SndADec adec(
cpu_mreq, cpu_wr, cpu_mw,
cpu_ad, cpu_cs_rom, cpu_cs_ram, cpu_wr_ram, cpu_cs_psg0, cpu_cs_psg1, cpu_cs_com
);
Z80IP cpu(
.clk(cpu_clk),
.reset(reset),
.adr(cpu_ad),
.data_in(cpu_di),
.data_out(cpu_do),
.intreq(cpu_irq),
.intack(cpu_irqa),
.nmireq(cpu_nmi),
.nmiack(cpu_nmia),
.mx(cpu_mreq),
.ix(cpu_iorq),
.rd(cpu_rd),
.wr(cpu_wr)
);
wire [7:0] rom_dt; // ROM
wire [7:0] ram_do; // RAM
wire [7:0] comlatch; // Sound Command Latch
//DLROM #(13,8) subir( cpuclkx2, cpu_ad[12:0], rom_dt, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:13]==4'b1_110)); // $1C000-$1DFFF
//snd_rom snd_rom(
// .clk(cpuclkx2),
// .addr(cpu_ad[12:0]),
// .data(rom_dt)
//);
assign snd_rom_addr = cpu_ad[12:0];
assign rom_dt = snd_rom_do;
SRAM_2048 wram( cpuclkx2, cpu_ad[10:0], ram_do, cpu_wr_ram, cpu_do );
dataselector3 scpudisel(
cpu_di,
cpu_cs_rom, rom_dt,
cpu_cs_ram, ram_do,
cpu_cs_com, comlatch,
8'hFF
);
SndPlayReq sndreq (
clk4M, reset,
sndno, sndstart,
cpu_irq, cpu_irqa,
cpu_nmi, cpu_nmia,
comlatch
);
//----------------------------------
// PSGs
//----------------------------------
wire [7:0] psg0out, psg1out;
SN76496 psg0(
clk2M,
cpu_clk,
reset,
cpu_cs_psg0,
cpu_mw,
cpu_do,
4'b1111,
psg0out
);
SN76496 psg1(
clk4M,
cpu_clk,
reset,
cpu_cs_psg1,
cpu_mw,
cpu_do,
4'b1111,
psg1out
);
wire [8:0] psgout = psg0out + psg1out;
assign sndout = { psgout, 6'h0 };
endmodule
module SndClkGen
(
input clk8M,
output clk4M,
output clk2M
);
reg [1:0] clkdiv;
always @ ( posedge clk8M ) clkdiv <= clkdiv+1;
assign clk4M = clkdiv[0];
assign clk2M = clkdiv[1];
endmodule
module SndADec
(
input cpu_mx,
input cpu_wr,
output cpu_mw,
input [15:0] cpu_ad,
output cpu_cs_rom,
output cpu_cs_ram,
output cpu_wr_ram,
output cpu_cs_psg0,
output cpu_cs_psg1,
output cpu_cs_com
);
assign cpu_mw = cpu_mx & cpu_wr;
assign cpu_cs_rom = ( cpu_ad[15] == 1'b0 );
assign cpu_cs_psg0 = ( cpu_ad[15:12] == 4'HA );
assign cpu_cs_psg1 = ( cpu_ad[15:12] == 4'HC );
assign cpu_cs_com = ( cpu_ad[15:12] == 4'HE );
assign cpu_cs_ram = ( cpu_ad[15:12] == 4'h8 );
assign cpu_wr_ram = cpu_cs_ram & cpu_mw;
endmodule
//----------------------------------
// Play Request & IRQ Generator
//----------------------------------
module SndPlayReq
(
input clk4M,
input reset,
input [7:0] sndno,
input sndstart,
output reg cpu_irq,
input cpu_irqa,
output reg cpu_nmi,
input cpu_nmia,
output reg [7:0] comlatch
);
reg [15:0] timercnt;
reg psndstart;
always @( posedge clk4M or posedge reset ) begin
if ( reset ) begin
cpu_nmi <= 0;
cpu_irq <= 0;
comlatch <= 0;
timercnt <= 0;
psndstart <= 0;
end
else begin
if ( cpu_irqa ) cpu_irq <= 1'b0;
if ( cpu_nmia ) cpu_nmi <= 1'b0;
if ( ( psndstart ^ sndstart ) & sndstart ) begin
comlatch <= sndno;
cpu_nmi <= 1'b1;
end
psndstart <= sndstart;
if ( timercnt == 16666 ) cpu_irq <= 1'b1;
if ( timercnt == 33333 ) cpu_irq <= 1'b1;
timercnt <= ( timercnt == 33333 ) ? 0 : (timercnt+1); // 1/60sec
end
end
endmodule

247
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/FlickySPRITE.v Normal file
View File

@@ -0,0 +1,247 @@
// Copyright (c) 2017,19 MiSTer-X
module FlickySPRITE
(
input VCLKx4,
input VCLK,
input [8:0] PH,
input [8:0] PV,
output [9:0] sprad,
input [15:0] sprdt,
output [17:0] sprchad,
input [7:0] sprchdt,
output reg sprcoll,
output reg [9:0] sprcoll_ad,
output reg [10:0] sprpx
);
wire [8:0] HPOS = PH+15;
wire [8:0] VPOS = PV;
wire HB = HPOS[8];
reg [5:0] spr_num;
reg [2:0] spr_ofs;
reg [1:0] phaseHB;
reg [7:0] svpos;
reg [5:0] hitsprnum [0:31];
reg [7:0] hitsprvps [0:31];
reg [4:0] hits;
reg [3:0] phaseHD;
reg [4:0] hitr;
reg [7:0] yofs;
reg [8:0] xpos;
reg [2:0] bank;
reg [15:0] stride;
reg [15:0] srcadrs;
reg [1:0] waitcnt;
reg [7:0] rdat;
reg [10:0] wdat;
reg hflip;
reg nowflip;
reg we;
wire [15:0] srca = sprdt[15:0] + (stride * yofs);
wire [10:0] col0 = { 2'b00, spr_num[4:0], nowflip ? rdat[3:0] : rdat[7:4] };
wire [10:0] col1 = { 2'b00, spr_num[4:0], nowflip ? rdat[7:4] : rdat[3:0] };
wire [10:0] _prevpix;
reg [10:0] prevpix;
wire side = VPOS[0];
wire [10:0] opix;
reg [9:0] rad0,rad1=1;
LineBuf lbuf(
VCLKx4, rad0, (rad0==rad1), opix,
VCLKx4, {~side,xpos}, wdat, we & (wdat[3:0] != 4'h0), _prevpix
);
always @(posedge VCLK) rad0 <= {side,HPOS};
always @(negedge VCLK) begin
sprpx <= opix;
rad1 <= rad0;
end
assign sprad = { spr_num, spr_ofs };
assign sprchad = { bank, srcadrs[14:0] };
wire [9:0] sprcoll_adr = { spr_num[4:0], prevpix[8:4] };
`define SPSTART 0
`define SPEND 31
always @ ( negedge VCLKx4 ) begin
// in H-Blank
if ( HB ) begin
phaseHD <= 0;
we <= 1'b0;
sprcoll <= 1'b0;
case ( phaseHB )
// initialize
2'h0: begin
svpos <= VPOS+1;
spr_num <= `SPSTART;
spr_ofs <= 0;
hits <= 0;
phaseHB <= 2'h1;
end
// check v-hit
2'h1: begin
if ( sprdt[7:0] != 8'hFF ) begin
if ( ( svpos >= sprdt[7:0] ) & ( svpos < sprdt[15:8] ) ) begin
hitsprnum[hits] <= spr_num;
hitsprvps[hits] <= (svpos-sprdt[7:0])+1;
hits <= hits+1;
end
end
phaseHB <= ( spr_num == `SPEND ) ? 2'h2 : 2'h1;
spr_num <= spr_num+1;
end
default:;
endcase
end
// in H-Disp
else begin
phaseHB <= 0;
case ( phaseHD )
// initialize
0: begin
hitr <= 0;
we <= 1'b0;
sprcoll <= 0;
phaseHD <= ( hits > 0 ) ? 1 : 15;
end
// get hit sprite number
1: begin
spr_num <= hitsprnum[hitr];
spr_ofs <= 1;
phaseHD <= 2;
end
// get yofs/xpos/bank
2: begin
yofs <= hitsprvps[hitr];
xpos <= sprdt[8:1]+14;
bank <= { sprdt[13], sprdt[14], sprdt[15] };
spr_ofs <= 2;
phaseHD <= 3;
end
// get stride
3: begin
stride <= sprdt;
spr_ofs <= 3;
phaseHD <= 4;
end
// get srcadrs & calc chiprom address
4: begin
srcadrs <= srca;
hflip <= srca[15];
waitcnt <= 3;
phaseHD <= 5;
end
// wait chiprom setup
5: begin
waitcnt <= waitcnt-1;
phaseHD <= ( waitcnt == 0 ) ? 6 : 5;
end
// rendering to linebuf
6: begin
sprcoll <= 1'b0;
we <= 1'b0;
rdat <= sprchdt;
nowflip <= srcadrs[15];
srcadrs <= hflip ? (srcadrs-1) : (srcadrs+1);
phaseHD <= 7;
end
7: begin
prevpix <= _prevpix;
if ( col0[3:0] != 4'hF ) begin
wdat <= col0;
we <= 1'b1;
phaseHD <= 8;
end
else begin
we <= 1'b0;
phaseHD <= 14;
end
end
8: begin
// sprite collide process
we <= 1'b0;
if ( col0[3:0] != 4'h0 ) begin
if ( prevpix[3:0] != 4'h0 ) begin
sprcoll <= 1'b1;
sprcoll_ad <= sprcoll_adr;
end
end
xpos <= xpos+1;
phaseHD <= 9;
end
9: begin
prevpix <= _prevpix;
sprcoll <= 1'b0;
if ( col1[3:0] != 4'hF ) begin
wdat <= col1;
we <= 1'b1;
phaseHD <= 10;
end
else begin
we <= 1'b0;
phaseHD <= 14;
end
end
10: begin
// sprite collide process
we <= 1'b0;
if ( col1[3:0] != 4'h0 ) begin
if ( prevpix[3:0] != 4'h0 ) begin
sprcoll <= 1'b1;
sprcoll_ad <= sprcoll_adr;
end
end
xpos <= xpos+1;
phaseHD <= 6;
end
// process next hit sprite
14: begin
phaseHD <= ( hitr == (hits-1) ) ? 15 : 1;
hitr <= hitr+1;
end
default: begin
we <= 1'b0;
sprcoll <= 1'b0;
end
endcase
end
end
endmodule

605
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/FlickyVIDEO.v Normal file
View File

@@ -0,0 +1,605 @@
// Copyright (c) 2017,19 MiSTer-X
module FlickyVIDEO
(
input VCLKx8,
input VCLKx4,
input VCLKx2,
input VCLK,
input [8:0] PH,
input [8:0] PV,
output VBLK,
output [7:0] RGB8,
input PALDSW,
input cpu_cl,
input [15:0] cpu_ad,
input cpu_wr,
input [7:0] cpu_dw,
output cpu_rd,
output [7:0] cpu_dr,
output [14:0] spr_rom_addr,
input [7:0] spr_rom_do,
output [13:0] tile_rom_addr,
input [23:0] tile_rom_do
);
// CPU Interface
wire [10:0] palno;
wire [7:0] palout;
wire [9:0] sprad;
wire [15:0] sprdt;
wire [9:0] vram0ad;
wire [15:0] vram0dt;
wire [9:0] vram1ad;
wire [15:0] vram1dt;
wire [5:0] mixcoll_ad;
wire mixcoll;
wire [9:0] sprcoll_ad;
wire sprcoll;
wire [15:0] scrx;
wire [7:0] scry;
VIDCPUINTF intf(
cpu_cl,
cpu_ad, cpu_wr, cpu_dw,
cpu_rd, cpu_dr,
VCLKx4, VCLK,
palno, palout,
sprad, sprdt,
vram0ad, vram0dt,
vram1ad, vram1dt,
mixcoll_ad, mixcoll,
sprcoll_ad, sprcoll,
scrx, scry
);
// HV Coordinate Generator
wire [8:0] HPOS, VPOS;
wire [8:0] BG0HP, BG0VP;
wire [8:0] BG1HP, BG1VP;
VIDHVGEN hv(
PH, PV,
scrx, scry,
HPOS, VPOS,
BG0HP, BG0VP,
BG1HP, BG1VP,
VBLK
);
// Sprite Engine
wire [10:0] SPRPX;
wire [14:0] sprchad;
wire [7:0] sprchdt;
//DLROM #(15,8) sprchr(VCLKx8,sprchad,sprchdt, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b0_1)); // $08000-$0FFFF
spr_rom spr_rom(
.clk(VCLKx8),
.addr(sprchad),
.data(sprchdt)
);
//assign spr_rom_addr = sprchad;
//assign sprchdt = spr_rom_do;
FlickySPRITE sprite(
.VCLKx4(VCLKx4),.VCLK(VCLK),
.PH(HPOS),.PV(VPOS),
.sprad(sprad),.sprdt(sprdt),
.sprchad(sprchad),.sprchdt(sprchdt),
.sprcoll(sprcoll),.sprcoll_ad(sprcoll_ad),
.sprpx(SPRPX)
);
// BG Scanline Generator
wire [10:0] BG0PX, BG1PX;
wire [13:0] tile0ad, tile1ad, tilead;
wire [23:0] tile0dt, tile1dt, tiledt;
TileChrMUX tilemux(VCLKx8, tile0ad, tile0dt, tile1ad, tile1dt, tilead, tiledt);
//TILES
//FlickyTileChr tilechr(VCLKx8, tilead, tiledt, ROMCL,ROMAD,ROMDT,ROMEN );
assign tile_rom_addr = tilead;
assign tiledt = tile_rom_do;
BGGEN bg0(VCLK,BG0HP,BG0VP,vram0ad,vram0dt,tile0ad,tile0dt,BG0PX);
BGGEN bg1(VCLK,BG1HP,BG1VP,vram1ad,vram1dt,tile1ad,tile1dt,BG1PX);
// Color Mixer & RGB Output
wire [7:0] cltidx,cltval;
//DLROM #(8,8) clut(VCLKx2, cltidx, cltval, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:8]==9'b1_1110_0000) ); // $1E000-$1E0FF
clut clut(
.clk(VCLKx2),
.addr(cltidx),
.data(cltval)
);
COLMIX cmix(
VCLK,
BG0PX, BG1PX, SPRPX,
PALDSW, HPOS, VPOS,
cltidx, cltval,
mixcoll, mixcoll_ad,
palno, palout,
RGB8
);
endmodule
//----------------------------------
// CPU Interface
//----------------------------------
module VIDCPUINTF
(
input cpu_cl,
input [15:0] cpu_ad,
input cpu_wr,
input [7:0] cpu_dw,
output cpu_rd,
output [7:0] cpu_dr,
input VCLKx4,
input VCLK,
input [10:0] palno,
output [7:0] palout,
input [9:0] sprad,
output [15:0] sprdt,
input [9:0] vram0ad,
output [15:0] vram0dt,
input [9:0] vram1ad,
output [15:0] vram1dt,
input [5:0] mixcoll_ad,
input mixcoll,
input [9:0] sprcoll_ad,
input sprcoll,
output reg [15:0] scrx,
output reg [7:0] scry
);
// CPU Address Decoders
wire cpu_cs_palram;
wire cpu_cs_spram;
wire cpu_cs_mixcoll;
wire cpu_cs_sprcoll;
wire cpu_cs_vram0;
wire cpu_cs_vram1;
wire cpu_wr_palram;
wire cpu_wr_spram;
wire cpu_wr_mixcoll;
wire cpu_wr_mixcollclr;
wire cpu_wr_sprcoll;
wire cpu_wr_sprcollclr;
wire cpu_wr_vram0;
wire cpu_wr_vram1;
wire cpu_wr_scrreg;
VIDADEC adecs(
cpu_ad,
cpu_wr,
cpu_cs_palram,
cpu_cs_spram,
cpu_cs_mixcoll,
cpu_cs_sprcoll,
cpu_cs_vram0,
cpu_cs_vram1,
cpu_wr_palram,
cpu_wr_spram,
cpu_wr_mixcoll,
cpu_wr_mixcollclr,
cpu_wr_sprcoll,
cpu_wr_sprcollclr,
cpu_wr_vram0,
cpu_wr_vram1,
cpu_wr_scrreg,
cpu_rd
);
// Scroll Register
always @ ( posedge cpu_cl ) begin
if (cpu_wr_scrreg) begin
case({cpu_ad[6],cpu_ad[0]})
2'b11: scrx[15:8] <= cpu_dw;
2'b10: scrx[ 7:0] <= cpu_dw;
2'b01: scry <= cpu_dw;
2'b00: ;
endcase
end
end
// Palette RAM
wire [7:0] cpu_rd_palram;
DPRAM2048 palram(
cpu_cl, cpu_ad[10:0], cpu_dw, cpu_wr_palram,
VCLK, palno, palout, cpu_rd_palram
);
// Sprite Attribute RAM
wire [7:0] cpu_rd_spram;
DPRAM2048_8_16 sprram(
cpu_cl, cpu_ad[10:0], cpu_dw, cpu_wr_spram,
VCLKx4, sprad, sprdt, cpu_rd_spram
);
// Collision RAM (Mixer & Sprite)
wire noclip = 1'b1;
wire [7:0] cpu_rd_mixcoll;
wire [7:0] cpu_rd_sprcoll;
COLLRAM_M mixc(
cpu_cl,cpu_ad[5:0],cpu_wr_mixcoll,cpu_wr_mixcollclr,cpu_rd_mixcoll,
VCLKx4,mixcoll_ad,mixcoll & noclip
);
COLLRAM_S sprc(
cpu_cl,cpu_ad[9:0],cpu_wr_sprcoll,cpu_wr_sprcollclr,cpu_rd_sprcoll,
VCLKx4,sprcoll_ad,sprcoll & noclip
);
// VRAM
wire [7:0] cpu_rd_vram0, cpu_rd_vram1;
VRAM vram0(
cpu_cl, cpu_ad[10:0], cpu_rd_vram0, cpu_dw, cpu_wr_vram0,
VCLKx4, vram0ad, vram0dt
);
VRAM vram1(
cpu_cl, cpu_ad[10:0], cpu_rd_vram1, cpu_dw, cpu_wr_vram1,
VCLKx4, vram1ad, vram1dt
);
// CPU Read Data Selector
dataselector6 videodsel(
cpu_dr,
cpu_cs_palram, cpu_rd_palram,
cpu_cs_vram0, cpu_rd_vram0,
cpu_cs_vram1, cpu_rd_vram1,
cpu_cs_spram, cpu_rd_spram,
cpu_cs_sprcoll, cpu_rd_sprcoll,
cpu_cs_mixcoll, cpu_rd_mixcoll,
8'hFF
);
endmodule
//----------------------------------
// Tile ROM
//----------------------------------
module TileChrMUX
(
input VCLKx8,
input [13:0] tile0ad,
output reg [23:0] tile0dt,
input [13:0] tile1ad,
output reg [23:0] tile1dt,
output [13:0] tilead,
input [23:0] tiledt
);
reg tphase;
always @(negedge VCLKx8) begin
if (tphase) tile1dt <= tiledt;
else tile0dt <= tiledt;
tphase <= ~tphase;
end
assign tilead = tphase ? tile1ad : tile0ad;
endmodule
/*
module FlickyTileChr
(
input clk,
input [13:0] adr,
output [23:0] dat,
input ROMCL, // Downloaded ROM image
input [24:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
wire [23:0] t0dt,t1dt;
assign dat = adr[13] ? t1dt : t0dt;
//DLROM #(13,8) t00( clk, adr[12:0], t0dt[7:0] ,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:13]==4'b1_000)); // $10000-$11FFF
//tile1 tile1(
// .clk(clk),
// .addr(adr[12:0]),
// .data(t0dt[7:0])
//);
//DLROM #(13,8) t01( clk, adr[12:0], t0dt[15:8] ,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:13]==4'b1_001)); // $12000-$13FFF
//DLROM #(13,8) t02( clk, adr[12:0], t0dt[23:16],ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:13]==4'b1_010)); // $14000-$15FFF
//DLROM #(13,8) t10( clk, adr[12:0], t1dt[7:0] ,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:13]==4'b1_011)); // $16000-$17FFF
//DLROM #(13,8) t11( clk, adr[12:0], t1dt[15:8] ,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:13]==4'b1_100)); // $18000-$19FFF
//DLROM #(13,8) t12( clk, adr[12:0], t1dt[23:16],ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:13]==4'b1_101)); // $1A000-$1BFFF
endmodule*/
//----------------------------------
// HV Coordinate Generator
//----------------------------------
module VIDHVGEN
(
input [8:0] PH,
input [8:0] PV,
input [15:0] scrx,
input [7:0] scry,
output [8:0] HPOS,
output [8:0] VPOS,
output [8:0] BG0HP,
output [8:0] BG0VP,
output [8:0] BG1HP,
output [8:0] BG1VP,
output VBLK
);
assign VBLK = (PV == 8'd224) & (PH <= 8'd64);
assign HPOS = PH+1;
assign VPOS = PV;
wire [8:0] BGHSCR = (511-scrx[9:1])-10;
wire [8:0] BGVSCR = { 1'b0, scry };
assign BG0HP = BGHSCR+HPOS;
assign BG0VP = BGVSCR+VPOS;
assign BG1HP = HPOS+3;
assign BG1VP = VPOS;
endmodule
//----------------------------------
// CPU Address Decoders
//----------------------------------
module VIDADEC
(
input [15:0] cpu_ad,
input cpu_wr,
output cpu_cs_palram,
output cpu_cs_spram,
output cpu_cs_mixcoll,
output cpu_cs_sprcoll,
output cpu_cs_vram0,
output cpu_cs_vram1,
output cpu_wr_palram,
output cpu_wr_spram,
output cpu_wr_mixcoll,
output cpu_wr_mixcollclr,
output cpu_wr_sprcoll,
output cpu_wr_sprcollclr,
output cpu_wr_vram0,
output cpu_wr_vram1,
output cpu_wr_scrreg,
output cpu_rd
);
assign cpu_cs_palram = ( cpu_ad[15:11] == 5'b1101_1 );
assign cpu_cs_spram = ( cpu_ad[15:11] == 5'b11010 );
assign cpu_cs_mixcoll = ( cpu_ad[15:10] == 6'b1111_00 );
wire cpu_cs_mixcollclr = ( cpu_ad[15:10] == 6'b1111_01 );
assign cpu_cs_sprcoll = ( cpu_ad[15:10] == 6'b1111_10 );
wire cpu_cs_sprcollclr = ( cpu_ad[15:10] == 6'b1111_11 );
assign cpu_cs_vram0 = ( cpu_ad[15:11] == 5'b11100 );
assign cpu_cs_vram1 = ( cpu_ad[15:11] == 5'b11101 );
wire cpu_cs_scrreg = ((cpu_ad[15: 0] & 16'b1111_1111_1011_1110) == 16'b1110_1111_1011_1100);
assign cpu_wr_palram = cpu_cs_palram & cpu_wr;
assign cpu_wr_spram = cpu_cs_spram & cpu_wr;
assign cpu_wr_mixcoll = cpu_cs_mixcoll & cpu_wr;
assign cpu_wr_mixcollclr = cpu_cs_mixcollclr & cpu_wr;
assign cpu_wr_sprcoll = cpu_cs_sprcoll & cpu_wr;
assign cpu_wr_sprcollclr = cpu_cs_sprcollclr & cpu_wr;
assign cpu_wr_vram0 = cpu_cs_vram0 & cpu_wr;
assign cpu_wr_vram1 = cpu_cs_vram1 & cpu_wr;
assign cpu_wr_scrreg = cpu_cs_scrreg & cpu_wr;
assign cpu_rd = cpu_cs_palram |
cpu_cs_vram0 |
cpu_cs_vram1 |
cpu_cs_spram |
cpu_cs_sprcoll |
cpu_cs_mixcoll ;
endmodule
//----------------------------------
// BG Scanline Generator
//----------------------------------
module BGGEN
(
input VCLK,
input [8:0] HP,
input [8:0] VP,
output [9:0] VRAMAD,
input [15:0] VRAMDT,
output [13:0] TILEAD,
input [23:0] TILEDT,
output [10:0] OPIX
);
assign VRAMAD = { VP[7:3], HP[7:3] };
assign TILEAD = { VRAMDT[15], VRAMDT[10:0], VP[2:0] };
reg [31:0] BGREG;
wire [23:0] BGCD = BGREG[23:0];
wire [7:0] BGPN = BGREG[31:24];
wire [31:0] BGPIX;
always @( posedge VCLK ) BGREG <= BGPIX;
dataselector1_32 pixsft(
BGPIX,
( HP[2:0] != 2 ),{ BGPN, BGCD[22:0], 1'b0 },
{ VRAMDT[12:5], TILEDT }
);
assign OPIX = { BGPN, BGCD[7], BGCD[15], BGCD[23] };
endmodule
//----------------------------------
// Color Mixer & RGB Output
//----------------------------------
module COLMIX
(
input VCLK,
input [10:0] BG0PX,
input [10:0] BG1PX,
input [10:0] SPRPX,
input PALDSW,
input [8:0] HPOS,
input [8:0] VPOS,
output [7:0] cltidx,
input [7:0] cltval,
output mixcoll,
output [5:0] mixcoll_ad,
output [10:0] palno,
input [7:0] palout,
output reg [7:0] RGB8
);
assign cltidx = { 1'b0,
BG0PX[10:9],(BG0PX[2:0]==0),
BG1PX[10:9],(BG1PX[2:0]==0),
(SPRPX[3:0]==0)
};
assign mixcoll = ~(cltval[2]);
assign mixcoll_ad = { cltval[3], SPRPX[8:4] };
wire [10:0] palno_i;
dataselector2_11 colsel(
palno_i,
cltval[1], ( 11'h400 | BG0PX[8:0] ),
cltval[0], ( 11'h200 | BG1PX[8:0] ),
( 11'h000 | SPRPX[8:0] )
);
wire [10:0] palno_d = {HPOS[7],VPOS[7:2],HPOS[6:3]};
assign palno = PALDSW ? palno_d : palno_i;
always @( negedge VCLK ) RGB8 <= palout;
endmodule
//----------------------------------
// Collision RAM
//----------------------------------
module COLLRAM_M
(
input cpu_cl,
input [5:0] cpu_ad,
input cpu_wr_coll,
input cpu_wr_collclr,
output [7:0] cpu_rd_coll,
input VCLKx4,
input [5:0] coll_ad,
input coll
);
reg [63:0] core;
reg coll_rd, coll_sm;
always @(posedge cpu_cl) coll_rd <= core[cpu_ad];
always @(posedge VCLKx4) begin
if (cpu_cl) begin
if (cpu_wr_coll) core[cpu_ad] <= 1'b0;
if (cpu_wr_collclr) coll_sm <= 1'b0;
end
else coll_sm <= coll;
if (coll) core[coll_ad] <= 1'b1;
end
assign cpu_rd_coll = { coll_sm, 6'b111111, coll_rd };
endmodule
module COLLRAM_S
(
input cpu_cl,
input [9:0] cpu_ad,
input cpu_wr_coll,
input cpu_wr_collclr,
output [7:0] cpu_rd_coll,
input VCLKx4,
input [9:0] coll_ad,
input coll
);
reg [1023:0] core;
reg coll_rd, coll_sm;
always @(posedge cpu_cl) coll_rd <= core[cpu_ad];
always @(posedge VCLKx4) begin
if (cpu_cl) begin
if (cpu_wr_coll) core[cpu_ad] <= 1'b0;
if (cpu_wr_collclr) coll_sm <= 1'b0;
end
else coll_sm <= coll;
if (coll) core[coll_ad] <= 1'b1;
end
assign cpu_rd_coll = { coll_sm, 6'b111111, coll_rd };
endmodule

282
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/Flicky_MiST.sv Normal file
View File

@@ -0,0 +1,282 @@
module Flicky_MiST(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl/build_id.v"
localparam CONF_STR = {
"FLICKY;ROM;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blend,Off,On;",
"O89,Lives,3,4,5,Infinite;",
"OAB,Extend,30k/80k/160k,30k/100k/200k,40k/120k/240k,40k/140k/280k;",
"OC,Difficulty,Easy,Hard;",
"T0,Reset;",
"V,v1.0.",`BUILD_DATE
};
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire [1:0] dsLives = ~status[9:8];
wire [1:0] dsExtend = ~status[11:10];
wire dsDifclt = ~status[12];
assign LED = ~ioctl_downl;
assign SDRAM_CLK = sdram_clk;
assign SDRAM_CKE = 1;
assign AUDIO_R = AUDIO_L;
wire clk_sys, sdram_clk;
wire pll_locked;
pll_mist pll(
.inclk0(CLOCK_27),
.c0(clk_sys),//48
.c1(sdram_clk),//96
.locked(pll_locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire key_pressed;
wire key_strobe;
wire [7:0] key_code;
wire scandoublerD;
wire ypbpr;
wire no_csync;
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
wire [15:0] audio;
wire hs, vs, cs, hb, vb;
wire blankn = ~(hb | vb);
wire [2:0] g, r;
wire [1:0] b;
wire [14:0] rom_addr;
wire [15:0] rom_do;
wire [14:0] spr_rom_addr;
wire [15:0] spr_rom_do;
wire [12:0] snd_rom_addr;
wire [15:0] snd_rom_do;
wire [13:0] tile_rom_addr;
wire [23:0] tile_rom_do;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
data_io data_io(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
reg port1_req, port2_req;
wire [24:0] tl_ioctl_addr = ioctl_addr - 17'h12000;
sdram sdram(
.*,
.init_n ( pll_locked ),
.clk ( sdram_clk ),
// port1 used for main + sound CPUs
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( ioctl_downl ? 16'hffff : {2'b00, rom_addr[14:1]}),
.cpu1_q ( rom_do ),
.cpu2_addr ( ioctl_downl ? 16'hffff : (16'h6000 + spr_rom_addr[14:1]) ),
.cpu2_q ( spr_rom_do ),
.cpu3_addr ( ioctl_downl ? 16'hffff : (16'h4000 + snd_rom_addr[12:1]) ),
.cpu3_q ( snd_rom_do ),
// port2 for sprite graphics
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( {tl_ioctl_addr[17:16], tl_ioctl_addr[13:0], tl_ioctl_addr[15]} ), // merge tile roms to 32-bit wide words
.port2_ds ( {tl_ioctl_addr[14], ~tl_ioctl_addr[14]} ),
.port2_we ( ioctl_downl ),
.port2_d ( {ioctl_dout, ioctl_dout} ),
.port2_q ( ),
.sp_addr ( ioctl_downl ? 15'h7fff : tile_rom_addr ),
.sp_q ( tile_rom_do )
);
always @(posedge clk_sys) begin
reg ioctl_wr_last = 0;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
port1_req <= ~port1_req;
port2_req <= ~port2_req;
end
end
end
reg reset = 1;
reg rom_loaded = 0;
always @(posedge sdram_clk) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ~rom_loaded;
end
wire [7:0] INP0 = ~{m_left, m_right,3'd0,m_fireA,2'd0};
wire [7:0] INP1 = ~{m_left2,m_right2,3'd0,m_fire2A,2'd0};
wire [7:0] INP2 = ~{2'd0,m_two_players, m_one_player,3'd0, m_coin1};
wire [7:0] DSW0 = 8'hFF;
wire [7:0] DSW1 = {dsDifclt,dsExtend,dsLives,2'b00};
FPGA_FLICKY FPGA_FLICKY(
.clk48M(clk_sys),
.reset(reset),
.INP0(INP0),
.INP1(INP1),
.INP2(INP2),
.DSW0(DSW0),
.DSW1(DSW1),
.video_r(r),
.video_g(g),
.video_b(b),
.video_hs(hs),
.video_vs(vs),
.video_hb(hb),
.video_vb(vb),
.cpu_rom_addr(rom_addr),
.cpu_rom_do( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
.snd_rom_addr(snd_rom_addr),
.snd_rom_do(snd_rom_addr[0] ? snd_rom_do[15:8] : snd_rom_do[7:0] ),
.spr_rom_addr(spr_rom_addr),//Internal for now
.spr_rom_do(spr_rom_addr[0] ? spr_rom_do[15:8] : spr_rom_do[7:0] ),
.tile_rom_addr(tile_rom_addr),
.tile_rom_do(tile_rom_do),
.SOUT(audio)
);
mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? r : 0 ),
.G ( blankn ? g : 0 ),
.B ( blankn ? {b,b[1]} : 0 ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.ce_divider ( 1'b0 ),
.blend ( blend ),
.rotate ( 2'b0 ),
.scandoubler_disable(scandoublerD ),
.scanlines ( scanlines ),
.ypbpr ( ypbpr ),
.no_csync ( no_csync )
);
dac #(
.C_bits(16))
dac(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(audio),
.dac_o(AUDIO_L)
);
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
arcade_inputs inputs (
.clk ( clk_sys ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( 1'b0 ),
.orientation ( 2'b00 ),
.joyswap ( 1'b0 ),
.oneplayer ( 1'b1 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
endmodule

41
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/Flicky_MiST.v Normal file
View File

@@ -0,0 +1,41 @@
module HVGEN
(
output [8:0] HPOS,
output [8:0] VPOS,
input PCLK,
input [14:0] iRGB,
output reg [14:0] oRGB,
output reg HBLK = 1,
output reg VBLK = 1,
output reg HSYN = 1,
output reg VSYN = 1
);
reg [8:0] hcnt = 0;
reg [8:0] vcnt = 0;
assign HPOS = hcnt-16;
assign VPOS = vcnt;
always @(posedge PCLK) begin
case (hcnt)
15: begin HBLK <= 0; hcnt <= hcnt+1; end
272: begin HBLK <= 1; hcnt <= hcnt+1; end
311: begin HSYN <= 0; hcnt <= hcnt+1; end
342: begin HSYN <= 1; hcnt <= 471; end
511: begin hcnt <= 0;
case (vcnt)
223: begin VBLK <= 1; vcnt <= vcnt+1; end
226: begin VSYN <= 0; vcnt <= vcnt+1; end
233: begin VSYN <= 1; vcnt <= 483; end
511: begin VBLK <= 0; vcnt <= 0; end
default: vcnt <= vcnt+1;
endcase
end
default: hcnt <= hcnt+1;
endcase
oRGB <= (HBLK|VBLK) ? 15'h0 : iRGB;
end
endmodule

174
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/SN76496.v Normal file
View File

@@ -0,0 +1,174 @@
// Copyright (c) 2017,19 MiSTer-X
module SN76496
(
input clk,
input cpuclk,
input reset,
input ce,
input we,
input [7:0] data,
input [3:0] chmsk,
output reg [7:0] sndout,
output reg [3:0] chactv,
output reg [2:0] lreg
);
`define RNGINI 16'h0F35
`define RNGFB0 16'h4000
`define RNGFB1 16'h8100
function [5:0] voltbl;
input [3:0] idx;
case (idx)
4'h0: voltbl = 63;
4'h1: voltbl = 50;
4'h2: voltbl = 40;
4'h3: voltbl = 32;
4'h4: voltbl = 25;
4'h5: voltbl = 20;
4'h6: voltbl = 16;
4'h7: voltbl = 13;
4'h8: voltbl = 10;
4'h9: voltbl = 8;
4'hA: voltbl = 6;
4'hB: voltbl = 5;
4'hC: voltbl = 4;
4'hD: voltbl = 3;
4'hE: voltbl = 2;
4'hF: voltbl = 0;
endcase
endfunction
reg [3:0] clks;
reg [2:0] nzc;
reg [9:0] fq0, fq1, fq2;
reg [9:0] fc0, fc1, fc2;
reg [5:0] fv0, fv1, fv2, fv3;
reg [5:0] _fv0,_fv1,_fv2,_fv3;
reg fo0, fo1, fo2;
reg [15:0] rng = `RNGINI;
wire [15:0] rfb = rng[0] ? ( nzc[2] ? `RNGFB1 : `RNGFB0 ) : 16'h0;
wire [1:0] nfq = nzc[1:0];
wire [10:0] fq3 = ( nfq == 2'b00 ) ? 64 :
( nfq == 2'b01 ) ? 128 :
( nfq == 2'b10 ) ? 256 : fq2;
reg [10:0] fc3;
wire fo3 = rng[0];
wire [7:0] o0 = ( fo0 & chmsk[0] ) ? { 1'b0, fv0, 1'b0 } : 8'h0;
wire [7:0] o1 = ( fo1 & chmsk[1] ) ? { 1'b0, fv1, 1'b0 } : 8'h0;
wire [7:0] o2 = ( fo2 & chmsk[2] ) ? { 1'b0, fv2, 1'b0 } : 8'h0;
wire [7:0] o3 = ( fo3 & chmsk[3] ) ? { 1'b0, fv3, 1'b0 } : 8'h0;
wire [8:0] sndmix = o0 + o1 + o2 + o3;
always @( posedge cpuclk or posedge reset ) begin
if ( reset ) begin
lreg <= 0;
_fv0 <= 0;
_fv1 <= 0;
_fv2 <= 0;
_fv3 <= 0;
fq0 <= 0;
fq1 <= 0;
fq2 <= 0;
nzc <= 0;
chactv <= 0;
end
else begin
// Register write
if ( ce & we ) begin
if ( data[7] ) begin
lreg <= data[6:4];
case ( data[6:4] )
3'h0: fq0[3:0] <= data[3:0];
3'h2: fq1[3:0] <= data[3:0];
3'h4: fq2[3:0] <= data[3:0];
3'h1: begin _fv0 <= voltbl(data[3:0]); chactv[0] <= (~data[3]); end
3'h3: begin _fv1 <= voltbl(data[3:0]); chactv[1] <= (~data[3]); end
3'h5: begin _fv2 <= voltbl(data[3:0]); chactv[2] <= (~data[3]); end
3'h7: begin _fv3 <= voltbl(data[3:0]); chactv[3] <= (~data[3]); end
3'h6: begin nzc <= data[2:0]; end
endcase
end
else begin
case ( lreg )
3'h0: fq0[9:4] <= data[5:0];
3'h2: fq1[9:4] <= data[5:0];
3'h4: fq2[9:4] <= data[5:0];
default: begin end
endcase
end
end
end
end
always @( posedge clk or posedge reset ) begin
// Reset
if ( reset ) begin
sndout <= 0;
fv0 <= 0;
fv1 <= 0;
fv2 <= 0;
fv3 <= 0;
fc0 <= 0;
fc1 <= 0;
fc2 <= 0;
fc3 <= 0;
fo0 <= 0;
fo1 <= 0;
fo2 <= 0;
clks <= 0;
rng <= `RNGINI;
end
else begin
// OSCs update
clks <= clks+1;
if ( clks == 0 ) begin
fv0 <= _fv0;
fv1 <= _fv1;
fv2 <= _fv2;
fv3 <= _fv3;
if ( fc0 == 0 ) begin
fc0 <= fq0;
fo0 <= ~fo0;
end
else fc0 <= fc0-1;
if ( fc1 == 0 ) begin
fc1 <= fq1;
fo1 <= ~fo1;
end
else fc1 <= fc1-1;
if ( fc2 == 0 ) begin
fc2 <= fq2;
fo2 <= ~fo2;
end
else fc2 <= fc2-1;
// NoiseGen update
if ( fc3 == 0 ) begin
fc3 <= fq3;
rng <= { 1'b0, rng[15:1] } ^ rfb;
end
else fc3 <= fc3-1;
// Sound update
sndout <= {8{sndmix[8]}}|(sndmix[7:0]);
end
end
end
endmodule

35
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/build_id.tcl Normal file
View File

@@ -0,0 +1,35 @@
# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

41
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/hvgen.v Normal file
View File

@@ -0,0 +1,41 @@
module hvgen
(
output [8:0] HPOS,
output [8:0] VPOS,
input PCLK,
input [14:0] iRGB,
output reg [14:0] oRGB,
output reg HBLK = 1,
output reg VBLK = 1,
output reg HSYN = 1,
output reg VSYN = 1
);
reg [8:0] hcnt = 0;
reg [8:0] vcnt = 0;
assign HPOS = hcnt-16;
assign VPOS = vcnt;
always @(posedge PCLK) begin
case (hcnt)
15: begin HBLK <= 0; hcnt <= hcnt+1; end
272: begin HBLK <= 1; hcnt <= hcnt+1; end
311: begin HSYN <= 0; hcnt <= hcnt+1; end
342: begin HSYN <= 1; hcnt <= 471; end
511: begin hcnt <= 0;
case (vcnt)
223: begin VBLK <= 1; vcnt <= vcnt+1; end
226: begin VSYN <= 0; vcnt <= vcnt+1; end
233: begin VSYN <= 1; vcnt <= 483; end
511: begin VBLK <= 0; vcnt <= 0; end
default: vcnt <= vcnt+1;
endcase
end
default: hcnt <= hcnt+1;
endcase
oRGB <= (HBLK|VBLK) ? 15'h0 : iRGB;
end
endmodule

389
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/parts.v Normal file
View File

@@ -0,0 +1,389 @@
// Copyright (c) 2017,19 MiSTer-X
/*
module DLROM #(parameter AW,parameter DW)
(
input CL0,
input [(AW-1):0] AD0,
output reg [(DW-1):0] DO0,
input CL1,
input [(AW-1):0] AD1,
input [(DW-1):0] DI1,
input WE1
);
reg [(DW-1):0] core[0:((2**AW)-1)];
always @(posedge CL0) DO0 <= core[AD0];
always @(posedge CL1) if (WE1) core[AD1] <= DI1;
endmodule*/
//----------------------------------
// 2K SRAM
//----------------------------------
module SRAM_2048( CL, ADRS, OUT, WR, IN );
input CL;
input [10:0] ADRS;
output [7:0] OUT;
input WR;
input [7:0] IN;
reg [7:0] ramcore [0:2047];
reg [7:0] OUT;
always @( posedge CL ) begin
if (WR) ramcore[ADRS] <= IN;
else OUT <= ramcore[ADRS];
end
endmodule
//----------------------------------
// 4K SRAM
//----------------------------------
module SRAM_4096(
input clk,
input [11:0] adrs,
output reg [7:0] out,
input wr,
input [7:0] in
);
reg [7:0] ramcore [0:4095];
always @( posedge clk ) begin
if (wr) ramcore[adrs] <= in;
else out <= ramcore[adrs];
end
endmodule
//----------------------------------
// DualPort RAM
//----------------------------------
module DPRAM2048
(
input clk0,
input [10:0] adr0,
input [7:0] dat0,
input wen0,
input clk1,
input [10:0] adr1,
output reg [7:0] dat1,
output reg [7:0] dtr0
);
reg [7:0] core [0:2047];
always @( posedge clk0 ) begin
if (wen0) core[adr0] <= dat0;
else dtr0 <= core[adr0];
end
always @( posedge clk1 ) begin
dat1 <= core[adr1];
end
endmodule
module DPRAM1024
(
input clk0,
input [9:0] adr0,
input [7:0] dat0,
input wen0,
input clk1,
input [9:0] adr1,
output reg [7:0] dat1,
output reg [7:0] dtr0
);
reg [7:0] core [0:1023];
always @( posedge clk0 ) begin
if (wen0) core[adr0] <= dat0;
else dtr0 <= core[adr0];
end
always @( posedge clk1 ) begin
dat1 <= core[adr1];
end
endmodule
module DPRAM2048_8_16
(
input clk0,
input [10:0] adr0,
input [7:0] dat0,
input wen0,
input clk1,
input [9:0] adr1,
output [15:0] dat1,
output [7:0] dtr0
);
wire [7:0] do0, do1;
wire [7:0] doH, doL;
DPRAM1024 core0( clk0, adr0[10:1], dat0, wen0 & (~adr0[0]), clk1, adr1, doL, do0 );
DPRAM1024 core1( clk0, adr0[10:1], dat0, wen0 & adr0[0], clk1, adr1, doH, do1 );
assign dtr0 = adr0[0] ? do1 : do0;
assign dat1 = { doH, doL };
endmodule
//----------------------------------
// VRAM
//----------------------------------
module VRAMs
(
input clk0,
input [9:0] adr0,
output reg [7:0] dat0,
input [7:0] dtw0,
input wen0,
input clk1,
input [9:0] adr1,
output reg [7:0] dat1
);
reg [7:0] core [0:1023];
always @( posedge clk0 ) begin
if (wen0) core[adr0] <= dtw0;
else dat0 <= core[adr0];
end
always @( posedge clk1 ) begin
dat1 <= core[adr1];
end
endmodule
module VRAM
(
input clk0,
input [10:0] adr0,
output [7:0] dat0,
input [7:0] dtw0,
input wen0,
input clk1,
input [9:0] adr1,
output [15:0] dat1
);
wire even = ~adr0[0];
wire odd = adr0[0];
wire [7:0] do00, do01, do10, do11;
VRAMs ram0( clk0, adr0[10:1], do00, dtw0, wen0 & even, clk1, adr1, do10 );
VRAMs ram1( clk0, adr0[10:1], do01, dtw0, wen0 & odd, clk1, adr1, do11 );
assign dat0 = adr0[0] ? do01 : do00;
assign dat1 = { do11, do10 };
endmodule
//----------------------------------
// ScanLine Buffer
//----------------------------------
module LineBuf
(
input clkr,
input [9:0] radr,
input clre,
output [10:0] rdat,
input clkw,
input [9:0] wadr,
input [10:0] wdat,
input we,
output [10:0] rdat1
);
DPRAM1024_11B core (
radr,wadr,
clkr,clkw,
16'h0,{5'h0,wdat},
clre,we,
rdat,rdat1
);
endmodule
//----------------------------------
// Data Selector (32bits)
//----------------------------------
module dataselector1_32(
output [31:0] oDATA,
input iSEL0,
input [31:0] iDATA0,
input [31:0] dData
);
assign oDATA = iSEL0 ? iDATA0 :
dData;
endmodule
//----------------------------------
// Data Selector 3 to 1
//----------------------------------
module dataselector3(
output [7:0] oDATA,
input iSEL0,
input [7:0] iDATA0,
input iSEL1,
input [7:0] iDATA1,
input iSEL2,
input [7:0] iDATA2,
input [7:0] dData
);
assign oDATA = iSEL0 ? iDATA0 :
iSEL1 ? iDATA1 :
iSEL2 ? iDATA2 :
dData;
endmodule
//----------------------------------
// Data Selector 2 to 1 (11bits)
//----------------------------------
module dataselector2_11(
output [10:0] oDATA,
input iSEL0,
input [10:0] iDATA0,
input iSEL1,
input [10:0] iDATA1,
input [10:0] dData
);
assign oDATA = iSEL0 ? iDATA0 :
iSEL1 ? iDATA1 :
dData;
endmodule
//----------------------------------
// Data Selector 8 to 1
//----------------------------------
module dataselector8(
output [7:0] oDATA,
input iSEL0,
input [7:0] iDATA0,
input iSEL1,
input [7:0] iDATA1,
input iSEL2,
input [7:0] iDATA2,
input iSEL3,
input [7:0] iDATA3,
input iSEL4,
input [7:0] iDATA4,
input iSEL5,
input [7:0] iDATA5,
input iSEL6,
input [7:0] iDATA6,
input iSEL7,
input [7:0] iDATA7,
input [7:0] dData
);
assign oDATA = iSEL0 ? iDATA0 :
iSEL1 ? iDATA1 :
iSEL2 ? iDATA2 :
iSEL3 ? iDATA3 :
iSEL4 ? iDATA4 :
iSEL5 ? iDATA5 :
iSEL6 ? iDATA6 :
iSEL7 ? iDATA7 :
dData;
endmodule
//----------------------------------
// Data Selector 6 to 1
//----------------------------------
module dataselector6(
output [7:0] oDATA,
input iSEL0,
input [7:0] iDATA0,
input iSEL1,
input [7:0] iDATA1,
input iSEL2,
input [7:0] iDATA2,
input iSEL3,
input [7:0] iDATA3,
input iSEL4,
input [7:0] iDATA4,
input iSEL5,
input [7:0] iDATA5,
input [7:0] dData
);
assign oDATA = iSEL0 ? iDATA0 :
iSEL1 ? iDATA1 :
iSEL2 ? iDATA2 :
iSEL3 ? iDATA3 :
iSEL4 ? iDATA4 :
iSEL5 ? iDATA5 :
dData;
endmodule

4
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/pll_mist.qip Normal file
View File

@@ -0,0 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_mist.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]

337
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/pll_mist.v Normal file
View File

@@ -0,0 +1,337 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_mist.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_mist (
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 9,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 16,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 9,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 32,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_mist",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "96.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "32"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "96.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "32"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

38
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/rom/clut.vhd Normal file
View File

@@ -0,0 +1,38 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity clut is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of clut is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"0C",X"0E",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0E",X"0C",X"0E",X"01",X"0D",X"0C",X"0E",
X"0C",X"0D",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0D",X"0C",X"0E",X"01",X"0D",X"0C",X"0E",
X"0E",X"0E",X"0E",X"0E",X"0D",X"0D",X"0E",X"0E",X"02",X"0E",X"0E",X"0E",X"01",X"0D",X"0E",X"0E",
X"0C",X"0D",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0D",X"0C",X"0E",X"01",X"0D",X"0C",X"0E",
X"08",X"0E",X"08",X"0E",X"09",X"0D",X"08",X"0E",X"08",X"0E",X"08",X"0E",X"09",X"0D",X"08",X"0E",
X"0C",X"0D",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0D",X"0C",X"0E",X"01",X"0D",X"0C",X"0E",
X"0A",X"0E",X"0A",X"0E",X"09",X"0D",X"0A",X"0E",X"0A",X"0E",X"0A",X"0E",X"09",X"0D",X"0A",X"0E",
X"0C",X"0D",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0D",X"0C",X"0E",X"01",X"0D",X"0C",X"0E",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

BIN
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/rom/dec_flicky.bin Normal file
View File

Binary file not shown.

30
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/rom/dec_rom.vhd Normal file
View File

@@ -0,0 +1,30 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity dec_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(6 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of dec_rom is
type rom is array(0 to 127) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"08",X"88",X"00",X"80",X"A0",X"80",X"A8",X"88",X"80",X"00",X"A0",X"20",X"88",X"80",X"08",X"00",
X"A0",X"80",X"A8",X"88",X"28",X"08",X"20",X"00",X"28",X"08",X"20",X"00",X"A0",X"80",X"A8",X"88",
X"08",X"88",X"00",X"80",X"80",X"00",X"A0",X"20",X"80",X"00",X"A0",X"20",X"88",X"80",X"08",X"00",
X"28",X"08",X"20",X"00",X"28",X"08",X"20",X"00",X"28",X"08",X"20",X"00",X"88",X"80",X"08",X"00",
X"08",X"88",X"00",X"80",X"A8",X"88",X"28",X"08",X"A8",X"88",X"28",X"08",X"80",X"00",X"A0",X"20",
X"28",X"08",X"20",X"00",X"88",X"80",X"08",X"00",X"A8",X"88",X"28",X"08",X"88",X"80",X"08",X"00",
X"08",X"88",X"00",X"80",X"80",X"00",X"A0",X"20",X"A8",X"88",X"28",X"08",X"80",X"00",X"A0",X"20",
X"28",X"08",X"20",X"00",X"28",X"08",X"20",X"00",X"08",X"88",X"00",X"80",X"88",X"80",X"08",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

19
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/rom/make.bat Normal file
View File

@@ -0,0 +1,19 @@
copy /b epr5978a.116 + epr5979a.109 prg.bin
make_vhdl_prom prg.bin prg_rom.vhd
copy /b epr-5855.117 + epr-5856.110 spr.bin
make_vhdl_prom spr.bin spr_rom.vhd
make_vhdl_prom epr-5869.120 snd_rom.vhd
make_vhdl_prom dec_flicky.bin dec_rom.vhd
make_vhdl_prom epr-5868.62 tile1.vhd
make_vhdl_prom pr-5317.76 clut.vhd
copy /b epr-5868.62 + epr-5867.61 + epr-5866.64 + epr-5865.63 + epr-5864.66 + epr-5863.65 tile.bin
copy /b prg.bin + epr-5869.120 + spr.bin + tile.bin FLICKY.ROM
pause

2070
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/rom/prg_rom.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

534
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/rom/snd_rom.vhd Normal file
View File

@@ -0,0 +1,534 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity snd_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of snd_rom is
type rom is array(0 to 8191) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"F3",X"ED",X"56",X"31",X"00",X"84",X"C3",X"7E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"09",X"38",X"30",X"48",
X"2C",X"31",X"33",X"48",X"2C",X"30",X"2C",X"30",X"F5",X"3E",X"01",X"32",X"10",X"80",X"F1",X"FB",
X"C9",X"44",X"45",X"46",X"57",X"09",X"54",X"41",X"42",X"30",X"30",X"0D",X"0A",X"09",X"44",X"45",
X"46",X"42",X"09",X"30",X"2C",X"46",X"4C",X"47",X"56",X"4F",X"4C",X"2C",X"30",X"2C",X"30",X"0D",
X"0A",X"0D",X"0A",X"0D",X"0A",X"54",X"F5",X"E5",X"3A",X"00",X"E0",X"2A",X"11",X"80",X"77",X"23",
X"CB",X"65",X"28",X"03",X"21",X"00",X"80",X"22",X"11",X"80",X"E1",X"F1",X"ED",X"45",X"CD",X"98",
X"04",X"21",X"00",X"80",X"11",X"01",X"80",X"01",X"FF",X"07",X"36",X"00",X"ED",X"B0",X"21",X"12",
X"80",X"36",X"80",X"21",X"00",X"80",X"11",X"01",X"80",X"01",X"0F",X"00",X"36",X"80",X"ED",X"B0",
X"FB",X"CD",X"B3",X"04",X"3A",X"10",X"80",X"A7",X"28",X"F7",X"AF",X"32",X"10",X"80",X"DD",X"21",
X"30",X"80",X"06",X"10",X"C5",X"DD",X"CB",X"00",X"7E",X"C4",X"C7",X"00",X"11",X"20",X"00",X"DD",
X"19",X"C1",X"10",X"F0",X"C3",X"A1",X"00",X"DD",X"5E",X"03",X"DD",X"56",X"04",X"13",X"DD",X"73",
X"03",X"DD",X"72",X"04",X"DD",X"6E",X"05",X"DD",X"66",X"06",X"B7",X"ED",X"52",X"CC",X"4D",X"02",
X"DD",X"CB",X"03",X"46",X"C0",X"DD",X"5E",X"11",X"DD",X"56",X"12",X"7B",X"B2",X"20",X"07",X"DD",
X"36",X"17",X"0F",X"C3",X"C2",X"01",X"DD",X"CB",X"00",X"6E",X"20",X"33",X"DD",X"7E",X"0B",X"B7",
X"20",X"08",X"DD",X"73",X"13",X"DD",X"72",X"14",X"18",X"59",X"3D",X"21",X"79",X"07",X"23",X"DD",
X"4E",X"0E",X"06",X"00",X"09",X"09",X"4E",X"23",X"66",X"69",X"0E",X"04",X"09",X"4E",X"23",X"66",
X"69",X"4F",X"06",X"00",X"09",X"09",X"7E",X"23",X"66",X"6F",X"CD",X"1A",X"02",X"18",X"34",X"D5",
X"DD",X"6E",X"15",X"DD",X"66",X"16",X"B7",X"ED",X"52",X"F5",X"7D",X"F2",X"40",X"01",X"ED",X"44",
X"67",X"DD",X"5E",X"03",X"CD",X"5A",X"07",X"DD",X"5E",X"05",X"CD",X"66",X"07",X"5F",X"16",X"00",
X"F1",X"7B",X"F2",X"5B",X"01",X"ED",X"44",X"28",X"02",X"15",X"5F",X"E1",X"19",X"DD",X"75",X"13",
X"DD",X"74",X"14",X"DD",X"7E",X"0C",X"B7",X"20",X"0B",X"DD",X"7E",X"0D",X"2F",X"E6",X"0F",X"DD",
X"77",X"17",X"18",X"23",X"3D",X"21",X"79",X"07",X"23",X"DD",X"4E",X"0E",X"06",X"00",X"09",X"09",
X"4E",X"23",X"66",X"69",X"0E",X"02",X"09",X"4E",X"23",X"66",X"69",X"4F",X"06",X"00",X"09",X"09",
X"7E",X"23",X"66",X"6F",X"CD",X"E0",X"01",X"DD",X"CB",X"00",X"76",X"20",X"25",X"DD",X"7E",X"01",
X"E6",X"0F",X"4F",X"06",X"00",X"21",X"D5",X"01",X"09",X"4E",X"DD",X"7E",X"13",X"E6",X"0F",X"B1",
X"CD",X"5C",X"04",X"DD",X"7E",X"13",X"E6",X"F0",X"DD",X"B6",X"14",X"0F",X"0F",X"0F",X"0F",X"CD",
X"5C",X"04",X"DD",X"7E",X"01",X"E6",X"0F",X"4F",X"06",X"00",X"21",X"D9",X"01",X"09",X"7E",X"DD",
X"B6",X"17",X"C3",X"5C",X"04",X"80",X"A0",X"C0",X"C0",X"90",X"B0",X"D0",X"F0",X"DD",X"77",X"0F",
X"E5",X"DD",X"7E",X"0F",X"CB",X"3F",X"F5",X"4F",X"06",X"00",X"09",X"F1",X"7E",X"E1",X"38",X"14",
X"0F",X"0F",X"0F",X"0F",X"B7",X"28",X"E6",X"FE",X"10",X"20",X"05",X"DD",X"35",X"0F",X"18",X"E0",
X"FE",X"20",X"28",X"0B",X"DD",X"34",X"0F",X"F6",X"F0",X"DD",X"86",X"0D",X"3C",X"38",X"01",X"AF",
X"2F",X"E6",X"0F",X"DD",X"77",X"17",X"C9",X"DD",X"77",X"10",X"E5",X"DD",X"7E",X"10",X"CB",X"3F",
X"F5",X"4F",X"06",X"00",X"09",X"F1",X"7E",X"E1",X"38",X"11",X"0F",X"0F",X"0F",X"0F",X"B7",X"CA",
X"17",X"02",X"FE",X"10",X"20",X"05",X"DD",X"35",X"10",X"18",X"DF",X"DD",X"34",X"10",X"2F",X"E6",
X"0F",X"6F",X"26",X"00",X"EB",X"19",X"DD",X"75",X"13",X"DD",X"74",X"14",X"C9",X"DD",X"5E",X"07",
X"DD",X"56",X"08",X"1A",X"13",X"B7",X"FA",X"D2",X"02",X"DD",X"CB",X"00",X"5E",X"20",X"59",X"B7",
X"28",X"03",X"DD",X"86",X"09",X"21",X"C6",X"06",X"4F",X"06",X"00",X"09",X"09",X"7E",X"DD",X"77",
X"11",X"23",X"7E",X"DD",X"77",X"12",X"DD",X"CB",X"00",X"6E",X"28",X"16",X"1A",X"13",X"DD",X"86",
X"09",X"21",X"C6",X"06",X"4F",X"06",X"00",X"09",X"09",X"7E",X"DD",X"77",X"15",X"23",X"7E",X"DD",
X"77",X"16",X"D5",X"1A",X"67",X"DD",X"5E",X"02",X"CD",X"5A",X"07",X"D1",X"DD",X"75",X"05",X"DD",
X"74",X"06",X"AF",X"DD",X"77",X"0F",X"DD",X"77",X"10",X"13",X"DD",X"73",X"07",X"DD",X"72",X"08",
X"AF",X"DD",X"77",X"03",X"DD",X"77",X"04",X"C9",X"DD",X"77",X"12",X"1A",X"13",X"DD",X"77",X"11",
X"DD",X"CB",X"00",X"6E",X"28",X"CC",X"1A",X"13",X"DD",X"77",X"16",X"1A",X"13",X"DD",X"77",X"15",
X"18",X"C0",X"21",X"E5",X"02",X"E5",X"E6",X"3F",X"21",X"E9",X"02",X"4F",X"06",X"00",X"09",X"09",
X"7E",X"23",X"66",X"6F",X"E9",X"13",X"C3",X"53",X"02",X"C4",X"03",X"1D",X"03",X"22",X"03",X"37",
X"03",X"E9",X"03",X"4B",X"03",X"62",X"03",X"67",X"03",X"72",X"03",X"8D",X"03",X"6C",X"03",X"A0",
X"03",X"A8",X"03",X"C0",X"03",X"C6",X"03",X"CC",X"03",X"D2",X"03",X"D8",X"03",X"E0",X"03",X"F3",
X"03",X"00",X"04",X"15",X"04",X"1D",X"04",X"25",X"04",X"34",X"04",X"45",X"04",X"1A",X"DD",X"77",
X"02",X"C9",X"1A",X"DD",X"77",X"0D",X"C9",X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"07",X"08",
X"06",X"05",X"04",X"03",X"02",X"01",X"00",X"1A",X"D5",X"5F",X"DD",X"66",X"02",X"CD",X"5A",X"07",
X"DD",X"75",X"03",X"DD",X"74",X"04",X"D1",X"E1",X"C3",X"A9",X"02",X"1A",X"F6",X"E0",X"F5",X"CD",
X"5C",X"04",X"F1",X"F6",X"FC",X"3C",X"20",X"05",X"DD",X"CB",X"00",X"B6",X"C9",X"DD",X"CB",X"00",
X"F6",X"C9",X"1A",X"DD",X"77",X"0C",X"C9",X"1A",X"DD",X"77",X"0B",X"C9",X"EB",X"5E",X"23",X"56",
X"1B",X"C9",X"1A",X"4F",X"13",X"1A",X"47",X"C5",X"DD",X"E5",X"E1",X"DD",X"35",X"0A",X"DD",X"4E",
X"0A",X"DD",X"35",X"0A",X"06",X"00",X"09",X"72",X"2B",X"73",X"D1",X"1B",X"C9",X"DD",X"E5",X"E1",
X"DD",X"4E",X"0A",X"06",X"00",X"09",X"5E",X"23",X"56",X"DD",X"34",X"0A",X"DD",X"34",X"0A",X"C9",
X"1A",X"DD",X"86",X"09",X"DD",X"77",X"09",X"C9",X"1A",X"13",X"C6",X"18",X"4F",X"06",X"00",X"DD",
X"E5",X"E1",X"09",X"7E",X"B7",X"20",X"02",X"1A",X"77",X"13",X"35",X"C2",X"6C",X"03",X"13",X"C9",
X"DD",X"CB",X"00",X"EE",X"1B",X"C9",X"DD",X"CB",X"00",X"AE",X"1B",X"C9",X"DD",X"CB",X"00",X"DE",
X"1B",X"C9",X"DD",X"CB",X"00",X"9E",X"1B",X"C9",X"1A",X"DD",X"B6",X"00",X"DD",X"77",X"00",X"C9",
X"1A",X"2F",X"DD",X"A6",X"00",X"DD",X"77",X"00",X"C9",X"CD",X"4D",X"04",X"DD",X"36",X"00",X"00",
X"E1",X"E1",X"C9",X"21",X"20",X"80",X"CB",X"96",X"21",X"90",X"80",X"CB",X"96",X"C3",X"E9",X"03",
X"21",X"20",X"80",X"36",X"00",X"06",X"04",X"11",X"20",X"00",X"21",X"30",X"80",X"CB",X"96",X"19",
X"10",X"FB",X"C3",X"E9",X"03",X"21",X"90",X"80",X"CB",X"96",X"C3",X"E9",X"03",X"21",X"30",X"80",
X"CB",X"96",X"C3",X"E9",X"03",X"21",X"20",X"80",X"CB",X"9E",X"CB",X"96",X"21",X"90",X"80",X"CB",
X"96",X"C3",X"E9",X"03",X"21",X"20",X"80",X"CB",X"A6",X"CB",X"9E",X"CB",X"96",X"21",X"90",X"80",
X"CB",X"96",X"C3",X"E9",X"03",X"21",X"70",X"80",X"CB",X"96",X"C3",X"E9",X"03",X"DD",X"7E",X"01",
X"E6",X"0F",X"4F",X"06",X"00",X"21",X"D9",X"01",X"09",X"7E",X"F6",X"0F",X"DD",X"CB",X"00",X"56",
X"C0",X"ED",X"47",X"DD",X"7E",X"01",X"E6",X"F0",X"FE",X"10",X"28",X"06",X"ED",X"57",X"32",X"00",
X"C0",X"C9",X"ED",X"57",X"32",X"00",X"A0",X"C9",X"E5",X"21",X"00",X"80",X"11",X"01",X"80",X"01",
X"0F",X"00",X"36",X"80",X"ED",X"B0",X"CD",X"8B",X"04",X"E1",X"C9",X"21",X"30",X"80",X"11",X"31",
X"80",X"01",X"FF",X"01",X"36",X"00",X"ED",X"B0",X"21",X"AF",X"04",X"11",X"00",X"A0",X"01",X"04",
X"00",X"ED",X"B0",X"21",X"AF",X"04",X"11",X"00",X"C0",X"01",X"04",X"00",X"ED",X"B0",X"C9",X"9F",
X"BF",X"DF",X"FF",X"06",X"10",X"21",X"00",X"80",X"7E",X"A7",X"28",X"BC",X"FE",X"80",X"28",X"09",
X"36",X"80",X"C5",X"E5",X"CD",X"CD",X"04",X"E1",X"C1",X"23",X"10",X"EC",X"C9",X"21",X"F4",X"04",
X"01",X"13",X"00",X"ED",X"B9",X"C0",X"21",X"F5",X"04",X"09",X"09",X"7E",X"23",X"66",X"6F",X"79",
X"08",X"E9",X"81",X"82",X"83",X"84",X"85",X"86",X"87",X"88",X"89",X"8A",X"8B",X"8C",X"8D",X"8E",
X"8F",X"90",X"91",X"92",X"93",X"1B",X"05",X"2F",X"05",X"43",X"05",X"6E",X"05",X"57",X"05",X"8F",
X"05",X"A3",X"05",X"B7",X"05",X"D0",X"05",X"E4",X"05",X"0B",X"06",X"24",X"06",X"25",X"06",X"26",
X"06",X"37",X"06",X"48",X"06",X"5F",X"06",X"78",X"06",X"79",X"06",X"CD",X"8B",X"04",X"21",X"20",
X"80",X"36",X"00",X"23",X"36",X"00",X"21",X"A1",X"07",X"11",X"30",X"80",X"C3",X"A4",X"06",X"CD",
X"8B",X"04",X"21",X"20",X"80",X"36",X"00",X"23",X"36",X"00",X"21",X"D9",X"08",X"11",X"30",X"80",
X"C3",X"A4",X"06",X"CD",X"8B",X"04",X"21",X"20",X"80",X"36",X"00",X"23",X"36",X"00",X"21",X"95",
X"0C",X"11",X"30",X"80",X"C3",X"A4",X"06",X"21",X"20",X"80",X"3A",X"20",X"80",X"E6",X"C0",X"C0",
X"CB",X"EE",X"CD",X"94",X"06",X"21",X"A7",X"10",X"11",X"30",X"81",X"C3",X"A4",X"06",X"3A",X"21",
X"80",X"CB",X"7F",X"C2",X"EA",X"05",X"21",X"20",X"80",X"3A",X"20",X"80",X"E6",X"F8",X"C0",X"CB",
X"D6",X"21",X"90",X"80",X"CB",X"D6",X"21",X"EB",X"0F",X"11",X"30",X"81",X"C3",X"A4",X"06",X"CD",
X"8B",X"04",X"21",X"20",X"80",X"36",X"00",X"23",X"36",X"00",X"21",X"F2",X"10",X"11",X"30",X"80",
X"C3",X"A4",X"06",X"CD",X"8B",X"04",X"21",X"20",X"80",X"36",X"00",X"23",X"36",X"00",X"21",X"10",
X"12",X"11",X"30",X"80",X"C3",X"A4",X"06",X"21",X"21",X"80",X"CB",X"FE",X"3A",X"20",X"80",X"E6",
X"FC",X"C0",X"21",X"90",X"80",X"CB",X"D6",X"21",X"2C",X"13",X"11",X"30",X"81",X"C3",X"A4",X"06",
X"3A",X"20",X"80",X"E6",X"E0",X"C0",X"21",X"30",X"80",X"CB",X"D6",X"21",X"A1",X"13",X"11",X"B0",
X"81",X"C3",X"A4",X"06",X"21",X"21",X"80",X"CB",X"7E",X"C8",X"21",X"21",X"80",X"CB",X"BE",X"21",
X"20",X"80",X"3A",X"20",X"80",X"E6",X"F8",X"C0",X"CB",X"D6",X"21",X"90",X"80",X"CB",X"D6",X"21",
X"25",X"14",X"11",X"30",X"81",X"3E",X"09",X"08",X"C3",X"A4",X"06",X"21",X"20",X"80",X"3A",X"20",
X"80",X"E6",X"F0",X"C0",X"CB",X"DE",X"21",X"90",X"80",X"CB",X"D6",X"21",X"39",X"15",X"11",X"30",
X"81",X"C3",X"A4",X"06",X"C9",X"C9",X"CD",X"8B",X"04",X"21",X"20",X"80",X"36",X"00",X"21",X"1F",
X"16",X"11",X"30",X"80",X"C3",X"A4",X"06",X"21",X"20",X"80",X"CB",X"FE",X"CD",X"94",X"06",X"21",
X"AE",X"16",X"11",X"30",X"81",X"C3",X"A4",X"06",X"21",X"20",X"80",X"3A",X"20",X"80",X"E6",X"80",
X"C0",X"CB",X"F6",X"CD",X"94",X"06",X"21",X"29",X"17",X"11",X"30",X"81",X"C3",X"A4",X"06",X"21",
X"20",X"80",X"3A",X"20",X"80",X"E6",X"E0",X"C0",X"CB",X"CE",X"21",X"90",X"80",X"CB",X"D6",X"21",
X"D2",X"17",X"11",X"30",X"81",X"C3",X"A4",X"06",X"C9",X"21",X"20",X"80",X"3A",X"20",X"80",X"E6",
X"E0",X"C0",X"21",X"70",X"80",X"CB",X"D6",X"21",X"A3",X"18",X"11",X"F0",X"81",X"C3",X"A4",X"06",
X"06",X"04",X"18",X"02",X"06",X"10",X"11",X"20",X"00",X"21",X"30",X"80",X"CB",X"D6",X"19",X"10",
X"FB",X"C3",X"98",X"04",X"7E",X"23",X"66",X"6F",X"46",X"23",X"C5",X"7E",X"23",X"E5",X"66",X"6F",
X"01",X"0E",X"00",X"ED",X"B0",X"08",X"12",X"08",X"13",X"AF",X"06",X"11",X"12",X"13",X"10",X"FC",
X"E1",X"23",X"C1",X"10",X"E5",X"C9",X"00",X"00",X"FF",X"03",X"C7",X"03",X"90",X"03",X"5D",X"03",
X"2D",X"03",X"FF",X"02",X"D4",X"02",X"AB",X"02",X"85",X"02",X"61",X"02",X"3F",X"02",X"1E",X"02",
X"00",X"02",X"E3",X"01",X"C8",X"01",X"AF",X"01",X"96",X"01",X"80",X"01",X"6A",X"01",X"56",X"01",
X"43",X"01",X"30",X"01",X"1F",X"01",X"0F",X"01",X"00",X"01",X"F2",X"00",X"E4",X"00",X"D7",X"00",
X"CB",X"00",X"C0",X"00",X"B5",X"00",X"AB",X"00",X"A1",X"00",X"98",X"00",X"90",X"00",X"88",X"00",
X"80",X"00",X"79",X"00",X"72",X"00",X"6C",X"00",X"66",X"00",X"60",X"00",X"5B",X"00",X"55",X"00",
X"51",X"00",X"4C",X"00",X"48",X"00",X"44",X"00",X"40",X"00",X"3C",X"00",X"39",X"00",X"36",X"00",
X"33",X"00",X"30",X"00",X"2D",X"00",X"2B",X"00",X"28",X"00",X"26",X"00",X"24",X"00",X"22",X"00",
X"20",X"00",X"1E",X"00",X"1C",X"00",X"1B",X"00",X"19",X"00",X"18",X"00",X"16",X"00",X"15",X"00",
X"13",X"00",X"12",X"00",X"11",X"00",X"10",X"00",X"0F",X"00",X"16",X"00",X"6A",X"06",X"08",X"29",
X"30",X"01",X"19",X"10",X"FA",X"C9",X"06",X"08",X"ED",X"6A",X"7C",X"38",X"03",X"BB",X"38",X"03",
X"93",X"67",X"B7",X"10",X"F3",X"7D",X"17",X"2F",X"C9",X"13",X"A1",X"07",X"D9",X"08",X"95",X"0C",
X"EB",X"0F",X"A7",X"10",X"F2",X"10",X"10",X"12",X"2C",X"13",X"A1",X"13",X"25",X"14",X"39",X"15",
X"C1",X"15",X"DB",X"15",X"1F",X"16",X"AE",X"16",X"29",X"17",X"D2",X"17",X"36",X"18",X"A3",X"18",
X"FF",X"A5",X"07",X"CA",X"08",X"04",X"AE",X"07",X"BB",X"07",X"C8",X"07",X"D5",X"07",X"80",X"10",
X"00",X"00",X"00",X"01",X"00",X"E2",X"07",X"07",X"20",X"00",X"00",X"80",X"11",X"00",X"00",X"00",
X"01",X"00",X"F7",X"07",X"07",X"20",X"00",X"00",X"80",X"12",X"00",X"00",X"00",X"01",X"00",X"21",
X"08",X"07",X"20",X"00",X"00",X"80",X"22",X"00",X"00",X"00",X"01",X"00",X"0C",X"08",X"EF",X"20",
X"00",X"00",X"82",X"0D",X"81",X"14",X"86",X"01",X"88",X"36",X"08",X"88",X"45",X"08",X"88",X"52",
X"08",X"88",X"5D",X"08",X"8A",X"E2",X"07",X"82",X"0E",X"81",X"14",X"86",X"02",X"88",X"62",X"08",
X"88",X"6A",X"08",X"88",X"72",X"08",X"88",X"7A",X"08",X"8A",X"F7",X"07",X"82",X"0D",X"81",X"14",
X"86",X"01",X"88",X"82",X"08",X"88",X"8C",X"08",X"88",X"82",X"08",X"88",X"96",X"08",X"8A",X"0C",
X"08",X"82",X"0D",X"81",X"14",X"86",X"01",X"88",X"A0",X"08",X"88",X"AE",X"08",X"88",X"A0",X"08",
X"88",X"BC",X"08",X"8A",X"21",X"08",X"19",X"02",X"1D",X"02",X"20",X"02",X"19",X"02",X"1D",X"02",
X"20",X"02",X"25",X"04",X"89",X"22",X"04",X"1E",X"04",X"22",X"02",X"1E",X"02",X"22",X"02",X"25",
X"02",X"89",X"25",X"02",X"25",X"02",X"29",X"04",X"2C",X"02",X"29",X"06",X"89",X"27",X"06",X"20",
X"0A",X"89",X"2C",X"01",X"8C",X"00",X"10",X"62",X"08",X"89",X"2A",X"01",X"8C",X"00",X"10",X"6A",
X"08",X"89",X"29",X"01",X"8C",X"00",X"10",X"72",X"08",X"89",X"27",X"01",X"8C",X"00",X"10",X"7A",
X"08",X"89",X"20",X"02",X"1D",X"02",X"8C",X"01",X"04",X"82",X"08",X"89",X"22",X"02",X"1E",X"02",
X"8C",X"01",X"04",X"8C",X"08",X"89",X"24",X"02",X"20",X"02",X"8C",X"01",X"04",X"96",X"08",X"89",
X"1D",X"02",X"19",X"02",X"20",X"02",X"19",X"02",X"8C",X"02",X"02",X"A0",X"08",X"89",X"1E",X"02",
X"19",X"02",X"22",X"02",X"19",X"02",X"8C",X"02",X"02",X"AE",X"08",X"89",X"20",X"02",X"1B",X"02",
X"20",X"02",X"18",X"02",X"8C",X"02",X"02",X"A0",X"08",X"89",X"CE",X"08",X"D4",X"08",X"CE",X"FE",
X"DC",X"BA",X"A9",X"01",X"EF",X"EC",X"BA",X"01",X"FF",X"DD",X"08",X"0C",X"0C",X"03",X"E4",X"08",
X"F1",X"08",X"FE",X"08",X"80",X"10",X"00",X"00",X"00",X"01",X"00",X"33",X"09",X"0C",X"20",X"00",
X"00",X"80",X"11",X"00",X"00",X"00",X"01",X"00",X"0E",X"09",X"0C",X"20",X"00",X"00",X"80",X"12",
X"00",X"00",X"00",X"01",X"00",X"52",X"09",X"18",X"20",X"00",X"00",X"81",X"1A",X"89",X"88",X"0B",
X"09",X"82",X"0E",X"88",X"6D",X"09",X"82",X"0D",X"88",X"F2",X"09",X"88",X"17",X"0A",X"88",X"3C",
X"0A",X"88",X"61",X"0A",X"88",X"86",X"0A",X"88",X"AB",X"0A",X"88",X"CA",X"0A",X"88",X"E5",X"0A",
X"8A",X"16",X"09",X"88",X"0B",X"09",X"82",X"0E",X"88",X"9E",X"09",X"82",X"0C",X"88",X"0E",X"0B",
X"88",X"1F",X"0B",X"88",X"2C",X"0B",X"88",X"45",X"0B",X"88",X"5A",X"0B",X"88",X"75",X"0B",X"8A",
X"3B",X"09",X"88",X"0B",X"09",X"82",X"0E",X"88",X"CF",X"09",X"82",X"0D",X"86",X"0C",X"88",X"84",
X"0B",X"88",X"A5",X"0B",X"88",X"C6",X"0B",X"88",X"E7",X"0B",X"8A",X"5A",X"09",X"86",X"01",X"2C",
X"01",X"2E",X"01",X"2C",X"01",X"2B",X"01",X"86",X"02",X"2C",X"02",X"20",X"02",X"86",X"07",X"2C",
X"02",X"2A",X"02",X"29",X"02",X"27",X"02",X"86",X"03",X"25",X"03",X"86",X"02",X"27",X"01",X"86",
X"0B",X"29",X"02",X"2A",X"02",X"2C",X"02",X"00",X"02",X"20",X"02",X"00",X"02",X"89",X"86",X"01",
X"29",X"01",X"2A",X"01",X"29",X"01",X"28",X"01",X"86",X"02",X"29",X"02",X"00",X"02",X"86",X"07",
X"29",X"02",X"27",X"02",X"25",X"02",X"24",X"02",X"86",X"03",X"20",X"03",X"86",X"02",X"1E",X"01",
X"86",X"0B",X"1D",X"02",X"1B",X"02",X"1D",X"02",X"00",X"02",X"1D",X"02",X"00",X"02",X"89",X"86",
X"0C",X"01",X"06",X"86",X"0B",X"01",X"02",X"86",X"07",X"01",X"02",X"08",X"02",X"0D",X"02",X"08",
X"02",X"86",X"0C",X"01",X"04",X"05",X"04",X"86",X"0B",X"01",X"02",X"00",X"02",X"01",X"02",X"00",
X"02",X"89",X"86",X"01",X"29",X"01",X"2A",X"01",X"29",X"01",X"2A",X"01",X"2C",X"01",X"2A",X"01",
X"2C",X"01",X"2A",X"01",X"29",X"01",X"2A",X"01",X"29",X"01",X"2A",X"01",X"2C",X"01",X"2A",X"01",
X"2C",X"01",X"86",X"02",X"2A",X"01",X"89",X"86",X"01",X"29",X"01",X"2A",X"01",X"2C",X"01",X"2E",
X"01",X"30",X"01",X"31",X"01",X"30",X"01",X"29",X"01",X"2A",X"01",X"2C",X"01",X"2A",X"01",X"86",
X"02",X"29",X"01",X"86",X"03",X"2A",X"02",X"86",X"04",X"27",X"02",X"89",X"86",X"01",X"27",X"01",
X"29",X"01",X"27",X"01",X"29",X"01",X"2A",X"01",X"29",X"01",X"2A",X"01",X"29",X"01",X"27",X"01",
X"29",X"01",X"27",X"01",X"29",X"01",X"2A",X"01",X"29",X"01",X"2A",X"01",X"86",X"02",X"29",X"01",
X"89",X"86",X"01",X"27",X"01",X"29",X"01",X"2A",X"01",X"2C",X"01",X"2E",X"01",X"30",X"01",X"2E",
X"01",X"2C",X"01",X"2A",X"01",X"2E",X"01",X"2C",X"01",X"86",X"02",X"2B",X"01",X"86",X"03",X"2C",
X"02",X"86",X"04",X"29",X"02",X"89",X"86",X"01",X"29",X"01",X"2A",X"01",X"29",X"01",X"2A",X"01",
X"2C",X"01",X"2B",X"01",X"2C",X"01",X"2A",X"01",X"29",X"01",X"2A",X"01",X"29",X"01",X"2A",X"01",
X"2C",X"01",X"2B",X"01",X"2C",X"01",X"86",X"02",X"2A",X"01",X"89",X"86",X"01",X"29",X"01",X"2A",
X"01",X"2C",X"01",X"2E",X"01",X"30",X"01",X"31",X"01",X"30",X"01",X"2E",X"01",X"2C",X"01",X"30",
X"01",X"2E",X"01",X"2D",X"01",X"86",X"05",X"2E",X"04",X"89",X"86",X"06",X"31",X"01",X"30",X"01",
X"31",X"02",X"25",X"01",X"24",X"01",X"25",X"02",X"2E",X"01",X"2D",X"01",X"2E",X"02",X"22",X"01",
X"21",X"01",X"22",X"02",X"89",X"86",X"01",X"2C",X"01",X"2E",X"01",X"2C",X"01",X"86",X"02",X"20",
X"01",X"86",X"01",X"2A",X"01",X"2C",X"01",X"2A",X"01",X"86",X"02",X"20",X"01",X"86",X"01",X"27",
X"01",X"26",X"01",X"27",X"01",X"86",X"02",X"20",X"01",X"2C",X"02",X"20",X"02",X"89",X"86",X"08",
X"20",X"0A",X"86",X"09",X"1D",X"02",X"1E",X"02",X"1F",X"02",X"86",X"08",X"20",X"0A",X"89",X"86",
X"09",X"25",X"02",X"24",X"02",X"22",X"02",X"86",X"08",X"20",X"0A",X"89",X"86",X"09",X"1E",X"02",
X"1D",X"02",X"1B",X"02",X"86",X"08",X"1E",X"0A",X"86",X"09",X"1D",X"02",X"1B",X"02",X"19",X"02",
X"86",X"08",X"20",X"0A",X"89",X"86",X"09",X"1D",X"02",X"1E",X"02",X"1F",X"02",X"86",X"08",X"20",
X"0A",X"86",X"09",X"1E",X"02",X"1D",X"02",X"1E",X"02",X"89",X"86",X"06",X"29",X"01",X"28",X"01",
X"29",X"02",X"1D",X"01",X"1C",X"01",X"1D",X"02",X"2A",X"01",X"29",X"01",X"2A",X"02",X"1E",X"01",
X"1D",X"01",X"1E",X"02",X"89",X"86",X"08",X"1B",X"09",X"00",X"01",X"86",X"09",X"1B",X"02",X"1D",
X"02",X"1E",X"02",X"89",X"01",X"02",X"0D",X"02",X"08",X"02",X"0D",X"02",X"01",X"02",X"0D",X"02",
X"08",X"02",X"0D",X"02",X"01",X"02",X"0D",X"02",X"08",X"02",X"0D",X"02",X"0A",X"02",X"08",X"02",
X"06",X"02",X"05",X"02",X"89",X"03",X"02",X"0C",X"02",X"0F",X"02",X"0C",X"02",X"08",X"02",X"0C",
X"02",X"08",X"02",X"0C",X"02",X"08",X"02",X"0C",X"02",X"0F",X"02",X"0C",X"02",X"0D",X"02",X"08",
X"02",X"05",X"02",X"01",X"02",X"89",X"01",X"02",X"0D",X"02",X"08",X"02",X"0D",X"02",X"01",X"02",
X"0D",X"02",X"08",X"02",X"0D",X"02",X"01",X"02",X"0D",X"02",X"08",X"02",X"0D",X"02",X"0A",X"02",
X"06",X"02",X"0D",X"02",X"06",X"02",X"89",X"86",X"0C",X"01",X"04",X"86",X"0B",X"08",X"02",X"0D",
X"02",X"86",X"0C",X"01",X"04",X"86",X"0B",X"06",X"02",X"0D",X"02",X"86",X"0C",X"0C",X"04",X"08",
X"04",X"86",X"0B",X"08",X"02",X"06",X"02",X"05",X"02",X"03",X"02",X"89",X"24",X"0C",X"2C",X"0C",
X"24",X"0C",X"2C",X"0C",X"33",X"0C",X"43",X"0C",X"4F",X"0C",X"5C",X"0C",X"5C",X"0C",X"65",X"0C",
X"7D",X"0C",X"86",X"0C",X"DE",X"FF",X"FF",X"EE",X"DC",X"BA",X"99",X"01",X"DE",X"FF",X"ED",X"B9",
X"75",X"32",X"01",X"CD",X"EF",X"FF",X"FE",X"ED",X"DC",X"CB",X"BB",X"AA",X"AA",X"99",X"99",X"98",
X"88",X"77",X"01",X"CD",X"ED",X"FF",X"FE",X"EE",X"DD",X"DC",X"CB",X"97",X"53",X"21",X"01",X"DE",
X"FF",X"FE",X"ED",X"DC",X"CC",X"BB",X"AA",X"99",X"88",X"76",X"65",X"01",X"DD",X"DD",X"EE",X"EE",
X"FF",X"FF",X"EE",X"EE",X"00",X"AB",X"CD",X"EF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"EE",
X"EE",X"ED",X"DD",X"DD",X"CC",X"CC",X"CB",X"BB",X"BB",X"AA",X"AA",X"A9",X"01",X"DE",X"FF",X"FF",
X"FF",X"ED",X"DA",X"87",X"43",X"01",X"EF",X"FF",X"FE",X"EE",X"EE",X"DD",X"DD",X"DC",X"CC",X"BB",
X"BA",X"A9",X"98",X"01",X"FF",X"99",X"0C",X"BE",X"0F",X"05",X"A4",X"0C",X"B2",X"0C",X"C0",X"0C",
X"CE",X"0C",X"DC",X"0C",X"80",X"20",X"00",X"00",X"00",X"01",X"00",X"EA",X"0C",X"0C",X"20",X"00",
X"00",X"0F",X"80",X"21",X"00",X"00",X"00",X"01",X"00",X"17",X"0D",X"0C",X"20",X"00",X"00",X"0E",
X"80",X"10",X"00",X"00",X"00",X"01",X"00",X"40",X"0D",X"00",X"20",X"00",X"00",X"0F",X"80",X"11",
X"00",X"00",X"00",X"05",X"00",X"EA",X"0C",X"0C",X"20",X"00",X"00",X"0E",X"80",X"12",X"00",X"00",
X"00",X"01",X"00",X"70",X"0D",X"00",X"20",X"00",X"00",X"0E",X"81",X"18",X"86",X"01",X"20",X"02",
X"88",X"9D",X"0D",X"88",X"A8",X"0D",X"88",X"B7",X"0D",X"88",X"C2",X"0D",X"88",X"9D",X"0D",X"88",
X"A8",X"0D",X"88",X"B7",X"0D",X"88",X"CD",X"0D",X"88",X"DA",X"0D",X"88",X"EB",X"0D",X"88",X"FC",
X"0D",X"88",X"0D",X"0E",X"8A",X"F0",X"0C",X"81",X"18",X"86",X"03",X"1D",X"02",X"88",X"18",X"0E",
X"88",X"2D",X"0E",X"88",X"42",X"0E",X"88",X"57",X"0E",X"8C",X"00",X"02",X"1D",X"0D",X"88",X"57",
X"0E",X"88",X"57",X"0E",X"88",X"6E",X"0E",X"88",X"8F",X"0E",X"88",X"8F",X"0E",X"8A",X"1D",X"0D",
X"81",X"18",X"86",X"04",X"0D",X"02",X"88",X"A4",X"0E",X"88",X"B9",X"0E",X"88",X"CE",X"0E",X"88",
X"E3",X"0E",X"88",X"A4",X"0E",X"88",X"B9",X"0E",X"88",X"CE",X"0E",X"88",X"F8",X"0E",X"88",X"0D",
X"0F",X"88",X"0D",X"0F",X"88",X"1E",X"0F",X"88",X"2F",X"0F",X"88",X"3C",X"0F",X"8A",X"46",X"0D",
X"81",X"18",X"00",X"02",X"86",X"02",X"88",X"51",X"0F",X"88",X"60",X"0F",X"88",X"6D",X"0F",X"88",
X"7A",X"0F",X"88",X"51",X"0F",X"88",X"60",X"0F",X"88",X"6D",X"0F",X"88",X"85",X"0F",X"88",X"92",
X"0F",X"88",X"A3",X"0F",X"88",X"B4",X"0F",X"88",X"BB",X"0F",X"8A",X"74",X"0D",X"25",X"04",X"25",
X"02",X"29",X"02",X"2C",X"06",X"2C",X"02",X"89",X"2E",X"02",X"2C",X"02",X"2A",X"02",X"29",X"02",
X"2A",X"04",X"27",X"02",X"20",X"02",X"89",X"24",X"04",X"24",X"02",X"25",X"02",X"27",X"06",X"20",
X"02",X"89",X"2C",X"04",X"2A",X"02",X"27",X"02",X"29",X"06",X"20",X"02",X"89",X"2C",X"02",X"2A",
X"02",X"29",X"02",X"27",X"02",X"25",X"06",X"20",X"02",X"89",X"27",X"02",X"27",X"02",X"27",X"02",
X"20",X"02",X"29",X"02",X"29",X"02",X"29",X"02",X"20",X"02",X"89",X"27",X"02",X"27",X"02",X"27",
X"02",X"20",X"02",X"29",X"02",X"2C",X"02",X"2E",X"02",X"30",X"02",X"89",X"31",X"02",X"2C",X"02",
X"2C",X"02",X"29",X"02",X"2A",X"02",X"25",X"02",X"25",X"02",X"22",X"02",X"89",X"25",X"0F",X"86",
X"03",X"25",X"0F",X"86",X"01",X"20",X"02",X"89",X"25",X"02",X"1D",X"01",X"20",X"02",X"25",X"01",
X"1D",X"02",X"25",X"02",X"1D",X"01",X"20",X"02",X"25",X"01",X"1D",X"02",X"89",X"25",X"02",X"1D",
X"01",X"20",X"02",X"25",X"01",X"1D",X"02",X"25",X"02",X"1E",X"01",X"20",X"02",X"27",X"01",X"18",
X"02",X"89",X"20",X"02",X"18",X"01",X"1B",X"02",X"20",X"01",X"18",X"02",X"20",X"02",X"18",X"01",
X"1B",X"02",X"20",X"01",X"18",X"02",X"89",X"20",X"02",X"18",X"01",X"1B",X"01",X"1E",X"01",X"20",
X"01",X"18",X"02",X"25",X"02",X"1D",X"01",X"20",X"02",X"25",X"01",X"1D",X"02",X"89",X"25",X"01",
X"2C",X"01",X"2C",X"01",X"29",X"01",X"2C",X"01",X"29",X"01",X"29",X"01",X"25",X"01",X"2A",X"01",
X"19",X"01",X"19",X"01",X"16",X"01",X"19",X"01",X"16",X"01",X"16",X"01",X"12",X"01",X"89",X"19",
X"02",X"1D",X"01",X"20",X"02",X"1D",X"01",X"19",X"02",X"19",X"02",X"1D",X"01",X"20",X"02",X"1D",
X"01",X"19",X"02",X"89",X"11",X"02",X"0D",X"02",X"14",X"02",X"0D",X"02",X"11",X"01",X"11",X"01",
X"0D",X"02",X"14",X"01",X"14",X"01",X"0D",X"02",X"89",X"11",X"02",X"0D",X"02",X"14",X"02",X"0D",
X"02",X"12",X"01",X"12",X"01",X"0D",X"02",X"0F",X"01",X"0F",X"01",X"08",X"02",X"89",X"0C",X"02",
X"08",X"02",X"0F",X"02",X"08",X"02",X"0C",X"01",X"0C",X"01",X"08",X"02",X"0F",X"01",X"0F",X"01",
X"08",X"02",X"89",X"0C",X"02",X"08",X"02",X"0F",X"02",X"08",X"02",X"11",X"01",X"11",X"01",X"0D",
X"02",X"14",X"01",X"14",X"01",X"14",X"02",X"89",X"0C",X"02",X"08",X"02",X"0F",X"02",X"08",X"02",
X"11",X"01",X"11",X"01",X"0D",X"02",X"0D",X"01",X"0D",X"01",X"0D",X"02",X"89",X"0C",X"02",X"08",
X"02",X"0F",X"02",X"08",X"02",X"11",X"02",X"0D",X"02",X"14",X"02",X"0D",X"02",X"89",X"0D",X"02",
X"01",X"02",X"0D",X"02",X"01",X"02",X"12",X"02",X"06",X"02",X"12",X"02",X"06",X"02",X"89",X"0D",
X"02",X"0D",X"01",X"0D",X"05",X"0D",X"02",X"0D",X"01",X"0D",X"05",X"89",X"0D",X"02",X"11",X"01",
X"14",X"02",X"11",X"01",X"0D",X"02",X"0D",X"02",X"11",X"01",X"14",X"02",X"11",X"01",X"0D",X"02",
X"89",X"00",X"02",X"2C",X"02",X"2C",X"02",X"2C",X"02",X"29",X"06",X"25",X"01",X"25",X"01",X"89",
X"25",X"02",X"24",X"02",X"20",X"02",X"20",X"02",X"1E",X"04",X"1B",X"04",X"89",X"00",X"02",X"27",
X"02",X"27",X"02",X"27",X"02",X"24",X"06",X"20",X"02",X"89",X"1B",X"02",X"1B",X"02",X"20",X"02",
X"20",X"02",X"20",X"08",X"89",X"1B",X"02",X"1B",X"02",X"20",X"04",X"20",X"02",X"1D",X"02",X"19",
X"04",X"89",X"20",X"02",X"20",X"02",X"20",X"02",X"20",X"02",X"20",X"02",X"20",X"02",X"20",X"02",
X"20",X"02",X"89",X"20",X"02",X"20",X"02",X"20",X"02",X"20",X"02",X"20",X"02",X"20",X"02",X"22",
X"02",X"24",X"02",X"89",X"86",X"04",X"25",X"08",X"25",X"08",X"89",X"25",X"20",X"89",X"C6",X"0F",
X"D0",X"0F",X"D9",X"0F",X"DF",X"0F",X"CE",X"FF",X"FE",X"DC",X"BB",X"BB",X"AA",X"AA",X"98",X"01",
X"BC",X"DE",X"FD",X"CB",X"BB",X"BB",X"BB",X"AA",X"01",X"CD",X"EF",X"FF",X"ED",X"CB",X"01",X"EF",
X"ED",X"CB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BA",X"98",X"01",X"FF",X"EF",X"0F",X"9B",X"10",X"03",
X"F6",X"0F",X"03",X"10",X"10",X"10",X"80",X"20",X"00",X"00",X"00",X"01",X"00",X"1D",X"10",X"00",
X"20",X"00",X"00",X"80",X"21",X"00",X"00",X"00",X"01",X"00",X"47",X"10",X"00",X"20",X"00",X"00",
X"80",X"22",X"00",X"00",X"00",X"01",X"00",X"71",X"10",X"00",X"20",X"00",X"00",X"81",X"01",X"86",
X"01",X"82",X"0E",X"31",X"02",X"36",X"03",X"3A",X"03",X"82",X"0F",X"8C",X"00",X"03",X"23",X"10",
X"3A",X"03",X"3D",X"03",X"42",X"03",X"82",X"0E",X"86",X"02",X"8D",X"31",X"3D",X"0A",X"8E",X"82",
X"0F",X"8C",X"00",X"03",X"3A",X"10",X"93",X"81",X"01",X"86",X"01",X"82",X"0E",X"3D",X"02",X"3A",
X"03",X"36",X"03",X"82",X"0F",X"8C",X"01",X"03",X"23",X"10",X"36",X"03",X"3A",X"03",X"3D",X"05",
X"82",X"0E",X"86",X"02",X"8D",X"38",X"44",X"0A",X"8E",X"82",X"0F",X"8C",X"01",X"03",X"64",X"10",
X"84",X"81",X"01",X"86",X"01",X"82",X"0E",X"36",X"02",X"31",X"03",X"36",X"03",X"82",X"0F",X"8C",
X"02",X"03",X"23",X"10",X"31",X"04",X"36",X"03",X"3A",X"03",X"86",X"02",X"82",X"0E",X"8D",X"29",
X"35",X"0A",X"8E",X"82",X"0F",X"8C",X"02",X"03",X"8E",X"10",X"84",X"9F",X"10",X"A2",X"10",X"FE",
X"DD",X"01",X"FE",X"DC",X"A9",X"01",X"FF",X"AB",X"10",X"E6",X"10",X"03",X"B2",X"10",X"BF",X"10",
X"CC",X"10",X"80",X"20",X"00",X"00",X"00",X"01",X"00",X"D9",X"10",X"02",X"20",X"00",X"00",X"80",
X"21",X"00",X"00",X"00",X"01",X"00",X"D9",X"10",X"0A",X"20",X"00",X"00",X"80",X"22",X"00",X"00",
X"00",X"01",X"00",X"D9",X"10",X"0E",X"20",X"00",X"00",X"82",X"0F",X"81",X"01",X"86",X"01",X"28",
X"01",X"29",X"1E",X"00",X"32",X"94",X"E8",X"10",X"EF",X"FE",X"DD",X"CC",X"BA",X"99",X"88",X"77",
X"01",X"FF",X"F6",X"10",X"A0",X"11",X"05",X"01",X"11",X"0E",X"11",X"1B",X"11",X"28",X"11",X"35",
X"11",X"80",X"20",X"00",X"00",X"00",X"01",X"00",X"42",X"11",X"11",X"20",X"00",X"00",X"80",X"21",
X"00",X"00",X"00",X"01",X"00",X"42",X"11",X"05",X"20",X"00",X"00",X"80",X"22",X"00",X"00",X"00",
X"01",X"00",X"62",X"11",X"05",X"20",X"00",X"00",X"80",X"10",X"00",X"00",X"00",X"01",X"00",X"62",
X"11",X"05",X"20",X"00",X"00",X"80",X"11",X"00",X"00",X"00",X"01",X"00",X"86",X"11",X"05",X"20",
X"00",X"00",X"81",X"14",X"82",X"0F",X"86",X"01",X"25",X"01",X"26",X"01",X"25",X"01",X"26",X"01",
X"86",X"02",X"25",X"02",X"1D",X"02",X"86",X"03",X"20",X"04",X"8D",X"86",X"04",X"25",X"19",X"08",
X"8E",X"84",X"81",X"14",X"82",X"0F",X"86",X"05",X"00",X"04",X"29",X"02",X"25",X"02",X"86",X"01",
X"25",X"01",X"26",X"01",X"25",X"01",X"26",X"01",X"86",X"02",X"25",X"02",X"1D",X"02",X"8D",X"86",
X"04",X"20",X"19",X"04",X"8E",X"84",X"81",X"14",X"82",X"0F",X"86",X"05",X"31",X"02",X"2C",X"02",
X"25",X"02",X"20",X"02",X"19",X"02",X"14",X"02",X"8D",X"86",X"04",X"0D",X"19",X"08",X"8E",X"84",
X"AA",X"11",X"B0",X"11",X"BB",X"11",X"D0",X"11",X"FA",X"11",X"BC",X"EF",X"FF",X"FE",X"DC",X"01",
X"DF",X"FE",X"DC",X"CC",X"CC",X"CC",X"CC",X"CB",X"A9",X"75",X"01",X"67",X"89",X"AB",X"CD",X"ED",
X"DF",X"DF",X"DF",X"CF",X"CF",X"CF",X"CF",X"BF",X"BF",X"BF",X"AF",X"AF",X"AE",X"DC",X"85",X"01",
X"EF",X"EF",X"EF",X"EF",X"EF",X"DE",X"DE",X"DE",X"DE",X"DE",X"CD",X"CD",X"CD",X"CD",X"CD",X"BC",
X"BC",X"BC",X"BC",X"BC",X"AB",X"AB",X"AB",X"AB",X"AB",X"9A",X"9A",X"9A",X"9A",X"9A",X"89",X"89",
X"89",X"78",X"78",X"67",X"67",X"67",X"56",X"56",X"42",X"01",X"EF",X"FF",X"FE",X"DC",X"BA",X"99",
X"88",X"77",X"66",X"55",X"44",X"77",X"66",X"55",X"44",X"33",X"55",X"44",X"33",X"22",X"01",X"FF",
X"14",X"12",X"FD",X"12",X"06",X"21",X"12",X"2E",X"12",X"3B",X"12",X"48",X"12",X"55",X"12",X"62",
X"12",X"80",X"20",X"00",X"00",X"00",X"01",X"00",X"6F",X"12",X"00",X"20",X"00",X"00",X"80",X"21",
X"00",X"00",X"00",X"01",X"00",X"6F",X"12",X"F4",X"20",X"00",X"00",X"80",X"22",X"00",X"00",X"00",
X"01",X"00",X"99",X"12",X"00",X"20",X"00",X"00",X"80",X"10",X"00",X"00",X"00",X"01",X"00",X"99",
X"12",X"00",X"20",X"00",X"00",X"80",X"11",X"00",X"00",X"00",X"01",X"00",X"D0",X"12",X"0C",X"20",
X"00",X"00",X"80",X"12",X"00",X"00",X"00",X"01",X"00",X"D0",X"12",X"00",X"20",X"00",X"00",X"82",
X"0F",X"81",X"14",X"86",X"01",X"3D",X"01",X"38",X"01",X"35",X"01",X"31",X"01",X"2C",X"01",X"29",
X"01",X"25",X"01",X"20",X"01",X"86",X"04",X"1D",X"01",X"19",X"01",X"14",X"01",X"11",X"01",X"8C",
X"00",X"02",X"6F",X"12",X"86",X"02",X"3D",X"04",X"84",X"82",X"0F",X"81",X"14",X"86",X"02",X"00",
X"04",X"3D",X"01",X"38",X"01",X"35",X"01",X"31",X"01",X"86",X"04",X"2C",X"01",X"29",X"01",X"25",
X"01",X"20",X"01",X"1D",X"01",X"19",X"01",X"14",X"01",X"11",X"01",X"0D",X"01",X"11",X"01",X"14",
X"01",X"19",X"01",X"1D",X"01",X"20",X"01",X"25",X"01",X"29",X"01",X"86",X"02",X"25",X"04",X"84",
X"82",X"0F",X"81",X"14",X"86",X"03",X"00",X"08",X"01",X"01",X"05",X"01",X"08",X"01",X"0D",X"01",
X"11",X"01",X"14",X"01",X"19",X"01",X"1D",X"01",X"20",X"01",X"25",X"01",X"29",X"01",X"2C",X"01",
X"25",X"01",X"20",X"01",X"1D",X"01",X"19",X"01",X"86",X"02",X"01",X"04",X"84",X"05",X"13",X"11",
X"13",X"26",X"13",X"0B",X"13",X"FE",X"DD",X"DC",X"BB",X"BA",X"01",X"DE",X"FF",X"FE",X"DC",X"BA",
X"01",X"CD",X"FF",X"FE",X"EE",X"DD",X"CC",X"CC",X"CC",X"CC",X"CC",X"BB",X"BA",X"AA",X"A9",X"99",
X"99",X"99",X"88",X"88",X"87",X"01",X"DE",X"FF",X"DC",X"BB",X"01",X"FF",X"30",X"13",X"8C",X"13",
X"03",X"37",X"13",X"44",X"13",X"51",X"13",X"80",X"20",X"00",X"00",X"00",X"01",X"00",X"5E",X"13",
X"0B",X"20",X"00",X"00",X"80",X"21",X"00",X"00",X"00",X"01",X"00",X"75",X"13",X"F7",X"20",X"00",
X"00",X"80",X"22",X"00",X"00",X"00",X"01",X"00",X"75",X"13",X"FD",X"20",X"00",X"00",X"82",X"0F",
X"81",X"01",X"86",X"01",X"2B",X"01",X"2C",X"09",X"86",X"00",X"2F",X"01",X"30",X"09",X"86",X"02",
X"30",X"01",X"31",X"10",X"95",X"82",X"0F",X"81",X"01",X"86",X"02",X"2B",X"01",X"2C",X"09",X"86",
X"01",X"2F",X"01",X"30",X"09",X"86",X"03",X"30",X"01",X"31",X"10",X"84",X"92",X"13",X"96",X"13",
X"9B",X"13",X"DF",X"ED",X"CC",X"01",X"DF",X"EE",X"DC",X"B7",X"01",X"EF",X"FF",X"EC",X"A8",X"01",
X"FF",X"A5",X"13",X"1C",X"14",X"01",X"A8",X"13",X"80",X"10",X"00",X"00",X"00",X"01",X"00",X"B5",
X"13",X"FF",X"20",X"00",X"00",X"81",X"01",X"82",X"0F",X"86",X"01",X"1B",X"02",X"1D",X"0D",X"1D",
X"02",X"1E",X"0D",X"1D",X"02",X"1F",X"0D",X"22",X"02",X"24",X"0D",X"18",X"02",X"19",X"0D",X"1B",
X"02",X"1D",X"0D",X"1D",X"02",X"1F",X"0D",X"24",X"02",X"25",X"0D",X"22",X"02",X"24",X"0D",X"24",
X"02",X"25",X"0D",X"1B",X"02",X"1D",X"0D",X"29",X"02",X"2A",X"0D",X"29",X"02",X"2A",X"0D",X"1E",
X"02",X"20",X"0D",X"16",X"02",X"18",X"0D",X"24",X"02",X"25",X"0D",X"25",X"02",X"27",X"0D",X"2A",
X"02",X"2C",X"0D",X"25",X"02",X"28",X"0D",X"22",X"02",X"24",X"0D",X"24",X"02",X"25",X"0D",X"25",
X"02",X"27",X"0D",X"2A",X"02",X"2D",X"0D",X"22",X"02",X"30",X"0D",X"96",X"1E",X"14",X"FF",X"FF",
X"EC",X"A8",X"77",X"01",X"FF",X"27",X"14",X"03",X"2E",X"14",X"3B",X"14",X"48",X"14",X"80",X"20",
X"00",X"00",X"00",X"01",X"00",X"55",X"14",X"00",X"20",X"00",X"00",X"80",X"21",X"00",X"00",X"00",
X"09",X"00",X"C5",X"14",X"F4",X"20",X"00",X"00",X"80",X"22",X"00",X"00",X"00",X"0C",X"00",X"C5",
X"14",X"F4",X"20",X"00",X"00",X"81",X"01",X"8F",X"82",X"0F",X"00",X"14",X"01",X"00",X"17",X"01",
X"00",X"1C",X"01",X"00",X"1E",X"01",X"00",X"20",X"01",X"00",X"24",X"01",X"00",X"28",X"01",X"00",
X"2C",X"01",X"00",X"30",X"01",X"00",X"37",X"01",X"00",X"41",X"01",X"00",X"4B",X"01",X"00",X"55",
X"01",X"00",X"64",X"01",X"00",X"78",X"01",X"00",X"82",X"01",X"00",X"8C",X"01",X"00",X"96",X"01",
X"00",X"A0",X"01",X"82",X"0E",X"00",X"AA",X"01",X"00",X"B4",X"01",X"00",X"BE",X"01",X"00",X"C8",
X"01",X"00",X"DC",X"01",X"00",X"F0",X"01",X"01",X"05",X"01",X"01",X"19",X"01",X"01",X"2D",X"01",
X"01",X"41",X"01",X"82",X"0D",X"01",X"55",X"01",X"01",X"69",X"01",X"01",X"7D",X"01",X"01",X"91",
X"01",X"01",X"A5",X"01",X"93",X"81",X"01",X"8F",X"82",X"0F",X"00",X"23",X"01",X"00",X"28",X"01",
X"00",X"2D",X"01",X"00",X"32",X"01",X"00",X"37",X"01",X"00",X"3C",X"01",X"00",X"41",X"01",X"00",
X"46",X"01",X"00",X"4B",X"01",X"00",X"50",X"01",X"00",X"55",X"01",X"00",X"5A",X"01",X"00",X"64",
X"01",X"00",X"6E",X"01",X"00",X"78",X"01",X"00",X"82",X"01",X"00",X"8C",X"01",X"00",X"96",X"01",
X"00",X"A0",X"01",X"00",X"AA",X"01",X"82",X"0E",X"00",X"B4",X"01",X"00",X"BE",X"01",X"00",X"C8",
X"01",X"00",X"D2",X"01",X"00",X"DC",X"01",X"00",X"E6",X"01",X"00",X"F0",X"01",X"00",X"FA",X"01",
X"01",X"05",X"01",X"01",X"0F",X"01",X"82",X"0D",X"01",X"19",X"01",X"01",X"23",X"01",X"01",X"2D",
X"01",X"01",X"41",X"01",X"01",X"55",X"01",X"84",X"FF",X"3D",X"15",X"B6",X"15",X"03",X"44",X"15",
X"51",X"15",X"5E",X"15",X"80",X"20",X"00",X"00",X"00",X"01",X"00",X"6B",X"15",X"00",X"20",X"00",
X"00",X"80",X"21",X"00",X"00",X"00",X"02",X"00",X"6B",X"15",X"00",X"20",X"00",X"00",X"80",X"22",
X"00",X"00",X"00",X"01",X"00",X"6B",X"15",X"00",X"20",X"00",X"00",X"81",X"01",X"86",X"02",X"82",
X"0C",X"36",X"01",X"82",X"0C",X"3A",X"01",X"82",X"0C",X"3A",X"01",X"82",X"0D",X"3B",X"01",X"82",
X"0D",X"3B",X"01",X"82",X"0E",X"3C",X"01",X"82",X"0F",X"3C",X"02",X"3D",X"02",X"82",X"0E",X"86",
X"01",X"3E",X"03",X"86",X"02",X"82",X"0D",X"30",X"02",X"82",X"0D",X"35",X"02",X"82",X"0C",X"33",
X"01",X"82",X"0E",X"31",X"01",X"82",X"0D",X"2F",X"02",X"82",X"0D",X"2F",X"02",X"2E",X"02",X"82",
X"0C",X"86",X"01",X"2D",X"09",X"97",X"BA",X"15",X"BE",X"15",X"FC",X"A7",X"51",X"01",X"FE",X"01",
X"FF",X"C3",X"15",X"01",X"C6",X"15",X"80",X"21",X"00",X"00",X"00",X"01",X"00",X"D3",X"15",X"00",
X"20",X"00",X"00",X"81",X"32",X"82",X"0F",X"00",X"0A",X"96",X"FF",X"DF",X"15",X"15",X"16",X"02",
X"E4",X"15",X"F1",X"15",X"80",X"23",X"00",X"00",X"00",X"01",X"00",X"FE",X"15",X"00",X"20",X"00",
X"00",X"80",X"13",X"00",X"00",X"00",X"01",X"00",X"06",X"16",X"00",X"20",X"00",X"00",X"88",X"0E",
X"16",X"85",X"04",X"0D",X"04",X"84",X"88",X"0E",X"16",X"85",X"00",X"3D",X"04",X"84",X"81",X"16",
X"82",X"0F",X"86",X"01",X"89",X"17",X"16",X"13",X"46",X"79",X"AB",X"AD",X"EF",X"00",X"FF",X"23",
X"16",X"9E",X"16",X"03",X"2A",X"16",X"37",X"16",X"44",X"16",X"80",X"20",X"00",X"00",X"00",X"01",
X"00",X"51",X"16",X"07",X"20",X"00",X"00",X"80",X"21",X"00",X"00",X"00",X"08",X"00",X"51",X"16",
X"FB",X"20",X"00",X"00",X"80",X"22",X"00",X"00",X"00",X"01",X"00",X"7E",X"16",X"FB",X"20",X"00",
X"00",X"81",X"15",X"82",X"0F",X"86",X"01",X"2E",X"01",X"2C",X"01",X"2A",X"02",X"2A",X"02",X"2A",
X"02",X"2E",X"01",X"2C",X"01",X"2A",X"02",X"2A",X"02",X"2A",X"02",X"2E",X"01",X"2C",X"01",X"2A",
X"02",X"35",X"01",X"33",X"01",X"31",X"02",X"38",X"01",X"35",X"01",X"36",X"02",X"84",X"81",X"15",
X"82",X"0F",X"86",X"02",X"00",X"02",X"22",X"01",X"1E",X"01",X"25",X"01",X"1E",X"01",X"8C",X"01",
X"05",X"86",X"16",X"19",X"01",X"19",X"01",X"19",X"01",X"19",X"01",X"1E",X"02",X"84",X"A2",X"16",
X"A8",X"16",X"AC",X"EF",X"FF",X"EC",X"BA",X"01",X"EF",X"FE",X"DC",X"BA",X"01",X"FF",X"B2",X"16",
X"21",X"17",X"03",X"B9",X"16",X"C6",X"16",X"D3",X"16",X"80",X"20",X"00",X"00",X"00",X"01",X"00",
X"E0",X"16",X"00",X"20",X"00",X"00",X"80",X"21",X"00",X"00",X"00",X"01",X"00",X"FB",X"16",X"00",
X"20",X"00",X"00",X"80",X"13",X"00",X"00",X"00",X"01",X"00",X"0A",X"17",X"00",X"20",X"00",X"00",
X"82",X"0F",X"81",X"01",X"86",X"01",X"2C",X"08",X"25",X"08",X"29",X"08",X"2C",X"07",X"31",X"07",
X"35",X"07",X"38",X"06",X"3D",X"06",X"41",X"06",X"41",X"03",X"94",X"82",X"0F",X"81",X"01",X"86",
X"01",X"19",X"10",X"25",X"0F",X"20",X"14",X"01",X"0C",X"84",X"82",X"0F",X"81",X"01",X"86",X"01",
X"85",X"07",X"8F",X"00",X"03",X"10",X"00",X"05",X"0F",X"00",X"07",X"14",X"00",X"14",X"0C",X"90",
X"84",X"23",X"17",X"EF",X"EF",X"CB",X"AA",X"01",X"FF",X"2D",X"17",X"C4",X"17",X"06",X"3A",X"17",
X"47",X"17",X"54",X"17",X"61",X"17",X"6E",X"17",X"7B",X"17",X"80",X"20",X"00",X"00",X"00",X"01",
X"00",X"88",X"17",X"00",X"20",X"00",X"00",X"80",X"21",X"00",X"00",X"00",X"0A",X"00",X"9B",X"17",
X"00",X"20",X"00",X"00",X"80",X"22",X"00",X"00",X"00",X"14",X"00",X"AE",X"17",X"00",X"20",X"00",
X"00",X"00",X"10",X"00",X"00",X"00",X"01",X"00",X"C1",X"17",X"00",X"20",X"00",X"00",X"00",X"11",
X"00",X"00",X"00",X"01",X"00",X"C1",X"17",X"00",X"20",X"00",X"00",X"00",X"12",X"00",X"00",X"00",
X"01",X"00",X"C1",X"17",X"00",X"20",X"00",X"00",X"81",X"08",X"82",X"0F",X"86",X"01",X"25",X"02",
X"31",X"02",X"3D",X"02",X"25",X"02",X"31",X"02",X"3D",X"06",X"94",X"81",X"08",X"82",X"0F",X"86",
X"01",X"2C",X"02",X"38",X"02",X"44",X"02",X"2C",X"02",X"38",X"02",X"44",X"06",X"94",X"81",X"08",
X"82",X"0F",X"86",X"01",X"29",X"02",X"35",X"02",X"41",X"02",X"29",X"02",X"35",X"02",X"41",X"05",
X"94",X"00",X"01",X"84",X"C6",X"17",X"CD",X"EF",X"FF",X"ED",X"DC",X"CB",X"BA",X"A9",X"98",X"87",
X"01",X"FF",X"D6",X"17",X"31",X"18",X"03",X"DD",X"17",X"EA",X"17",X"F7",X"17",X"80",X"20",X"00",
X"00",X"00",X"01",X"00",X"04",X"18",X"00",X"20",X"00",X"00",X"80",X"21",X"00",X"00",X"00",X"01",
X"00",X"04",X"18",X"00",X"20",X"00",X"00",X"80",X"22",X"00",X"00",X"00",X"01",X"00",X"04",X"18",
X"00",X"20",X"00",X"00",X"81",X"04",X"86",X"01",X"82",X"0B",X"20",X"01",X"82",X"0D",X"2C",X"01",
X"82",X"0C",X"25",X"01",X"82",X"0E",X"31",X"01",X"82",X"0D",X"29",X"01",X"82",X"0F",X"35",X"01",
X"82",X"0E",X"2C",X"01",X"82",X"0E",X"38",X"01",X"82",X"0D",X"31",X"01",X"82",X"0C",X"3D",X"01",
X"98",X"33",X"18",X"EF",X"01",X"FF",X"38",X"18",X"03",X"3F",X"18",X"4C",X"18",X"59",X"18",X"80",
X"10",X"00",X"00",X"00",X"01",X"00",X"66",X"18",X"00",X"20",X"00",X"00",X"80",X"11",X"00",X"00",
X"00",X"01",X"00",X"7A",X"18",X"00",X"20",X"00",X"00",X"80",X"12",X"00",X"00",X"00",X"01",X"00",
X"8E",X"18",X"00",X"20",X"00",X"00",X"81",X"0D",X"82",X"0F",X"0D",X"01",X"01",X"01",X"05",X"01",
X"08",X"01",X"0D",X"01",X"8C",X"00",X"02",X"66",X"18",X"99",X"81",X"0D",X"82",X"0F",X"01",X"01",
X"0D",X"01",X"08",X"01",X"05",X"01",X"01",X"01",X"8C",X"00",X"02",X"7A",X"18",X"99",X"81",X"0D",
X"82",X"0F",X"05",X"01",X"11",X"01",X"01",X"01",X"01",X"01",X"05",X"01",X"8C",X"00",X"02",X"8E",
X"18",X"99",X"FF",X"A5",X"18",X"01",X"A8",X"18",X"80",X"13",X"00",X"00",X"00",X"01",X"00",X"B5",
X"18",X"00",X"20",X"00",X"00",X"82",X"0F",X"81",X"05",X"85",X"07",X"8F",X"8D",X"00",X"01",X"00",
X"05",X"01",X"00",X"05",X"00",X"0A",X"01",X"00",X"0A",X"00",X"0F",X"01",X"00",X"0F",X"00",X"14",
X"01",X"00",X"14",X"00",X"1E",X"01",X"00",X"1E",X"00",X"28",X"01",X"00",X"28",X"00",X"3C",X"01",
X"00",X"3C",X"00",X"37",X"01",X"00",X"37",X"00",X"32",X"01",X"8C",X"00",X"0A",X"DB",X"18",X"82",
X"0E",X"00",X"37",X"00",X"32",X"01",X"82",X"0D",X"00",X"36",X"00",X"31",X"01",X"82",X"0C",X"00",
X"35",X"00",X"30",X"01",X"82",X"0B",X"00",X"34",X"00",X"2F",X"01",X"82",X"0A",X"00",X"33",X"00",
X"2E",X"01",X"82",X"09",X"00",X"32",X"00",X"2D",X"01",X"99",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

2070
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/rom/spr_rom.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

534
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/rom/tile1.vhd Normal file
View File

@@ -0,0 +1,534 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity tile1 is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of tile1 is
type rom is array(0 to 8191) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"10",X"38",X"10",X"7C",X"FE",X"00",X"00",X"02",X"04",X"7C",X"38",X"10",X"00",X"00",X"00",
X"00",X"10",X"10",X"10",X"10",X"38",X"10",X"10",X"00",X"18",X"1C",X"12",X"12",X"70",X"70",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"7C",X"D6",X"FE",X"BA",X"44",X"38",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"FF",X"80",X"C0",X"E0",X"E0",X"E7",X"E7",X"E7",X"FF",X"00",X"00",X"80",X"80",X"E7",X"E7",X"E7",
X"FF",X"01",X"03",X"87",X"87",X"E7",X"E7",X"E7",X"FF",X"00",X"00",X"80",X"80",X"FF",X"FF",X"FF",
X"BF",X"A7",X"A7",X"A7",X"A7",X"A7",X"A7",X"A7",X"FF",X"A7",X"A6",X"A1",X"A1",X"BF",X"BF",X"FF",
X"BF",X"27",X"3E",X"C1",X"C1",X"FF",X"FF",X"FF",X"BF",X"E7",X"67",X"87",X"87",X"FF",X"FF",X"FF",
X"81",X"C3",X"A7",X"A7",X"A7",X"A7",X"A7",X"A7",X"BF",X"A7",X"A7",X"A7",X"A7",X"A7",X"BF",X"FF",
X"FF",X"C0",X"C0",X"C0",X"C0",X"FF",X"FF",X"FF",X"FF",X"01",X"03",X"83",X"83",X"FF",X"FF",X"FF",
X"BF",X"A6",X"A4",X"A2",X"A2",X"A7",X"A7",X"A7",X"BF",X"E7",X"27",X"87",X"87",X"E7",X"A7",X"A7",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"FF",X"FF",X"FF",X"F1",X"E1",X"E1",X"C1",X"C1",X"C1",X"C1",X"C1",X"FD",X"FD",X"C1",X"C1",X"C1",
X"C1",X"C1",X"C1",X"C1",X"C1",X"C1",X"FF",X"FF",X"BF",X"EF",X"FB",X"9D",X"8D",X"8E",X"86",X"86",
X"86",X"86",X"86",X"BE",X"BE",X"86",X"86",X"86",X"86",X"86",X"86",X"86",X"86",X"86",X"FE",X"FE",
X"FF",X"F0",X"E6",X"E8",X"D0",X"D0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"BE",X"80",X"FF",X"FF",X"0F",X"67",X"17",X"0B",X"0B",X"05",X"05",
X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"7D",X"01",X"FF",
X"EB",X"FE",X"5F",X"F9",X"B1",X"71",X"F1",X"A1",X"C1",X"C1",X"C1",X"C2",X"C6",X"C4",X"C2",X"C1",
X"C1",X"C1",X"C1",X"C1",X"C1",X"C1",X"FF",X"FE",X"B4",X"DB",X"F6",X"3F",X"18",X"1F",X"1E",X"0A",
X"06",X"06",X"06",X"86",X"C6",X"46",X"86",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"FE",X"F9",
X"FF",X"F0",X"E0",X"E0",X"E0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
X"80",X"C0",X"C0",X"E0",X"E0",X"E0",X"F0",X"FF",X"F7",X"37",X"2B",X"2B",X"25",X"25",X"22",X"22",
X"21",X"21",X"31",X"31",X"31",X"21",X"21",X"21",X"22",X"22",X"25",X"25",X"2B",X"2B",X"37",X"E7",
X"FF",X"FF",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"84",X"84",X"84",X"80",X"84",X"83",X"80",
X"80",X"80",X"80",X"80",X"80",X"80",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"20",X"20",X"20",X"20",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FE",X"FF",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"74",X"44",X"64",X"44",X"47",X"10",X"00",X"00",X"4D",X"55",X"51",X"55",X"4D",X"A4",
X"00",X"00",X"54",X"94",X"9C",X"C8",X"48",X"62",X"FF",X"80",X"80",X"80",X"80",X"80",X"80",X"82",
X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"FF",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"1A",X"18",X"00",X"82",X"03",X"02",X"1A",X"42",X"5A",X"58",X"58",X"40",X"93",X"12",X"12",X"18",
X"FF",X"7E",X"7E",X"00",X"00",X"00",X"00",X"00",X"7E",X"7E",X"00",X"00",X"00",X"00",X"7E",X"00",
X"7E",X"7E",X"7E",X"40",X"56",X"34",X"56",X"7E",X"FF",X"01",X"FD",X"00",X"00",X"04",X"08",X"10",
X"01",X"01",X"10",X"98",X"10",X"00",X"01",X"E4",X"05",X"05",X"05",X"04",X"09",X"91",X"11",X"01",
X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00",X"00",X"FF",X"00",
X"FF",X"FF",X"FF",X"C0",X"57",X"35",X"57",X"FF",X"FF",X"80",X"BF",X"20",X"00",X"00",X"18",X"27",
X"A0",X"80",X"00",X"20",X"30",X"28",X"A7",X"20",X"A0",X"84",X"80",X"80",X"30",X"2C",X"20",X"80",
X"FF",X"07",X"F7",X"00",X"00",X"10",X"20",X"44",X"07",X"07",X"46",X"66",X"46",X"06",X"07",X"96",
X"17",X"17",X"17",X"14",X"23",X"45",X"47",X"07",X"FF",X"E0",X"EF",X"08",X"00",X"00",X"06",X"09",
X"E8",X"E0",X"00",X"08",X"0C",X"0A",X"E9",X"28",X"E8",X"E1",X"E0",X"80",X"4C",X"2B",X"48",X"E0",
X"FF",X"1F",X"DF",X"00",X"00",X"40",X"90",X"1C",X"1F",X"17",X"16",X"9E",X"16",X"16",X"17",X"5E",
X"5F",X"5F",X"5F",X"5C",X"93",X"05",X"17",X"1F",X"FF",X"F8",X"FB",X"02",X"00",X"00",X"01",X"0A",
X"FA",X"F8",X"18",X"1A",X"1B",X"1A",X"FA",X"3A",X"FA",X"F8",X"F8",X"98",X"43",X"32",X"4A",X"F8",
X"FF",X"7F",X"7F",X"00",X"00",X"40",X"70",X"7C",X"5F",X"57",X"56",X"7E",X"56",X"56",X"57",X"7E",
X"7F",X"7F",X"7F",X"7C",X"73",X"45",X"17",X"1F",X"FF",X"FE",X"FE",X"00",X"00",X"02",X"06",X"0E",
X"FE",X"FA",X"1A",X"1E",X"1A",X"1A",X"FA",X"3E",X"FE",X"FE",X"FE",X"9E",X"46",X"30",X"48",X"F8",
X"3F",X"40",X"5F",X"40",X"5F",X"50",X"50",X"50",X"50",X"50",X"50",X"5F",X"40",X"50",X"70",X"00",
X"FC",X"02",X"FA",X"00",X"F8",X"08",X"08",X"08",X"08",X"08",X"08",X"F8",X"00",X"0A",X"02",X"00",
X"3F",X"40",X"5F",X"40",X"5F",X"50",X"50",X"5C",X"5E",X"5E",X"5F",X"5F",X"40",X"50",X"70",X"00",
X"3F",X"40",X"5F",X"40",X"5F",X"50",X"57",X"5F",X"5D",X"5F",X"5F",X"5F",X"40",X"50",X"70",X"00",
X"FC",X"02",X"FA",X"00",X"F8",X"08",X"08",X"C8",X"C8",X"E8",X"E8",X"F8",X"00",X"0A",X"02",X"00",
X"3F",X"40",X"5F",X"40",X"5F",X"50",X"53",X"57",X"55",X"57",X"5F",X"5F",X"40",X"50",X"70",X"00",
X"FC",X"02",X"FA",X"00",X"F8",X"08",X"C8",X"E8",X"68",X"E8",X"F8",X"F8",X"00",X"0A",X"02",X"00",
X"3F",X"40",X"5F",X"40",X"5F",X"50",X"53",X"57",X"5F",X"57",X"5F",X"5F",X"40",X"50",X"70",X"00",
X"FC",X"02",X"FA",X"00",X"F8",X"08",X"C8",X"E8",X"E8",X"E8",X"F8",X"F8",X"00",X"0A",X"02",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"10",X"38",X"10",X"7C",X"FE",X"00",X"00",X"02",X"04",X"7C",X"38",X"10",X"00",X"00",X"00",
X"00",X"10",X"10",X"10",X"10",X"38",X"10",X"10",X"00",X"18",X"1C",X"12",X"12",X"70",X"70",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"7C",X"D6",X"FE",X"BA",X"44",X"38",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",
X"81",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"81",
X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"76",X"39",X"19",X"06",X"0E",X"0D",X"0B",X"07",
X"76",X"B9",X"D9",X"E6",X"6E",X"9D",X"9B",X"67",X"00",X"80",X"C0",X"C0",X"60",X"80",X"90",X"60",
X"70",X"B0",X"D0",X"E0",X"60",X"90",X"90",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",
X"07",X"1F",X"3F",X"03",X"F0",X"61",X"00",X"00",X"00",X"80",X"81",X"00",X"00",X"FF",X"FF",X"74",
X"00",X"70",X"F0",X"78",X"30",X"00",X"00",X"00",X"00",X"00",X"07",X"78",X"84",X"02",X"02",X"01",
X"50",X"88",X"00",X"00",X"20",X"24",X"58",X"80",X"03",X"01",X"01",X"01",X"03",X"01",X"01",X"00",
X"80",X"80",X"9C",X"BC",X"BC",X"3C",X"3C",X"3F",X"74",X"74",X"74",X"7C",X"7C",X"7C",X"FC",X"FC",
X"00",X"60",X"78",X"7E",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"80",X"87",X"3F",X"7F",
X"00",X"00",X"00",X"00",X"F0",X"F0",X"F0",X"F0",X"05",X"0D",X"1B",X"00",X"00",X"00",X"00",X"00",
X"B8",X"B8",X"70",X"01",X"00",X"00",X"00",X"00",X"00",X"06",X"38",X"C0",X"00",X"00",X"00",X"00",
X"3E",X"1E",X"0C",X"04",X"00",X"00",X"00",X"00",X"7F",X"3F",X"3F",X"1F",X"04",X"00",X"08",X"00",
X"F0",X"F0",X"C0",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"11",X"EE",X"EE",X"0E",X"EE",X"EE",X"E0",X"EE",X"11",X"EE",X"EE",X"0E",X"EE",X"CE",X"9F",X"2B",
X"11",X"EE",X"EE",X"0E",X"EE",X"EE",X"E0",X"EE",X"11",X"EE",X"EE",X"0E",X"EE",X"EE",X"E0",X"EE",
X"EE",X"0E",X"EE",X"EE",X"E0",X"EE",X"EE",X"EE",X"49",X"88",X"88",X"FF",X"FF",X"EE",X"EE",X"EE",
X"EE",X"8E",X"EE",X"EE",X"E0",X"EE",X"EE",X"EE",X"EE",X"0E",X"EE",X"EE",X"E0",X"EE",X"EE",X"EE",
X"8F",X"88",X"88",X"E8",X"17",X"11",X"11",X"F1",X"8F",X"88",X"88",X"E8",X"17",X"11",X"11",X"F1",
X"8F",X"88",X"88",X"E8",X"17",X"11",X"11",X"F1",X"8F",X"88",X"88",X"E8",X"17",X"11",X"11",X"F1",
X"8F",X"88",X"88",X"E8",X"17",X"11",X"11",X"F1",X"8F",X"88",X"88",X"E8",X"17",X"11",X"11",X"F1",
X"8F",X"88",X"88",X"E8",X"17",X"11",X"11",X"F1",X"8F",X"88",X"88",X"E8",X"17",X"11",X"11",X"F1",
X"89",X"40",X"2F",X"1F",X"9F",X"3F",X"3F",X"BF",X"FD",X"7F",X"BF",X"FF",X"FF",X"FF",X"FD",X"F8",
X"89",X"46",X"A6",X"99",X"D1",X"E2",X"E4",X"D8",X"89",X"46",X"26",X"19",X"91",X"62",X"64",X"98",
X"BF",X"3F",X"3F",X"3F",X"BF",X"3F",X"3F",X"DF",X"F8",X"FD",X"FF",X"FF",X"FF",X"FF",X"FD",X"DD",
X"E9",X"E6",X"E6",X"F8",X"F0",X"E2",X"E4",X"F8",X"89",X"02",X"00",X"01",X"90",X"62",X"64",X"90",
X"9F",X"2F",X"2F",X"37",X"B8",X"3F",X"3F",X"BF",X"DF",X"DF",X"BD",X"7D",X"FE",X"FE",X"FE",X"FF",
X"C8",X"E6",X"F6",X"E9",X"F1",X"F2",X"F4",X"78",X"81",X"46",X"26",X"11",X"91",X"62",X"64",X"90",
X"BF",X"5F",X"1F",X"1F",X"8E",X"6F",X"6F",X"8F",X"FF",X"FF",X"FF",X"FF",X"0F",X"6F",X"6F",X"0F",
X"79",X"3A",X"3E",X"1D",X"9F",X"6F",X"67",X"9B",X"89",X"46",X"3E",X"1D",X"B9",X"FA",X"F4",X"C8",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"10",X"38",X"10",X"7C",X"FE",X"00",X"00",X"02",X"04",X"7C",X"38",X"10",X"00",X"00",X"00",
X"00",X"10",X"10",X"10",X"10",X"38",X"10",X"10",X"00",X"18",X"1C",X"12",X"12",X"70",X"70",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"7C",X"D6",X"FE",X"BA",X"44",X"38",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7F",X"3F",X"3F",X"1F",X"1F",X"0F",X"0F",X"07",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"80",X"80",X"C0",X"C0",X"E0",X"E0",X"F0",
X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"73",X"AD",X"DE",X"AD",X"73",X"AD",X"DE",X"AD",X"9B",X"67",X"EE",X"5E",X"BE",X"76",X"E6",X"C6",
X"D9",X"E6",X"F7",X"FA",X"FD",X"EE",X"E7",X"E3",X"CE",X"B5",X"7B",X"B5",X"CE",X"B5",X"7B",X"B5",
X"73",X"AF",X"DF",X"BD",X"78",X"F1",X"E2",X"FF",X"8E",X"16",X"86",X"C6",X"E6",X"76",X"3E",X"FE",
X"F1",X"E8",X"E1",X"E3",X"E7",X"EE",X"FC",X"FF",X"CE",X"F5",X"FB",X"BD",X"1E",X"8F",X"47",X"FF",
X"FF",X"FF",X"FF",X"FF",X"DC",X"EB",X"F7",X"DB",X"FF",X"FF",X"FF",X"FF",X"EF",X"5D",X"BE",X"6D",
X"FF",X"FF",X"FF",X"FF",X"57",X"7F",X"AF",X"D7",X"FF",X"FF",X"FF",X"FF",X"AB",X"FA",X"D5",X"AE",
X"F7",X"8F",X"F7",X"DB",X"F7",X"EB",X"DC",X"FF",X"BC",X"C7",X"BE",X"6D",X"BE",X"5D",X"EF",X"FF",
X"BB",X"7C",X"BB",X"D7",X"AF",X"7F",X"57",X"FF",X"74",X"FB",X"75",X"AE",X"D5",X"FA",X"AB",X"FF",
X"88",X"11",X"00",X"44",X"00",X"01",X"22",X"40",X"88",X"11",X"00",X"44",X"00",X"01",X"22",X"40",
X"88",X"11",X"00",X"44",X"00",X"01",X"22",X"40",X"88",X"11",X"00",X"44",X"00",X"01",X"22",X"40",
X"88",X"11",X"00",X"44",X"00",X"01",X"22",X"40",X"88",X"11",X"00",X"44",X"00",X"01",X"22",X"40",
X"88",X"11",X"00",X"44",X"00",X"01",X"22",X"40",X"88",X"11",X"00",X"44",X"00",X"01",X"22",X"40",
X"88",X"11",X"00",X"44",X"00",X"FF",X"FF",X"FF",X"88",X"11",X"00",X"44",X"00",X"FF",X"FF",X"FF",
X"88",X"11",X"00",X"44",X"00",X"FF",X"FF",X"FF",X"88",X"11",X"00",X"44",X"00",X"FF",X"FF",X"FF",
X"E8",X"71",X"38",X"5C",X"3E",X"77",X"E3",X"C1",X"8F",X"17",X"0E",X"5C",X"38",X"79",X"FA",X"D8",
X"C8",X"F1",X"70",X"7C",X"3C",X"3F",X"37",X"73",X"8E",X"1D",X"38",X"7C",X"EE",X"C7",X"A3",X"41",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"10",X"38",X"10",X"7C",X"FE",X"00",X"00",X"02",X"04",X"7C",X"38",X"10",X"00",X"00",X"00",
X"00",X"10",X"10",X"10",X"10",X"38",X"10",X"10",X"00",X"18",X"1C",X"12",X"12",X"70",X"70",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"7C",X"D6",X"FE",X"BA",X"44",X"38",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"16",X"0D",X"0E",X"07",X"07",X"02",X"03",X"01",
X"B7",X"7D",X"FE",X"E7",X"E7",X"FE",X"7D",X"B7",X"00",X"00",X"C0",X"C0",X"E0",X"E0",X"70",X"B0",
X"B0",X"70",X"F0",X"E0",X"E0",X"F0",X"70",X"B0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"D0",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"0C",
X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"04",X"00",X"00",X"02",X"07",X"01",X"02",X"00",X"80",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"06",X"07",X"07",X"03",X"01",X"38",X"34",X"1A",
X"30",X"F0",X"F0",X"E0",X"CC",X"9A",X"B6",X"FC",X"D7",X"3F",X"1F",X"0E",X"0E",X"05",X"E5",X"F7",
X"C2",X"80",X"00",X"00",X"E0",X"40",X"C0",X"00",X"00",X"00",X"20",X"90",X"F0",X"00",X"00",X"00",
X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"64",X"34",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"C0",X"C0",X"E0",X"FF",X"FF",X"01",X"FC",X"7E",X"01",X"3F",X"3F",X"FF",X"FE",X"00",X"7E",X"FF",
X"C0",X"FE",X"FE",X"FF",X"7F",X"00",X"7E",X"FF",X"01",X"01",X"03",X"FF",X"FF",X"80",X"3F",X"7E",
X"33",X"11",X"11",X"33",X"7E",X"FC",X"01",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"7E",X"00",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"7E",X"00",X"FF",X"CC",X"88",X"88",X"CC",X"7E",X"3F",X"80",X"FF",
X"55",X"AA",X"FF",X"FF",X"00",X"00",X"FF",X"7F",X"55",X"AA",X"FF",X"FF",X"00",X"00",X"FE",X"FF",
X"55",X"AA",X"FF",X"FF",X"00",X"00",X"7E",X"FF",X"55",X"AA",X"FF",X"FF",X"00",X"00",X"3F",X"7E",
X"33",X"11",X"11",X"33",X"7E",X"FC",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"7E",X"00",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"7E",X"00",X"FF",X"CC",X"88",X"88",X"CC",X"7E",X"3F",X"00",X"FF",
X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"0C",X"30",X"40",X"80",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"40",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"02",X"02",X"04",X"04",X"04",X"05",X"07",X"07",X"02",X"00",X"00",X"40",X"E0",X"F0",X"F8",X"FC",
X"00",X"00",X"06",X"0F",X"0F",X"1F",X"1F",X"3F",X"00",X"00",X"00",X"00",X"80",X"C0",X"C0",X"C0",
X"07",X"07",X"07",X"07",X"07",X"04",X"04",X"04",X"FE",X"FF",X"FF",X"FF",X"FE",X"01",X"01",X"03",
X"3F",X"7F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",
X"04",X"04",X"04",X"04",X"04",X"04",X"00",X"00",X"03",X"07",X"00",X"00",X"00",X"00",X"00",X"00",
X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"EF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

355
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/sdram.sv Normal file
View File

@@ -0,0 +1,355 @@
//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output reg [15:0] port1_q,
input [16:1] cpu1_addr,
output reg [15:0] cpu1_q,
input [16:1] cpu2_addr,
output reg [15:0] cpu2_q,
input [16:1] cpu3_addr,
output reg [15:0] cpu3_q,
input port2_req,
output reg port2_ack,
input port2_we,
input [23:1] port2_a,
input [1:0] port2_ds,
input [15:0] port2_d,
output reg [31:0] port2_q,
input [16:2] sp_addr,
output reg [31:0] sp_q
);
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
localparam RFRSH_CYCLES = 10'd842;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
/*
SDRAM state machine for 2 bank interleaved access
1 word burst, CL2
cmd issued registered
0 RAS0 cas1 - data0 read burst terminated
1 ras0
2 data1 returned
3 CAS0 data1 returned
4 RAS1 cas0
5 ras1
6 CAS1 data0 returned
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
localparam STATE_READ1 = 3'd3;
localparam STATE_DS1b = 3'd0;
localparam STATE_READ1b = 3'd4;
localparam STATE_LAST = 3'd6;
reg [2:0] t;
always @(posedge clk) begin
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[3];
reg [24:1] addr_latch_next[2];
reg [16:1] addr_last[4];
reg [16:2] addr_last2[2];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
reg [1:0] we_latch;
reg [1:0] ds[2];
reg port1_state;
reg port2_state;
localparam PORT_NONE = 3'd0;
localparam PORT_CPU1 = 3'd1;
localparam PORT_CPU2 = 3'd2;
localparam PORT_CPU3 = 3'd3;
localparam PORT_SP = 3'd1;
localparam PORT_REQ = 3'd4;
reg [2:0] next_port[2];
reg [2:0] port[2];
reg refresh;
reg [10:0] refresh_cnt;
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
// PORT1: bank 0,1
always @(*) begin
if (refresh) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end else if (port1_req ^ port1_state) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
next_port[0] = PORT_CPU1;
addr_latch_next[0] = { 8'd0, cpu1_addr };
end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
next_port[0] = PORT_CPU2;
addr_latch_next[0] = { 8'd0, cpu2_addr };
end else if (cpu3_addr != addr_last[PORT_CPU3]) begin
next_port[0] = PORT_CPU3;
addr_latch_next[0] = { 8'd0, cpu3_addr };
end else begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end
end
// PORT1: bank 2,3
always @(*) begin
if (port2_req ^ port2_state) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (sp_addr != addr_last2[PORT_SP]) begin
next_port[1] = PORT_SP;
addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
end
end
always @(posedge clk) begin
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
if(init) begin
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
end
end else begin
// RAS phase
// bank 0,1
if(t == STATE_RAS0) begin
addr_latch[0] <= addr_latch_next[0];
port[0] <= next_port[0];
{ oe_latch[0], we_latch[0] } <= 2'b00;
if (next_port[0] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
addr_last[next_port[0]] <= addr_latch_next[0][16:1];
if (next_port[0] == PORT_REQ) begin
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
ds[0] <= port1_ds;
din_latch[0] <= port1_d;
port1_state <= port1_req;
end else begin
{ oe_latch[0], we_latch[0] } <= 2'b10;
ds[0] <= 2'b11;
end
end
end
// bank 2,3
if(t == STATE_RAS1) begin
refresh <= 1'b0;
addr_latch[1] <= addr_latch_next[1];
{ oe_latch[1], we_latch[1] } <= 2'b00;
port[1] <= next_port[1];
if (next_port[1] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[1][22:10];
SDRAM_BA <= addr_latch_next[1][24:23];
addr_last2[next_port[1]] <= addr_latch_next[1][16:2];
if (next_port[1] == PORT_REQ) begin
{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
port2_state <= port2_req;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
end
end
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
refresh <= 1'b1;
refresh_cnt <= 0;
sd_cmd <= CMD_AUTO_REFRESH;
end
end
// CAS phase
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
if (we_latch[0]) begin
SDRAM_DQ <= din_latch[0];
port1_ack <= port1_req;
end
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[0][24:23];
end
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if (we_latch[1]) begin
SDRAM_DQ <= din_latch[1];
port2_ack <= port2_req;
end
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[1][24:23];
end
// Data returned
if(t == STATE_READ0 && oe_latch[0]) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; end
PORT_CPU2: begin cpu2_q <= sd_din; end
PORT_CPU3: begin cpu3_q <= sd_din; end
default: ;
endcase;
end
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ: port2_q[15:0] <= sd_din;
PORT_SP : sp_q[15:0] <= sd_din;
default: ;
endcase;
end
if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if(t == STATE_READ1b && oe_latch[1]) begin
case(port[1])
PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
PORT_SP : begin sp_q[31:16] <= sd_din; end
default: ;
endcase;
end
end
end
endmodule

59
Arcade_MiST/Sega System 1 Hardware/MiST-Arcade-Flicky/rtl/z80ip.v Normal file
View File

@@ -0,0 +1,59 @@
// Copyright (c) 2017,19 MiSTer-X
module Z80IP
(
input reset,
input clk,
output [15:0] adr,
input [7:0] data_in,
output [7:0] data_out,
output m1,
output mx,
output ix,
output rd,
output wr,
input intreq,
output intack,
input nmireq,
output nmiack
);
wire i_mreq, i_iorq, i_rd, i_wr, i_rfsh, i_m1;
T80s cpu
(
.CLK(~clk),
.RESET_n(~reset),
.INT_n(~intreq),
.NMI_n(~nmireq),
.MREQ_n(i_mreq),
.IORQ_n(i_iorq),
.RFSH_n(i_rfsh),
.RD_n(i_rd),
.WR_n(i_wr),
.A(adr),
.DI(data_in),
.DO(data_out),
.WAIT_n(1'b1),
.BUSRQ_n(1'b1),
.BUSAK_n(),
.HALT_n(),
.M1_n(i_m1)
);
wire mreq = (~i_mreq) & (i_rfsh);
wire iorq = ~i_iorq;
wire rdr = ~i_rd;
wire wrr = ~i_wr;
assign intack = (adr==16'h38) & mx & rdr;
assign nmiack = (adr==16'h66) & mx & rdr;
assign m1 = ~i_m1;
assign mx = mreq;
assign ix = iorq;
assign rd = rdr;
assign wr = wrr;
endmodule

34
Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/RobotronFPGA_MiST.sv
View File

@@ -56,14 +56,18 @@ wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire joyswap = status[6];
wire autoup = status[7];// Memory Protect for Lotto Fun
wire adv = status[8];
wire autoup = status[7] | (core_mod != 7'h8);// Memory Protect for Lotto Fun
wire adv = status[8] ;
reg [7:0] SW;
reg [7:0] JA;
reg [7:0] JB;
reg [7:0] AN0;
reg [7:0] AN1;
reg [7:0] AN2;
reg [7:0] AN3;
reg [3:0] BTN;
reg blitter_sc2, sinistar;
reg blitter_sc2, sinistar, speedball;
reg speech_en;
wire [6:0] core_mod;
@@ -87,8 +91,13 @@ always @(*) begin
JA = 8'hFF;
JB = 8'hFF;
BTN = 4'hF;
AN0 = 8'hFF;
AN1 = 8'hFF;
AN2 = 8'hFF;
AN3 = 8'hFF;
blitter_sc2 = 0;
sinistar = 0;
speedball = 0;
speech_en = 0;
case (core_mod)
@@ -150,9 +159,21 @@ always @(*) begin
end
7'h8: // LOTTO FUN
begin
BTN = { m_one_player, m_two_players, m_coin1 | m_coin2, reset };
JA = ~{ 1'b0, 1'b0, m_fireB, m_fireA, m_right, m_left, m_down, m_up };
JB = JA;
BTN = { m_one_player | m_fireA, 1'b0, m_coin1 | m_coin2, reset };
JA = ~{ 4'b0000, m_right, m_left, m_down, m_up };
JB = 8'b11111111;//IN1
end
7'h9: // Speed Ball
begin
speedball = 1;
BTN = { m_two_players, m_one_player, m_coin1 | m_coin2, reset };//IN2
JA = 8'b11111111;//IN0
JB = 8'b11111111;//IN1
//todo
// AN0 =;
// AN1 =;
// AN2 =;
// AN3 =;
end
default: ;
endcase
@@ -324,6 +345,7 @@ robotron_soc robotron_soc (
.blitter_sc2 ( blitter_sc2 ),
.sinistar ( sinistar ),
.speedball ( speedball ),
.BTN ( BTN ),
.SIN_FIRE ( ~m_fireA & ~m_fire2A ),
.SIN_BOMB ( ~m_fireB & ~m_fire2B ),

171
Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/robotron_cpu.vhd
View File

@@ -39,7 +39,7 @@ entity robotron_cpu is
clock : in std_logic;
blitter_sc2 : in std_logic;
sinistar : in std_logic;
speedball : in std_logic;
-- MC6809 signals
A : in std_logic_vector(15 downto 0);
Dout : in std_logic_vector(7 downto 0);
@@ -123,7 +123,11 @@ entity robotron_cpu is
JB : in std_logic_vector(7 downto 0);
SIN_FIRE : in std_logic;
SIN_BOMB : in std_logic;
-- Analog Input
AN0 : in std_logic_vector(7 downto 0);
AN1 : in std_logic_vector(7 downto 0);
AN2 : in std_logic_vector(7 downto 0);
AN3 : in std_logic_vector(7 downto 0);
-- To sound board
HAND : in std_logic := '1';
PB : out std_logic_vector(5 downto 0)
@@ -224,6 +228,7 @@ architecture Behavioral of robotron_cpu is
signal hiram_access : boolean; -- Sinistar hiram
signal color_table_access : boolean;
signal widget_pia_access : boolean;
signal extra_pia_access : boolean;
signal rom_pia_access : boolean;
signal blt_register_access : boolean;
signal video_counter_access : boolean;
@@ -315,6 +320,35 @@ architecture Behavioral of robotron_cpu is
signal widget_ic4_y : std_logic_vector(4 downto 1);
-------------------------------------------------------------------
-- signal SLAM : std_logic := '1';
-- signal R_COIN : std_logic := '1';
-- signal C_COIN : std_logic := '1';
-- signal L_COIN : std_logic := '1';
-- signal H_S_RESET : std_logic := '1';
-- signal ADVANCE : std_logic := '1';
-- signal AUTO_UP : std_logic := '0';
signal extra_pia_rs : std_logic_vector(1 downto 0) := (others => '0');
signal extra_pia_cs : std_logic := '0';
signal extra_pia_write : std_logic := '0';
signal extra_pia_data_in : std_logic_vector(7 downto 0);
signal extra_pia_data_out : std_logic_vector(7 downto 0);
signal extra_pia_ca2_out : std_logic;
signal extra_pia_ca2_dir : std_logic;
signal extra_pia_irq_a : std_logic;
signal extra_pia_pa_in : std_logic_vector(7 downto 0);
signal extra_pia_pa_out : std_logic_vector(7 downto 0);
signal extra_pia_pa_dir : std_logic_vector(7 downto 0);
signal extra_pia_cb2_out : std_logic;
signal extra_pia_cb2_dir : std_logic;
signal extra_pia_irq_b : std_logic;
signal extra_pia_pb_in : std_logic_vector(7 downto 0);
signal extra_pia_pb_out : std_logic_vector(7 downto 0);
signal extra_pia_pb_dir : std_logic_vector(7 downto 0);
-------------------------------------------------------------------
signal blt_rs : std_logic_vector(2 downto 0) := (others => '0');
signal blt_reg_cs : std_logic := '0';
@@ -431,6 +465,9 @@ begin
-- Widget PIA: read/write: C8X4 - C8X7
widget_pia_access <= std_match(address, "11001000----01--");
-- Speedball PIA: read/write: C8X8 - C8XB
extra_pia_access <= std_match(address, "11001000----1---");
-- ROM PIA: read/write: C8XC - C8XF
rom_pia_access <= std_match(address, "11001000----11--");
@@ -502,6 +539,9 @@ begin
widget_pia_cs <= '0';
widget_pia_write <= '0';
extra_pia_cs <= '0';
extra_pia_write <= '0';
if clock_12_phase( 0) = '1' then
memory_address <= "00" & video_prom_address &
@@ -676,6 +716,15 @@ begin
widget_pia_write <= to_std_logic(write);
widget_pia_cs <= '1';
end if;
if speedball = '1' then
if extra_pia_access then
extra_pia_rs <= address(1 downto 0);
extra_pia_data_in <= mpu_data_in;
extra_pia_write <= to_std_logic(write);
extra_pia_cs <= '1';
end if;
end if;
if control_access and write then
blt_win_en <= mpu_data_in(2) and sinistar;
@@ -699,6 +748,10 @@ begin
if widget_pia_access then
mpu_data_out <= widget_pia_data_out;
end if;
if extra_pia_access then
mpu_data_out <= extra_pia_data_out;
end if;
if rom_pia_access then
mpu_data_out <= rom_pia_data_out;
@@ -720,6 +773,7 @@ begin
to_std_logic(rom_access) &
to_std_logic(rom_pia_access) &
to_std_logic(widget_pia_access) &
-- to_std_logic(extra_pia_access) &
to_std_logic(blt_register_access);
led_bcd_in <= debug_blt_source_address;
@@ -773,7 +827,7 @@ begin
);
-------------------------------------------------------------------
--IN2
rom_pia_pa_in <= not HAND &
not SLAM &
not C_COIN &
@@ -833,28 +887,30 @@ begin
widget_ic4_b <= not (FIRE_RIGHT_1 & FIRE_LEFT_1 & FIRE_DOWN_1 & FIRE_UP_1);
widget_ic4_y <= widget_ic4_b when widget_pia_input_select = '1' else widget_ic4_a;
widget_pia_pa_in <= widget_ic4_y(2) &
widget_ic4_y(1) &
--IN0
widget_pia_pa_in <= widget_ic4_y(2) &--fire down
widget_ic4_y(1) &--fire up
not PLAYER_2_START &
not PLAYER_1_START &
widget_ic3_y(4) &
widget_ic3_y(3) &
widget_ic3_y(2) &
widget_ic3_y(1) when sinistar = '0' else
widget_ic4_y(4) &
widget_ic4_y(3) &
widget_ic4_y(2) &
widget_ic4_y(1) &
widget_ic3_y(4) &
widget_ic3_y(3) &
widget_ic3_y(2) &
widget_ic3_y(1);
widget_ic3_y(4) &--right
widget_ic3_y(3) &--left
widget_ic3_y(2) &--down
widget_ic3_y(1) when sinistar = '0' else--up
widget_ic4_y(4) &--fire right
widget_ic4_y(3) &--fire left
widget_ic4_y(2) &--fire down
widget_ic4_y(1) &--fire up
widget_ic3_y(4) &--right
widget_ic3_y(3) &--left
widget_ic3_y(2) &--down
widget_ic3_y(1);--up
--IN1
widget_pia_pb_in <= not board_interface_w1 &
"00000" &
widget_ic4_y(4) &
widget_ic4_y(3) when sinistar = '0' else
not board_interface_w1 &
widget_ic4_y(4) &--fire right
widget_ic4_y(3) when sinistar = '0' else --fire left
not board_interface_w1 &
"0" &
not PLAYER_2_START &
not PLAYER_1_START &
@@ -894,6 +950,79 @@ begin
);
-------------------------------------------------------------------
-- PORT_START("IN3")
-- PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
-- PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
-- PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
-- PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
-- PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(1)
-- PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
-- PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2)
-- PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
--IN3
extra_pia_pa_in <= '0' & --unknown
FIRE_UP_2 & --fire 2
'0' & --unknown
FIRE_UP_1 & --fire 1
MOVE_DOWN_2 &--down2
MOVE_UP_2 &--up2
MOVE_DOWN_1 &--down1
MOVE_UP_1;--up1
-- PORT_START("IN4")
-- PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
-- PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
-- PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
-- PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
-- PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNKNOWN )
-- PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
-- PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_START1 )
-- PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_START2 )
--IN4
extra_pia_pb_in <= not PLAYER_2_START &
not PLAYER_1_START &
"00" &
MOVE_RIGHT_2 &
MOVE_LEFT_2 &
MOVE_RIGHT_1 &
MOVE_LEFT_1;
extra_pia: work.pia6821
port map(
rst => reset,
clk => clock,
addr => address(1 downto 0),
cs => extra_pia_cs,
rw => not extra_pia_write,
data_in => mpu_data_in,
data_out => extra_pia_data_out,
ca1 => '0',
ca2_i => '0',
ca2_o => extra_pia_ca2_out,
ca2_oe => extra_pia_ca2_dir,
irqa => extra_pia_irq_a,
pa_i => extra_pia_pa_in,
pa_o => extra_pia_pa_out,
pa_oe => extra_pia_pa_dir,
cb1 => '0',
cb2_i => '1',
cb2_o => extra_pia_cb2_out,
cb2_oe => extra_pia_cb2_dir,
irqb => extra_pia_irq_b,
pb_i => extra_pia_pb_in,
pb_o => extra_pia_pb_out,
pb_oe => extra_pia_pb_dir
);
-------------------------------------------------------------------
E <= clock_e;
Q <= clock_q;

15
Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_soc.vhd
View File

@@ -58,7 +58,7 @@ port (
blitter_sc2 : in std_logic;
sinistar : in std_logic;
speedball : in std_logic;
-- Switches
SW : in std_logic_vector(7 downto 0);
@@ -81,7 +81,10 @@ port (
-- 12-pin connectors
JA : in std_logic_vector(7 downto 0);
JB : in std_logic_vector(7 downto 0);
AN0 : in std_logic_vector(7 downto 0);
AN1 : in std_logic_vector(7 downto 0);
AN2 : in std_logic_vector(7 downto 0);
AN3 : in std_logic_vector(7 downto 0);
dl_clock : in std_logic;
dl_addr : in std_logic_vector(16 downto 0);
dl_data : in std_logic_vector(7 downto 0);
@@ -166,7 +169,7 @@ port map (
clock => clock,
blitter_sc2 => blitter_sc2,
sinistar => sinistar,
speedball => speedball,
A => cpu_a,
Dout => cpu_dout,
Din => cpu_din,
@@ -231,7 +234,11 @@ port map (
-- 12-pin connectors
JA => JA,
JB => JB,
-- Analog Input
AN0 => AN0,
AN1 => AN1,
AN2 => AN2,
AN3 => AN3,
-- Sound board
PB => select_sound,
HAND => hand

372
common/Sound/opl3/NextZ80ALU.v Normal file
View File

@@ -0,0 +1,372 @@
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the NextZ80 project
// http://www.opencores.org/cores/nextz80/
//
// Filename: NextZ80ALU.v
// Description: Implementation of Z80 compatible CPU - ALU
// Version 1.0
// Creation date: 28Jan2011 - 18Mar2011
//
// Author: Nicolae Dumitrache
// e-mail: ndumitrache@opencores.org
//
/////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2011 Nicolae Dumitrache
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
///////////////////////////////////////////////////////////////////////////////////
//FLAGS: S Z X1 N X2 PV N C
// OP[4:0]
// 00000 - ADD D0,D1
// 00001 - ADC D0,D1
// 00010 - SUB D0,D1
// 00011 - SBC D0,D1
// 00100 - AND D0,D1
// 00101 - XOR D0,D1
// 00110 - OR D0,D1
// 00111 - CP D0,D1
// 01000 - INC D0
// 01001 - CPL D0
// 01010 - DEC D0
// 01011 - RRD
// 01100 - RLD
// 01101 - DAA
// 01110 - INC16
// 01111 - DEC16
// 10000 - ADD16LO
// 10001 - ADD16HI
// 10010 -
// 10011 -
// 10100 - CCF, pass D0
// 10101 - SCF, pass D0
// 10110 -
// 10111 -
// 11000 - RLCA D0
// 11001 - RRCA D0
// 11010 - RLA D0
// 11011 - RRA D0
// 11100 - {ROT, BIT, SET, RES} D0,EXOP
// RLC D0 C <-- D0 <-- D0[7]
// RRC D0 D0[0] --> D0 --> C
// RL D0 C <-- D0 <-- C
// RR D0 C --> D0 --> C
// SLA D0 C <-- D0 <-- 0
// SRA D0 D0[7] --> D0 --> C
// SLL D0 C <-- D0 <-- 1
// SRL D0 0 --> D0 --> C
// 11101 - IN, pass D1
// 11110 - FLAGS <- D0
// 11111 - NEG D1
///////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module ALU8(
input [7:0] D0,
input [7:0] D1,
input [7:0] FIN,
output reg[7:0] FOUT,
output reg [15:0] ALU8DOUT,
input [4:0] OP,
input [5:0] EXOP, // EXOP[5:4] = 2'b11 for CPI/D/R
input LDIFLAGS, // zero HF and NF on inc/dec16
input DSTHI // destination lo
);
wire [7:0] daaadjust;
wire cdaa, hdaa;
daa daa_adjust(.flags(FIN), .val(D0), .adjust(daaadjust), .cdaa(cdaa), .hdaa(hdaa));
wire parity = ~^ALU8DOUT[15:8];
wire zero = ALU8DOUT[15:8] == 0;
reg csin, cin;
wire [7:0]d0mux = OP[4:1] == 4'b1111 ? 8'd0 : D0;
reg [7:0]_d1mux;
wire [7:0]d1mux = OP[1] ? ~_d1mux : _d1mux;
wire [8:0]sum;
wire hf;
assign {hf, sum[3:0]} = d0mux[3:0] + d1mux[3:0] + cin;
assign sum[8:4] = d0mux[7:4] + d1mux[7:4] + hf;
wire overflow = (d0mux[7] & d1mux[7] & !sum[7]) | (!d0mux[7] & !d1mux[7] & sum[7]);
reg [7:0]dbit;
always @* begin
ALU8DOUT = 16'hxxxx;
FOUT = 8'hxx;
case({OP[4:2]})
0,1,4,7: _d1mux = D1;
2: _d1mux = 1;
3: _d1mux = daaadjust; // DAA
6,5: _d1mux = 8'hxx;
endcase
case({OP[2:0], FIN[0]})
0,1,2,7,8,9,10,11,12,13: cin = 0;
3,4,5,6,14,15: cin = 1;
endcase
case(EXOP[3:0])
0: dbit = 8'b11111110;
1: dbit = 8'b11111101;
2: dbit = 8'b11111011;
3: dbit = 8'b11110111;
4: dbit = 8'b11101111;
5: dbit = 8'b11011111;
6: dbit = 8'b10111111;
7: dbit = 8'b01111111;
8: dbit = 8'b00000001;
9: dbit = 8'b00000010;
10: dbit = 8'b00000100;
11: dbit = 8'b00001000;
12: dbit = 8'b00010000;
13: dbit = 8'b00100000;
14: dbit = 8'b01000000;
15: dbit = 8'b10000000;
endcase
case(OP[3] ? EXOP[2:0] : OP[2:0])
0,5: csin = D0[7];
1: csin = D0[0];
2,3: csin = FIN[0];
4,7: csin = 0;
6: csin = 1;
endcase
case(OP[4:0])
0,1,2,3,8,10: begin // ADD, ADC, SUB, SBC, INC, DEC
ALU8DOUT[15:8] = sum[7:0];
ALU8DOUT[7:0] = sum[7:0];
FOUT[0] = OP[3] ? FIN[0] : (sum[8] ^ OP[1]); // inc/dec
FOUT[1] = OP[1];
FOUT[2] = overflow;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = hf ^ OP[1];
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero & (FIN[6] | ~EXOP[5] | ~DSTHI | OP[3]); //(EXOP[5] & DSTHI) ? (zero & FIN[6]) : zero; // adc16/sbc16
FOUT[7] = ALU8DOUT[15];
end
16,17: begin // ADD16LO, ADD16HI
ALU8DOUT[15:8] = sum[7:0];
ALU8DOUT[7:0] = sum[7:0];
FOUT[0] = sum[8];
FOUT[1] = OP[1];
FOUT[2] = FIN[2];
FOUT[3] = ALU8DOUT[11];
FOUT[4] = hf ^ OP[1];
FOUT[5] = ALU8DOUT[13];
FOUT[6] = FIN[6];
FOUT[7] = FIN[7];
end
7: begin // CP
ALU8DOUT[15:8] = sum[7:0];
FOUT[0] = EXOP[5] ? FIN[0] : !sum[8]; // CPI/D/R
FOUT[1] = OP[1];
FOUT[2] = overflow;
FOUT[3] = D1[3];
FOUT[4] = !hf;
FOUT[5] = D1[5];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
31: begin // NEG
ALU8DOUT[15:8] = sum[7:0];
FOUT[0] = !sum[8];
FOUT[1] = OP[1];
FOUT[2] = overflow;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = !hf;
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
4: begin // AND
ALU8DOUT[15:8] = D0 & D1;
FOUT[0] = 0;
FOUT[1] = 0;
FOUT[2] = parity;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = 1;
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
5,6: begin //XOR, OR
ALU8DOUT[15:8] = OP[0] ? (D0 ^ D1) : (D0 | D1);
FOUT[0] = 0;
FOUT[1] = 0;
FOUT[2] = parity;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = 0;
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
9: begin // CPL
ALU8DOUT[15:8] = ~D0;
FOUT[0] = FIN[0];
FOUT[1] = 1;
FOUT[2] = FIN[2];
FOUT[3] = ALU8DOUT[11];
FOUT[4] = 1;
FOUT[5] = ALU8DOUT[13];
FOUT[7:6] = FIN[7:6];
end
11,12: begin // RLD, RRD
if(OP[0]) ALU8DOUT = {D0[7:4], D1[3:0], D0[3:0], D1[7:4]};
else ALU8DOUT = {D0[7:4], D1[7:0], D0[3:0]};
FOUT[0] = FIN[0];
FOUT[1] = 0;
FOUT[2] = parity;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = 0;
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
13: begin // DAA
ALU8DOUT[15:8] = sum[7:0];
FOUT[0] = cdaa;
FOUT[1] = FIN[1];
FOUT[2] = parity;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = hdaa;
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
14,15: begin // inc/dec 16
ALU8DOUT = {D0, D1} + (OP[0] ? 16'hffff : 16'h0001);
FOUT[0] = FIN[0];
FOUT[1] = LDIFLAGS ? 1'b0 : FIN[1];
FOUT[2] = ALU8DOUT != 0;
FOUT[3] = FIN[3];
FOUT[4] = LDIFLAGS ? 1'b0 : FIN[4];
FOUT[5] = FIN[5];
FOUT[6] = FIN[6];
FOUT[7] = FIN[7];
end
20,21: begin // CCF, SCF
ALU8DOUT[15:8] = D0;
FOUT[0] = OP[0] ? 1'b1 : !FIN[0];
FOUT[1] = 1'b0;
FOUT[2] = FIN[2];
FOUT[3] = ALU8DOUT[11];
FOUT[4] = OP[0] ? 1'b0 : FIN[0];
FOUT[5] = ALU8DOUT[13];
FOUT[6] = FIN[6];
FOUT[7] = FIN[7];
end
24,25,26,27, 28: begin // ROT, BIT, RES, SET
case({OP[2], EXOP[4:3]})
0,1,2,3,4: // rot - shift
if(OP[2] ? EXOP[0] : OP[0]){ALU8DOUT[15:8], FOUT[0]} = {csin, D0}; // right
else {FOUT[0], ALU8DOUT[15:8]} = {D0, csin}; // left
5,6: begin // BIT, RES
FOUT[0] = FIN[0];
ALU8DOUT[15:8] = D0 & dbit;
end
7: begin // SET
FOUT[0] = FIN[0];
ALU8DOUT[15:8] = D0 | dbit;
end
endcase
ALU8DOUT[7:0] = ALU8DOUT[15:8];
FOUT[1] = 0;
FOUT[2] = OP[2] ? (EXOP[3] ? zero : parity) : FIN[2];
FOUT[3] = ALU8DOUT[11];
FOUT[4] = OP[2] & EXOP[3];
FOUT[5] = ALU8DOUT[13];
FOUT[6] = OP[2] ? zero : FIN[6];
FOUT[7] = OP[2] ? ALU8DOUT[15] : FIN[7];
end
29: begin // IN, pass D1
ALU8DOUT = {D1, D1};
FOUT[0] = FIN[0];
FOUT[1] = 0;
FOUT[2] = parity;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = 0;
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
30: FOUT = D0; // FLAGS <- D0
default:;
endcase
end
endmodule
module daa (
input [7:0]flags,
input [7:0]val,
output wire [7:0]adjust,
output reg cdaa,
output reg hdaa
);
wire h08 = val[7:4] < 9;
wire h09 = val[7:4] < 10;
wire l05 = val[3:0] < 6;
wire l09 = val[3:0] < 10;
reg [1:0]aa;
assign adjust = ({1'b0, aa[1], aa[1], 2'b0, aa[0], aa[0], 1'b0} ^ {8{flags[1]}}) + flags[1];
always @* begin
case({flags[0], h08, h09, flags[4], l09})
5'b00101, 5'b01101: aa = 0;
5'b00111, 5'b01111, 5'b01000, 5'b01010, 5'b01100, 5'b01110: aa = 1;
5'b00001, 5'b01001, 5'b10001, 5'b10101, 5'b11001, 5'b11101: aa = 2;
default: aa = 3;
endcase
case({flags[0], h08, h09, l09})
4'b0011, 4'b0111, 4'b0100, 4'b0110: cdaa = 0;
default: cdaa = 1;
endcase
case({flags[1], flags[4], l05, l09})
4'b0000, 4'b0010, 4'b0100, 4'b0110, 4'b1110, 4'b1111: hdaa = 1;
default: hdaa = 0;
endcase
end
endmodule
module ALU16(
input [15:0] D0,
input [7:0] D1,
output wire[15:0] DOUT,
input [2:0]OP // 0-NOP, 1-INC, 2-INC2, 3-ADD, 4-NOP, 5-DEC, 6-DEC2
);
reg [15:0] mux;
always @*
case(OP)
0: mux = 0; // post inc
1: mux = 1; // post inc
2: mux = 2; // post inc
3: mux = {D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7:0]}; // post inc
4: mux = 0; // no post inc
5: mux = 16'hffff; // no post inc
6: mux = 16'hfffe; // no post inc
default: mux = 16'hxxxx;
endcase
assign DOUT = D0 + mux;
endmodule

1501
common/Sound/opl3/NextZ80CPU.v Normal file
View File

File diff suppressed because it is too large Load Diff

202
common/Sound/opl3/NextZ80Reg.v Normal file
View File

@@ -0,0 +1,202 @@
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the NextZ80 project
// http://www.opencores.org/cores/nextz80/
//
// Filename: NextZ80Regs.v
// Description: Implementation of Z80 compatible CPU - registers
// Version 1.0
// Creation date: 28Jan2011 - 18Mar2011
//
// Author: Nicolae Dumitrache
// e-mail: ndumitrache@opencores.org
//
/////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2011 Nicolae Dumitrache
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
///////////////////////////////////////////////////////////////////////////////////
// altera message_off 10027
`timescale 1ns / 1ps
module Z80Reg(
input wire [7:0]rstatus, // 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy, 6=IFF1, 7=IFF2
input wire M1,
input wire [5:0]WE, // 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo
input wire CLK,
input wire [15:0]ALU8OUT, // CPU data out bus (output of alu8)
input wire [7:0]DI, // CPU data in bus
output reg [7:0]DO, // CPU data out bus
input wire [15:0]ADDR, // CPU addr bus
input wire [7:0]CONST,
output reg [7:0]ALU80,
output reg [7:0]ALU81,
output reg [15:0]ALU160,
output wire[7:0]ALU161,
input wire [7:0]ALU8FLAGS,
output wire [7:0]FLAGS,
input wire [1:0]DO_SEL, // select DO betwen ALU8OUT lo and th register
input wire ALU160_sel, // 0=REG_RSEL, 1=PC
input wire [3:0]REG_WSEL, // rdow: [3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-x ----- [0] = 0HI,1LO
input wire [3:0]REG_RSEL, // mux_rdor: [3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-R, 5=SP, 7=tmpSP ----- [0] = 0HI, 1LO
input wire DINW_SEL, // select RAM write data between (0)ALU8OUT, and 1(DI)
input wire XMASK, // 0 if REG_WSEL should not use IX, IY, even if rstatus[4] == 1
input wire [2:0]ALU16OP, // ALU16OP
input wire WAIT // wait
);
// latch registers
reg [15:0]pc=0; // program counter
reg [15:0]sp; // stack pointer
reg [7:0]r; // refresh
reg [15:0]flg = 0;
reg [7:0]th; // temp high
// internal wires
wire [15:0]rdor; // R out from RAM
wire [15:0]rdow; // W out from RAM
wire [3:0]SELW; // RAM W port sel
wire [3:0]SELR; // RAM R port sel
reg [15:0]DIN; // RAM W in data
reg [15:0]mux_rdor; // (3)A reversed mixed with TL, (4)I mixed with R (5)SP
//------------------------------------ RAM block registers ----------------------------------
// 0:BC, 1:DE, 2:HL, 3:A-x, 4:I-x, 5:IX, 6:IY, 7:x-x, 8:BC', 9:DE', 10:HL', 11:A'-x, 12: tmpSP, 13:zero
RAM16X8D_regs regs_lo (
.DPO(rdor[7:0]), // Read-only data output
.SPO(rdow[7:0]), // R/W data output
.A(SELW), // R/W address
.D(DIN[7:0]), // Write data input
.DPRA(SELR), // Read-only address
.WCLK(CLK), // Write clock input
.WE(WE[0] & !WAIT) // Write enable input
);
RAM16X8D_regs regs_hi (
.DPO(rdor[15:8]), // Read-only data output
.SPO(rdow[15:8]), // R/W data output
.A(SELW), // R/W address
.D(DIN[15:8]), // Write data input
.DPRA(SELR), // Read-only address
.WCLK(CLK), // Write clock input
.WE(WE[1] & !WAIT) // Write enable input
);
wire [15:0]ADDR1 = ADDR + !ALU16OP[2]; // address post increment
wire [7:0]flgmux = {ALU8FLAGS[7:3], SELR[3:0] == 4'b0100 ? rstatus[7] : ALU8FLAGS[2], ALU8FLAGS[1:0]}; // LD A, I/R IFF2 flag on parity
always @(posedge CLK)
if(!WAIT) begin
if(WE[2]) th <= DI;
if(WE[3]) sp <= ADDR1;
if(WE[4]) pc <= ADDR1;
if({REG_WSEL, WE[0]} == 5'b10011) r <= ALU8OUT[7:0];
else if(M1) r[6:0] <= r[6:0] + 1'd1;
if(WE[5])
if(rstatus[0]) flg[15:8] <= flgmux;
else flg[7:0] <= flgmux;
end
assign ALU161 = th;
assign FLAGS = rstatus[0] ? flg[15:8] : flg[7:0];
always @* begin
DIN = DINW_SEL ? {DI, DI} : ALU8OUT;
ALU80 = REG_WSEL[0] ? rdow[7:0] : rdow[15:8];
ALU81 = REG_RSEL[0] ? mux_rdor[7:0] : mux_rdor[15:8];
ALU160 = ALU160_sel ? pc : mux_rdor;
case({REG_WSEL[3], DO_SEL})
0: DO = ALU80;
1: DO = th;
2: DO = FLAGS;
3: DO = ALU8OUT[7:0];
4: DO = pc[15:8];
5: DO = pc[7:0];
6: DO = sp[15:8];
7: DO = sp[7:0];
endcase
case({ALU16OP == 4, REG_RSEL[3:0]})
5'b01001, 5'b11001: mux_rdor = {rdor[15:8], r};
5'b01010, 5'b01011: mux_rdor = sp;
5'b01100, 5'b01101, 5'b11100, 5'b11101: mux_rdor = {8'b0, CONST};
default: mux_rdor = rdor;
endcase
end
RegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus({rstatus[5], rstatus[4] & XMASK, rstatus[3:0]}));
RegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus[5:0]));
endmodule
module RegSelect(
input [2:0]SEL,
output reg [3:0]RAMSEL,
input [5:0]rstatus // 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy
);
always @* begin
RAMSEL = 4'bxxxx;
case(SEL)
0: RAMSEL = {rstatus[1], 3'b000}; // BC
1: //DE
if(rstatus[{1'b1, rstatus[1]}]) RAMSEL = {rstatus[1], 3'b010}; // HL
else RAMSEL = {rstatus[1], 3'b001}; // DE
2: // HL
case({rstatus[5:4], rstatus[{1'b1, rstatus[1]}]})
0,4: RAMSEL = {rstatus[1], 3'b010}; // HL
1,5: RAMSEL = {rstatus[1], 3'b001}; // DE
2,3: RAMSEL = 4'b0101; // IX
6,7: RAMSEL = 4'b0110; // IY
endcase
3: RAMSEL = {rstatus[0], 3'b011}; // A-TL
4: RAMSEL = 4; // I-R
5: RAMSEL = 12; // tmp SP
6: RAMSEL = 13; // zero
7: RAMSEL = 7; // temp reg for BIT/SET/RES
endcase
end
endmodule
module RAM16X8D_regs(
output [7:0]DPO, // Read-only data output
output [7:0]SPO, // R/W data output
input [3:0]A, // R/W address
input [7:0]D, // Write data input
input [3:0]DPRA, // Read-only address
input WCLK, // Write clock
input WE // Write enable
);
reg [7:0]data[15:0];
assign DPO = data[DPRA];
assign SPO = data[A];
always @(posedge WCLK)
if(WE) data[A] <= D;
endmodule

297
common/Sound/opl3/compressor.sv Normal file
View File

@@ -0,0 +1,297 @@
//============================================================================
// Audio compressor (signed samples)
//
// Copyright (C) 2018 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module compressor
(
input clk,
input ce,
input [11:0] in1, in2,
output [15:0] out1, out2
);
always @(posedge clk) if(ce) out1 <= {in1[11], in1[11] ? ~tbl[~in1[10:0]] : tbl[in1[10:0]]};
always @(posedge clk) if(ce) out2 <= {in2[11], in2[11] ? ~tbl[~in2[10:0]] : tbl[in2[10:0]]};
wire [14:0] tbl[0:2047] =
'{
/*
//sin(x)
15'h0000, 15'h0019, 15'h0032, 15'h004B, 15'h0064, 15'h007D, 15'h0096, 15'h00B0, 15'h00C9, 15'h00E2, 15'h00FB, 15'h0114, 15'h012D, 15'h0146, 15'h0160, 15'h0179,
15'h0192, 15'h01AB, 15'h01C4, 15'h01DD, 15'h01F6, 15'h0210, 15'h0229, 15'h0242, 15'h025B, 15'h0274, 15'h028D, 15'h02A6, 15'h02BF, 15'h02D9, 15'h02F2, 15'h030B,
15'h0324, 15'h033D, 15'h0356, 15'h036F, 15'h0389, 15'h03A2, 15'h03BB, 15'h03D4, 15'h03ED, 15'h0406, 15'h041F, 15'h0439, 15'h0452, 15'h046B, 15'h0484, 15'h049D,
15'h04B6, 15'h04CF, 15'h04E8, 15'h0502, 15'h051B, 15'h0534, 15'h054D, 15'h0566, 15'h057F, 15'h0598, 15'h05B1, 15'h05CB, 15'h05E4, 15'h05FD, 15'h0616, 15'h062F,
15'h0648, 15'h0661, 15'h067A, 15'h0693, 15'h06AD, 15'h06C6, 15'h06DF, 15'h06F8, 15'h0711, 15'h072A, 15'h0743, 15'h075C, 15'h0775, 15'h078E, 15'h07A8, 15'h07C1,
15'h07DA, 15'h07F3, 15'h080C, 15'h0825, 15'h083E, 15'h0857, 15'h0870, 15'h0889, 15'h08A3, 15'h08BC, 15'h08D5, 15'h08EE, 15'h0907, 15'h0920, 15'h0939, 15'h0952,
15'h096B, 15'h0984, 15'h099D, 15'h09B6, 15'h09CF, 15'h09E9, 15'h0A02, 15'h0A1B, 15'h0A34, 15'h0A4D, 15'h0A66, 15'h0A7F, 15'h0A98, 15'h0AB1, 15'h0ACA, 15'h0AE3,
15'h0AFC, 15'h0B15, 15'h0B2E, 15'h0B47, 15'h0B60, 15'h0B79, 15'h0B92, 15'h0BAC, 15'h0BC5, 15'h0BDE, 15'h0BF7, 15'h0C10, 15'h0C29, 15'h0C42, 15'h0C5B, 15'h0C74,
15'h0C8D, 15'h0CA6, 15'h0CBF, 15'h0CD8, 15'h0CF1, 15'h0D0A, 15'h0D23, 15'h0D3C, 15'h0D55, 15'h0D6E, 15'h0D87, 15'h0DA0, 15'h0DB9, 15'h0DD2, 15'h0DEB, 15'h0E04,
15'h0E1D, 15'h0E36, 15'h0E4F, 15'h0E68, 15'h0E81, 15'h0E9A, 15'h0EB3, 15'h0ECC, 15'h0EE5, 15'h0EFE, 15'h0F17, 15'h0F30, 15'h0F49, 15'h0F62, 15'h0F7B, 15'h0F94,
15'h0FAC, 15'h0FC5, 15'h0FDE, 15'h0FF7, 15'h1010, 15'h1029, 15'h1042, 15'h105B, 15'h1074, 15'h108D, 15'h10A6, 15'h10BF, 15'h10D8, 15'h10F1, 15'h110A, 15'h1123,
15'h113B, 15'h1154, 15'h116D, 15'h1186, 15'h119F, 15'h11B8, 15'h11D1, 15'h11EA, 15'h1203, 15'h121C, 15'h1234, 15'h124D, 15'h1266, 15'h127F, 15'h1298, 15'h12B1,
15'h12CA, 15'h12E3, 15'h12FB, 15'h1314, 15'h132D, 15'h1346, 15'h135F, 15'h1378, 15'h1391, 15'h13A9, 15'h13C2, 15'h13DB, 15'h13F4, 15'h140D, 15'h1426, 15'h143E,
15'h1457, 15'h1470, 15'h1489, 15'h14A2, 15'h14BB, 15'h14D3, 15'h14EC, 15'h1505, 15'h151E, 15'h1537, 15'h154F, 15'h1568, 15'h1581, 15'h159A, 15'h15B3, 15'h15CB,
15'h15E4, 15'h15FD, 15'h1616, 15'h162E, 15'h1647, 15'h1660, 15'h1679, 15'h1691, 15'h16AA, 15'h16C3, 15'h16DC, 15'h16F4, 15'h170D, 15'h1726, 15'h173F, 15'h1757,
15'h1770, 15'h1789, 15'h17A1, 15'h17BA, 15'h17D3, 15'h17EC, 15'h1804, 15'h181D, 15'h1836, 15'h184E, 15'h1867, 15'h1880, 15'h1898, 15'h18B1, 15'h18CA, 15'h18E2,
15'h18FB, 15'h1914, 15'h192C, 15'h1945, 15'h195E, 15'h1976, 15'h198F, 15'h19A8, 15'h19C0, 15'h19D9, 15'h19F2, 15'h1A0A, 15'h1A23, 15'h1A3B, 15'h1A54, 15'h1A6D,
15'h1A85, 15'h1A9E, 15'h1AB6, 15'h1ACF, 15'h1AE8, 15'h1B00, 15'h1B19, 15'h1B31, 15'h1B4A, 15'h1B62, 15'h1B7B, 15'h1B94, 15'h1BAC, 15'h1BC5, 15'h1BDD, 15'h1BF6,
15'h1C0E, 15'h1C27, 15'h1C3F, 15'h1C58, 15'h1C70, 15'h1C89, 15'h1CA1, 15'h1CBA, 15'h1CD2, 15'h1CEB, 15'h1D03, 15'h1D1C, 15'h1D34, 15'h1D4D, 15'h1D65, 15'h1D7E,
15'h1D96, 15'h1DAF, 15'h1DC7, 15'h1DE0, 15'h1DF8, 15'h1E10, 15'h1E29, 15'h1E41, 15'h1E5A, 15'h1E72, 15'h1E8B, 15'h1EA3, 15'h1EBB, 15'h1ED4, 15'h1EEC, 15'h1F05,
15'h1F1D, 15'h1F35, 15'h1F4E, 15'h1F66, 15'h1F7F, 15'h1F97, 15'h1FAF, 15'h1FC8, 15'h1FE0, 15'h1FF8, 15'h2011, 15'h2029, 15'h2041, 15'h205A, 15'h2072, 15'h208A,
15'h20A3, 15'h20BB, 15'h20D3, 15'h20EC, 15'h2104, 15'h211C, 15'h2134, 15'h214D, 15'h2165, 15'h217D, 15'h2196, 15'h21AE, 15'h21C6, 15'h21DE, 15'h21F7, 15'h220F,
15'h2227, 15'h223F, 15'h2257, 15'h2270, 15'h2288, 15'h22A0, 15'h22B8, 15'h22D1, 15'h22E9, 15'h2301, 15'h2319, 15'h2331, 15'h2349, 15'h2362, 15'h237A, 15'h2392,
15'h23AA, 15'h23C2, 15'h23DA, 15'h23F3, 15'h240B, 15'h2423, 15'h243B, 15'h2453, 15'h246B, 15'h2483, 15'h249B, 15'h24B3, 15'h24CB, 15'h24E4, 15'h24FC, 15'h2514,
15'h252C, 15'h2544, 15'h255C, 15'h2574, 15'h258C, 15'h25A4, 15'h25BC, 15'h25D4, 15'h25EC, 15'h2604, 15'h261C, 15'h2634, 15'h264C, 15'h2664, 15'h267C, 15'h2694,
15'h26AC, 15'h26C4, 15'h26DC, 15'h26F4, 15'h270C, 15'h2724, 15'h273C, 15'h2754, 15'h276C, 15'h2783, 15'h279B, 15'h27B3, 15'h27CB, 15'h27E3, 15'h27FB, 15'h2813,
15'h282B, 15'h2843, 15'h285A, 15'h2872, 15'h288A, 15'h28A2, 15'h28BA, 15'h28D2, 15'h28EA, 15'h2901, 15'h2919, 15'h2931, 15'h2949, 15'h2961, 15'h2978, 15'h2990,
15'h29A8, 15'h29C0, 15'h29D7, 15'h29EF, 15'h2A07, 15'h2A1F, 15'h2A36, 15'h2A4E, 15'h2A66, 15'h2A7E, 15'h2A95, 15'h2AAD, 15'h2AC5, 15'h2ADC, 15'h2AF4, 15'h2B0C,
15'h2B24, 15'h2B3B, 15'h2B53, 15'h2B6B, 15'h2B82, 15'h2B9A, 15'h2BB1, 15'h2BC9, 15'h2BE1, 15'h2BF8, 15'h2C10, 15'h2C28, 15'h2C3F, 15'h2C57, 15'h2C6E, 15'h2C86,
15'h2C9D, 15'h2CB5, 15'h2CCD, 15'h2CE4, 15'h2CFC, 15'h2D13, 15'h2D2B, 15'h2D42, 15'h2D5A, 15'h2D71, 15'h2D89, 15'h2DA0, 15'h2DB8, 15'h2DCF, 15'h2DE7, 15'h2DFE,
15'h2E16, 15'h2E2D, 15'h2E45, 15'h2E5C, 15'h2E73, 15'h2E8B, 15'h2EA2, 15'h2EBA, 15'h2ED1, 15'h2EE9, 15'h2F00, 15'h2F17, 15'h2F2F, 15'h2F46, 15'h2F5D, 15'h2F75,
15'h2F8C, 15'h2FA3, 15'h2FBB, 15'h2FD2, 15'h2FE9, 15'h3001, 15'h3018, 15'h302F, 15'h3047, 15'h305E, 15'h3075, 15'h308C, 15'h30A4, 15'h30BB, 15'h30D2, 15'h30E9,
15'h3101, 15'h3118, 15'h312F, 15'h3146, 15'h315E, 15'h3175, 15'h318C, 15'h31A3, 15'h31BA, 15'h31D1, 15'h31E9, 15'h3200, 15'h3217, 15'h322E, 15'h3245, 15'h325C,
15'h3273, 15'h328A, 15'h32A2, 15'h32B9, 15'h32D0, 15'h32E7, 15'h32FE, 15'h3315, 15'h332C, 15'h3343, 15'h335A, 15'h3371, 15'h3388, 15'h339F, 15'h33B6, 15'h33CD,
15'h33E4, 15'h33FB, 15'h3412, 15'h3429, 15'h3440, 15'h3457, 15'h346E, 15'h3485, 15'h349C, 15'h34B3, 15'h34CA, 15'h34E1, 15'h34F7, 15'h350E, 15'h3525, 15'h353C,
15'h3553, 15'h356A, 15'h3581, 15'h3597, 15'h35AE, 15'h35C5, 15'h35DC, 15'h35F3, 15'h360A, 15'h3620, 15'h3637, 15'h364E, 15'h3665, 15'h367B, 15'h3692, 15'h36A9,
15'h36C0, 15'h36D6, 15'h36ED, 15'h3704, 15'h371A, 15'h3731, 15'h3748, 15'h375E, 15'h3775, 15'h378C, 15'h37A2, 15'h37B9, 15'h37D0, 15'h37E6, 15'h37FD, 15'h3814,
15'h382A, 15'h3841, 15'h3857, 15'h386E, 15'h3884, 15'h389B, 15'h38B2, 15'h38C8, 15'h38DF, 15'h38F5, 15'h390C, 15'h3922, 15'h3939, 15'h394F, 15'h3966, 15'h397C,
15'h3993, 15'h39A9, 15'h39BF, 15'h39D6, 15'h39EC, 15'h3A03, 15'h3A19, 15'h3A30, 15'h3A46, 15'h3A5C, 15'h3A73, 15'h3A89, 15'h3A9F, 15'h3AB6, 15'h3ACC, 15'h3AE2,
15'h3AF9, 15'h3B0F, 15'h3B25, 15'h3B3C, 15'h3B52, 15'h3B68, 15'h3B7F, 15'h3B95, 15'h3BAB, 15'h3BC1, 15'h3BD7, 15'h3BEE, 15'h3C04, 15'h3C1A, 15'h3C30, 15'h3C47,
15'h3C5D, 15'h3C73, 15'h3C89, 15'h3C9F, 15'h3CB5, 15'h3CCB, 15'h3CE2, 15'h3CF8, 15'h3D0E, 15'h3D24, 15'h3D3A, 15'h3D50, 15'h3D66, 15'h3D7C, 15'h3D92, 15'h3DA8,
15'h3DBE, 15'h3DD4, 15'h3DEA, 15'h3E00, 15'h3E16, 15'h3E2C, 15'h3E42, 15'h3E58, 15'h3E6E, 15'h3E84, 15'h3E9A, 15'h3EB0, 15'h3EC6, 15'h3EDC, 15'h3EF2, 15'h3F08,
15'h3F1D, 15'h3F33, 15'h3F49, 15'h3F5F, 15'h3F75, 15'h3F8B, 15'h3FA1, 15'h3FB6, 15'h3FCC, 15'h3FE2, 15'h3FF8, 15'h400E, 15'h4023, 15'h4039, 15'h404F, 15'h4065,
15'h407A, 15'h4090, 15'h40A6, 15'h40BB, 15'h40D1, 15'h40E7, 15'h40FC, 15'h4112, 15'h4128, 15'h413D, 15'h4153, 15'h4169, 15'h417E, 15'h4194, 15'h41A9, 15'h41BF,
15'h41D5, 15'h41EA, 15'h4200, 15'h4215, 15'h422B, 15'h4240, 15'h4256, 15'h426B, 15'h4281, 15'h4296, 15'h42AC, 15'h42C1, 15'h42D7, 15'h42EC, 15'h4301, 15'h4317,
15'h432C, 15'h4342, 15'h4357, 15'h436C, 15'h4382, 15'h4397, 15'h43AC, 15'h43C2, 15'h43D7, 15'h43EC, 15'h4402, 15'h4417, 15'h442C, 15'h4442, 15'h4457, 15'h446C,
15'h4481, 15'h4497, 15'h44AC, 15'h44C1, 15'h44D6, 15'h44EB, 15'h4501, 15'h4516, 15'h452B, 15'h4540, 15'h4555, 15'h456A, 15'h4580, 15'h4595, 15'h45AA, 15'h45BF,
15'h45D4, 15'h45E9, 15'h45FE, 15'h4613, 15'h4628, 15'h463D, 15'h4652, 15'h4667, 15'h467C, 15'h4691, 15'h46A6, 15'h46BB, 15'h46D0, 15'h46E5, 15'h46FA, 15'h470F,
15'h4724, 15'h4739, 15'h474D, 15'h4762, 15'h4777, 15'h478C, 15'h47A1, 15'h47B6, 15'h47CB, 15'h47DF, 15'h47F4, 15'h4809, 15'h481E, 15'h4833, 15'h4847, 15'h485C,
15'h4871, 15'h4885, 15'h489A, 15'h48AF, 15'h48C4, 15'h48D8, 15'h48ED, 15'h4902, 15'h4916, 15'h492B, 15'h4940, 15'h4954, 15'h4969, 15'h497D, 15'h4992, 15'h49A6,
15'h49BB, 15'h49D0, 15'h49E4, 15'h49F9, 15'h4A0D, 15'h4A22, 15'h4A36, 15'h4A4B, 15'h4A5F, 15'h4A74, 15'h4A88, 15'h4A9C, 15'h4AB1, 15'h4AC5, 15'h4ADA, 15'h4AEE,
15'h4B02, 15'h4B17, 15'h4B2B, 15'h4B40, 15'h4B54, 15'h4B68, 15'h4B7C, 15'h4B91, 15'h4BA5, 15'h4BB9, 15'h4BCE, 15'h4BE2, 15'h4BF6, 15'h4C0A, 15'h4C1F, 15'h4C33,
15'h4C47, 15'h4C5B, 15'h4C6F, 15'h4C84, 15'h4C98, 15'h4CAC, 15'h4CC0, 15'h4CD4, 15'h4CE8, 15'h4CFC, 15'h4D10, 15'h4D24, 15'h4D38, 15'h4D4C, 15'h4D61, 15'h4D75,
15'h4D89, 15'h4D9D, 15'h4DB1, 15'h4DC5, 15'h4DD8, 15'h4DEC, 15'h4E00, 15'h4E14, 15'h4E28, 15'h4E3C, 15'h4E50, 15'h4E64, 15'h4E78, 15'h4E8C, 15'h4E9F, 15'h4EB3,
15'h4EC7, 15'h4EDB, 15'h4EEF, 15'h4F03, 15'h4F16, 15'h4F2A, 15'h4F3E, 15'h4F52, 15'h4F65, 15'h4F79, 15'h4F8D, 15'h4FA0, 15'h4FB4, 15'h4FC8, 15'h4FDB, 15'h4FEF,
15'h5003, 15'h5016, 15'h502A, 15'h503E, 15'h5051, 15'h5065, 15'h5078, 15'h508C, 15'h509F, 15'h50B3, 15'h50C6, 15'h50DA, 15'h50ED, 15'h5101, 15'h5114, 15'h5128,
15'h513B, 15'h514F, 15'h5162, 15'h5175, 15'h5189, 15'h519C, 15'h51B0, 15'h51C3, 15'h51D6, 15'h51EA, 15'h51FD, 15'h5210, 15'h5223, 15'h5237, 15'h524A, 15'h525D,
15'h5270, 15'h5284, 15'h5297, 15'h52AA, 15'h52BD, 15'h52D1, 15'h52E4, 15'h52F7, 15'h530A, 15'h531D, 15'h5330, 15'h5343, 15'h5356, 15'h5369, 15'h537D, 15'h5390,
15'h53A3, 15'h53B6, 15'h53C9, 15'h53DC, 15'h53EF, 15'h5402, 15'h5415, 15'h5428, 15'h543B, 15'h544D, 15'h5460, 15'h5473, 15'h5486, 15'h5499, 15'h54AC, 15'h54BF,
15'h54D2, 15'h54E4, 15'h54F7, 15'h550A, 15'h551D, 15'h5530, 15'h5542, 15'h5555, 15'h5568, 15'h557B, 15'h558D, 15'h55A0, 15'h55B3, 15'h55C5, 15'h55D8, 15'h55EB,
15'h55FD, 15'h5610, 15'h5622, 15'h5635, 15'h5648, 15'h565A, 15'h566D, 15'h567F, 15'h5692, 15'h56A4, 15'h56B7, 15'h56C9, 15'h56DC, 15'h56EE, 15'h5701, 15'h5713,
15'h5726, 15'h5738, 15'h574A, 15'h575D, 15'h576F, 15'h5781, 15'h5794, 15'h57A6, 15'h57B8, 15'h57CB, 15'h57DD, 15'h57EF, 15'h5802, 15'h5814, 15'h5826, 15'h5838,
15'h584A, 15'h585D, 15'h586F, 15'h5881, 15'h5893, 15'h58A5, 15'h58B7, 15'h58CA, 15'h58DC, 15'h58EE, 15'h5900, 15'h5912, 15'h5924, 15'h5936, 15'h5948, 15'h595A,
15'h596C, 15'h597E, 15'h5990, 15'h59A2, 15'h59B4, 15'h59C6, 15'h59D8, 15'h59EA, 15'h59FC, 15'h5A0D, 15'h5A1F, 15'h5A31, 15'h5A43, 15'h5A55, 15'h5A67, 15'h5A78,
15'h5A8A, 15'h5A9C, 15'h5AAE, 15'h5ABF, 15'h5AD1, 15'h5AE3, 15'h5AF5, 15'h5B06, 15'h5B18, 15'h5B2A, 15'h5B3B, 15'h5B4D, 15'h5B5E, 15'h5B70, 15'h5B82, 15'h5B93,
15'h5BA5, 15'h5BB6, 15'h5BC8, 15'h5BD9, 15'h5BEB, 15'h5BFC, 15'h5C0E, 15'h5C1F, 15'h5C31, 15'h5C42, 15'h5C54, 15'h5C65, 15'h5C76, 15'h5C88, 15'h5C99, 15'h5CAB,
15'h5CBC, 15'h5CCD, 15'h5CDE, 15'h5CF0, 15'h5D01, 15'h5D12, 15'h5D24, 15'h5D35, 15'h5D46, 15'h5D57, 15'h5D68, 15'h5D7A, 15'h5D8B, 15'h5D9C, 15'h5DAD, 15'h5DBE,
15'h5DCF, 15'h5DE0, 15'h5DF2, 15'h5E03, 15'h5E14, 15'h5E25, 15'h5E36, 15'h5E47, 15'h5E58, 15'h5E69, 15'h5E7A, 15'h5E8B, 15'h5E9C, 15'h5EAD, 15'h5EBD, 15'h5ECE,
15'h5EDF, 15'h5EF0, 15'h5F01, 15'h5F12, 15'h5F23, 15'h5F33, 15'h5F44, 15'h5F55, 15'h5F66, 15'h5F77, 15'h5F87, 15'h5F98, 15'h5FA9, 15'h5FB9, 15'h5FCA, 15'h5FDB,
15'h5FEB, 15'h5FFC, 15'h600D, 15'h601D, 15'h602E, 15'h603E, 15'h604F, 15'h6060, 15'h6070, 15'h6081, 15'h6091, 15'h60A2, 15'h60B2, 15'h60C3, 15'h60D3, 15'h60E4,
15'h60F4, 15'h6104, 15'h6115, 15'h6125, 15'h6135, 15'h6146, 15'h6156, 15'h6166, 15'h6177, 15'h6187, 15'h6197, 15'h61A8, 15'h61B8, 15'h61C8, 15'h61D8, 15'h61E9,
15'h61F9, 15'h6209, 15'h6219, 15'h6229, 15'h6239, 15'h6249, 15'h625A, 15'h626A, 15'h627A, 15'h628A, 15'h629A, 15'h62AA, 15'h62BA, 15'h62CA, 15'h62DA, 15'h62EA,
15'h62FA, 15'h630A, 15'h631A, 15'h6329, 15'h6339, 15'h6349, 15'h6359, 15'h6369, 15'h6379, 15'h6389, 15'h6398, 15'h63A8, 15'h63B8, 15'h63C8, 15'h63D7, 15'h63E7,
15'h63F7, 15'h6407, 15'h6416, 15'h6426, 15'h6436, 15'h6445, 15'h6455, 15'h6464, 15'h6474, 15'h6484, 15'h6493, 15'h64A3, 15'h64B2, 15'h64C2, 15'h64D1, 15'h64E1,
15'h64F0, 15'h6500, 15'h650F, 15'h651F, 15'h652E, 15'h653D, 15'h654D, 15'h655C, 15'h656B, 15'h657B, 15'h658A, 15'h6599, 15'h65A9, 15'h65B8, 15'h65C7, 15'h65D6,
15'h65E6, 15'h65F5, 15'h6604, 15'h6613, 15'h6622, 15'h6631, 15'h6641, 15'h6650, 15'h665F, 15'h666E, 15'h667D, 15'h668C, 15'h669B, 15'h66AA, 15'h66B9, 15'h66C8,
15'h66D7, 15'h66E6, 15'h66F5, 15'h6704, 15'h6713, 15'h6722, 15'h6731, 15'h673F, 15'h674E, 15'h675D, 15'h676C, 15'h677B, 15'h678A, 15'h6798, 15'h67A7, 15'h67B6,
15'h67C5, 15'h67D3, 15'h67E2, 15'h67F1, 15'h67FF, 15'h680E, 15'h681D, 15'h682B, 15'h683A, 15'h6848, 15'h6857, 15'h6866, 15'h6874, 15'h6883, 15'h6891, 15'h68A0,
15'h68AE, 15'h68BD, 15'h68CB, 15'h68D9, 15'h68E8, 15'h68F6, 15'h6905, 15'h6913, 15'h6921, 15'h6930, 15'h693E, 15'h694C, 15'h695B, 15'h6969, 15'h6977, 15'h6985,
15'h6994, 15'h69A2, 15'h69B0, 15'h69BE, 15'h69CC, 15'h69DA, 15'h69E9, 15'h69F7, 15'h6A05, 15'h6A13, 15'h6A21, 15'h6A2F, 15'h6A3D, 15'h6A4B, 15'h6A59, 15'h6A67,
15'h6A75, 15'h6A83, 15'h6A91, 15'h6A9F, 15'h6AAD, 15'h6ABB, 15'h6AC8, 15'h6AD6, 15'h6AE4, 15'h6AF2, 15'h6B00, 15'h6B0E, 15'h6B1B, 15'h6B29, 15'h6B37, 15'h6B45,
15'h6B52, 15'h6B60, 15'h6B6E, 15'h6B7B, 15'h6B89, 15'h6B97, 15'h6BA4, 15'h6BB2, 15'h6BBF, 15'h6BCD, 15'h6BDA, 15'h6BE8, 15'h6BF6, 15'h6C03, 15'h6C11, 15'h6C1E,
15'h6C2B, 15'h6C39, 15'h6C46, 15'h6C54, 15'h6C61, 15'h6C6E, 15'h6C7C, 15'h6C89, 15'h6C96, 15'h6CA4, 15'h6CB1, 15'h6CBE, 15'h6CCC, 15'h6CD9, 15'h6CE6, 15'h6CF3,
15'h6D00, 15'h6D0E, 15'h6D1B, 15'h6D28, 15'h6D35, 15'h6D42, 15'h6D4F, 15'h6D5C, 15'h6D69, 15'h6D76, 15'h6D83, 15'h6D90, 15'h6D9D, 15'h6DAA, 15'h6DB7, 15'h6DC4,
15'h6DD1, 15'h6DDE, 15'h6DEB, 15'h6DF8, 15'h6E05, 15'h6E12, 15'h6E1E, 15'h6E2B, 15'h6E38, 15'h6E45, 15'h6E52, 15'h6E5E, 15'h6E6B, 15'h6E78, 15'h6E84, 15'h6E91,
15'h6E9E, 15'h6EAA, 15'h6EB7, 15'h6EC4, 15'h6ED0, 15'h6EDD, 15'h6EE9, 15'h6EF6, 15'h6F02, 15'h6F0F, 15'h6F1B, 15'h6F28, 15'h6F34, 15'h6F41, 15'h6F4D, 15'h6F5A,
15'h6F66, 15'h6F72, 15'h6F7F, 15'h6F8B, 15'h6F97, 15'h6FA4, 15'h6FB0, 15'h6FBC, 15'h6FC8, 15'h6FD5, 15'h6FE1, 15'h6FED, 15'h6FF9, 15'h7006, 15'h7012, 15'h701E,
15'h702A, 15'h7036, 15'h7042, 15'h704E, 15'h705A, 15'h7066, 15'h7072, 15'h707E, 15'h708A, 15'h7096, 15'h70A2, 15'h70AE, 15'h70BA, 15'h70C6, 15'h70D2, 15'h70DE,
15'h70EA, 15'h70F5, 15'h7101, 15'h710D, 15'h7119, 15'h7125, 15'h7130, 15'h713C, 15'h7148, 15'h7153, 15'h715F, 15'h716B, 15'h7176, 15'h7182, 15'h718E, 15'h7199,
15'h71A5, 15'h71B0, 15'h71BC, 15'h71C7, 15'h71D3, 15'h71DE, 15'h71EA, 15'h71F5, 15'h7201, 15'h720C, 15'h7218, 15'h7223, 15'h722E, 15'h723A, 15'h7245, 15'h7250,
15'h725C, 15'h7267, 15'h7272, 15'h727E, 15'h7289, 15'h7294, 15'h729F, 15'h72AA, 15'h72B6, 15'h72C1, 15'h72CC, 15'h72D7, 15'h72E2, 15'h72ED, 15'h72F8, 15'h7303,
15'h730E, 15'h7319, 15'h7324, 15'h732F, 15'h733A, 15'h7345, 15'h7350, 15'h735B, 15'h7366, 15'h7371, 15'h737B, 15'h7386, 15'h7391, 15'h739C, 15'h73A7, 15'h73B1,
15'h73BC, 15'h73C7, 15'h73D2, 15'h73DC, 15'h73E7, 15'h73F2, 15'h73FC, 15'h7407, 15'h7412, 15'h741C, 15'h7427, 15'h7431, 15'h743C, 15'h7446, 15'h7451, 15'h745B,
15'h7466, 15'h7470, 15'h747B, 15'h7485, 15'h7490, 15'h749A, 15'h74A4, 15'h74AF, 15'h74B9, 15'h74C3, 15'h74CE, 15'h74D8, 15'h74E2, 15'h74EC, 15'h74F7, 15'h7501,
15'h750B, 15'h7515, 15'h751F, 15'h7529, 15'h7533, 15'h753E, 15'h7548, 15'h7552, 15'h755C, 15'h7566, 15'h7570, 15'h757A, 15'h7584, 15'h758E, 15'h7598, 15'h75A2,
15'h75AB, 15'h75B5, 15'h75BF, 15'h75C9, 15'h75D3, 15'h75DD, 15'h75E6, 15'h75F0, 15'h75FA, 15'h7604, 15'h760D, 15'h7617, 15'h7621, 15'h762B, 15'h7634, 15'h763E,
15'h7647, 15'h7651, 15'h765B, 15'h7664, 15'h766E, 15'h7677, 15'h7681, 15'h768A, 15'h7694, 15'h769D, 15'h76A7, 15'h76B0, 15'h76B9, 15'h76C3, 15'h76CC, 15'h76D6,
15'h76DF, 15'h76E8, 15'h76F2, 15'h76FB, 15'h7704, 15'h770D, 15'h7717, 15'h7720, 15'h7729, 15'h7732, 15'h773B, 15'h7744, 15'h774E, 15'h7757, 15'h7760, 15'h7769,
15'h7772, 15'h777B, 15'h7784, 15'h778D, 15'h7796, 15'h779F, 15'h77A8, 15'h77B1, 15'h77BA, 15'h77C2, 15'h77CB, 15'h77D4, 15'h77DD, 15'h77E6, 15'h77EF, 15'h77F7,
15'h7800, 15'h7809, 15'h7812, 15'h781A, 15'h7823, 15'h782C, 15'h7834, 15'h783D, 15'h7845, 15'h784E, 15'h7857, 15'h785F, 15'h7868, 15'h7870, 15'h7879, 15'h7881,
15'h788A, 15'h7892, 15'h789B, 15'h78A3, 15'h78AB, 15'h78B4, 15'h78BC, 15'h78C4, 15'h78CD, 15'h78D5, 15'h78DD, 15'h78E6, 15'h78EE, 15'h78F6, 15'h78FE, 15'h7906,
15'h790F, 15'h7917, 15'h791F, 15'h7927, 15'h792F, 15'h7937, 15'h793F, 15'h7947, 15'h794F, 15'h7957, 15'h795F, 15'h7967, 15'h796F, 15'h7977, 15'h797F, 15'h7987,
15'h798F, 15'h7997, 15'h799F, 15'h79A7, 15'h79AE, 15'h79B6, 15'h79BE, 15'h79C6, 15'h79CD, 15'h79D5, 15'h79DD, 15'h79E4, 15'h79EC, 15'h79F4, 15'h79FB, 15'h7A03,
15'h7A0B, 15'h7A12, 15'h7A1A, 15'h7A21, 15'h7A29, 15'h7A30, 15'h7A38, 15'h7A3F, 15'h7A47, 15'h7A4E, 15'h7A55, 15'h7A5D, 15'h7A64, 15'h7A6C, 15'h7A73, 15'h7A7A,
15'h7A81, 15'h7A89, 15'h7A90, 15'h7A97, 15'h7A9E, 15'h7AA6, 15'h7AAD, 15'h7AB4, 15'h7ABB, 15'h7AC2, 15'h7AC9, 15'h7AD0, 15'h7AD8, 15'h7ADF, 15'h7AE6, 15'h7AED,
15'h7AF4, 15'h7AFB, 15'h7B02, 15'h7B09, 15'h7B0F, 15'h7B16, 15'h7B1D, 15'h7B24, 15'h7B2B, 15'h7B32, 15'h7B39, 15'h7B3F, 15'h7B46, 15'h7B4D, 15'h7B54, 15'h7B5A,
15'h7B61, 15'h7B68, 15'h7B6E, 15'h7B75, 15'h7B7C, 15'h7B82, 15'h7B89, 15'h7B8F, 15'h7B96, 15'h7B9D, 15'h7BA3, 15'h7BAA, 15'h7BB0, 15'h7BB7, 15'h7BBD, 15'h7BC3,
15'h7BCA, 15'h7BD0, 15'h7BD7, 15'h7BDD, 15'h7BE3, 15'h7BE9, 15'h7BF0, 15'h7BF6, 15'h7BFC, 15'h7C03, 15'h7C09, 15'h7C0F, 15'h7C15, 15'h7C1B, 15'h7C21, 15'h7C28,
15'h7C2E, 15'h7C34, 15'h7C3A, 15'h7C40, 15'h7C46, 15'h7C4C, 15'h7C52, 15'h7C58, 15'h7C5E, 15'h7C64, 15'h7C6A, 15'h7C70, 15'h7C75, 15'h7C7B, 15'h7C81, 15'h7C87,
15'h7C8D, 15'h7C93, 15'h7C98, 15'h7C9E, 15'h7CA4, 15'h7CA9, 15'h7CAF, 15'h7CB5, 15'h7CBB, 15'h7CC0, 15'h7CC6, 15'h7CCB, 15'h7CD1, 15'h7CD6, 15'h7CDC, 15'h7CE2,
15'h7CE7, 15'h7CED, 15'h7CF2, 15'h7CF7, 15'h7CFD, 15'h7D02, 15'h7D08, 15'h7D0D, 15'h7D12, 15'h7D18, 15'h7D1D, 15'h7D22, 15'h7D28, 15'h7D2D, 15'h7D32, 15'h7D37,
15'h7D3D, 15'h7D42, 15'h7D47, 15'h7D4C, 15'h7D51, 15'h7D56, 15'h7D5B, 15'h7D60, 15'h7D65, 15'h7D6A, 15'h7D70, 15'h7D74, 15'h7D79, 15'h7D7E, 15'h7D83, 15'h7D88,
15'h7D8D, 15'h7D92, 15'h7D97, 15'h7D9C, 15'h7DA1, 15'h7DA5, 15'h7DAA, 15'h7DAF, 15'h7DB4, 15'h7DB8, 15'h7DBD, 15'h7DC2, 15'h7DC6, 15'h7DCB, 15'h7DD0, 15'h7DD4,
15'h7DD9, 15'h7DDE, 15'h7DE2, 15'h7DE7, 15'h7DEB, 15'h7DF0, 15'h7DF4, 15'h7DF9, 15'h7DFD, 15'h7E01, 15'h7E06, 15'h7E0A, 15'h7E0F, 15'h7E13, 15'h7E17, 15'h7E1C,
15'h7E20, 15'h7E24, 15'h7E28, 15'h7E2D, 15'h7E31, 15'h7E35, 15'h7E39, 15'h7E3D, 15'h7E42, 15'h7E46, 15'h7E4A, 15'h7E4E, 15'h7E52, 15'h7E56, 15'h7E5A, 15'h7E5E,
15'h7E62, 15'h7E66, 15'h7E6A, 15'h7E6E, 15'h7E72, 15'h7E76, 15'h7E7A, 15'h7E7D, 15'h7E81, 15'h7E85, 15'h7E89, 15'h7E8D, 15'h7E90, 15'h7E94, 15'h7E98, 15'h7E9C,
15'h7E9F, 15'h7EA3, 15'h7EA6, 15'h7EAA, 15'h7EAE, 15'h7EB1, 15'h7EB5, 15'h7EB8, 15'h7EBC, 15'h7EBF, 15'h7EC3, 15'h7EC6, 15'h7ECA, 15'h7ECD, 15'h7ED1, 15'h7ED4,
15'h7ED7, 15'h7EDB, 15'h7EDE, 15'h7EE2, 15'h7EE5, 15'h7EE8, 15'h7EEB, 15'h7EEF, 15'h7EF2, 15'h7EF5, 15'h7EF8, 15'h7EFB, 15'h7EFF, 15'h7F02, 15'h7F05, 15'h7F08,
15'h7F0B, 15'h7F0E, 15'h7F11, 15'h7F14, 15'h7F17, 15'h7F1A, 15'h7F1D, 15'h7F20, 15'h7F23, 15'h7F26, 15'h7F29, 15'h7F2B, 15'h7F2E, 15'h7F31, 15'h7F34, 15'h7F37,
15'h7F39, 15'h7F3C, 15'h7F3F, 15'h7F42, 15'h7F44, 15'h7F47, 15'h7F4A, 15'h7F4C, 15'h7F4F, 15'h7F51, 15'h7F54, 15'h7F57, 15'h7F59, 15'h7F5C, 15'h7F5E, 15'h7F61,
15'h7F63, 15'h7F65, 15'h7F68, 15'h7F6A, 15'h7F6D, 15'h7F6F, 15'h7F71, 15'h7F74, 15'h7F76, 15'h7F78, 15'h7F7B, 15'h7F7D, 15'h7F7F, 15'h7F81, 15'h7F83, 15'h7F86,
15'h7F88, 15'h7F8A, 15'h7F8C, 15'h7F8E, 15'h7F90, 15'h7F92, 15'h7F94, 15'h7F96, 15'h7F98, 15'h7F9A, 15'h7F9C, 15'h7F9E, 15'h7FA0, 15'h7FA2, 15'h7FA4, 15'h7FA6,
15'h7FA7, 15'h7FA9, 15'h7FAB, 15'h7FAD, 15'h7FAF, 15'h7FB0, 15'h7FB2, 15'h7FB4, 15'h7FB6, 15'h7FB7, 15'h7FB9, 15'h7FBA, 15'h7FBC, 15'h7FBE, 15'h7FBF, 15'h7FC1,
15'h7FC2, 15'h7FC4, 15'h7FC5, 15'h7FC7, 15'h7FC8, 15'h7FCA, 15'h7FCB, 15'h7FCD, 15'h7FCE, 15'h7FCF, 15'h7FD1, 15'h7FD2, 15'h7FD3, 15'h7FD4, 15'h7FD6, 15'h7FD7,
15'h7FD8, 15'h7FD9, 15'h7FDB, 15'h7FDC, 15'h7FDD, 15'h7FDE, 15'h7FDF, 15'h7FE0, 15'h7FE1, 15'h7FE2, 15'h7FE3, 15'h7FE4, 15'h7FE5, 15'h7FE6, 15'h7FE7, 15'h7FE8,
15'h7FE9, 15'h7FEA, 15'h7FEB, 15'h7FEC, 15'h7FED, 15'h7FED, 15'h7FEE, 15'h7FEF, 15'h7FF0, 15'h7FF1, 15'h7FF1, 15'h7FF2, 15'h7FF3, 15'h7FF3, 15'h7FF4, 15'h7FF5,
15'h7FF5, 15'h7FF6, 15'h7FF6, 15'h7FF7, 15'h7FF7, 15'h7FF8, 15'h7FF8, 15'h7FF9, 15'h7FF9, 15'h7FFA, 15'h7FFA, 15'h7FFB, 15'h7FFB, 15'h7FFB, 15'h7FFC, 15'h7FFC,
15'h7FFC, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFF
*/
// sin((pi/2)*sin(x))
15'h0000, 15'h0027, 15'h004E, 15'h0076, 15'h009D, 15'h00C5, 15'h00EC, 15'h0114, 15'h013B, 15'h0163, 15'h018A, 15'h01B2, 15'h01D9, 15'h0201, 15'h0228, 15'h0250,
15'h0277, 15'h029F, 15'h02C6, 15'h02EE, 15'h0315, 15'h033D, 15'h0364, 15'h038C, 15'h03B3, 15'h03DB, 15'h0402, 15'h042A, 15'h0451, 15'h0479, 15'h04A0, 15'h04C7,
15'h04EF, 15'h0516, 15'h053E, 15'h0565, 15'h058D, 15'h05B4, 15'h05DC, 15'h0603, 15'h062B, 15'h0652, 15'h0679, 15'h06A1, 15'h06C8, 15'h06F0, 15'h0717, 15'h073E,
15'h0766, 15'h078D, 15'h07B5, 15'h07DC, 15'h0803, 15'h082B, 15'h0852, 15'h087A, 15'h08A1, 15'h08C8, 15'h08F0, 15'h0917, 15'h093E, 15'h0966, 15'h098D, 15'h09B4,
15'h09DC, 15'h0A03, 15'h0A2A, 15'h0A52, 15'h0A79, 15'h0AA0, 15'h0AC8, 15'h0AEF, 15'h0B16, 15'h0B3E, 15'h0B65, 15'h0B8C, 15'h0BB3, 15'h0BDB, 15'h0C02, 15'h0C29,
15'h0C50, 15'h0C78, 15'h0C9F, 15'h0CC6, 15'h0CED, 15'h0D14, 15'h0D3C, 15'h0D63, 15'h0D8A, 15'h0DB1, 15'h0DD8, 15'h0E00, 15'h0E27, 15'h0E4E, 15'h0E75, 15'h0E9C,
15'h0EC3, 15'h0EEA, 15'h0F12, 15'h0F39, 15'h0F60, 15'h0F87, 15'h0FAE, 15'h0FD5, 15'h0FFC, 15'h1023, 15'h104A, 15'h1071, 15'h1098, 15'h10BF, 15'h10E6, 15'h110D,
15'h1134, 15'h115B, 15'h1182, 15'h11A9, 15'h11D0, 15'h11F7, 15'h121E, 15'h1245, 15'h126C, 15'h1293, 15'h12BA, 15'h12E1, 15'h1308, 15'h132E, 15'h1355, 15'h137C,
15'h13A3, 15'h13CA, 15'h13F1, 15'h1417, 15'h143E, 15'h1465, 15'h148C, 15'h14B3, 15'h14D9, 15'h1500, 15'h1527, 15'h154E, 15'h1574, 15'h159B, 15'h15C2, 15'h15E8,
15'h160F, 15'h1636, 15'h165C, 15'h1683, 15'h16AA, 15'h16D0, 15'h16F7, 15'h171D, 15'h1744, 15'h176B, 15'h1791, 15'h17B8, 15'h17DE, 15'h1805, 15'h182B, 15'h1852,
15'h1878, 15'h189F, 15'h18C5, 15'h18EC, 15'h1912, 15'h1938, 15'h195F, 15'h1985, 15'h19AC, 15'h19D2, 15'h19F8, 15'h1A1F, 15'h1A45, 15'h1A6B, 15'h1A92, 15'h1AB8,
15'h1ADE, 15'h1B04, 15'h1B2B, 15'h1B51, 15'h1B77, 15'h1B9D, 15'h1BC4, 15'h1BEA, 15'h1C10, 15'h1C36, 15'h1C5C, 15'h1C82, 15'h1CA8, 15'h1CCE, 15'h1CF5, 15'h1D1B,
15'h1D41, 15'h1D67, 15'h1D8D, 15'h1DB3, 15'h1DD9, 15'h1DFF, 15'h1E25, 15'h1E4B, 15'h1E70, 15'h1E96, 15'h1EBC, 15'h1EE2, 15'h1F08, 15'h1F2E, 15'h1F54, 15'h1F79,
15'h1F9F, 15'h1FC5, 15'h1FEB, 15'h2011, 15'h2036, 15'h205C, 15'h2082, 15'h20A7, 15'h20CD, 15'h20F3, 15'h2118, 15'h213E, 15'h2163, 15'h2189, 15'h21AF, 15'h21D4,
15'h21FA, 15'h221F, 15'h2245, 15'h226A, 15'h2290, 15'h22B5, 15'h22DA, 15'h2300, 15'h2325, 15'h234B, 15'h2370, 15'h2395, 15'h23BB, 15'h23E0, 15'h2405, 15'h242A,
15'h2450, 15'h2475, 15'h249A, 15'h24BF, 15'h24E4, 15'h250A, 15'h252F, 15'h2554, 15'h2579, 15'h259E, 15'h25C3, 15'h25E8, 15'h260D, 15'h2632, 15'h2657, 15'h267C,
15'h26A1, 15'h26C6, 15'h26EB, 15'h2710, 15'h2735, 15'h2759, 15'h277E, 15'h27A3, 15'h27C8, 15'h27ED, 15'h2811, 15'h2836, 15'h285B, 15'h287F, 15'h28A4, 15'h28C9,
15'h28ED, 15'h2912, 15'h2937, 15'h295B, 15'h2980, 15'h29A4, 15'h29C9, 15'h29ED, 15'h2A12, 15'h2A36, 15'h2A5A, 15'h2A7F, 15'h2AA3, 15'h2AC8, 15'h2AEC, 15'h2B10,
15'h2B34, 15'h2B59, 15'h2B7D, 15'h2BA1, 15'h2BC5, 15'h2BEA, 15'h2C0E, 15'h2C32, 15'h2C56, 15'h2C7A, 15'h2C9E, 15'h2CC2, 15'h2CE6, 15'h2D0A, 15'h2D2E, 15'h2D52,
15'h2D76, 15'h2D9A, 15'h2DBE, 15'h2DE2, 15'h2E06, 15'h2E29, 15'h2E4D, 15'h2E71, 15'h2E95, 15'h2EB8, 15'h2EDC, 15'h2F00, 15'h2F23, 15'h2F47, 15'h2F6B, 15'h2F8E,
15'h2FB2, 15'h2FD5, 15'h2FF9, 15'h301C, 15'h3040, 15'h3063, 15'h3087, 15'h30AA, 15'h30CE, 15'h30F1, 15'h3114, 15'h3138, 15'h315B, 15'h317E, 15'h31A1, 15'h31C4,
15'h31E8, 15'h320B, 15'h322E, 15'h3251, 15'h3274, 15'h3297, 15'h32BA, 15'h32DD, 15'h3300, 15'h3323, 15'h3346, 15'h3369, 15'h338C, 15'h33AF, 15'h33D2, 15'h33F4,
15'h3417, 15'h343A, 15'h345D, 15'h347F, 15'h34A2, 15'h34C5, 15'h34E7, 15'h350A, 15'h352D, 15'h354F, 15'h3572, 15'h3594, 15'h35B7, 15'h35D9, 15'h35FB, 15'h361E,
15'h3640, 15'h3663, 15'h3685, 15'h36A7, 15'h36C9, 15'h36EC, 15'h370E, 15'h3730, 15'h3752, 15'h3774, 15'h3796, 15'h37B9, 15'h37DB, 15'h37FD, 15'h381F, 15'h3841,
15'h3863, 15'h3884, 15'h38A6, 15'h38C8, 15'h38EA, 15'h390C, 15'h392E, 15'h394F, 15'h3971, 15'h3993, 15'h39B4, 15'h39D6, 15'h39F8, 15'h3A19, 15'h3A3B, 15'h3A5C,
15'h3A7E, 15'h3A9F, 15'h3AC1, 15'h3AE2, 15'h3B04, 15'h3B25, 15'h3B46, 15'h3B68, 15'h3B89, 15'h3BAA, 15'h3BCB, 15'h3BED, 15'h3C0E, 15'h3C2F, 15'h3C50, 15'h3C71,
15'h3C92, 15'h3CB3, 15'h3CD4, 15'h3CF5, 15'h3D16, 15'h3D37, 15'h3D58, 15'h3D79, 15'h3D99, 15'h3DBA, 15'h3DDB, 15'h3DFC, 15'h3E1C, 15'h3E3D, 15'h3E5E, 15'h3E7E,
15'h3E9F, 15'h3EC0, 15'h3EE0, 15'h3F01, 15'h3F21, 15'h3F41, 15'h3F62, 15'h3F82, 15'h3FA3, 15'h3FC3, 15'h3FE3, 15'h4003, 15'h4024, 15'h4044, 15'h4064, 15'h4084,
15'h40A4, 15'h40C4, 15'h40E4, 15'h4104, 15'h4124, 15'h4144, 15'h4164, 15'h4184, 15'h41A4, 15'h41C4, 15'h41E4, 15'h4204, 15'h4223, 15'h4243, 15'h4263, 15'h4282,
15'h42A2, 15'h42C2, 15'h42E1, 15'h4301, 15'h4320, 15'h4340, 15'h435F, 15'h437E, 15'h439E, 15'h43BD, 15'h43DC, 15'h43FC, 15'h441B, 15'h443A, 15'h4459, 15'h4479,
15'h4498, 15'h44B7, 15'h44D6, 15'h44F5, 15'h4514, 15'h4533, 15'h4552, 15'h4571, 15'h4590, 15'h45AE, 15'h45CD, 15'h45EC, 15'h460B, 15'h4629, 15'h4648, 15'h4667,
15'h4685, 15'h46A4, 15'h46C3, 15'h46E1, 15'h4700, 15'h471E, 15'h473C, 15'h475B, 15'h4779, 15'h4797, 15'h47B6, 15'h47D4, 15'h47F2, 15'h4810, 15'h482F, 15'h484D,
15'h486B, 15'h4889, 15'h48A7, 15'h48C5, 15'h48E3, 15'h4901, 15'h491F, 15'h493D, 15'h495B, 15'h4978, 15'h4996, 15'h49B4, 15'h49D2, 15'h49EF, 15'h4A0D, 15'h4A2A,
15'h4A48, 15'h4A66, 15'h4A83, 15'h4AA1, 15'h4ABE, 15'h4ADB, 15'h4AF9, 15'h4B16, 15'h4B33, 15'h4B51, 15'h4B6E, 15'h4B8B, 15'h4BA8, 15'h4BC6, 15'h4BE3, 15'h4C00,
15'h4C1D, 15'h4C3A, 15'h4C57, 15'h4C74, 15'h4C91, 15'h4CAD, 15'h4CCA, 15'h4CE7, 15'h4D04, 15'h4D21, 15'h4D3D, 15'h4D5A, 15'h4D77, 15'h4D93, 15'h4DB0, 15'h4DCC,
15'h4DE9, 15'h4E05, 15'h4E22, 15'h4E3E, 15'h4E5B, 15'h4E77, 15'h4E93, 15'h4EAF, 15'h4ECC, 15'h4EE8, 15'h4F04, 15'h4F20, 15'h4F3C, 15'h4F58, 15'h4F74, 15'h4F90,
15'h4FAC, 15'h4FC8, 15'h4FE4, 15'h5000, 15'h501C, 15'h5038, 15'h5053, 15'h506F, 15'h508B, 15'h50A6, 15'h50C2, 15'h50DE, 15'h50F9, 15'h5115, 15'h5130, 15'h514C,
15'h5167, 15'h5182, 15'h519E, 15'h51B9, 15'h51D4, 15'h51EF, 15'h520B, 15'h5226, 15'h5241, 15'h525C, 15'h5277, 15'h5292, 15'h52AD, 15'h52C8, 15'h52E3, 15'h52FE,
15'h5319, 15'h5334, 15'h534E, 15'h5369, 15'h5384, 15'h539E, 15'h53B9, 15'h53D4, 15'h53EE, 15'h5409, 15'h5423, 15'h543E, 15'h5458, 15'h5473, 15'h548D, 15'h54A7,
15'h54C2, 15'h54DC, 15'h54F6, 15'h5510, 15'h552A, 15'h5544, 15'h555E, 15'h5579, 15'h5593, 15'h55AC, 15'h55C6, 15'h55E0, 15'h55FA, 15'h5614, 15'h562E, 15'h5648,
15'h5661, 15'h567B, 15'h5695, 15'h56AE, 15'h56C8, 15'h56E1, 15'h56FB, 15'h5714, 15'h572E, 15'h5747, 15'h5760, 15'h577A, 15'h5793, 15'h57AC, 15'h57C6, 15'h57DF,
15'h57F8, 15'h5811, 15'h582A, 15'h5843, 15'h585C, 15'h5875, 15'h588E, 15'h58A7, 15'h58C0, 15'h58D9, 15'h58F1, 15'h590A, 15'h5923, 15'h593C, 15'h5954, 15'h596D,
15'h5985, 15'h599E, 15'h59B6, 15'h59CF, 15'h59E7, 15'h5A00, 15'h5A18, 15'h5A30, 15'h5A49, 15'h5A61, 15'h5A79, 15'h5A91, 15'h5AAA, 15'h5AC2, 15'h5ADA, 15'h5AF2,
15'h5B0A, 15'h5B22, 15'h5B3A, 15'h5B52, 15'h5B69, 15'h5B81, 15'h5B99, 15'h5BB1, 15'h5BC8, 15'h5BE0, 15'h5BF8, 15'h5C0F, 15'h5C27, 15'h5C3E, 15'h5C56, 15'h5C6D,
15'h5C85, 15'h5C9C, 15'h5CB4, 15'h5CCB, 15'h5CE2, 15'h5CF9, 15'h5D11, 15'h5D28, 15'h5D3F, 15'h5D56, 15'h5D6D, 15'h5D84, 15'h5D9B, 15'h5DB2, 15'h5DC9, 15'h5DE0,
15'h5DF7, 15'h5E0E, 15'h5E24, 15'h5E3B, 15'h5E52, 15'h5E68, 15'h5E7F, 15'h5E96, 15'h5EAC, 15'h5EC3, 15'h5ED9, 15'h5EF0, 15'h5F06, 15'h5F1C, 15'h5F33, 15'h5F49,
15'h5F5F, 15'h5F76, 15'h5F8C, 15'h5FA2, 15'h5FB8, 15'h5FCE, 15'h5FE4, 15'h5FFA, 15'h6010, 15'h6026, 15'h603C, 15'h6052, 15'h6068, 15'h607E, 15'h6093, 15'h60A9,
15'h60BF, 15'h60D4, 15'h60EA, 15'h6100, 15'h6115, 15'h612B, 15'h6140, 15'h6156, 15'h616B, 15'h6180, 15'h6196, 15'h61AB, 15'h61C0, 15'h61D5, 15'h61EB, 15'h6200,
15'h6215, 15'h622A, 15'h623F, 15'h6254, 15'h6269, 15'h627E, 15'h6293, 15'h62A8, 15'h62BC, 15'h62D1, 15'h62E6, 15'h62FB, 15'h630F, 15'h6324, 15'h6339, 15'h634D,
15'h6362, 15'h6376, 15'h638B, 15'h639F, 15'h63B4, 15'h63C8, 15'h63DC, 15'h63F1, 15'h6405, 15'h6419, 15'h642D, 15'h6441, 15'h6455, 15'h646A, 15'h647E, 15'h6492,
15'h64A6, 15'h64B9, 15'h64CD, 15'h64E1, 15'h64F5, 15'h6509, 15'h651D, 15'h6530, 15'h6544, 15'h6558, 15'h656B, 15'h657F, 15'h6592, 15'h65A6, 15'h65B9, 15'h65CD,
15'h65E0, 15'h65F3, 15'h6607, 15'h661A, 15'h662D, 15'h6640, 15'h6654, 15'h6667, 15'h667A, 15'h668D, 15'h66A0, 15'h66B3, 15'h66C6, 15'h66D9, 15'h66EC, 15'h66FF,
15'h6711, 15'h6724, 15'h6737, 15'h674A, 15'h675C, 15'h676F, 15'h6782, 15'h6794, 15'h67A7, 15'h67B9, 15'h67CC, 15'h67DE, 15'h67F1, 15'h6803, 15'h6815, 15'h6828,
15'h683A, 15'h684C, 15'h685E, 15'h6870, 15'h6883, 15'h6895, 15'h68A7, 15'h68B9, 15'h68CB, 15'h68DD, 15'h68EE, 15'h6900, 15'h6912, 15'h6924, 15'h6936, 15'h6948,
15'h6959, 15'h696B, 15'h697C, 15'h698E, 15'h69A0, 15'h69B1, 15'h69C3, 15'h69D4, 15'h69E6, 15'h69F7, 15'h6A08, 15'h6A1A, 15'h6A2B, 15'h6A3C, 15'h6A4D, 15'h6A5E,
15'h6A70, 15'h6A81, 15'h6A92, 15'h6AA3, 15'h6AB4, 15'h6AC5, 15'h6AD6, 15'h6AE7, 15'h6AF7, 15'h6B08, 15'h6B19, 15'h6B2A, 15'h6B3B, 15'h6B4B, 15'h6B5C, 15'h6B6D,
15'h6B7D, 15'h6B8E, 15'h6B9E, 15'h6BAF, 15'h6BBF, 15'h6BD0, 15'h6BE0, 15'h6BF0, 15'h6C01, 15'h6C11, 15'h6C21, 15'h6C31, 15'h6C42, 15'h6C52, 15'h6C62, 15'h6C72,
15'h6C82, 15'h6C92, 15'h6CA2, 15'h6CB2, 15'h6CC2, 15'h6CD2, 15'h6CE1, 15'h6CF1, 15'h6D01, 15'h6D11, 15'h6D20, 15'h6D30, 15'h6D40, 15'h6D4F, 15'h6D5F, 15'h6D6E,
15'h6D7E, 15'h6D8D, 15'h6D9D, 15'h6DAC, 15'h6DBC, 15'h6DCB, 15'h6DDA, 15'h6DEA, 15'h6DF9, 15'h6E08, 15'h6E17, 15'h6E26, 15'h6E35, 15'h6E44, 15'h6E53, 15'h6E62,
15'h6E71, 15'h6E80, 15'h6E8F, 15'h6E9E, 15'h6EAD, 15'h6EBC, 15'h6ECB, 15'h6ED9, 15'h6EE8, 15'h6EF7, 15'h6F05, 15'h6F14, 15'h6F22, 15'h6F31, 15'h6F3F, 15'h6F4E,
15'h6F5C, 15'h6F6B, 15'h6F79, 15'h6F88, 15'h6F96, 15'h6FA4, 15'h6FB2, 15'h6FC1, 15'h6FCF, 15'h6FDD, 15'h6FEB, 15'h6FF9, 15'h7007, 15'h7015, 15'h7023, 15'h7031,
15'h703F, 15'h704D, 15'h705B, 15'h7069, 15'h7076, 15'h7084, 15'h7092, 15'h709F, 15'h70AD, 15'h70BB, 15'h70C8, 15'h70D6, 15'h70E3, 15'h70F1, 15'h70FE, 15'h710C,
15'h7119, 15'h7127, 15'h7134, 15'h7141, 15'h714F, 15'h715C, 15'h7169, 15'h7176, 15'h7183, 15'h7190, 15'h719E, 15'h71AB, 15'h71B8, 15'h71C5, 15'h71D2, 15'h71DF,
15'h71EB, 15'h71F8, 15'h7205, 15'h7212, 15'h721F, 15'h722B, 15'h7238, 15'h7245, 15'h7251, 15'h725E, 15'h726B, 15'h7277, 15'h7284, 15'h7290, 15'h729D, 15'h72A9,
15'h72B6, 15'h72C2, 15'h72CE, 15'h72DB, 15'h72E7, 15'h72F3, 15'h72FF, 15'h730B, 15'h7318, 15'h7324, 15'h7330, 15'h733C, 15'h7348, 15'h7354, 15'h7360, 15'h736C,
15'h7378, 15'h7384, 15'h7390, 15'h739B, 15'h73A7, 15'h73B3, 15'h73BF, 15'h73CA, 15'h73D6, 15'h73E2, 15'h73ED, 15'h73F9, 15'h7404, 15'h7410, 15'h741B, 15'h7427,
15'h7432, 15'h743E, 15'h7449, 15'h7454, 15'h7460, 15'h746B, 15'h7476, 15'h7481, 15'h748D, 15'h7498, 15'h74A3, 15'h74AE, 15'h74B9, 15'h74C4, 15'h74CF, 15'h74DA,
15'h74E5, 15'h74F0, 15'h74FB, 15'h7506, 15'h7511, 15'h751C, 15'h7526, 15'h7531, 15'h753C, 15'h7546, 15'h7551, 15'h755C, 15'h7566, 15'h7571, 15'h757C, 15'h7586,
15'h7591, 15'h759B, 15'h75A5, 15'h75B0, 15'h75BA, 15'h75C5, 15'h75CF, 15'h75D9, 15'h75E3, 15'h75EE, 15'h75F8, 15'h7602, 15'h760C, 15'h7616, 15'h7621, 15'h762B,
15'h7635, 15'h763F, 15'h7649, 15'h7653, 15'h765D, 15'h7666, 15'h7670, 15'h767A, 15'h7684, 15'h768E, 15'h7698, 15'h76A1, 15'h76AB, 15'h76B5, 15'h76BE, 15'h76C8,
15'h76D2, 15'h76DB, 15'h76E5, 15'h76EE, 15'h76F8, 15'h7701, 15'h770B, 15'h7714, 15'h771D, 15'h7727, 15'h7730, 15'h7739, 15'h7743, 15'h774C, 15'h7755, 15'h775E,
15'h7767, 15'h7771, 15'h777A, 15'h7783, 15'h778C, 15'h7795, 15'h779E, 15'h77A7, 15'h77B0, 15'h77B9, 15'h77C2, 15'h77CB, 15'h77D3, 15'h77DC, 15'h77E5, 15'h77EE,
15'h77F7, 15'h77FF, 15'h7808, 15'h7811, 15'h7819, 15'h7822, 15'h782A, 15'h7833, 15'h783C, 15'h7844, 15'h784D, 15'h7855, 15'h785D, 15'h7866, 15'h786E, 15'h7877,
15'h787F, 15'h7887, 15'h7890, 15'h7898, 15'h78A0, 15'h78A8, 15'h78B0, 15'h78B9, 15'h78C1, 15'h78C9, 15'h78D1, 15'h78D9, 15'h78E1, 15'h78E9, 15'h78F1, 15'h78F9,
15'h7901, 15'h7909, 15'h7911, 15'h7918, 15'h7920, 15'h7928, 15'h7930, 15'h7938, 15'h793F, 15'h7947, 15'h794F, 15'h7956, 15'h795E, 15'h7966, 15'h796D, 15'h7975,
15'h797C, 15'h7984, 15'h798B, 15'h7993, 15'h799A, 15'h79A2, 15'h79A9, 15'h79B0, 15'h79B8, 15'h79BF, 15'h79C6, 15'h79CE, 15'h79D5, 15'h79DC, 15'h79E3, 15'h79EA,
15'h79F2, 15'h79F9, 15'h7A00, 15'h7A07, 15'h7A0E, 15'h7A15, 15'h7A1C, 15'h7A23, 15'h7A2A, 15'h7A31, 15'h7A38, 15'h7A3F, 15'h7A46, 15'h7A4D, 15'h7A53, 15'h7A5A,
15'h7A61, 15'h7A68, 15'h7A6E, 15'h7A75, 15'h7A7C, 15'h7A83, 15'h7A89, 15'h7A90, 15'h7A96, 15'h7A9D, 15'h7AA4, 15'h7AAA, 15'h7AB1, 15'h7AB7, 15'h7ABE, 15'h7AC4,
15'h7ACA, 15'h7AD1, 15'h7AD7, 15'h7ADE, 15'h7AE4, 15'h7AEA, 15'h7AF1, 15'h7AF7, 15'h7AFD, 15'h7B03, 15'h7B09, 15'h7B10, 15'h7B16, 15'h7B1C, 15'h7B22, 15'h7B28,
15'h7B2E, 15'h7B34, 15'h7B3A, 15'h7B40, 15'h7B46, 15'h7B4C, 15'h7B52, 15'h7B58, 15'h7B5E, 15'h7B64, 15'h7B6A, 15'h7B70, 15'h7B76, 15'h7B7B, 15'h7B81, 15'h7B87,
15'h7B8D, 15'h7B92, 15'h7B98, 15'h7B9E, 15'h7BA3, 15'h7BA9, 15'h7BAF, 15'h7BB4, 15'h7BBA, 15'h7BBF, 15'h7BC5, 15'h7BCA, 15'h7BD0, 15'h7BD5, 15'h7BDB, 15'h7BE0,
15'h7BE6, 15'h7BEB, 15'h7BF0, 15'h7BF6, 15'h7BFB, 15'h7C00, 15'h7C06, 15'h7C0B, 15'h7C10, 15'h7C15, 15'h7C1B, 15'h7C20, 15'h7C25, 15'h7C2A, 15'h7C2F, 15'h7C34,
15'h7C3A, 15'h7C3F, 15'h7C44, 15'h7C49, 15'h7C4E, 15'h7C53, 15'h7C58, 15'h7C5D, 15'h7C62, 15'h7C67, 15'h7C6B, 15'h7C70, 15'h7C75, 15'h7C7A, 15'h7C7F, 15'h7C84,
15'h7C88, 15'h7C8D, 15'h7C92, 15'h7C97, 15'h7C9B, 15'h7CA0, 15'h7CA5, 15'h7CA9, 15'h7CAE, 15'h7CB3, 15'h7CB7, 15'h7CBC, 15'h7CC1, 15'h7CC5, 15'h7CCA, 15'h7CCE,
15'h7CD3, 15'h7CD7, 15'h7CDC, 15'h7CE0, 15'h7CE4, 15'h7CE9, 15'h7CED, 15'h7CF2, 15'h7CF6, 15'h7CFA, 15'h7CFF, 15'h7D03, 15'h7D07, 15'h7D0B, 15'h7D10, 15'h7D14,
15'h7D18, 15'h7D1C, 15'h7D21, 15'h7D25, 15'h7D29, 15'h7D2D, 15'h7D31, 15'h7D35, 15'h7D39, 15'h7D3D, 15'h7D41, 15'h7D45, 15'h7D49, 15'h7D4D, 15'h7D51, 15'h7D55,
15'h7D59, 15'h7D5D, 15'h7D61, 15'h7D65, 15'h7D69, 15'h7D6D, 15'h7D71, 15'h7D74, 15'h7D78, 15'h7D7C, 15'h7D80, 15'h7D84, 15'h7D87, 15'h7D8B, 15'h7D8F, 15'h7D92,
15'h7D96, 15'h7D9A, 15'h7D9D, 15'h7DA1, 15'h7DA5, 15'h7DA8, 15'h7DAC, 15'h7DAF, 15'h7DB3, 15'h7DB7, 15'h7DBA, 15'h7DBE, 15'h7DC1, 15'h7DC5, 15'h7DC8, 15'h7DCB,
15'h7DCF, 15'h7DD2, 15'h7DD6, 15'h7DD9, 15'h7DDC, 15'h7DE0, 15'h7DE3, 15'h7DE6, 15'h7DEA, 15'h7DED, 15'h7DF0, 15'h7DF4, 15'h7DF7, 15'h7DFA, 15'h7DFD, 15'h7E00,
15'h7E04, 15'h7E07, 15'h7E0A, 15'h7E0D, 15'h7E10, 15'h7E13, 15'h7E17, 15'h7E1A, 15'h7E1D, 15'h7E20, 15'h7E23, 15'h7E26, 15'h7E29, 15'h7E2C, 15'h7E2F, 15'h7E32,
15'h7E35, 15'h7E38, 15'h7E3B, 15'h7E3E, 15'h7E40, 15'h7E43, 15'h7E46, 15'h7E49, 15'h7E4C, 15'h7E4F, 15'h7E52, 15'h7E54, 15'h7E57, 15'h7E5A, 15'h7E5D, 15'h7E60,
15'h7E62, 15'h7E65, 15'h7E68, 15'h7E6A, 15'h7E6D, 15'h7E70, 15'h7E72, 15'h7E75, 15'h7E78, 15'h7E7A, 15'h7E7D, 15'h7E80, 15'h7E82, 15'h7E85, 15'h7E87, 15'h7E8A,
15'h7E8C, 15'h7E8F, 15'h7E91, 15'h7E94, 15'h7E96, 15'h7E99, 15'h7E9B, 15'h7E9E, 15'h7EA0, 15'h7EA3, 15'h7EA5, 15'h7EA7, 15'h7EAA, 15'h7EAC, 15'h7EAF, 15'h7EB1,
15'h7EB3, 15'h7EB6, 15'h7EB8, 15'h7EBA, 15'h7EBC, 15'h7EBF, 15'h7EC1, 15'h7EC3, 15'h7EC5, 15'h7EC8, 15'h7ECA, 15'h7ECC, 15'h7ECE, 15'h7ED1, 15'h7ED3, 15'h7ED5,
15'h7ED7, 15'h7ED9, 15'h7EDB, 15'h7EDD, 15'h7EDF, 15'h7EE2, 15'h7EE4, 15'h7EE6, 15'h7EE8, 15'h7EEA, 15'h7EEC, 15'h7EEE, 15'h7EF0, 15'h7EF2, 15'h7EF4, 15'h7EF6,
15'h7EF8, 15'h7EFA, 15'h7EFC, 15'h7EFE, 15'h7F00, 15'h7F02, 15'h7F03, 15'h7F05, 15'h7F07, 15'h7F09, 15'h7F0B, 15'h7F0D, 15'h7F0F, 15'h7F10, 15'h7F12, 15'h7F14,
15'h7F16, 15'h7F18, 15'h7F19, 15'h7F1B, 15'h7F1D, 15'h7F1F, 15'h7F20, 15'h7F22, 15'h7F24, 15'h7F26, 15'h7F27, 15'h7F29, 15'h7F2B, 15'h7F2C, 15'h7F2E, 15'h7F30,
15'h7F31, 15'h7F33, 15'h7F35, 15'h7F36, 15'h7F38, 15'h7F39, 15'h7F3B, 15'h7F3D, 15'h7F3E, 15'h7F40, 15'h7F41, 15'h7F43, 15'h7F44, 15'h7F46, 15'h7F47, 15'h7F49,
15'h7F4A, 15'h7F4C, 15'h7F4D, 15'h7F4F, 15'h7F50, 15'h7F52, 15'h7F53, 15'h7F54, 15'h7F56, 15'h7F57, 15'h7F59, 15'h7F5A, 15'h7F5B, 15'h7F5D, 15'h7F5E, 15'h7F60,
15'h7F61, 15'h7F62, 15'h7F64, 15'h7F65, 15'h7F66, 15'h7F68, 15'h7F69, 15'h7F6A, 15'h7F6B, 15'h7F6D, 15'h7F6E, 15'h7F6F, 15'h7F70, 15'h7F72, 15'h7F73, 15'h7F74,
15'h7F75, 15'h7F77, 15'h7F78, 15'h7F79, 15'h7F7A, 15'h7F7B, 15'h7F7D, 15'h7F7E, 15'h7F7F, 15'h7F80, 15'h7F81, 15'h7F82, 15'h7F83, 15'h7F85, 15'h7F86, 15'h7F87,
15'h7F88, 15'h7F89, 15'h7F8A, 15'h7F8B, 15'h7F8C, 15'h7F8D, 15'h7F8E, 15'h7F8F, 15'h7F90, 15'h7F91, 15'h7F92, 15'h7F93, 15'h7F94, 15'h7F95, 15'h7F96, 15'h7F97,
15'h7F98, 15'h7F99, 15'h7F9A, 15'h7F9B, 15'h7F9C, 15'h7F9D, 15'h7F9E, 15'h7F9F, 15'h7FA0, 15'h7FA1, 15'h7FA2, 15'h7FA3, 15'h7FA4, 15'h7FA4, 15'h7FA5, 15'h7FA6,
15'h7FA7, 15'h7FA8, 15'h7FA9, 15'h7FAA, 15'h7FAB, 15'h7FAB, 15'h7FAC, 15'h7FAD, 15'h7FAE, 15'h7FAF, 15'h7FAF, 15'h7FB0, 15'h7FB1, 15'h7FB2, 15'h7FB3, 15'h7FB3,
15'h7FB4, 15'h7FB5, 15'h7FB6, 15'h7FB6, 15'h7FB7, 15'h7FB8, 15'h7FB9, 15'h7FB9, 15'h7FBA, 15'h7FBB, 15'h7FBC, 15'h7FBC, 15'h7FBD, 15'h7FBE, 15'h7FBE, 15'h7FBF,
15'h7FC0, 15'h7FC0, 15'h7FC1, 15'h7FC2, 15'h7FC2, 15'h7FC3, 15'h7FC4, 15'h7FC4, 15'h7FC5, 15'h7FC6, 15'h7FC6, 15'h7FC7, 15'h7FC8, 15'h7FC8, 15'h7FC9, 15'h7FC9,
15'h7FCA, 15'h7FCB, 15'h7FCB, 15'h7FCC, 15'h7FCC, 15'h7FCD, 15'h7FCD, 15'h7FCE, 15'h7FCF, 15'h7FCF, 15'h7FD0, 15'h7FD0, 15'h7FD1, 15'h7FD1, 15'h7FD2, 15'h7FD2,
15'h7FD3, 15'h7FD3, 15'h7FD4, 15'h7FD4, 15'h7FD5, 15'h7FD5, 15'h7FD6, 15'h7FD6, 15'h7FD7, 15'h7FD7, 15'h7FD8, 15'h7FD8, 15'h7FD9, 15'h7FD9, 15'h7FDA, 15'h7FDA,
15'h7FDB, 15'h7FDB, 15'h7FDB, 15'h7FDC, 15'h7FDC, 15'h7FDD, 15'h7FDD, 15'h7FDE, 15'h7FDE, 15'h7FDE, 15'h7FDF, 15'h7FDF, 15'h7FE0, 15'h7FE0, 15'h7FE0, 15'h7FE1,
15'h7FE1, 15'h7FE2, 15'h7FE2, 15'h7FE2, 15'h7FE3, 15'h7FE3, 15'h7FE3, 15'h7FE4, 15'h7FE4, 15'h7FE5, 15'h7FE5, 15'h7FE5, 15'h7FE6, 15'h7FE6, 15'h7FE6, 15'h7FE7,
15'h7FE7, 15'h7FE7, 15'h7FE8, 15'h7FE8, 15'h7FE8, 15'h7FE9, 15'h7FE9, 15'h7FE9, 15'h7FE9, 15'h7FEA, 15'h7FEA, 15'h7FEA, 15'h7FEB, 15'h7FEB, 15'h7FEB, 15'h7FEB,
15'h7FEC, 15'h7FEC, 15'h7FEC, 15'h7FED, 15'h7FED, 15'h7FED, 15'h7FED, 15'h7FEE, 15'h7FEE, 15'h7FEE, 15'h7FEE, 15'h7FEF, 15'h7FEF, 15'h7FEF, 15'h7FEF, 15'h7FF0,
15'h7FF0, 15'h7FF0, 15'h7FF0, 15'h7FF0, 15'h7FF1, 15'h7FF1, 15'h7FF1, 15'h7FF1, 15'h7FF2, 15'h7FF2, 15'h7FF2, 15'h7FF2, 15'h7FF2, 15'h7FF3, 15'h7FF3, 15'h7FF3,
15'h7FF3, 15'h7FF3, 15'h7FF4, 15'h7FF4, 15'h7FF4, 15'h7FF4, 15'h7FF4, 15'h7FF4, 15'h7FF5, 15'h7FF5, 15'h7FF5, 15'h7FF5, 15'h7FF5, 15'h7FF5, 15'h7FF6, 15'h7FF6,
15'h7FF6, 15'h7FF6, 15'h7FF6, 15'h7FF6, 15'h7FF6, 15'h7FF7, 15'h7FF7, 15'h7FF7, 15'h7FF7, 15'h7FF7, 15'h7FF7, 15'h7FF7, 15'h7FF8, 15'h7FF8, 15'h7FF8, 15'h7FF8,
15'h7FF8, 15'h7FF8, 15'h7FF8, 15'h7FF8, 15'h7FF9, 15'h7FF9, 15'h7FF9, 15'h7FF9, 15'h7FF9, 15'h7FF9, 15'h7FF9, 15'h7FF9, 15'h7FF9, 15'h7FFA, 15'h7FFA, 15'h7FFA,
15'h7FFA, 15'h7FFA, 15'h7FFA, 15'h7FFA, 15'h7FFA, 15'h7FFA, 15'h7FFA, 15'h7FFA, 15'h7FFB, 15'h7FFB, 15'h7FFB, 15'h7FFB, 15'h7FFB, 15'h7FFB, 15'h7FFB, 15'h7FFB,
15'h7FFB, 15'h7FFB, 15'h7FFB, 15'h7FFB, 15'h7FFC, 15'h7FFC, 15'h7FFC, 15'h7FFC, 15'h7FFC, 15'h7FFC, 15'h7FFC, 15'h7FFC, 15'h7FFC, 15'h7FFC, 15'h7FFC, 15'h7FFC,
15'h7FFC, 15'h7FFC, 15'h7FFC, 15'h7FFC, 15'h7FFC, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD,
15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFD, 15'h7FFE, 15'h7FFE, 15'h7FFE,
15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE,
15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE,
15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE,
15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE,
15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE,
15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE,
15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE,
15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFE, 15'h7FFF
};
endmodule

6656
common/Sound/opl3/exp_tab.mem Normal file
View File

File diff suppressed because it is too large Load Diff

BIN
common/Sound/opl3/fw/OPL3.COM Normal file
View File

Binary file not shown.

101
common/Sound/opl3/fw/OPL3.PRJ Normal file
View File

@@ -0,0 +1,101 @@
;Project file: Z:\OPL3FW\OPL3.PRJ for HI-TECH C Z80/Z180/64180 V7.80
List: Source Files Rel Auto
Entry: YMF262.C
Endlist:
List: Object Files Abs Auto
Entry: $(LIB)\RTZ80-c.OBJ
Endlist:
List: CPP Include Paths Abs Auto
Entry: $(INC)
Endlist:
List: CPP Pre-defined Symbols Abs Auto
Entry: -Dz80
Entry: -DHI_TECH_C
Entry: -SP2,2,2,2,2,2,2
Entry: -S1,2,2,4,4,4
Entry: -D_HOSTED
Entry: -DCPM
Entry: -DSMALL_MODEL
Entry: -D_HTC_VER_MAJOR_=7
Entry: -D_HTC_VER_MINOR_=80
Entry: -D_HTC_VER_PATCH_=2
Endlist:
List: Libraries Abs Auto
Entry: $(LIB)\Z80-cC.LIB
Endlist:
List: Linker options Abs Frozen Warned
Entry: -pvectors=0,lowtext,text,strings,const,im2vecs,bss
Entry: -pnvram=bss,heap
Entry: -Pdata=1900h
Endlist:
List: Objtohex options Abs Auto
Entry: -b100h
Endlist:
Depfiles:
Entry: $(INC)\STRING.H
Entry: $(INC)\SYS.H
Entry: ymf262.h
Enddeps:
Dependencies:
Entry: 1528935816 3 0 1 2
Enddeps:
Int: Checksize: 1
Int: OuputFormat: 0
Int: Warnlevel: 0
Int: IdLength: 31
Int: DebugBaud: 0
Int: ComPort: 0
Int: GlobOptLevel: 9
Time: OptionsModified: 1528921310
Int: Rom_addr: 0
Int: Ram_addr: 32768
Int: Ram_size: 32768
Int: Nvram_addr: 0
Int: Ram_phys: 262144
Int: Bank_addr: 8192
Int: Bank_size: 24576
Int: Bank_phys: 8192
Int: Size_phys: 1040384
Int: Modelno: 2
Int: Chiptype: 0
Bool: Globopt: 1
Bool: Postopt: 1
Bool: Assemopt: 0
Bool: Symbolic_debug: 0
Bool: Nolocal: 0
Bool: Uselong: 0
Bool: Usefloat: 0
Bool: Autoload: 0
Bool: Cppasm: 0
Bool: Genlist: 0
Bool: GenSrclist: 0
Bool: Gotadrs: 1
Bool: Multirom: 0
Bool: Avocet_symbols: 0
Bool: Stopwarn: 1
Bool: StrictANSI: 0
Bool: Savedeps: 1
Bool: NumericSort: 0
Bool: Romdata: 0
Bool: Port8: 0
Bool: UseAltReg: 0
String: Outfile:OPL3.COM
String: Mapfile:
String: Symfile:
ROM Ranges:
EndROM
Checksums:
EndChecksums

346
common/Sound/opl3/fw/TEST.H Normal file
View File

@@ -0,0 +1,346 @@
#define delay(x) Sleep(x)
const //List of FNumbers
uint16_t FNr[12] = {
/*C*/ 343,
/*C#/Db*/ 363,
/*D*/ 385,
/*D#/Eb*/ 408,
/*E*/ 432,
/*F*/ 458,
/*F#/Gb*/ 485,
/*G*/ 514,
/*G#/Ab*/ 544,
/*A*/ 577,
/*A#/Bb*/ 611,
/*B*/ 647 };
//Flat Whole Sharp}
#define C 0
#define CSharp 1
#define DFlat 1
#define D 2
#define DSharp 3
#define EFlat 3
#define E 4
#define F 5
#define FSharp 6
#define GFlat 6
#define G 7
#define GSharp 8
#define AFlat 8
#define A 9
#define ASharp 10
#define BFlat 10
#define B 11
struct Operator {
uint8_t
//Tremolo
Tremolo,
//Vibrato
Vibrato,
//Envelop generator type
EGType,
//KSR
KSR,
//Frequency multiplier
Multi,
//Key scaling level
KSL,
//Volume
TotalLevel,
//Shape of the wave envelop
Attack, Decay, Sustain, Release,
//Type of wave
WaveShape;
};
struct Instrument {
struct Operator Modulator, Carrier;
uint8_t
//Feedback strength
Feedback,
//Synthesis type
SynType;
};
struct Instrument Flute, Piano, Harp;
uint8_t CurNote, CurBlock;
/**************************************************************************
** Writes a value to a specified index register on the FM card **
**************************************************************************/
void WriteFM(uint8_t Register, uint8_t Value)
{
OPL3Write(0, Register);
OPL3Write(1, Value);
// unsigned char Counter;
//Select register
// outportb(0x388, Register);
//Wait for card to accept value
// for (Counter = 1; Counter < 25; Counter++) { inportb(0x388); }
//Send value
// outportb(0x389, Value);
//Wait for card to accept value
// for (Counter = 1; Counter < 100; Counter++) { inportb(0x388); }
}
/**************************************************************************
** Checks for the presence of an FM card **
**************************************************************************/
uint8_t FMInstalled()
{
// unsigned char A, B;
// WriteFM(1, 0);
// WriteFM(4, 0x60);
// WriteFM(4, 0x80);
// A = inportb(0x388);
// A = OPL3Read(0);
// WriteFM(2, 0xFF);
// WriteFM(4, 0x21);
// B = inportb(0x388);
// OPL3TimerOver(0);
// B = OPL3Read(0);
// WriteFM(4, 0x60);
// WriteFM(4, 0x80);
// if ((A & 0xE0) == 0 && (B & 0xE0) == 0xC0) {
return (1);
// }
// else {
// return (0);
// }
}
/**************************************************************************
** Activates a voice on the FM card **
***************************************************************************
** Voice selects one of the 9 FM voices **
** FNumber selects the note to be played **
** Block selects the octave for the specified note **
**************************************************************************/
void NoteOn(uint8_t Voice, uint8_t Note, uint8_t Block)
{
WriteFM(0xA0 + Voice, FNr[Note] & 0xFF);
WriteFM(0xB0 + Voice, (FNr[Note] >> 8) + (Block << 2) + 32);
}
/**************************************************************************
** Deactivates a voice on the FM card **
***************************************************************************
** Make sure to give the same values for Note and Block or this will **
** sound very odd. **
**************************************************************************/
void NoteOff(uint8_t Voice, uint8_t Note, uint8_t Block)
{
WriteFM(0xA0 + Voice, FNr[Note] & 0xFF);
WriteFM(0xB0 + Voice, (FNr[Note] >> 8) + (Block << 2));
}
/**************************************************************************
** Sets instrument settings for a voice on the FM card **
**************************************************************************/
const static unsigned char OpAdr[9] = { 0, 1, 2, 8, 9, 10, 16, 17, 18 }; //Addresses of the operators used to form voice data
void SetInstrument(uint8_t Voice, struct Instrument *Instr)
{
uint8_t Value;
//Set up voice modulator
Value = Instr->Modulator.Tremolo << 8
| Instr->Modulator.Vibrato << 7
| Instr->Modulator.EGType << 6
| Instr->Modulator.KSR << 5
| Instr->Modulator.Multi;
WriteFM(0x20 + OpAdr[Voice], Value);
Value = Instr->Modulator.KSL << 7
| Instr->Modulator.TotalLevel;
WriteFM(0x40 + OpAdr[Voice], Value);
Value = Instr->Modulator.Attack << 4
| Instr->Modulator.Decay;
WriteFM(0x60 + OpAdr[Voice], Value);
Value = Instr->Modulator.Sustain << 4
| Instr->Modulator.Release;
WriteFM(0x80 + OpAdr[Voice], Value);
WriteFM(0xE0 + OpAdr[Voice], Instr->Modulator.WaveShape);
Value = Instr->Feedback << 1
| Instr->SynType;
WriteFM(0xC0 + OpAdr[Voice], Value);
//Set up voice carrier
Value = Instr->Carrier.Tremolo << 8
| Instr->Carrier.Vibrato << 7
| Instr->Carrier.EGType << 6
| Instr->Carrier.KSR << 5
| Instr->Carrier.Multi;
WriteFM(0x23 + OpAdr[Voice], Value);
Value = Instr->Carrier.KSL << 7
| Instr->Carrier.TotalLevel;
WriteFM(0x43 + OpAdr[Voice], Value);
Value = Instr->Carrier.Attack << 4
| Instr->Carrier.Decay;
WriteFM(0x63 + OpAdr[Voice], Value);
Value = Instr->Carrier.Sustain << 4
| Instr->Carrier.Release;
WriteFM(0x83 + OpAdr[Voice], Value);
WriteFM(0xE3 + OpAdr[Voice], Instr->Carrier.WaveShape);
}
void test()
{
// clrscr();
again:
printf("Demonstration of programming a FM sound card [AdLib, SB and compatibles]\n");
printf("--------------------------------------------------------------------------\n");
//Check to see if an FM sound card is present
/* if (FMInstalled()) {
printf("AdLib/SB or compatible FM sound card found.\n");
}
else {
//If not, end the programme
printf("AdLib/SB or compatible FM sound card not found.\n");
return;
}
*/
//Set up voices 0 - 3 to a "harp" - note, only the values other than 0 are set
Harp.Modulator.Attack = 15;
Harp.Modulator.Decay = 5;
Harp.Modulator.Sustain = 8;
Harp.Modulator.Release = 5;
Harp.Modulator.Multi = 2;
Harp.Modulator.TotalLevel = 41;
Harp.Carrier.Attack = 15;
Harp.Carrier.Decay = 2;
Harp.Carrier.Release = 3;
Harp.Carrier.Multi = 1;
Harp.Carrier.KSL = 2;
Harp.Carrier.TotalLevel = 3;
SetInstrument(0, &Harp);
SetInstrument(1, &Harp);
SetInstrument(2, &Harp);
//Play C chord using Harp
printf("Playing C chord.\n");
NoteOn(0, C, 4);
NoteOn(1, E, 4);
NoteOn(2, G, 4);
delay(1000); //Wait 1 second
NoteOff(0, C, 4);
NoteOff(1, E, 4);
NoteOff(2, G, 4);
//Wait a while
delay(500);
//Set up voice 3 to a "piano" - this doesn't really sound like a piano,
//but that's what they call it!
Piano.Modulator.Attack = 15;
Piano.Modulator.Decay = 1;
Piano.Modulator.Sustain = 10;
Piano.Modulator.Release = 3;
Piano.Modulator.Multi = 1;
Piano.Modulator.KSL = 1;
Piano.Modulator.TotalLevel = 16;
Piano.Carrier.Attack = 13;
Piano.Carrier.Decay = 2;
Piano.Carrier.Sustain = 8;
Piano.Carrier.Release = 4;
Piano.Carrier.Multi = 1;
Piano.Carrier.TotalLevel = 0;
Piano.Carrier.KSR = 1;
Piano.Feedback = 3;
SetInstrument(3, &Piano);
//Play all notes in octave 4 for .1 seconds using piano [voice 3]
printf("Playing all notes in octave four.\n");
CurBlock = 4;
for (CurNote = 0; CurNote < 12; CurNote++) {
NoteOn(3, CurNote, CurBlock);
delay(100); //Wait .1 seconds
NoteOff(3, CurNote, CurBlock);
}
//Wait a while
delay(500);
//Set up voice 4 to a "flute"
Flute.Modulator.Attack = 6;
Flute.Modulator.Decay = 14;
Flute.Modulator.Sustain = 7;
Flute.Modulator.Release = 15;
Flute.Modulator.Vibrato = 1;
Flute.Modulator.Tremolo = 1;
Flute.Modulator.EGType = 1;
Flute.Modulator.KSL = 3;
Flute.Modulator.TotalLevel = 44;
Flute.Carrier.Attack = 6;
Flute.Carrier.Decay = 5;
Flute.Carrier.Sustain = 13;
Flute.Carrier.Release = 10;
Flute.Carrier.Vibrato = 1;
Flute.Carrier.EGType = 1;
Flute.Carrier.Multi = 1;
Flute.Carrier.TotalLevel = 0;
Flute.Feedback = 7;
Flute.SynType = 3;
SetInstrument(4, &Flute);
//Play short tune using Flute [voice 4] as primary, Harp [voice 0] as secondary voice
printf("Playing short tune.\n");
NoteOn(4, C, 5); NoteOn(0, C, 3);
delay(250);
NoteOff(4, C, 5);
NoteOn(4, E, 5);
delay(250);
NoteOff(4, E, 5); NoteOff(0, C, 3);
NoteOn(4, C, 5); NoteOn(0, G, 3);
delay(250);
NoteOff(4, C, 5);
NoteOn(4, G, 4);
delay(250);
NoteOff(4, G, 4); NoteOff(0, G, 3);
NoteOn(4, E, 4); NoteOn(0, C, 4);
delay(250);
NoteOff(4, E, 4);
NoteOn(4, G, 4);
delay(250);
NoteOff(4, G, 4); NoteOff(0, C, 4);
NoteOn(4, E, 4); NoteOn(0, G, 3);
delay(250);
NoteOff(4, E, 4);
NoteOn(4, D, 4);
delay(250);
NoteOff(4, D, 4); NoteOff(0, G, 3);
NoteOn(4, C, 4); NoteOn(0, C, 3);
delay(2000);
NoteOff(4, C, 4); NoteOff(0, C, 3);
goto again;
}

767
common/Sound/opl3/fw/YMF262.C Normal file
View File

@@ -0,0 +1,767 @@
// license:GPL-2.0+
// copyright-holders:Jarek Burczynski
/*
**
** File: ymf262.c - software implementation of YMF262
** FM sound generator type OPL3
**
** Copyright Jarek Burczynski
**
** Version 0.2
**
Revision History:
03-03-2003: initial release
- thanks to Olivier Galibert and Chris Hardy for YMF262 and YAC512 chips
- thanks to Stiletto for the datasheets
Features as listed in 4MF262A6 data sheet:
1. Registers are compatible with YM3812 (OPL2) FM sound source.
2. Up to six sounds can be used as four-operator melody sounds for variety.
3. 18 simultaneous melody sounds, or 15 melody sounds with 5 rhythm sounds (with two operators).
4. 6 four-operator melody sounds and 6 two-operator melody sounds, or 6 four-operator melody
sounds, 3 two-operator melody sounds and 5 rhythm sounds (with four operators).
5. 8 selectable waveforms.
6. 4-channel sound output.
7. YMF262 compabile DAC (YAC512) is available.
8. LFO for vibrato and tremolo effedts.
9. 2 programable timers.
10. Shorter register access time compared with YM3812.
11. 5V single supply silicon gate CMOS process.
12. 24 Pin SOP Package (YMF262-M), 48 Pin SQFP Package (YMF262-S).
differences between OPL2 and OPL3 not documented in Yamaha datahasheets:
- sinus table is a little different: the negative part is off by one...
- in order to enable selection of four different waveforms on OPL2
one must set bit 5 in register 0x01(test).
on OPL3 this bit is ignored and 4-waveform select works *always*.
(Don't confuse this with OPL3's 8-waveform select.)
- Envelope Generator: all 15 x rates take zero time on OPL3
(on OPL2 15 0 and 15 1 rates take some time while 15 2 and 15 3 rates
take zero time)
- channel calculations: output of operator 1 is in perfect sync with
output of operator 2 on OPL3; on OPL and OPL2 output of operator 1
is always delayed by one sample compared to output of operator 2
differences between OPL2 and OPL3 shown in datasheets:
- YMF262 does not support CSM mode
*/
//#include "stdafx.h"
#include <string.h>
#include <sys.h>
#include "ymf262.h"
#define PITCH_COEF 1154
//#define PITCH_COEF 1024
#define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
#define EG_SH 16 /* 16.16 fixed point (EG timing) */
#define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
#define FREQ_MASK ((1<<FREQ_SH)-1)
OPL3 chip = {0xcc, 0xcd};
/* mapping of register number (offset) to slot number used by the emulator */
static const int8_t slot_array[32] = { 0, 2, 4, 1, 3, 5,-1,-1, 6, 8,10, 7, 9,11,-1,-1, 12,14,16,13,15,17,-1,-1, -1,-1,-1,-1,-1,-1,-1,-1 };
static const uint8_t ksl_tab[8 * 16] = { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,8,12,16,20,24,28,32,0,0,0,0,0,12,20,28,32,40,44,48,52,56,60,64,0,0,0,20,32,44,52,60,64,72,76,80,84,88,92,96,0,0,32,52,64,76,84,92,96,104,108,112,116,120,124,128,0,32,64,84,96,108,116,124,128,136,140,144,148,152,156,160,0,64,96,116,128,140,148,156,160,168,172,176,180,184,188,192,0,96,128,148,160,172,180,188,192,200,204,208,212,216,220,224 };
static const uint8_t ksl_shift[4] = { 31, 1, 2, 0 };
static const uint8_t sl_tab[16] = { 0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 248 };
static const uint8_t eg_rate_select[16 + 64 + 16] = { 112,112,112,112,112,112,112,112,112,112,112,112,112,112,112,112,0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24,0,8,16,24,32,40,48,56,64,72,80,88,96,96,96,96,96,96,96,96,96,96,96,96,96,96,96,96,96,96,96,96 };
static const uint8_t eg_rate_shift[16 + 64 + 16] = { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,12,12,12,12,11,11,11,11,10,10,10,10,9,9,9,9,8,8,8,8,7,7,7,7,6,6,6,6,5,5,5,5,4,4,4,4,3,3,3,3,2,2,2,2,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 };
static const uint8_t mul_tab[16]= { 1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 20, 24, 24, 30, 30 }; /* multiple table */
static void FM_KEYON(OPL3_SLOT *SLOT, uint8_t key_set)
{
if( !SLOT->key )
{
SLOT->Cnt = 0; /* restart Phase Generator */
SLOT->state = EG_ATT; /* phase -> Attack */
}
SLOT->key |= key_set;
}
static void FM_KEYOFF(OPL3_SLOT *SLOT, uint8_t key_clr)
{
if( SLOT->key )
{
SLOT->key &= key_clr;
if( !SLOT->key )
if (SLOT->state>EG_REL) SLOT->state = EG_REL; /* phase -> Release */
}
}
/* update phase increment counter of operator (also update the EG rates if necessary) */
static void CALC_FCSLOT(OPL3_CH *CH, OPL3_SLOT *SLOT)
{
uint8_t ksr;
/* (frequency) phase increment counter */
uint8_t shift = 7 - (CH->block_fnum >> 10);
SLOT->Incr = ((CH->block_fnum & 0x03ff) * (uint32_t)SLOT->mul << 2) >> shift;
ksr = CH->kcode >> SLOT->KSR;
if( SLOT->ksr != ksr )
{
SLOT->ksr = ksr;
ksr += SLOT->ar;
/* calculate envelope generator rates */
if (ksr < 16+60)
{
SLOT->eg_sh_ar = eg_rate_shift [ksr];
SLOT->eg_sel_ar = eg_rate_select[ksr];
}
else
{
SLOT->eg_sh_ar = 0;
SLOT->eg_sel_ar = 13*RATE_STEPS;
}
ksr = SLOT->dr + SLOT->ksr;
SLOT->eg_sh_dr = eg_rate_shift [ksr];
SLOT->eg_sel_dr = eg_rate_select[ksr];
ksr = SLOT->rr + SLOT->ksr;
SLOT->eg_sh_rr = eg_rate_shift [ksr];
SLOT->eg_sel_rr = eg_rate_select[ksr];
}
}
/* set multi,am,vib,EG-TYP,KSR,mul */
static void set_mul(uint8_t slot, uint8_t v)
{
OPL3_CH *CH = &chip.P_CH[slot >> 1];
OPL3_SLOT *SLOT = (slot & 1) ? &CH->SLOT1 : &CH->SLOT0;
SLOT->mul = PITCH_COEF*mul_tab[v & 0x0f];
SLOT->KSR = (v & 0x10) ? 0 : 2;
SLOT->eg_type = !!(v & 0x20);
SLOT->vib = !!(v & 0x40);
SLOT->AMmask_TLL = ((uint16_t)(v & 0x80) << 8) + (SLOT->AMmask_TLL & 0x7fff);
if (chip.OPL3_mode)
{
int8_t chan_no = slot >> 1;
switch(chan_no)
{
case 0: case 1: case 2:
case 9: case 10: case 11:
if (CH->extended) CALC_FCSLOT(CH,SLOT); /* normal */
else CALC_FCSLOT(CH,SLOT); /* normal */
break;
case 3: case 4: case 5:
case 12: case 13: case 14:
if ((CH-3)->extended) CALC_FCSLOT(CH-3,SLOT); /* update this SLOT using frequency data for 1st channel of a pair */
else CALC_FCSLOT(CH,SLOT); /* normal */
break;
default:
CALC_FCSLOT(CH,SLOT); /* normal */
break;
}
}
else CALC_FCSLOT(CH,SLOT); /* in OPL2 mode */
}
/* set ksl & tl */
static void set_ksl_tl(uint8_t slot, uint8_t v)
{
OPL3_CH *CH = &chip.P_CH[slot >> 1];
OPL3_SLOT *SLOT = (slot & 1) ? &CH->SLOT1 : &CH->SLOT0;
SLOT->ksl = ksl_shift[v >> 6];
SLOT->TL = (v & 0x3f) << (ENV_BITS-1-7); /* 7 bits TL (bit 6 = always 0) */
SLOT->AMmask_TLL = SLOT->TL + (CH->ksl_base >> SLOT->ksl) + (SLOT->AMmask_TLL & 0x8000);
if (chip.OPL3_mode)
{
uint8_t chan_no = slot >> 2;
switch(chan_no)
{
case 3: case 4: case 5:
case 12: case 13: case 14:
if ((CH-3)->extended) SLOT->AMmask_TLL = SLOT->TL + ((CH-3)->ksl_base>>SLOT->ksl) + (SLOT->AMmask_TLL & 0x8000); /* update this SLOT using frequency data for 1st channel of a pair */
break;
}
}
}
/* set attack rate & decay rate */
static void set_ar_dr(uint8_t slot, uint8_t v)
{
OPL3_CH *CH = &chip.P_CH[slot >> 1];
OPL3_SLOT *SLOT = (slot & 1) ? &CH->SLOT1 : &CH->SLOT0;
uint8_t ksr;
SLOT->ar = (v & 0xf0) ? 16 + ((v & 0xf0) >> 2) : 0;
ksr = SLOT->ar + SLOT->ksr;
if (ksr < 16+60) /* verified on real YMF262 - all 15 x rates take "zero" time */
{
SLOT->eg_sh_ar = eg_rate_shift [ksr];
SLOT->eg_sel_ar = eg_rate_select[ksr];
}
else
{
SLOT->eg_sh_ar = 0;
SLOT->eg_sel_ar = 13*RATE_STEPS;
}
SLOT->dr = (v&0x0f) ? 16 + ((v&0x0f)<<2) : 0;
ksr = SLOT->dr + SLOT->ksr;
SLOT->eg_sh_dr = eg_rate_shift [ksr];
SLOT->eg_sel_dr = eg_rate_select[ksr];
}
/* set sustain level & release rate */
static void set_sl_rr(uint8_t slot, uint8_t v)
{
OPL3_CH *CH = &chip.P_CH[slot >> 1];
OPL3_SLOT *SLOT = (slot & 1) ? &CH->SLOT1 : &CH->SLOT0;
uint8_t ksr = SLOT->ksr;
SLOT->sl = (uint16_t)sl_tab[ v>>4 ] << 1;
SLOT->rr = (v&0x0f) ? 16 + ((v&0x0f)<<2) : 0;
ksr += SLOT->rr;
SLOT->eg_sh_rr = eg_rate_shift [ksr];
SLOT->eg_sel_rr = eg_rate_select[ksr];
}
void fn_a0(uint16_t r, uint8_t v, uint8_t ch_offset)
{
OPL3_CH *CH;
uint16_t block_fnum;
if (r == 0xbd) /* am depth, vibrato depth, r,bd,sd,tom,tc,hh */
{
if (ch_offset != 0) return; /* 0xbd register is present in set #1 only */
chip.lfo_am_depth = !!(v & 0x80);
chip.lfo_pm_depth_range = (v & 0x40) ? 8 : 0;
chip.rhythm = !!(v & 0x20);
if (chip.rhythm)
{
/* BD key on/off */
if (v & 0x10)
{
FM_KEYON(&chip.P_CH[6].SLOT0, 2);
FM_KEYON(&chip.P_CH[6].SLOT1, 2);
}
else
{
FM_KEYOFF(&chip.P_CH[6].SLOT0, ~2);
FM_KEYOFF(&chip.P_CH[6].SLOT1, ~2);
}
/* HH key on/off */
if (v & 0x01) FM_KEYON(&chip.P_CH[7].SLOT0, 2);
else FM_KEYOFF(&chip.P_CH[7].SLOT0, ~2);
/* SD key on/off */
if (v & 0x08) FM_KEYON(&chip.P_CH[7].SLOT1, 2);
else FM_KEYOFF(&chip.P_CH[7].SLOT1, ~2);
/* TOM key on/off */
if (v & 0x04) FM_KEYON(&chip.P_CH[8].SLOT0, 2);
else FM_KEYOFF(&chip.P_CH[8].SLOT0, ~2);
/* TOP-CY key on/off */
if (v & 0x02) FM_KEYON(&chip.P_CH[8].SLOT1, 2);
else FM_KEYOFF(&chip.P_CH[8].SLOT1, ~2);
}
else
{
/* BD key off */
FM_KEYOFF(&chip.P_CH[6].SLOT0, ~2);
FM_KEYOFF(&chip.P_CH[6].SLOT1, ~2);
/* HH key off */
FM_KEYOFF(&chip.P_CH[7].SLOT0, ~2);
/* SD key off */
FM_KEYOFF(&chip.P_CH[7].SLOT1, ~2);
/* TOM key off */
FM_KEYOFF(&chip.P_CH[8].SLOT0, ~2);
/* TOP-CY off */
FM_KEYOFF(&chip.P_CH[8].SLOT1, ~2);
}
return;
}
/* keyon,block,fnum */
if ((r & 0x0f) > 8) return;
CH = &chip.P_CH[(r & 0x0f) + ch_offset];
if (!(r & 0x10)) block_fnum = (CH->block_fnum & 0x1f00) | v; /* a0-a8 */
else
{ /* b0-b8 */
block_fnum = ((v & 0x1f) << 8) | (CH->block_fnum & 0xff);
if (chip.OPL3_mode)
{
uint8_t chan_no = (r & 0x0f) + ch_offset;
switch (chan_no)
{
case 0: case 1: case 2:
case 9: case 10: case 11:
if (CH->extended)
{
if (v & 0x20)
{
FM_KEYON(&CH->SLOT0, 1);
FM_KEYON(&CH->SLOT1, 1);
FM_KEYON(&(CH + 3)->SLOT0, 1);
FM_KEYON(&(CH + 3)->SLOT1, 1);
}
else
{
FM_KEYOFF(&CH->SLOT0, ~1);
FM_KEYOFF(&CH->SLOT1, ~1);
FM_KEYOFF(&(CH + 3)->SLOT0, ~1);
FM_KEYOFF(&(CH + 3)->SLOT1, ~1);
}
}
else
{
if (v & 0x20)
{
FM_KEYON(&CH->SLOT0, 1);
FM_KEYON(&CH->SLOT1, 1);
}
else
{
FM_KEYOFF(&CH->SLOT0, ~1);
FM_KEYOFF(&CH->SLOT1, ~1);
}
}
break;
case 3: case 4: case 5:
case 12: case 13: case 14:
if ((CH - 3)->extended)
{
//if this is 2nd channel forming up 4-op channel just do nothing
}
else
{
if (v & 0x20)
{
FM_KEYON(&CH->SLOT0, 1);
FM_KEYON(&CH->SLOT1, 1);
}
else
{
FM_KEYOFF(&CH->SLOT0, ~1);
FM_KEYOFF(&CH->SLOT1, ~1);
}
}
break;
default:
if (v & 0x20)
{
FM_KEYON(&CH->SLOT0, 1);
FM_KEYON(&CH->SLOT1, 1);
}
else
{
FM_KEYOFF(&CH->SLOT0, ~1);
FM_KEYOFF(&CH->SLOT1, ~1);
}
break;
}
}
else
{
if (v & 0x20)
{
FM_KEYON(&CH->SLOT0, 1);
FM_KEYON(&CH->SLOT1, 1);
}
else
{
FM_KEYOFF(&CH->SLOT0, ~1);
FM_KEYOFF(&CH->SLOT1, ~1);
}
}
}
/* update */
if (CH->block_fnum != block_fnum)
{
CH->block_fnum = block_fnum;
CH->ksl_base = ksl_tab[block_fnum >> 6];
/* BLK 2,1,0 bits -> bits 3,2,1 of kcode */
CH->kcode = (CH->block_fnum & 0x1c00) >> 9;
/* the info below is actually opposite to what is stated in the Manuals (verifed on real YMF262) */
/* if notesel == 0 -> lsb of kcode is bit 10 (MSB) of fnum */
/* if notesel == 1 -> lsb of kcode is bit 9 (MSB-1) of fnum */
if (chip.nts & 0x40) CH->kcode |= (CH->block_fnum >> 8) & 1; /* notesel == 1 */
else CH->kcode |= (CH->block_fnum >> 9) & 1; /* notesel == 0 */
if (chip.OPL3_mode)
{
uint8_t chan_no = (r & 0x0f) + ch_offset;
switch (chan_no)
{
case 0: case 1: case 2:
case 9: case 10: case 11:
if (CH->extended)
{
/* refresh Total Level in FOUR SLOTs of this channel and channel+3 using data from THIS channel */
(CH + 3)->SLOT0.AMmask_TLL = (CH + 3)->SLOT0.TL + (CH->ksl_base >> (CH + 3)->SLOT0.ksl) + ((CH + 3)->SLOT0.AMmask_TLL & 0x8000);
(CH + 3)->SLOT1.AMmask_TLL = (CH + 3)->SLOT1.TL + (CH->ksl_base >> (CH + 3)->SLOT1.ksl) + ((CH + 3)->SLOT1.AMmask_TLL & 0x8000);
/* refresh frequency counter in FOUR SLOTs of this channel and channel+3 using data from THIS channel */
CALC_FCSLOT(CH, &(CH + 3)->SLOT0);
CALC_FCSLOT(CH, &(CH + 3)->SLOT1);
}
break;
case 3: case 4: case 5:
case 12: case 13: case 14:
if ((CH - 3)->extended) return; //if this is 2nd channel forming up 4-op channel just do nothing
break;
}
}
/* in OPL2 mode */
/* refresh Total Level in both SLOTs of this channel */
CH->SLOT0.AMmask_TLL = CH->SLOT0.TL + (CH->ksl_base >> CH->SLOT0.ksl) + (CH->SLOT0.AMmask_TLL & 0x8000);
CH->SLOT1.AMmask_TLL = CH->SLOT1.TL + (CH->ksl_base >> CH->SLOT1.ksl) + (CH->SLOT1.AMmask_TLL & 0x8000);
/* refresh frequency counter in both SLOTs of this channel */
CALC_FCSLOT(CH, &CH->SLOT0);
CALC_FCSLOT(CH, &CH->SLOT1);
}
}
uint16_t packptr16(void *ptr)
{
uint16_t v;
uint16_t i = (uint8_t*)ptr - (uint8_t*)&chip;
uint8_t j;
for (j = 0; i >= 96; i -= 96, j++);
v = (uint16_t)j << 7;
j = i & 0xff;
if (j >= 48) j -= 48, v |= 64;
return v | j;
}
/* write a value v to register r on OPL chip */
static void OPL3WriteReg(uint16_t r, uint8_t v)
{
OPL3_CH *CH;
uint8_t ch_offset = 0, base;
int8_t slot;
uint32_t mask;
if(r & 0x100)
{
switch(r)
{
case 0x101: return; /* test register */
case 0x104: /* 6 channels enable */
{
CH = &chip.P_CH[0]; /* channel 0 */
CH->extended = v & 1;
CH++; /* channel 1 */
CH->extended = (v>>=1) & 1;
CH++; /* channel 2 */
CH->extended = (v>>=1) & 1;
CH = &chip.P_CH[9]; /* channel 9 */
CH->extended = (v>>=1) & 1;
CH++; /* channel 10 */
CH->extended = (v>>=1) & 1;
CH++; /* channel 11 */
CH->extended = (v>>1) & 1;
}
return;
case 0x105: /* OPL3 extensions enable register */
chip.OPL3_mode = v & 0x01; /* OPL3 mode when bit0=1 otherwise it is OPL2 mode */
return;
}
ch_offset = 9; /* register page #2 starts from channel 9 (counting from 0) */
}
r &= 0xff; /* adjust bus to 8 bits */
switch(r & 0xe0)
{
case 0x00: /* 00-1f:control */
switch(r & 0x1f)
{
case 0x01: /* test register */
break;
case 0x02: /* Timer 1 */
break;
case 0x03: /* Timer 2 */
break;
case 0x04: /* IRQ clear / mask and Timer enable */
break;
case 0x08: /* x,NTS,x,x, x,x,x,x */
chip.nts = v;
break;
}
break;
case 0x20: /* am ON, vib ON, ksr, eg_type, mul */
slot = slot_array[r & 0x1f];
if(slot < 0) return;
set_mul(slot + ch_offset*2, v);
break;
case 0x40:
slot = slot_array[r & 0x1f];
if(slot < 0) return;
set_ksl_tl(slot + ch_offset*2, v);
break;
case 0x60:
slot = slot_array[r&0x1f];
if(slot < 0) return;
set_ar_dr(slot + ch_offset*2, v);
break;
case 0x80:
slot = slot_array[r&0x1f];
if(slot < 0) return;
set_sl_rr(slot + ch_offset*2, v);
break;
case 0xa0:
fn_a0(r, v, ch_offset);
break;
case 0xc0:
/* CH.D, CH.C, CH.B, CH.A, FB(3bits), C */
if( (r & 0xf) > 8) return;
CH = &chip.P_CH[(r & 0xf) + ch_offset];
base = (r & 0xf) + ch_offset;
mask = 1l << base;
if (chip.OPL3_mode) /* OPL3 mode */
{
chip.panA = (chip.panA & ~mask) | ((uint32_t)((v & 0x10) >> 4) << base);
chip.panB = (chip.panB & ~mask) | ((uint32_t)((v & 0x20) >> 5) << base);
// chip.pan[ base ] = (v & 0x10) != 0; /* ch.A */
// chip.pan[ base +1 ] = (v & 0x20) != 0; /* ch.B */
// chip.pan[ base +2 ] = (v & 0x40) != 0; /* ch.C */
// chip.pan[ base +3 ] = (v & 0x80) != 0; /* ch.D */
}
else /* OPL2 mode - always enabled */
{
chip.panA |= mask;
chip.panB |= mask;
// chip.pan[ base ] = 1; /* ch.A */
// chip.pan[ base +1 ] = 1; /* ch.B */
// chip.pan[ base +2 ] = 1; /* ch.C */
// chip.pan[ base +3 ] = 1; /* ch.D */
}
CH->SLOT0.FB = (v & 0xe) ? 9 - ((v & 0xe) >> 1) : 0;
CH->SLOT0.CON = v & 1;
if( chip.OPL3_mode )
{
uint8_t chan_no = (r & 0x0f) + ch_offset;
switch(chan_no)
{
case 0: case 1: case 2:
case 9: case 10: case 11:
if (CH->extended)
{
uint8_t conn = (CH->SLOT0.CON << 1) | (CH+3)->SLOT0.CON;
switch(conn)
{
case 0:
/* 1 -> 2 -> 3 -> 4 - out */
CH->SLOT0.connect = packptr16(&chip.phase_modulation);
CH->SLOT1.connect = packptr16(&chip.phase_modulation2);
(CH+3)->SLOT0.connect = packptr16(&chip.phase_modulation);
(CH + 3)->SLOT1.connect = packptr16(&chip.P_CH[chan_no + 3].chanout);// chanout[chan_no + 3];
break;
case 1:
/* 1 -> 2 -\
3 -> 4 -+- out */
CH->SLOT0.connect = packptr16(&chip.phase_modulation);
CH->SLOT1.connect = packptr16(&chip.P_CH[chan_no].chanout); // chanout[chan_no];
(CH+3)->SLOT0.connect = packptr16(&chip.phase_modulation);
(CH+3)->SLOT1.connect = packptr16(&chip.P_CH[chan_no + 3].chanout);
break;
case 2:
/* 1 -----------\
2 -> 3 -> 4 -+- out */
CH->SLOT0.connect = packptr16(&chip.P_CH[chan_no].chanout);
CH->SLOT1.connect = packptr16(&chip.phase_modulation2);
(CH+3)->SLOT0.connect = packptr16(&chip.phase_modulation);
(CH+3)->SLOT1.connect = packptr16(&chip.P_CH[chan_no + 3].chanout);
break;
case 3:
/* 1 ------\
2 -> 3 -+- out
4 ------/ */
CH->SLOT0.connect = packptr16(&chip.P_CH[chan_no].chanout);
CH->SLOT1.connect = packptr16(&chip.phase_modulation2);
(CH+3)->SLOT0.connect = packptr16(&chip.P_CH[chan_no + 3].chanout);
(CH+3)->SLOT1.connect = packptr16(&chip.P_CH[chan_no + 3].chanout);
break;
}
}
else
{
/* 2 operators mode */
CH->SLOT0.connect = packptr16(CH->SLOT0.CON ? &chip.P_CH[(r & 0xf) + ch_offset].chanout : &chip.phase_modulation);
CH->SLOT1.connect = packptr16(&chip.P_CH[(r & 0xf) + ch_offset].chanout);
}
break;
case 3: case 4: case 5:
case 12: case 13: case 14:
if ((CH-3)->extended)
{
uint8_t conn = ((CH-3)->SLOT0.CON << 1) | CH->SLOT0.CON;
switch(conn)
{
case 0:
/* 1 -> 2 -> 3 -> 4 - out */
(CH-3)->SLOT0.connect = packptr16(&chip.phase_modulation);
(CH-3)->SLOT1.connect = packptr16(&chip.phase_modulation2);
CH->SLOT0.connect = packptr16(&chip.phase_modulation);
CH->SLOT1.connect = packptr16(&chip.P_CH[ chan_no ].chanout);
break;
case 1:
/* 1 -> 2 -\
3 -> 4 -+- out */
(CH-3)->SLOT0.connect = packptr16(&chip.phase_modulation);
(CH-3)->SLOT1.connect = packptr16(&chip.P_CH[ chan_no - 3 ].chanout);
CH->SLOT0.connect = packptr16(&chip.phase_modulation);
CH->SLOT1.connect = packptr16(&chip.P_CH[ chan_no ].chanout);
break;
case 2:
/* 1 -----------\
2 -> 3 -> 4 -+- out */
(CH-3)->SLOT0.connect = packptr16(&chip.P_CH[ chan_no - 3 ].chanout);
(CH-3)->SLOT1.connect = packptr16(&chip.phase_modulation2);
CH->SLOT0.connect = packptr16(&chip.phase_modulation);
CH->SLOT1.connect = packptr16(&chip.P_CH[ chan_no ].chanout);
break;
case 3:
/* 1 ------\
2 -> 3 -+- out
4 ------/ */
(CH-3)->SLOT0.connect = packptr16(&chip.P_CH[ chan_no - 3 ].chanout);
(CH-3)->SLOT1.connect = packptr16(&chip.phase_modulation2);
CH->SLOT0.connect = packptr16(&chip.P_CH[ chan_no ].chanout);
CH->SLOT1.connect = packptr16(&chip.P_CH[ chan_no ].chanout);
break;
}
}
else
{
/* 2 operators mode */
CH->SLOT0.connect = packptr16(CH->SLOT0.CON ? &chip.P_CH[(r & 0xf) + ch_offset].chanout : &chip.phase_modulation);
CH->SLOT1.connect = packptr16(&chip.P_CH[(r & 0xf)+ch_offset].chanout);
}
break;
default:
/* 2 operators mode */
CH->SLOT0.connect = packptr16(CH->SLOT0.CON ? &chip.P_CH[(r & 0xf) + ch_offset].chanout : &chip.phase_modulation);
CH->SLOT1.connect = packptr16(&chip.P_CH[(r & 0xf) + ch_offset].chanout);
break;
}
}
else
{
/* OPL2 mode - always 2 operators mode */
CH->SLOT0.connect = packptr16(CH->SLOT0.CON ? &chip.P_CH[(r&0xf)+ch_offset].chanout : &chip.phase_modulation);
CH->SLOT1.connect = packptr16(&chip.P_CH[(r&0xf)+ch_offset].chanout);
}
break;
case 0xe0: /* waveform select */
slot = slot_array[r&0x1f];
if(slot < 0) return;
slot += ch_offset*2;
CH = &chip.P_CH[slot >> 1];
/* store 3-bit value written regardless of current OPL2 or OPL3 mode... (verified on real YMF262) */
v &= 7;
if(slot & 1) CH->SLOT1.waveform_number = v;
else CH->SLOT0.waveform_number = v;
/* ... but select only waveforms 0-3 in OPL2 mode */
if( !chip.OPL3_mode ) v &= 3; /* we're in OPL2 mode */
if(slot & 1) CH->SLOT1.wavetable = v;
else CH->SLOT0.wavetable = v;
break;
}
}
void OPL3ResetChip()
{
uint16_t c;
// eg_cnt = 0;
// noise_rng = 1; /* noise shift register */
memset(&chip, 0, sizeof(chip));
for(c = 0xff ; c >= 0x20 ; c-- ) OPL3WriteReg(c, 0);
for(c = 0x1ff ; c >= 0x120 ; c-- ) OPL3WriteReg(c, 0);
/* reset operator parameters */
for( c = 0 ; c < 9*2 ; c++ )
{
OPL3_CH *CH = &chip.P_CH[c];
CH->SLOT0.state = EG_OFF;
CH->SLOT0.volume = MAX_ATT_INDEX;
CH->SLOT1.state = EG_OFF;
CH->SLOT1.volume = MAX_ATT_INDEX;
}
c = (uint16_t)&chip;
outp(0, (uint8_t)c);
outp(1, (uint8_t)(c>>8));
}
/* YMF262 I/O interface */
void OPL3Write(uint8_t a, uint8_t v)
{
switch(a&3)
{
case 0: /* address port 0 (register set #1) */
chip.address = v;
break;
case 1: /* data port - ignore A1 */
case 3: /* data port - ignore A1 */
// if(chip->UpdateHandler) chip->UpdateHandler(chip->UpdateParam,0);
OPL3WriteReg(chip.address, v);
break;
case 2: /* address port 1 (register set #2) */
if( chip.OPL3_mode ) chip.address = v | 0x100; /* OPL3 mode */
else
{
if( v==5 ) chip.address = v | 0x100; /* in OPL2 mode the only accessible in set #2 is register 0x05 */
else chip.address = v; /* verified range: 0x01, 0x04, 0x20-0xef(set #2 becomes set #1 in opl2 mode) */
}
break;
}
}
#define READY 1
#define QEMPTY 2
int main()
{
uint8_t c;
OPL3ResetChip();
while(1)
{
c = inp(0);
if((c & 3) == READY) OPL3Write((c >> 2) & 3, inp(1));
}
}

122
common/Sound/opl3/fw/YMF262.H Normal file
View File

@@ -0,0 +1,122 @@
// license:GPL-2.0+
// copyright-holders:Jarek Burczynski
#define OPL3_SAMPLE_BITS 16
#define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
#define TL_TAB_LEN (13*2*TL_RES_LEN)
/* sinwave entries */
#define SIN_BITS 10
#define SIN_LEN (1<<SIN_BITS)
#define SIN_MASK (SIN_LEN-1)
#define RATE_STEPS (8)
/* Envelope Generator phases */
#define EG_ATT 4
#define EG_DEC 3
#define EG_SUS 2
#define EG_REL 1
#define EG_OFF 0
#define MAX_ATT_INDEX ((1<<(ENV_BITS-1))-1) /*511*/
#define MIN_ATT_INDEX (0)
/* envelope output entries */
#define ENV_BITS 10
typedef unsigned char uint8_t; /* unsigned 8bit */
typedef unsigned short uint16_t; /* unsigned 16bit */
typedef unsigned long uint32_t; /* unsigned 32bit */
typedef signed char int8_t; /* signed 8bit */
typedef signed short int16_t; /* signed 16bit */
typedef signed long int32_t; /* signed 32bit */
typedef int16_t OPL3SAMPLE;
typedef void (*OPL3_TIMERHANDLER)(void *param,int timer,const uint16_t period);
typedef void (*OPL3_IRQHANDLER)(void *param, int irq);
typedef void (*OPL3_UPDATEHANDLER)(void *param, int min_interval_us);
/* 36 operators, 8 waveforms */
#pragma pack(1)
typedef struct _OPL3_SLOT // 44 bytes
{
uint8_t ar; /* 0 - attack rate: AR<<2 */
uint8_t dr; /* 1 - decay rate: DR<<2 */
uint8_t rr; /* 2 - release rate:RR<<2 */
uint8_t pad1; /* 3 */
/* Phase Generator */
uint32_t Cnt; /* 4 - frequency counter */
uint32_t Incr; /* 8 - frequency counter step */
int16_t op1_out[2]; /* 12 - slot1 output for feedback */
uint8_t TL; /* 16 - total level: TL << 2 */
uint8_t CON; /* 17 - connection (algorithm) type */
/* Envelope Generator */
uint8_t state; /* 18 - phase type */
uint8_t eg_type; /* 19 - bool - percussive/non-percussive mode */
uint16_t AMmask_TLL; /* 20 - bit15 = LFO Amplitude Modulation enable mask, bit 8..0 = adjusted now TL */
int16_t volume; /* 22 - envelope counter */
uint8_t FB; /* 24 - feedback shift value */
uint8_t wavetable; /* 25 */
uint8_t KSR; /* 26 - key scale rate */
uint8_t ksl; /* 27 - keyscale level */
uint8_t ksr; /* 28 - key scale rate: kcode>>KSR */
uint8_t key; /* 29 - 0 = KEY OFF, >0 = KEY ON */
uint16_t mul; /* 30 - multiple: mul_tab[ML] */
uint16_t sl; /* 32 - sustain level: sl_tab[SL] */
uint8_t vib; /* 34 - bool - LFO Phase Modulation enable flag (active high)*/
uint8_t waveform_number; /* 35 */
int16_t connect; /* 36 - slot output pointer */
uint8_t eg_sh_ar; /* 38 - (attack state) */
uint8_t eg_sel_ar; /* 39 - (attack state) */
uint8_t eg_sh_dr; /* 40 - (decay state) */
uint8_t eg_sel_dr; /* 41 - (decay state) */
uint8_t eg_sh_rr; /* 42 - (release state) */
uint8_t eg_sel_rr; /* 43 - (release state) */
} OPL3_SLOT;
typedef struct _OPL3_CH // 96 bytes
{
OPL3_SLOT SLOT0; /* 0 */
uint16_t block_fnum; /* 44 - block+fnum */
int16_t chanout; /* 46 */
/*
there are 12 2-operator channels which can be combined in pairs
to form six 4-operator channel, they are:
0 and 3,
1 and 4,
2 and 5,
9 and 12,
10 and 13,
11 and 14
*/
OPL3_SLOT SLOT1; /* 48 */
uint8_t extended; /* SLOT1+44 - bool - set to 1 if this channel forms up a 4op channel with another channel(only used by first of pair of channels, ie 0,1,2 and 9,10,11) */
uint8_t ksl_base; /* 45 - KeyScaleLevel Base step */
uint8_t kcode; /* 46 - key code (for key scaling) */
uint8_t pad; /* 47 */
} OPL3_CH;
/* OPL3 state */
typedef struct _OPL3
{
OPL3_CH P_CH[18]; /* OPL3 chips have 18 channels */
int16_t phase_modulation; /* 0 - phase modulation input (SLOT 2) */
int16_t phase_modulation2; /* 2 - phase modulation input (SLOT 3 in 4 operator channels) */
uint32_t panA; /* 4 - channels output masks */
uint32_t panB; /* 8 - channels output masks */
/* LFO */
uint8_t lfo_am_depth; /* 12 - bool */
uint8_t lfo_pm_depth_range;/* 13 */
uint8_t OPL3_mode; /* 14 - bool - OPL3 extension enable flag */
uint8_t rhythm; /* 15 - bool - Rhythm mode */
uint16_t address; /* 16 - address register */
uint8_t nts; /* 20 - NTS (note select) */
} OPL3;
void OPL3ResetChip();
void OPL3Write(uint8_t a, uint8_t v);

49
common/Sound/opl3/fw/bin2mem.c Normal file
View File

@@ -0,0 +1,49 @@
#include <stdlib.h>
#include <stdio.h>
int main()
{
int c1,c2,d=1,i;
FILE *in = fopen("opl3.com", "rb");
for(i=0; i<4096; i++)
{
if(i<128)
{
switch(i)
{
case 0: printf("00C3\n"); break;
case 1: printf("0001\n"); break;
case 2: printf("C300\n"); break;
case 3: printf("00FF\n"); break;
case 127: printf("C900\n"); break;
default: printf("0000\n"); break;
}
}
else if(d)
{
c1 = fgetc(in);
if(c1 == -1)
{
d = 0;
c1 = 0;
c2 = 0;
}
else
{
c2 = fgetc(in);
if(c2 == -1)
{
d = 0;
c2 = 0;
}
}
printf("%02X%02X\n", c2&0xff, c1&0xff);
}
else
{
printf("0000\n");
}
}
fclose(in);
}

BIN
common/Sound/opl3/fw/bin2mem.exe Normal file
View File

Binary file not shown.

5
common/Sound/opl3/fw/clean.bat Normal file
View File

@@ -0,0 +1,5 @@
del /q *.as
del /q *.obj
del /q *.map
del /q *.sym
del /q *.bak

7
common/Sound/opl3/opl3.qip Normal file
View File

@@ -0,0 +1,7 @@
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) opl3.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) opl3fm.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) opl3seq.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) compressor.sv]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) NextZ80Reg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) NextZ80CPU.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) NextZ80ALU.v ]

186
common/Sound/opl3/opl3.sv Normal file
View File

@@ -0,0 +1,186 @@
/*
* Copyright (c) 2014, Aleksander Osman
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module opl3
#(
parameter OPLCLK = 64000000 // opl_clk in Hz
)
(
input clk,
input clk_opl,
input rst_n,
output reg irq_n,
input [12:0] period_80us, // from clk
input [1:0] addr,
output [7:0] dout,
input [7:0] din,
input we,
output signed [15:0] sample_l,
output signed [15:0] sample_r
);
//------------------------------------------------------------------------------
wire [7:0] io_readdata = { timer1_overflow | timer2_overflow, timer1_overflow, timer2_overflow, 5'd0 };
assign dout = !addr ? io_readdata : 8'hFF;
//------------------------------------------------------------------------------
reg old_write;
always @(posedge clk) old_write <= we;
wire write = (~old_write & we);
reg [8:0] index;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 0) index <= 0;
else if(~addr[0] && write) index <= {addr[1], din};
end
wire io_write = (addr[0] && write);
wire [7:0] io_writedata = din;
//------------------------------------------------------------------------------ timer 1
reg [7:0] timer1_preset;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 0) timer1_preset <= 0;
else if(io_write && index == 2) timer1_preset <= io_writedata;
end
reg timer1_mask;
reg timer1_active;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 0) {timer1_mask, timer1_active} <= 0;
else if(io_write && index == 4 && ~io_writedata[7]) {timer1_mask, timer1_active} <= {io_writedata[6], io_writedata[0]};
end
wire timer1_pulse;
timer timer1( clk, period_80us, timer1_preset, timer1_active, timer1_pulse );
reg timer1_overflow;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 0) timer1_overflow <= 0;
else begin
if(io_write && index == 4 && io_writedata[7]) timer1_overflow <= 0;
if(timer1_pulse) timer1_overflow <= 1;
end
end
//------------------------------------------------------------------------------ timer 2
reg [7:0] timer2_preset;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 0) timer2_preset <= 0;
else if(io_write && index == 3) timer2_preset <= io_writedata;
end
reg timer2_mask;
reg timer2_active;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 0) {timer2_mask, timer2_active} <= 0;
else if(io_write && index == 4 && ~io_writedata[7]) {timer2_mask, timer2_active} <= {io_writedata[5], io_writedata[1]};
end
wire timer2_pulse;
timer timer2( clk, {period_80us, 2'b00}, timer2_preset, timer2_active, timer2_pulse );
reg timer2_overflow;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 0) timer2_overflow <= 0;
else begin
if(io_write && index == 4 && io_writedata[7]) timer2_overflow <= 0;
if(timer2_pulse) timer2_overflow <= 1;
end
end
//------------------------------------------------------------------------------ IRQ
always @(posedge clk or negedge rst_n) begin
if(rst_n == 0) irq_n <= 1;
else begin
if(io_write && index == 4 && io_writedata[7]) irq_n <= 1;
if(~timer1_mask && timer1_pulse) irq_n <= 0;
if(~timer2_mask && timer2_pulse) irq_n <= 0;
end
end
opl3sw #(OPLCLK) opl3
(
.reset(~rst_n),
.cpu_clk(clk),
.addr(addr),
.din(din),
.wr(write),
.clk(clk_opl),
.left(sample_l),
.right(sample_r)
);
endmodule
module timer
(
input clk,
input [14:0] resolution,
input [7:0] init,
input active,
output reg overflow_pulse
);
always @(posedge clk) begin
reg [7:0] counter = 0;
reg [14:0] sub_counter = 0;
reg old_act;
old_act <= active;
overflow_pulse <= 0;
if(~old_act && active) begin
counter <= init;
sub_counter <= resolution;
end
else if(active) begin
sub_counter <= sub_counter - 1'd1;
if(!sub_counter) begin
sub_counter <= resolution;
counter <= counter + 1'd1;
if(&counter) begin
overflow_pulse <= 1;
counter <= init;
end
end
end
end
endmodule

263
common/Sound/opl3/opl3fm.sv Normal file
View File

@@ -0,0 +1,263 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the Next186 Soc PC project
// http://opencores.org/project,next186
//
// Filename: opl3seq.v
// Description: Part of the Next186 SoC PC project, OPL3
// Version 1.0
// Creation date: 13:55:57 02/27/2017
//
// Author: Nicolae Dumitrache
// e-mail: ndumitrache@opencores.org
//
/////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2017 Nicolae Dumitrache
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
///////////////////////////////////////////////////////////////////////////////////
// Additional Comments:
//
// Port0 (R) = 4'b0000, Addr[1:0], qempty, ready
// Port1 (R) = Value[7:0], advance queue
//
///////////////////////////////////////////////////////////////////////////////////
//
// Improved reset stability and firmware portability by Sorgelig.
//
module opl3sw #(parameter OPLCLK = 50000000)
(
input reset,
// CPU interface
input cpu_clk,
input [1:0] addr,
input [7:0] din,
input wr,
// OPL sequencer
input clk, // 50Mhz (min 45Mhz)
output [15:0] left,
output [15:0] right
);
wire [7:0] ram_dout;
opl3_mem ram
(
.clk(clk),
.addr1(CPU_ADDR[12:0]),
.we1(CPU_MREQ & CPU_WR & CE),
.data_in1(CPU_DOUT),
.data_out1(ram_dout),
.addr2(OPL3Struct_base+seq_addr),
.we2(seq_wr),
.data_in2(seq_wdata),
.data_out2(seq_rdata)
);
wire [9:0] qdata;
wire qempty;
// show ahead fifo
opl3_fifo in_queue
(
.aclr(reset),
.wrclk(cpu_clk),
.data({addr, din}),
.wrreq(wr),
.rdclk(clk),
.q(qdata),
.rdreq(CE && CPU_IORQ && !CPU_WR && CPU_ADDR[0]),
.rdempty(qempty)
);
reg stb44100;
always @(posedge clk) begin
integer cnt;
localparam RATE = (OPLCLK/44100)-1;
cnt <= cnt+1;
if(cnt == RATE) cnt <= 0;
stb44100 <= !cnt;
end
wire seq_wr;
wire [11:0] seq_addr;
wire [15:0] seq_rdata;
wire [15:0] seq_wdata;
wire ready;
reg [11:0] OPL3Struct_base = 0;
reg seq_reset_n = 0;
always @(posedge clk) begin
if(reset) seq_reset_n <= 0;
if(CPU_IORQ & CPU_WR & CE) begin
if(CPU_ADDR[0]) {seq_reset_n, OPL3Struct_base[11:7]} <= {1'b1, CPU_DOUT[4:0]};
else OPL3Struct_base[6:0] <= CPU_DOUT[7:1];
end
end
opl3seq opl3seq
(
.clk(clk),
.reset(~seq_reset_n),
.rd(stb44100),
.A(A),
.B(B),
.ready(ready),
.ram_wr(seq_wr),
.ram_addr(seq_addr),
.ram_rdata(seq_rdata),
.ram_wdata(seq_wdata)
);
wire [15:0] A,B;
compressor compressor
(
clk,
stb44100,
A[15:4], B[15:4],
left, right
);
wire [15:0] CPU_ADDR;
wire [7:0] CPU_DOUT;
wire CPU_WR;
wire CPU_MREQ;
wire CPU_IORQ;
NextZ80 Z80
(
.DI(~CPU_IORQ ? ram_dout : CPU_ADDR[0] ? qdata[7:0] : {4'b0000, qdata[9:8], qempty, ready}),
.DO(CPU_DOUT),
.ADDR(CPU_ADDR),
.WR(CPU_WR),
.MREQ(CPU_MREQ),
.IORQ(CPU_IORQ),
.HALT(),
.M1(),
.CLK(clk),
.RESET(reset),
.INT(0),
.NMI(0),
.WAIT(!CE)
);
reg CE = 0;
always @(posedge clk) CE <= !CE;
endmodule
module opl3_mem
#(
parameter
DATA_WIDTH1 = 8,
ADDRESS_WIDTH1 = 13,
ADDRESS_WIDTH2 = 12,
INIT_FILE = "opl3prg.mem"
)
(
input clk,
input we1,
input [ADDRESS_WIDTH1-1:0] addr1,
input [DATA_WIDTH1-1:0] data_in1,
output reg [DATA_WIDTH1-1:0] data_out1,
input we2,
input [ADDRESS_WIDTH2-1:0] addr2,
input [DATA_WIDTH2-1:0] data_in2,
output reg [DATA_WIDTH2-1:0] data_out2
);
localparam RATIO = 1 << (ADDRESS_WIDTH1 - ADDRESS_WIDTH2);
localparam DATA_WIDTH2 = DATA_WIDTH1 * RATIO;
localparam RAM_DEPTH = 1 << ADDRESS_WIDTH2;
reg [RATIO-1:0] [DATA_WIDTH1-1:0] ram[0:RAM_DEPTH-1];
initial $readmemh(INIT_FILE, ram);
// Port A
always@(posedge clk) if(we1) ram[addr1 / RATIO][addr1 % RATIO] = data_in1;
always@(posedge clk) data_out1 <= ram[addr1 / RATIO][addr1 % RATIO];
// port B
always@(posedge clk) if(we2) ram[addr2] = data_in2;
always@(posedge clk) data_out2 <= ram[addr2];
endmodule
module opl3_fifo
(
input aclr,
input [9:0] data,
input rdclk,
input rdreq,
input wrclk,
input wrreq,
output [9:0] q,
output rdempty
);
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (q),
.rdempty (rdempty),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 1024,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 10,
dcfifo_component.lpm_widthu = 10,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "ON",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 5;
endmodule

4096
common/Sound/opl3/opl3prg.mem Normal file
View File

File diff suppressed because it is too large Load Diff

482
common/Sound/opl3/opl3seq.sv Normal file
View File

@@ -0,0 +1,482 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the Next186 Soc PC project
// http://opencores.org/project,next186
//
// Filename: opl3seq.v
// Description: Part of the Next186 SoC PC project, OPL3 Sequencer
// Version 1.0
// Creation date: 13:55:57 02/27/2017
//
// Author: Nicolae Dumitrache
// e-mail: ndumitrache@opencores.org
//
/////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2017 Nicolae Dumitrache
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
///////////////////////////////////////////////////////////////////////////////////
// Additional Comments:
//
// It shares OPL3 structure (~1.7KB DP RAM) with the main processor. It drives 36 operators at 44100Hz, with at least 45Mhz clock
///////////////////////////////////////////////////////////////////////////////////
// altera message_off 10030
`define LFO_AM_TAB_ELEMENTS 210
`define phase_modulation_o 0 // CH18
`define panA_o 6'd4 // CH18
`define panB_o 6'd8 // CH18
`define lfo_am_depth_o 12 // CH18
`define block_fnum_o 44 // SLOT0
`define chanout_o 6'd46 // SLOT0
`define Cnt_o 6'd4
`define Incr_o 6'd8
`define op1_out_o 6'd12
`define state_o 18
`define AMmask_o 20
`define volume_o 22
`define FB_o 24
`define mul_o 30
`define sl_o 32
`define vib_o 34
`define connect_o 36
`define eg_sh_ar_o 38
`define eg_sh_dr_o 40
`define eg_sh_rr_o 42
module opl3seq
(
input clk,
input reset,
input rd, // clk synchronous pulse, read only while <ready> == 1
output reg [15:0] A,
output reg [15:0] B,
output reg ready,
output reg ram_wr,
output [11:0] ram_addr,
input [15:0] ram_rdata,
output reg [15:0] ram_wdata
);
reg [13:0]lfo_am_cnt = 0;
reg [4:0]r_lfo_am_cnt = 0;
wire [13:0]lfo_am_cnt1 = lfo_am_cnt + 1'b1;
reg [9:0]lfo_pm_cnt = 0;
reg [4:0]LFO_AM; // unsigned
reg [3:0]LFO_PM = 0; // unsigned
reg [5:0]STATE = 0;
reg [5:0]nextSTATE;
reg [5:0]RET;
reg [5:0]ram_offset; // OPL3Struct_base + (CHindex*96 + OPindex*48 + offset)
reg [4:0]ram_CHindex;
reg [4:0]s_ram_CHindex;
wire s_ram_CHindex17 = s_ram_CHindex == 17;
wire s_ram_CHindex18 = s_ram_CHindex == 18;
wire [4:0]s_ram_CHindex1 = s_ram_CHindex + 1'b1;
reg ram_OPindex;
reg s_ram_OPindex;
reg [15:0]ram_rdata_lo;
reg [15:0]eg_cnt = 0;
// reg [22:0]noise_rng = 1;
reg [9:0]env;
reg [12:0]sinaddr;
reg [12:0]r_sinaddr;
wire [12:0]op_calc1;
wire signed [15:0]op_calc = {{3{op_calc1[12]}}, op_calc1};
reg [15:0]tmp1;
wire [13:0]outshift1 = $signed(tmp1[13:0]) >>> ram_rdata[3:0];
wire [9:0]outshift = |ram_rdata[3:0] ? outshift1[9:0] : 10'b0000000000;
reg [17:0]pan;
reg signed [18:0]rAcc;
wire [15:0]limAcc = rAcc > 32767 ? 16'h7fff : rAcc < -32768 ? 16'h8000 : rAcc[15:0]; // (~|rAcc[18:15] | &rAcc[18:15]) ? rAcc[15:0] : {rAcc[18], {15{!rAcc[18]}}};
reg [11:0]phmask;// = (1'b1 << ram_rdata[3:0]) - 1'b1;
wire phtest = ~|(eg_cnt & phmask);
reg cond;
wire [15:0]eg_inc1 = eg_cnt >> ram_rdata[3:0];
wire [6:0]eg_inc = ram_rdata[14:8] + eg_inc1[2:0];
reg [2:0]r_eg_inc;
wire [9:0]volume_attack1 = $signed(~ram_rdata[9:0]) >>> (~r_eg_inc[1:0]);
wire [9:0]volume_attack = {1'b0, ram_rdata[8:0]} + (r_eg_inc[2] ? 10'h000 : volume_attack1);
reg [9:0]r_volume;
wire [2:0]exp_r_eg_inc = 3'b1 << r_eg_inc;
wire [9:0]volume_dsr = ram_rdata[8:0] + exp_r_eg_inc; // new volume for decay/sustain/release
reg signed [3:0]lfo_fn_table_index_offset;
reg [11:0]inc_hi;
reg [15:0]inc_lo;
reg carry = 1'b0;
reg cy;
reg [2:0]phase;
wire [25:0]mul1 = tmp1[9:0] * ram_rdata_lo;
// tmp1 adder
reg [3:0]tmp1op;
reg [15:0]tmp1op1;
reg [15:0]tmp1op2;
// .addrb(OPL3Struct_offset + {1'b1, ram_CHindex, ram_OPindex, ram_offset[5:1]})
assign ram_addr = (ram_OPindex ? 12'd24 : 12'd0) + {ram_CHindex + {ram_CHindex, ram_offset[5]}, ram_offset[4:1]};
wire [4:0] lfo_am_table [`LFO_AM_TAB_ELEMENTS] = '{
0,0,0,0,0,0,0, 1,1,1,1, 2,2,2,2, 3,3,3,3, 4,4,4,4, 5,5,5,5, 6,6,6,6, 7,7,7,7, 8,8,8,8, 9,9,9,9, 10,10,10,10, 11,11,11,11, 12,12,12,12, 13,13,13,13, 14,14,14,14,
15,15,15,15, 16,16,16,16, 17,17,17,17, 18,18,18,18, 19,19,19,19, 20,20,20,20, 21,21,21,21, 22,22,22,22, 23,23,23,23, 24,24,24,24, 25,25,25,25, 26,26,26, 25,25,25,25,
24,24,24,24, 23,23,23,23, 22,22,22,22, 21,21,21,21, 20,20,20,20, 19,19,19,19, 18,18,18,18, 17,17,17,17, 16,16,16,16, 15,15,15,15, 14,14,14,14, 13,13,13,13, 12,12,12,12,
11,11,11,11, 10,10,10,10, 9,9,9,9, 8,8,8,8, 7,7,7,7, 6,6,6,6, 5,5,5,5, 4,4,4,4, 3,3,3,3, 2,2,2,2, 1,1,1,1
};
wire signed [3:0]lfo_pm_table[128] = '{
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,-1, 0, 0, 0, 1, 0, 0, 0,-1, 0, 0, 0, 2, 1, 0,-1,-2,-1, 0, 1, 1, 0, 0, 0,-1, 0, 0, 0, 3, 1, 0,-1,-3,-1, 0, 1,
2, 1, 0,-1,-2,-1, 0, 1, 4, 2, 0,-2,-4,-2, 0, 2, 2, 1, 0,-1,-2,-1, 0, 1, 5, 2, 0,-2,-5,-2, 0, 2, 3, 1, 0,-1,-3,-1, 0, 1, 6, 3, 0,-3,-6,-3, 0, 3, 3, 1, 0,-1,-3,-1, 0, 1, 7, 3, 0,-3,-7,-3, 0, 3
};
wire [2:0]eg_inc_tab[120] = '{
4,0, 4,0, 4,0, 4,0, 4,0, 4,0, 0,0, 4,0, 4,0, 0,0, 4,0, 0,0, 4,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,1, 0,0, 0,2, 0,1, 0,1, 0,1, 0,1,
0,1, 1,1, 0,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,2, 1,1, 1,2, 1,2, 1,2, 1,2, 1,2, 1,2, 2,2, 1,2, 2,2, 2,2, 2,2, 2,2, 2,2, 3,3, 3,3, 3,3, 3,3, 4,4, 4,4, 4,4, 4,4
}; // log tablle, 4 = log(0)
sampler sampler_inst
(
.clk(clk),
.index(r_sinaddr),
.ampl(env[8:0]),
.sample(op_calc1)
);
always @(posedge clk) begin
STATE <= nextSTATE;
s_ram_CHindex <= ram_CHindex;
s_ram_OPindex <= ram_OPindex;
r_sinaddr <= sinaddr;
r_lfo_am_cnt <= lfo_am_table[lfo_am_cnt[13:6]];
ram_rdata_lo <= ram_rdata;
r_eg_inc <= eg_inc_tab[eg_inc];
lfo_fn_table_index_offset <= lfo_pm_table[{ram_rdata[9:7], LFO_PM}]; //34
{carry, tmp1} <= tmp1op1 + tmp1op2 + cy;
pan <= pan >> 1;
if(pan[0]) rAcc <= rAcc + {{3{ram_rdata[15]}}, ram_rdata};
if(reset) STATE <= 0;
else
case(STATE)
0: begin
if(lfo_am_cnt1[13:6] == `LFO_AM_TAB_ELEMENTS) lfo_am_cnt <= 14'h0000;
else lfo_am_cnt <= lfo_am_cnt1;
{LFO_PM[2:0], lfo_pm_cnt} <= {LFO_PM[2:0], lfo_pm_cnt} + 1'b1;
eg_cnt <= eg_cnt + 1'b1;
// noise_rng <= {noise_rng[0], noise_rng[22:1]} ^ (noise_rng[0] ? 9'h181 : 9'h000);
end
1: begin
LFO_AM <= r_lfo_am_cnt >> {!ram_rdata[0], 1'b0};
LFO_PM[3] <= ram_rdata[11];
RET <= 3;
end
2: s_ram_CHindex <= s_ram_CHindex17 ? 5'd0 : s_ram_CHindex1;
3: s_ram_CHindex <= s_ram_CHindex;
7: RET <= 8;
8: begin
s_ram_CHindex <= s_ram_CHindex;
RET <= 18;
end
10: s_ram_OPindex <= 1'b1;
13: env <= ram_rdata_lo[9:0] + ram_rdata[8:0] + (ram_rdata_lo[15] ? LFO_AM : 10'd0); // env = volume_calc(SLOT1);
15: {s_ram_CHindex, s_ram_OPindex} <= {s_ram_CHindex, s_ram_OPindex};
17: {s_ram_CHindex, s_ram_OPindex} <= {s_ram_CHindex, s_ram_OPindex};
18: s_ram_CHindex <= s_ram_CHindex1;
20: begin
pan <= {ram_rdata[1:0], ram_rdata_lo};
s_ram_CHindex <= 1;
rAcc <= 0;
end
21: s_ram_CHindex <= s_ram_CHindex18 ? s_ram_CHindex : s_ram_CHindex1;
22: A <= limAcc;
23: begin
pan <= {ram_rdata[1:0], ram_rdata_lo};
s_ram_CHindex <= 1;
rAcc <= 0;
end
24: s_ram_CHindex <= s_ram_CHindex18 ? 5'd0 : s_ram_CHindex1;
25: B <= limAcc;
// advance
27: cond <= phtest;
28: r_volume <= tmp1[2] ? volume_attack : volume_dsr;
29: if(r_volume[9]) r_volume <= (tmp1[2:0] < 3) ? 10'd511 : 10'd0;
// phase gen
32: inc_lo <= ram_rdata;
33: begin
inc_hi <= ram_rdata[11:0];
s_ram_OPindex <= s_ram_OPindex;
end
35: cond <= |lfo_fn_table_index_offset;
36: if(cond && ram_rdata[0]) {inc_hi, inc_lo} <= {mul1, 2'b00} >> ~tmp1[12:10];
37,38: inc_lo <= {4'b0000, inc_hi};
39: begin
s_ram_OPindex <= !s_ram_OPindex;
if(s_ram_OPindex) s_ram_CHindex <= s_ram_CHindex1;
end
endcase
end
always @(*) begin
ram_offset = 6'b000000;
ram_CHindex = s_ram_CHindex;
ram_OPindex = s_ram_OPindex;
ram_wdata = 16'h0000;
ram_wr = 1'b0;
nextSTATE = STATE + 1'b1;
sinaddr = r_sinaddr;
tmp1op = 4'b1111; // tmp1 <= tmp1, carry <= 0
cy = 1'b0;
ready = 1'b0;
case(STATE)
0: begin
ram_offset = `lfo_am_depth_o;
ram_CHindex = 18;
ram_OPindex = 0;
end
1: ram_CHindex = 0;
2: begin
ram_offset = `chanout_o;
ram_wr = 1'b1;
nextSTATE = s_ram_CHindex17 ? 6'd3 : 6'd2;
end
// chan_calc
3: begin // chip.phase_modulation = 0;
ram_CHindex = 18;
ram_offset = `phase_modulation_o;
ram_wr = 1'b1;
end
4: ram_offset = `op1_out_o; // op1_out[0]
5: ram_offset = `op1_out_o+6'd2; // op1_out[1]
6: begin
ram_offset = `FB_o; // read {FB, wavetable, x, x}
tmp1op = 4'b0000; // tmp1 <= ram_rdata + ram_rdata_lo; // out = SLOT1->op1_out[0] + SLOT1->op1_out[1];
end
7: begin // SLOT->op1_out[0] = SLOT->op1_out[1];
ram_offset = `op1_out_o;
ram_wdata = ram_rdata_lo;
ram_wr = 1'b1;
sinaddr = {ram_rdata[10:8], outshift}; // wavetable, out>>FB
nextSTATE = 11; // call
end
8: begin
ram_CHindex = 18;
ram_offset = `phase_modulation_o;
end
9: begin
ram_offset = `FB_o; // read {FB, wavetable, x, x}
ram_OPindex = 1;
end
10: begin // SLOT->op1_out[1] = op_calc
ram_offset = `op1_out_o+6'd2;
ram_OPindex = 0;
ram_wdata = tmp1;
ram_wr = 1'b1;
sinaddr = {ram_rdata[10:8], ram_rdata_lo[9:0]}; // wavetable, phase_modulation
end
11: ram_offset = `AMmask_o; // read {TLL, AMmask}
12: ram_offset = `volume_o; // read volume[15:0]
13: ram_offset = `Cnt_o+6'd2;
14: begin
ram_offset = `connect_o;
sinaddr[9:0] = sinaddr[9:0] + ram_rdata[9:0];
if(env >= 416) nextSTATE = RET;
end
15: {ram_CHindex, ram_OPindex, ram_offset} = ram_rdata[11:0];
16: ram_offset = `connect_o;
17: begin
{ram_CHindex, ram_OPindex, ram_offset} = ram_rdata[11:0];
ram_wdata = ram_rdata_lo + op_calc;//tmp1;
ram_wr = 1'b1;
nextSTATE = RET;
tmp1op = 4'b1110; // tmp1 <= op_calc;
end
18: begin
ram_offset = `panA_o;
ram_OPindex = 0;
ram_CHindex = 18;
nextSTATE = s_ram_CHindex17 ? 6'd19 : 6'd3;
end
19: ram_offset = `panA_o+6'd2;
20: begin
ram_offset = `chanout_o;
ram_CHindex = 0;
end
21: begin
ram_offset = s_ram_CHindex18 ? `panB_o : `chanout_o;
nextSTATE = s_ram_CHindex18 ? 6'd22 : 6'd21;
end
22: ram_offset = `panB_o+6'd2;
23: begin
ram_offset = `chanout_o;
ram_CHindex = 0;
end
24: begin
ram_offset = `chanout_o;
nextSTATE = s_ram_CHindex18 ? 6'd25 : 6'd24;
end
// envelope
25: ram_offset = `state_o;
26: begin
case(ram_rdata[2:0])
3'd1: ram_offset = `eg_sh_rr_o; // release phase
3'd2: begin // sustain phase
ram_offset = `eg_sh_rr_o;
if(ram_rdata[8]) nextSTATE = 31; // if (!op->eg_type)
end
3'd3: ram_offset = `eg_sh_dr_o; // decay phase
3'd4: ram_offset = `eg_sh_ar_o; // attack phase
default: nextSTATE = 31;
endcase
tmp1op = 4'b1100; // tmp1 <= ram_rdata; // {eg_type, state}
end
27: ram_offset = `volume_o;
28: ram_offset = `sl_o;
29: begin
ram_offset = `state_o;
ram_wdata = tmp1;
case(tmp1[1:0])
2'b00: if(r_volume[9]) ram_wdata[2:0] = 3'd3; // attack
2'b11: if(r_volume >= {1'b0, ram_rdata[8:0]}) ram_wdata[2:0] = 3'd2; // decay
2'b10:; // sustain
2'b01: if(r_volume[9]) ram_wdata[2:0] = 3'd0; // release
endcase
ram_wr = cond;
end
30: begin
ram_offset = `volume_o;
ram_wdata[9:0] = r_volume;
ram_wr = cond;
end
// phase gen
31: ram_offset = `Incr_o;
32: ram_offset = `Incr_o+6'd2;
33: begin
ram_offset = `block_fnum_o;
ram_OPindex = 0;
end
34: ram_offset = `mul_o;
35: begin
ram_offset = `vib_o;
tmp1op = 4'b0001; //tmp1 <= ram_rdata_lo + lfo_fn_table_index_offset;
end
36: ram_offset = `Cnt_o;
37: begin
ram_offset = `Cnt_o+6'd2;
tmp1op = 4'b0100; //{carry, tmp1} <= inc_lo + ram_rdata;
end
38: begin
ram_offset = `Cnt_o;
ram_wdata = tmp1;
ram_wr = 1'b1;
tmp1op = 4'b0100; //{carry, tmp1} <= inc_lo + ram_rdata + carry;
cy = carry;
end
39: begin
ram_offset = `Cnt_o+6'd2;
ram_wdata = tmp1;
ram_wr = 1'b1;
if(!(s_ram_CHindex17 && s_ram_OPindex)) nextSTATE = 6'd25;
end
default: begin
ready = 1'b1;
nextSTATE = rd ? 6'd0 : 6'd40;
end
endcase
case(tmp1op[1:0])
2'b00: tmp1op1 = ram_rdata;
2'b01: tmp1op1 = lfo_fn_table_index_offset;
2'b10: tmp1op1 = op_calc;
2'b11: tmp1op1 = tmp1;
endcase
case(tmp1op[3:2])
2'b00: tmp1op2 = ram_rdata_lo;
2'b01: tmp1op2 = inc_lo;
default: tmp1op2 = 16'h0000;
endcase
case(ram_rdata[3:0]) // ((1 << ram_rdata[3:0]) - 1)[11:0]
4'h0: phmask = 12'h000;
4'h1: phmask = 12'h001;
4'h2: phmask = 12'h003;
4'h3: phmask = 12'h007;
4'h4: phmask = 12'h00f;
4'h5: phmask = 12'h01f;
4'h6: phmask = 12'h03f;
4'h7: phmask = 12'h07f;
4'h8: phmask = 12'h0ff;
4'h9: phmask = 12'h1ff;
4'ha: phmask = 12'h3ff;
4'hb: phmask = 12'h7ff;
default: phmask = 12'hfff;
endcase
end
endmodule
module sampler
(
input clk,
input [12:0] index,
input [8:0] ampl,
output [12:0] sample
);
reg [15:0] sin_tab[8191:0];
initial $readmemh("sin_tab_full.mem", sin_tab);
reg [15:0] exp_tab[6655:0];
initial $readmemh("exp_tab.mem", exp_tab);
reg [15:0] logsin;
wire [13:0] ilog = logsin[13:0] + {ampl, 4'b0000};
reg log_rng;
reg [15:0] isample;
assign sample = log_rng ? isample[12:0] : 13'd0;
always @(posedge clk) begin
logsin <= sin_tab[index];
log_rng <= ilog < 6656;
isample <= exp_tab[ilog[12:0]];
end
endmodule

8192
common/Sound/opl3/sin_tab_full.mem Normal file
View File

File diff suppressed because it is too large Load Diff

0
common/Sound/sn76489/pll_mist.qip Normal file
View File

6
common/Sound/sn76489/sn76489.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sn76489_top.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sn76489_attenuator.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sn76489_clock_div.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sn76489_latch_ctrl.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sn76489_noise.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sn76489_tone.vhd]