mirror of
https://github.com/Gehstock/Mist_FPGA.git
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Moon Patrol: sync sound board with Traverse USA
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@@ -27,11 +27,11 @@ use ieee.numeric_std.all;
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entity moon_patrol_sound_board is
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port(
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clock_E : in std_logic; -- 3.58 Mhz/4
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reset : in std_logic;
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areset : in std_logic;
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select_sound : in std_logic_vector(7 downto 0);
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audio_out : out std_logic_vector(11 downto 0);
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dbg_cpu_addr : out std_logic_vector(15 downto 0)
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);
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end moon_patrol_sound_board;
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@@ -65,6 +65,9 @@ architecture struct of moon_patrol_sound_board is
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);
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end component;
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signal reset : std_logic := '1';
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signal reset_cnt : integer range 0 to 1000000 := 1000000;
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signal cpu_addr : std_logic_vector(15 downto 0);
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signal cpu_di : std_logic_vector( 7 downto 0);
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signal cpu_do : std_logic_vector( 7 downto 0);
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@@ -112,10 +115,10 @@ architecture struct of moon_patrol_sound_board is
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signal adpcm_we : std_logic;
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signal adpcm_0_di : std_logic_vector(3 downto 0);
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signal select_sound_7r : std_logic;
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signal select_sound_r : std_logic_vector(7 downto 0);
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signal audio : std_logic_vector(12 downto 0);
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type t_step_size is array(0 to 48) of integer range 0 to 1552;
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constant step_size : t_step_size := (
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16, 17, 19, 21, 23, 25, 28, 31,
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@@ -175,14 +178,29 @@ cpu_di <=
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port2_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
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rom_do when rom_cs = '1' else X"55";
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process (clock_E)
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begin
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if rising_edge(clock_E) then
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reset <= '0';
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if reset_cnt /= 0 then
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reset_cnt <= reset_cnt - 1;
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reset <= '1';
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end if;
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if areset = '1' then
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reset_cnt <= 1000000;
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end if;
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end if;
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end process;
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-- irq to cpu
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process (reset, clock_E)
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begin
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if reset='1' then
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cpu_irq <= '0';
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select_sound_r(7) <= '1';
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elsif rising_edge(clock_E) then
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select_sound_7r <= select_sound(7);
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if select_sound_7r = '0' then
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select_sound_r <= select_sound;
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if select_sound_r(7) = '0' then
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cpu_irq <= '1';
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end if;
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if irqraz_we = '1' then
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@@ -334,27 +352,17 @@ port map(
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data => rom_do
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);
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-- cpu wram
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cpu_ram : entity work.spram
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generic map( widthad_a => 7)
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port map(
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clock => clock_E,
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address => cpu_addr(6 downto 0),
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data => cpu_do,
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wren => wram_we,
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q => wram_do
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clock => clock_E,
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wren => wram_we,
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address => cpu_addr(6 downto 0),
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data => cpu_do,
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q => wram_do
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);
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-- cpu wram
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--cpu_ram : entity work.gen_ram
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--generic map( width_a => 8, aWidth => 7)
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--port map(
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-- clk => clock_div(0), -- 3p58/2
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-- we => wram_we,
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-- addr => cpu_addr(6 downto 0),
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-- d => cpu_do,
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-- q => wram_do
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--);
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ay83910_inst1: YM2149
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port map (
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CLK => clock_E,
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@@ -375,7 +383,7 @@ port map(
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ACTIVE => open,
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IOA_in => select_sound,
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IOA_in => select_sound_r,
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IOA_out => open,
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IOB_in => (others => '0'),
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@@ -226,7 +226,7 @@ u_keyboard : keyboard
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moon_patrol_sound_board : entity work.moon_patrol_sound_board
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port map(
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clock_E => clk_aud,
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reset => rst_aud,
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areset => rst_aud,
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select_sound => sound_data,
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audio_out => audio_out,
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dbg_cpu_addr => open
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@@ -157,7 +157,7 @@ begin
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process (clk_sys, rst_sys) begin
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if rst_sys = '1' then
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sound_data_o <= X"FF";
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sound_data_o <= X"00";
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elsif rising_edge(clk_sys) then
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if cpu_clk_en = '1' and cpu_mem_wr = '1' and snd_cs = '1' then
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sound_data_o <= cpu_d_o;
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