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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-02-03 07:10:20 +00:00

Moon Patrol: sync sound board with Traverse USA

This commit is contained in:
Gyorgy Szombathelyi
2019-06-05 22:44:11 +02:00
parent 41da646d9c
commit 69e9031717
3 changed files with 34 additions and 26 deletions

View File

@@ -27,11 +27,11 @@ use ieee.numeric_std.all;
entity moon_patrol_sound_board is
port(
clock_E : in std_logic; -- 3.58 Mhz/4
reset : in std_logic;
areset : in std_logic;
select_sound : in std_logic_vector(7 downto 0);
audio_out : out std_logic_vector(11 downto 0);
dbg_cpu_addr : out std_logic_vector(15 downto 0)
);
end moon_patrol_sound_board;
@@ -65,6 +65,9 @@ architecture struct of moon_patrol_sound_board is
);
end component;
signal reset : std_logic := '1';
signal reset_cnt : integer range 0 to 1000000 := 1000000;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0);
@@ -112,10 +115,10 @@ architecture struct of moon_patrol_sound_board is
signal adpcm_we : std_logic;
signal adpcm_0_di : std_logic_vector(3 downto 0);
signal select_sound_7r : std_logic;
signal select_sound_r : std_logic_vector(7 downto 0);
signal audio : std_logic_vector(12 downto 0);
type t_step_size is array(0 to 48) of integer range 0 to 1552;
constant step_size : t_step_size := (
16, 17, 19, 21, 23, 25, 28, 31,
@@ -175,14 +178,29 @@ cpu_di <=
port2_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
rom_do when rom_cs = '1' else X"55";
process (clock_E)
begin
if rising_edge(clock_E) then
reset <= '0';
if reset_cnt /= 0 then
reset_cnt <= reset_cnt - 1;
reset <= '1';
end if;
if areset = '1' then
reset_cnt <= 1000000;
end if;
end if;
end process;
-- irq to cpu
process (reset, clock_E)
begin
if reset='1' then
cpu_irq <= '0';
select_sound_r(7) <= '1';
elsif rising_edge(clock_E) then
select_sound_7r <= select_sound(7);
if select_sound_7r = '0' then
select_sound_r <= select_sound;
if select_sound_r(7) = '0' then
cpu_irq <= '1';
end if;
if irqraz_we = '1' then
@@ -334,27 +352,17 @@ port map(
data => rom_do
);
-- cpu wram
cpu_ram : entity work.spram
generic map( widthad_a => 7)
port map(
clock => clock_E,
address => cpu_addr(6 downto 0),
data => cpu_do,
wren => wram_we,
q => wram_do
clock => clock_E,
wren => wram_we,
address => cpu_addr(6 downto 0),
data => cpu_do,
q => wram_do
);
-- cpu wram
--cpu_ram : entity work.gen_ram
--generic map( width_a => 8, aWidth => 7)
--port map(
-- clk => clock_div(0), -- 3p58/2
-- we => wram_we,
-- addr => cpu_addr(6 downto 0),
-- d => cpu_do,
-- q => wram_do
--);
ay83910_inst1: YM2149
port map (
CLK => clock_E,
@@ -375,7 +383,7 @@ port map(
ACTIVE => open,
IOA_in => select_sound,
IOA_in => select_sound_r,
IOA_out => open,
IOB_in => (others => '0'),

View File

@@ -226,7 +226,7 @@ u_keyboard : keyboard
moon_patrol_sound_board : entity work.moon_patrol_sound_board
port map(
clock_E => clk_aud,
reset => rst_aud,
areset => rst_aud,
select_sound => sound_data,
audio_out => audio_out,
dbg_cpu_addr => open

View File

@@ -157,7 +157,7 @@ begin
process (clk_sys, rst_sys) begin
if rst_sys = '1' then
sound_data_o <= X"FF";
sound_data_o <= X"00";
elsif rising_edge(clk_sys) then
if cpu_clk_en = '1' and cpu_mem_wr = '1' and snd_cs = '1' then
sound_data_o <= cpu_d_o;