Merge pull request #83 from gyurco/loderunner

IremM62 - 90% ready
2026-04-09 14:13:25 +00:00 · 2020-03-13 21:39:43 +01:00
parent 150c7377fd 1320b05a40
commit 6cf1b592b9
112 changed files with 5715 additions and 14577 deletions
--- a/Hardware/LodeRunner_MiST/LodeRunner_MiST.qpf
+++ b/Hardware/LodeRunner_MiST/LodeRunner_MiST.qpf
@@ -27,4 +27,4 @@ DATE = "23:49:02  July 13, 2012"

 # Revisions

-PROJECT_REVISION = "LodeRunner_MiST"
+PROJECT_REVISION = "IremM62"
--- a/Hardware/LodeRunner_MiST/LodeRunner_MiST.qsf
+++ b/Hardware/LodeRunner_MiST/LodeRunner_MiST.qsf
@@ -25,7 +25,7 @@
 # Notes:
 #
 # 1) The default values for assignments are stored in the file:
-#		LodeRunner_MiST_assignment_defaults.qdf
+#		IremM62_MiST_assignment_defaults.qdf
 #    If this file doesn't exist, see file:
 #		assignment_defaults.qdf
 #
@@ -41,46 +41,9 @@
 # ========================
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
 set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/LodeRunner_MiST.sv
-set_global_assignment -name VHDL_FILE rtl/target_top.vhd
-set_global_assignment -name VHDL_FILE rtl/platform_variant_pkg.vhd
-set_global_assignment -name VHDL_FILE rtl/platform_pkg.vhd
-set_global_assignment -name VHDL_FILE rtl/platform.vhd
-set_global_assignment -name VHDL_FILE rtl/pace_pkg_body.vhd
-set_global_assignment -name VHDL_FILE rtl/pace_pkg.vhd
-set_global_assignment -name VHDL_FILE rtl/pace.vhd
-set_global_assignment -name VHDL_FILE rtl/Graphics.VHD
-set_global_assignment -name VHDL_FILE rtl/video_mixer.vhd
-set_global_assignment -name VHDL_FILE rtl/video_controller_pkg_body.vhd
-set_global_assignment -name VHDL_FILE rtl/video_controller_pkg.vhd
-set_global_assignment -name VHDL_FILE rtl/video_controller.vhd
-set_global_assignment -name VHDL_FILE rtl/tilemapctl_e.vhd
-set_global_assignment -name VHDL_FILE rtl/tilemapctl.vhd
-set_global_assignment -name VHDL_FILE rtl/bitmapctl_e.vhd
-set_global_assignment -name VHDL_FILE rtl/spritereg.vhd
-set_global_assignment -name VHDL_FILE rtl/spritectl.vhd
-set_global_assignment -name VHDL_FILE rtl/sprite_pkg_body.vhd
-set_global_assignment -name VHDL_FILE rtl/sprite_pkg.vhd
-set_global_assignment -name VHDL_FILE rtl/sprite_array.vhd
-set_global_assignment -name VHDL_FILE rtl/Inputs.VHD
-set_global_assignment -name VHDL_FILE rtl/input_mapper.vhd
-set_global_assignment -name VHDL_FILE rtl/dprom_2r.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/sprom.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/clk_div.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
-set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu68.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
-set_global_assignment -name VHDL_FILE rtl/Sound_Board.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/ldrun/snd_prg.vhd
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
-set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
-set_global_assignment -name VHDL_FILE ../../../common/CPU/T80/Z80.vhd

 # Pin & Location Assignments
 # ==========================
@@ -153,7 +116,6 @@ set_location_assignment PIN_66 -to SDRAM_nWE
 set_location_assignment PIN_59 -to SDRAM_nCS
 set_location_assignment PIN_33 -to SDRAM_CKE
 set_location_assignment PIN_43 -to SDRAM_CLK
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"

 # Classic Timing Assignments
 # ==========================
@@ -164,11 +126,11 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
 # Analysis & Synthesis Assignments
 # ================================
 set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY LodeRunner_MiST
+set_global_assignment -name TOP_LEVEL_ENTITY IremM62_MiST
 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
 set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
 set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
 set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE ON
 set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
@@ -194,7 +156,7 @@ set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULA
 set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
 set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"

 # Assembler Assignments
 # =====================
@@ -204,7 +166,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
 # SignalTap II Assignments
 # ========================
 set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE output_files/mcr3.stp
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/snd.stp

 # Power Estimation Assignments
 # ============================
@@ -219,57 +181,98 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall

 # -----------------------------
-# start ENTITY(LodeRunner_MiST)
+# start ENTITY(IremM62_MiST)

 	# Pin & Location Assignments
 	# ==========================
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
-	set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]

 	# Fitter Assignments
 	# ==================
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO

 	# start DESIGN_PARTITION(Top)
 	# ---------------------------

 		# Incremental Compilation Assignments
 		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

 	# end DESIGN_PARTITION(Top)
 	# -------------------------

-# end ENTITY(LodeRunner_MiST)
-# ---------------------------
+# end ENTITY(IremM62_MiST)
+# ---------------------------
+set_location_assignment PLL_1 -to pll|altpll_component|auto_generated|pll1
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/IremM62_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/target_top.vhd
+set_global_assignment -name VHDL_FILE rtl/platform_variant_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/platform_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/platform.vhd
+set_global_assignment -name VHDL_FILE rtl/pace_pkg_body.vhd
+set_global_assignment -name VHDL_FILE rtl/pace_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/pace.vhd
+set_global_assignment -name VHDL_FILE rtl/Graphics.VHD
+set_global_assignment -name VHDL_FILE rtl/video_mixer.vhd
+set_global_assignment -name VHDL_FILE rtl/iremm62_video_controller.vhd
+set_global_assignment -name VHDL_FILE rtl/video_controller_pkg_body.vhd
+set_global_assignment -name VHDL_FILE rtl/video_controller_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/tilemapctl.vhd
+set_global_assignment -name VHDL_FILE rtl/bitmapctl_e.vhd
+set_global_assignment -name VHDL_FILE rtl/spritereg.vhd
+set_global_assignment -name VHDL_FILE rtl/spritectl.vhd
+set_global_assignment -name VHDL_FILE rtl/sprite_pkg_body.vhd
+set_global_assignment -name VHDL_FILE rtl/sprite_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/sprite_array.vhd
+set_global_assignment -name VHDL_FILE rtl/Inputs.VHD
+set_global_assignment -name VHDL_FILE rtl/input_mapper.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/clk_div.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
+set_global_assignment -name QIP_FILE rtl/jt5205/jt5205.qip
+set_global_assignment -name VHDL_FILE rtl/Sound_Board.vhd
+set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
+set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
+set_global_assignment -name VHDL_FILE ../../common/CPU/T80/Z80.vhd
+set_global_assignment -name VHDL_FILE ../../common/CPU/6800/cpu68.vhd
+set_global_assignment -name SIGNALTAP_FILE output_files/sp.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/tilemap.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/sprite.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/cpu.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/snd.stp
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--- a/Hardware/IremM62.sdc
+++ b/Hardware/IremM62.sdc
@@ -0,0 +1,139 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
+set vid_clk   "pll|altpll_component|auto_generated|pll1|clk[2]"
+set game_clk  "pll|altpll_component|auto_generated|pll1|clk[1]"
+set aud_clk   "pll|altpll_component|auto_generated|pll1|clk[3]"
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.4 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.2 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay   -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay   -clock [get_clocks $aud_clk]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay   -clock [get_clocks $aud_clk]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay   -clock [get_clocks $game_clk] 1.000 [get_ports {LED}]
+set_output_delay -add_delay   -clock [get_clocks $vid_clk]  1.000 [get_ports {VGA_*}]
+
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+set_clock_groups -asynchronous -group [get_clocks $sdram_clk] -group [get_clocks $aud_clk]
+set_clock_groups -asynchronous -group [get_clocks $game_clk] -group [get_clocks $aud_clk]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 3
+set_multicycle_path -to {VGA_*[*]} -hold 2
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
--- a/Hardware/LodeRunner_MiST/rtl/clk_div.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/clk_div.vhd
@@ -1,39 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity clk_div is
-	generic
-	(
-		DIVISOR   : natural
-	);
-  port
-  (
-    clk       : in std_logic;
-    reset     : in std_logic;
-
-		clk_en    : out std_logic
-  );
-end clk_div;
-
-architecture SYN of clk_div is
-
-begin
-
-	process (clk, reset)
-		variable count : integer range 0 to DIVISOR-1;
-	begin
-		if reset = '1' then
-			count := 0;
-			clk_en <= '0';
-		elsif rising_edge(clk) then
-			clk_en <= '0';
-			if count = DIVISOR-1 then
-				clk_en <= '1';
-				count := 0;
-			else
-				count := count + 1;
-			end if;
-		end if;
-	end process;
-
-end SYN;
--- a/Hardware/LodeRunner_MiST/rtl/cpu68.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/cpu68.vhd
--- a/Hardware/LodeRunner_MiST/rtl/dprom_2r.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/dprom_2r.vhd
@@ -1,135 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY dprom_2r IS
-	GENERIC
-	(
-		INIT_FILE			: string := "";
-		--NUMWORDS_A		: natural;
-		WIDTHAD_A			: natural;
-		WIDTH_A				: natural := 8;
-		--NUMWORDS_B		: natural;
-		WIDTHAD_B			: natural;
-		WIDTH_B				: natural := 8;
-    outdata_reg_a : string := "UNREGISTERED";
-    outdata_reg_b : string := "UNREGISTERED"
-	);
-	PORT
-	(
-		address_a		: in std_logic_vector (WIDTHAD_A-1 downto 0);
-		address_b		: in std_logic_vector (WIDTHAD_B-1 downto 0);
-		clock				: in std_logic ;
-		q_a					: out std_logic_vector (WIDTH_A-1 downto 0);
-		q_b					: out std_logic_vector (WIDTH_B-1 downto 0)
-	);
-END dprom_2r;
-
-
-ARCHITECTURE SYN OF dprom_2r IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0);
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3_bv	: BIT_VECTOR (WIDTH_A-1 DOWNTO 0);
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
-	SIGNAL sub_wire4_bv	: BIT_VECTOR (WIDTH_B-1 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0);
-
-
-
-	COMPONENT altsyncram
-	GENERIC (
-		address_reg_b		: STRING;
-		clock_enable_input_a		: STRING;
-		clock_enable_input_b		: STRING;
-		clock_enable_output_a		: STRING;
-		clock_enable_output_b		: STRING;
-		indata_reg_b		: STRING;
-		init_file		: STRING;
-		init_file_layout		: STRING;
-		intended_device_family		: STRING;
-		lpm_type		: STRING;
-		numwords_a		: NATURAL;
-		numwords_b		: NATURAL;
-		operation_mode		: STRING;
-		outdata_aclr_a		: STRING;
-		outdata_aclr_b		: STRING;
-		outdata_reg_a		: STRING;
-		outdata_reg_b		: STRING;
-		power_up_uninitialized		: STRING;
-		ram_block_type		: STRING;
-		widthad_a		: NATURAL;
-		widthad_b		: NATURAL;
-		width_a		: NATURAL;
-		width_b		: NATURAL;
-		width_byteena_a		: NATURAL;
-		width_byteena_b		: NATURAL;
-		wrcontrol_wraddress_reg_b		: STRING
-	);
-	PORT (
-			wren_a	: IN STD_LOGIC ;
-			wren_b	: IN STD_LOGIC ;
-			clock0	: IN STD_LOGIC ;
-			address_a	: IN STD_LOGIC_VECTOR (WIDTHAD_A-1 DOWNTO 0);
-			address_b	: IN STD_LOGIC_VECTOR (WIDTHAD_B-1 DOWNTO 0);
-			q_a	: OUT STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
-			q_b	: OUT STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0);
-			data_a	: IN STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
-			data_b	: IN STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire2    <= '0';
-	sub_wire3_bv(WIDTH_A-1 DOWNTO 0) <= (others => '0');
-	sub_wire3    <= To_stdlogicvector(sub_wire3_bv);
-	sub_wire4_bv(WIDTH_B-1 DOWNTO 0) <= (others => '0');
-	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
-	q_a    <= sub_wire0(WIDTH_A-1 DOWNTO 0);
-	q_b    <= sub_wire1(WIDTH_B-1 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK0",
-		clock_enable_input_a => "BYPASS",
-		clock_enable_input_b => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK0",
-		init_file => INIT_FILE,
-		init_file_layout => "PORT_A",
-		intended_device_family => "Cyclone III",
-		lpm_type => "altsyncram",
-		numwords_a => 2**WIDTHAD_A,
-		numwords_b => 2**WIDTHAD_B,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => outdata_reg_a,
-		outdata_reg_b => outdata_reg_b,
-		power_up_uninitialized => "FALSE",
-		ram_block_type => "M9K",
-		widthad_a => WIDTHAD_A,
-		widthad_b => WIDTHAD_B,
-		width_a => WIDTH_A,
-		width_b => WIDTH_B,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK0"
-	)
-	PORT MAP (
-		wren_a => sub_wire2,
-		wren_b => sub_wire2,
-		clock0 => clock,
-		address_a => address_a,
-		address_b => address_b,
-		data_a => sub_wire3,
-		data_b => sub_wire4,
-		q_a => sub_wire0,
-		q_b => sub_wire1
-	);
-
-END SYN;
--- a/Hardware/LodeRunner_MiST/rtl/pace.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/pace.vhd
@@ -1,146 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.pace_pkg.all;
-use work.video_controller_pkg.all;
-use work.sprite_pkg.all;
-use work.platform_pkg.all;
--use work.project_pkg.all;
-
-entity PACE is
-  port
-  (
-  	-- clocks and resets
-    clkrst_i        : in from_CLKRST_t;
-
-    -- misc I/O
-    buttons_i       : in from_BUTTONS_t;
-    switches_i      : in from_SWITCHES_t;
-    leds_o          : out to_LEDS_t;
-
-    -- controller inputs
-    inputs_i        : in from_INPUTS_t;
-
-    -- video
-    video_i         : in from_VIDEO_t;
-    video_o         : out to_VIDEO_t;
-	 sound_data_o    : out std_logic_vector(7 downto 0);
-
-    -- custom i/o
- --   project_i       : in from_PROJECT_IO_t;
- --   project_o       : out to_PROJECT_IO_t;
-    platform_i      : in from_PLATFORM_IO_t;
-    platform_o      : out to_PLATFORM_IO_t;
-	 cpu_rom_addr          : out std_logic_vector(14 downto 0);
-	 cpu_rom_do          : in std_logic_vector(7 downto 0)
-  );
-end entity PACE;
-
-architecture SYN of PACE is
-
-	constant CLK_1US_COUNTS : integer := 
-    integer(27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY);
-
-	signal mapped_inputs		: from_MAPPED_INPUTS_t(0 to PACE_INPUTS_NUM_BYTES-1);
-
-  signal to_tilemap_ctl   : to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
-  signal from_tilemap_ctl : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
-
-  signal to_bitmap_ctl    : to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
-  signal from_bitmap_ctl  : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
-
-  signal to_sprite_reg    : to_SPRITE_REG_t;
-  signal to_sprite_ctl    : to_SPRITE_CTL_t;
-  signal from_sprite_ctl  : from_SPRITE_CTL_t;
-	signal spr0_hit					: std_logic;
-
-  signal to_graphics      : to_GRAPHICS_t;
-	signal from_graphics    : from_GRAPHICS_t;
-
-begin
-
-	inputs_inst : entity work.inputs
-		generic map
-		(
-      NUM_DIPS        => PACE_NUM_SWITCHES,
-			NUM_INPUTS	    => PACE_INPUTS_NUM_BYTES,
-			CLK_1US_DIV	    => CLK_1US_COUNTS
-		)
-	  port map
-	  (
-	    clk     	      => clkrst_i.clk(0),
-	    reset   	      => clkrst_i.rst(0),
-			jamma			      => inputs_i.jamma_n,
-	
-	    dips     	      => switches_i,
-	    inputs		      => mapped_inputs
-	  );
-
-  platform_inst : entity work.platform
-    generic map
-    (
-      NUM_INPUT_BYTES => PACE_INPUTS_NUM_BYTES
-    )
-    port map
-    (
-      -- clocking and reset
-      clkrst_i        => clkrst_i,
-      
-      -- misc inputs and outputs
-      buttons_i       => buttons_i,
-      switches_i      => switches_i,
-      leds_o          => leds_o,
-      sound_data_o    => sound_data_o,
-      -- controller inputs
-      inputs_i        => mapped_inputs,
-
-      -- graphics
-      bitmap_i        => from_bitmap_ctl,
-      bitmap_o        => to_bitmap_ctl,
-      
-      tilemap_i       => from_tilemap_ctl,
-      tilemap_o       => to_tilemap_ctl,
-      
-      sprite_reg_o    => to_sprite_reg,
-      sprite_i        => from_sprite_ctl,
-      sprite_o        => to_sprite_ctl,
-			spr0_hit				=> spr0_hit,
-      
-      graphics_i      => from_graphics,
-      graphics_o      => to_graphics,
-
-      -- custom i/o
--      project_i       => project_i,
--      project_o       => project_o,
-      platform_i      => platform_i,
-      platform_o      => platform_o,
-		
-		cpu_rom_addr    => cpu_rom_addr,
-	   cpu_rom_do      => cpu_rom_do
-    );
-
-  graphics_inst : entity work.Graphics                                    
-    Port Map
-    (
-      bitmap_ctl_i    => to_bitmap_ctl,
-      bitmap_ctl_o    => from_bitmap_ctl,
-
-      tilemap_ctl_i   => to_tilemap_ctl,
-      tilemap_ctl_o   => from_tilemap_ctl,
-
-      sprite_reg_i    => to_sprite_reg,
-      sprite_ctl_i    => to_sprite_ctl,
-      sprite_ctl_o    => from_sprite_ctl,
-      spr0_hit				=> spr0_hit,
-      
-      graphics_i      => to_graphics,
-      graphics_o      => from_graphics,
-      
-			-- video (incl. clk)
-			video_i					=> video_i,
-			video_o					=> video_o
-    );
-	
-end SYN;
--- a/Hardware/LodeRunner_MiST/rtl/platform.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/platform.vhd
@@ -1,479 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.pace_pkg.all;
-use work.video_controller_pkg.all;
-use work.sprite_pkg.all;
-use work.platform_pkg.all;
-use work.platform_variant_pkg.all;
--use work.project_pkg.all;
-
-entity platform is
-  generic
-  (
-    NUM_INPUT_BYTES   : integer
-  );
-  port
-  (
-    -- clocking and reset
-    clkrst_i        : in from_CLKRST_t;
-
-    -- misc I/O
-    buttons_i       : in from_BUTTONS_t;
-    switches_i      : in from_SWITCHES_t;
-    leds_o          : out to_LEDS_t;
-
-    -- controller inputs
-    inputs_i        : in from_MAPPED_INPUTS_t(0 to NUM_INPUT_BYTES-1);
-
-    -- graphics
-    
-    bitmap_i        : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
-    bitmap_o        : out to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
-    
-    tilemap_i       : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
-    tilemap_o       : out to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
-
-    sprite_reg_o    : out to_SPRITE_REG_t;
-    sprite_i        : in from_SPRITE_CTL_t;
-    sprite_o        : out to_SPRITE_CTL_t;
-		spr0_hit				: in std_logic;
-
-    -- various graphics information
-    graphics_i      : in from_GRAPHICS_t;
-    graphics_o      : out to_GRAPHICS_t;
-	 sound_data_o    : out std_logic_vector(7 downto 0);
-
-    -- custom i/o
--    project_i       : in from_PROJECT_IO_t;
--    project_o       : out to_PROJECT_IO_t;
-    platform_i      : in from_PLATFORM_IO_t;
-    platform_o      : out to_PLATFORM_IO_t;
-	 cpu_rom_addr          : out std_logic_vector(14 downto 0);
-	 cpu_rom_do          : in std_logic_vector(7 downto 0)
-  );
-
-end platform;
-
-architecture SYN of platform is
-
-	alias clk_sys				  : std_logic is clkrst_i.clk(0);
-	alias rst_sys				  : std_logic is clkrst_i.rst(0);
-	alias clk_video       : std_logic is clkrst_i.clk(1);
-	
-  -- cpu signals  
-  signal clk_3M072_en		: std_logic;
-  signal cpu_clk_en     : std_logic;
-  signal cpu_a          : std_logic_vector(15 downto 0);
-  signal cpu_d_i        : std_logic_vector(7 downto 0);
-  signal cpu_d_o        : std_logic_vector(7 downto 0);
-  signal cpu_mem_wr     : std_logic;
-  signal cpu_io_rd      : std_logic;
-  signal cpu_io_wr      : std_logic;
-  signal cpu_irq        : std_logic;
-
-  -- ROM signals        
-	signal rom_cs					: std_logic;
--  signal rom_d_o        : std_logic_vector(7 downto 0);
-  
-  -- keyboard signals
-	                        
-  -- VRAM signals       
-	signal vram_cs				: std_logic;
-	signal vram_wr				: std_logic;
-   signal vram_d_o       : std_logic_vector(7 downto 0);
-
-   signal snd_cs              : std_logic;
-
-  
-  -- RAM signals        
-  signal wram_cs        : std_logic;
-  signal wram_wr        : std_logic;
-  signal wram_d_o       : std_logic_vector(7 downto 0);
-
-  -- CRAM/SPRITE signals        
-  signal cram_cs        : std_logic;
-  signal cram_wr        : std_logic;
-	signal cram_d_o		    : std_logic_vector(7 downto 0);
-	signal sprite_cs      : std_logic;
-  
-  -- misc signals      
-  signal in_cs          : std_logic;
-  signal in_d_o         : std_logic_vector(7 downto 0);
-  
-  -- other signals
-  signal rst_platform   : std_logic;
-  signal pause          : std_logic;
-  signal rot_en         : std_logic;
-
-begin
-
-  -- handle special keys
-  process (clk_sys, rst_sys)
-    variable spec_keys_r  : std_logic_vector(7 downto 0);
-    alias spec_keys       : std_logic_vector(7 downto 0) is inputs_i(PACE_INPUTS_NUM_BYTES-1).d;
-    variable layer_en     : std_logic_vector(4 downto 0);
-  begin
-    if rst_sys = '1' then
-      rst_platform <= '0';
-      pause <= '0';
-      rot_en <= '0';  -- to default later
-      spec_keys_r := (others => '0');
-      layer_en := "11111";
-    elsif rising_edge(clk_sys) then
-      rst_platform <= spec_keys(0);
-      if spec_keys_r(1) = '0' and spec_keys(1) = '1' then
-        pause <= not pause;
-      end if;
-      if spec_keys_r(2) = '0' and spec_keys(2) = '1' then
-        rot_en <= not rot_en;
-        if layer_en = "11111" then
-          layer_en := "00001";
-        elsif layer_en = "10000" then
-          layer_en := "11111";
-        else
-          layer_en := layer_en(3 downto 0) & layer_en(4);
-        end if;
-      end if;
-      spec_keys_r := spec_keys;
-    end if;
-    graphics_o.bit8(0)(4 downto 0) <= layer_en;
-  end process;
-  
-  --graphics_o.bit8(0)(0) <= rot_en;
-  
-  -- chip select logic
-  -- ROM $0000-$7FFF
-  rom_cs <=     '1' when STD_MATCH(cpu_a,  "0---------------") else '0';
-  -- SPRITE $C000-$C0FF
-  sprite_cs <=  '1' when STD_MATCH(cpu_a, X"C0"&   "--------") else '0';
-  -- VRAM/CRAM $D000-$DFFF
-  vram_cs <=    '1' when PLATFORM_VARIANT = "kungfum" and
-                          STD_MATCH(cpu_a, X"D"&"0-----------") else 
-                '1' when PLATFORM_VARIANT /= "kungfum" and
-                          STD_MATCH(cpu_a, X"D"&"-----------0") else 
-                '0';
-  cram_cs <=    '1' when PLATFORM_VARIANT = "kungfum" and
-                          STD_MATCH(cpu_a, X"D"&"1-----------") else 
-                '1' when PLATFORM_VARIANT /= "kungfum" and
-                          STD_MATCH(cpu_a, X"D"&"-----------1") else 
-                '0';
-  -- RAM $E000-$EFFF
-  wram_cs <=    '1' when STD_MATCH(cpu_a, X"E"&"------------") else '0';
-
-  -- OUTPUT $DXX0
-  snd_cs <=      '1' when STD_MATCH(cpu_a(7 downto 0), X"0"&"00--") else '0';
-
-  -- INPUTS (I/O) $00-$04
-  in_cs <=      '1' when STD_MATCH(cpu_a(7 downto 0), X"0"&"00--") else 
-                '1' when STD_MATCH(cpu_a(7 downto 0), X"04") else
-                '0';
-					 
-process (clk_sys, rst_sys) begin
-	if rst_sys = '1' then
-		sound_data_o <= X"00";
-	elsif rising_edge(clk_sys) then
-      if cpu_clk_en = '1' and cpu_mem_wr = '1' and snd_cs = '1' then
-			sound_data_o <= cpu_d_o;
-		end if;
-	end if; 
-  end process;
-
-  
-	-- memory read mux
-	cpu_d_i <=  in_d_o when (cpu_io_rd = '1' and in_cs = '1') else
-					cpu_rom_do when rom_cs = '1' else
-					vram_d_o when vram_cs = '1' else
-					cram_d_o when cram_cs = '1' else
-					wram_d_o when wram_cs = '1' else
-					(others => '1');
-              
-  -- memory block write signals 
-	vram_wr <= vram_cs and cpu_mem_wr;
-	cram_wr <= cram_cs and cpu_mem_wr;
-	wram_wr <= wram_cs and cpu_mem_wr;
-
-  -- sprite registers
-  sprite_reg_o.clk <= clk_sys;
-  sprite_reg_o.clk_ena <= clk_3M072_en;
-  sprite_reg_o.a <= cpu_a(7 downto 0);
-  sprite_reg_o.d <= cpu_d_o;
-  sprite_reg_o.wr <= sprite_cs and cpu_mem_wr;
-
-  --
-  -- COMPONENT INSTANTIATION
-  --
-
-  BLK_CPU : block
-    signal cpu_rst        : std_logic;
-  begin
-    -- generate CPU enable clock (3MHz from 27/30MHz)
-    clk_en_inst : entity work.clk_div
-      generic map
-      (
-        DIVISOR		=> M62_CPU_CLK_ENA_DIVIDE_BY
-      )
-      port map
-      (
-        clk				=> clk_sys,
-        reset			=> rst_sys,
-        clk_en		=> clk_3M072_en
-      );
-    
-    -- gated CPU signals
-    cpu_clk_en <= clk_3M072_en and not pause;
-    cpu_rst <= rst_sys or rst_platform;
-    
-    cpu_inst : entity work.Z80                                                
-      port map
-      (
-        clk 		=> clk_sys,                                   
-        clk_en	=> cpu_clk_en,
-        reset  	=> cpu_rst,
-
-        addr   	=> cpu_a,
-        datai  	=> cpu_d_i,
-        datao  	=> cpu_d_o,
-
-        mem_rd 	=> open,
-        mem_wr 	=> cpu_mem_wr,
-        io_rd  	=> cpu_io_rd,
-        io_wr  	=> cpu_io_wr,
-
-        intreq 	=> cpu_irq,
-        intvec 	=> cpu_d_i,
-        intack 	=> open,
-        nmi    	=> '0'
-      );
-
-  end block BLK_CPU;
-  
-  BLK_INTERRUPTS : block
-  
-    signal vblank_int     : std_logic;
-
-  begin
-  
-		process (clk_sys, rst_sys)
-			variable vblank_r : std_logic_vector(3 downto 0);
-			alias vblank_prev : std_logic is vblank_r(vblank_r'left);
-			alias vblank_um   : std_logic is vblank_r(vblank_r'left-1);
-      -- 1us duty for VBLANK_INT
-      variable count    : integer range 0 to CLK0_FREQ_MHz * 100;
-		begin
-			if rst_sys = '1' then
-				vblank_int <= '0';
-				vblank_r := (others => '0');
-        count := count'high;
-			elsif rising_edge(clk_sys) then
-        -- rising edge vblank only
-        if vblank_prev = '0' and vblank_um = '1' then
-          count := 0;
-        end if;
-        if count /= count'high then
-          vblank_int <= '1';
-          count := count + 1;
-        else
-          vblank_int <= '0';
-        end if;
-        vblank_r := vblank_r(vblank_r'left-1 downto 0) & graphics_i.vblank;
-			end if; -- rising_edge(clk_sys)
-		end process;
-
-    -- generate INT
-    cpu_irq <= vblank_int;
-    
-  end block BLK_INTERRUPTS;
-  
-  BLK_INPUTS : block
-  begin
-    in_d_o <= inputs_i(0).d when cpu_a(2 downto 0) = "000" else
-              inputs_i(1).d when cpu_a(2 downto 0) = "001" else
-              inputs_i(2).d when cpu_a(2 downto 0) = "010" else
-              inputs_i(3).d when cpu_a(2 downto 0) = "011" else
-              inputs_i(4).d;
-  end block BLK_INPUTS;
-  
-  BLK_SCROLL : block
-    signal m62_hscroll  : std_logic_vector(15 downto 0);
-  begin
-    process (clk_sys, rst_sys)
-    begin
-      if rst_sys = '1' then
-        m62_hscroll <= (others => '0');
-      elsif rising_edge(clk_sys) then
-        if cpu_clk_en = '1' and cpu_mem_wr = '1' then
-          case cpu_a is
-            when X"A000" =>
-              if PLATFORM_VARIANT = "kungfum" then
-                m62_hscroll(7 downto 0) <= cpu_d_o;
-              end if;
-            when X"B000" =>
-              if PLATFORM_VARIANT = "kungfum" then
-                m62_hscroll(15 downto 8) <= cpu_d_o;
-              end if;
-            when others =>
-              null;
-          end case;
-        end if; -- cpu_wr
-      end if; -- rising_edge(clk_sys)
-    end process;
-    graphics_o.bit16(0) <= m62_hscroll;
-  end block BLK_SCROLL;
-  
-cpu_rom_addr <= cpu_a(14 downto 0);
-  
-  BLK_GFX_ROMS : block
-  
-    type gfx_rom_d_a is array(M62_CHAR_ROM'range) of std_logic_vector(7 downto 0);
-    signal chr_rom_d      : gfx_rom_d_a;
-    type spr_rom_d_a is array(0 to 11) of std_logic_vector(7 downto 0);
-    signal spr_rom_left   : spr_rom_d_a;
-    signal spr_rom_right  : spr_rom_d_a;
-    
-  begin
-  
-    GEN_CHAR_ROMS : for i in M62_CHAR_ROM'range generate
-      char_rom_inst : entity work.sprom
-        generic map
-        (
-          init_file		=> "./roms/" &
-                          M62_CHAR_ROM(i) & ".hex",
-          widthad_a		=> 13
-        )
-        port map
-        (
-          clock			=> clk_video,
-          address		=> tilemap_i(1).tile_a(12 downto 0),
-          q					=> chr_rom_d(i)
-        );
-    end generate GEN_CHAR_ROMS;
-
- tilemap_o(1).tile_d(23 downto 0) <= chr_rom_d(0) & chr_rom_d(1) & chr_rom_d(2);
-
-- chr_rom_addr <= tilemap_i(1).tile_a(12 downto 0);
- --tilemap_o(1).tile_d(23 downto 0) <= chr_rom_do;
- 
- 
-    GEN_SPRITE_ROMS : for i in M62_SPRITE_ROM'range generate
-      sprite_rom_inst : entity work.dprom_2r
-        generic map
-        (
-          init_file		=> "./roms/" &
-                          M62_SPRITE_ROM(i) & ".hex",
-          widthad_a		=> 13,
-          widthad_b		=> 13
-        )
-        port map
-        (
-          clock			              => clk_video,
-          address_a(12 downto 5)  => sprite_i.a(12 downto 5),
-          address_a(4)            => '0',
-          address_a(3 downto 0)   => sprite_i.a(3 downto 0),
-          q_a 			              => spr_rom_left(i),
-          address_b(12 downto 5)  => sprite_i.a(12 downto 5),
-          address_b(4)            => '1',
-          address_b(3 downto 0)   => sprite_i.a(3 downto 0),
-          q_b                     => spr_rom_right(i)
-        );
-    end generate GEN_SPRITE_ROMS;
-
-    sprite_o.d(sprite_o.d'left downto 48) <= (others => '0');
-    sprite_o.d(47 downto 0) <=  spr_rom_left(0) & spr_rom_right(0) & 
-                                spr_rom_left(1) & spr_rom_right(1) &
-                                spr_rom_left(2) & spr_rom_right(2)
-                                  when sprite_i.a(14 downto 13) = "00" else
-                                spr_rom_left(3) & spr_rom_right(3) &
-                                spr_rom_left(4) & spr_rom_right(4) &
-                                spr_rom_left(5) & spr_rom_right(5) 
-                                  when sprite_i.a(14 downto 13) = "01" else
-                                spr_rom_left(6) & spr_rom_right(6) &
-                                spr_rom_left(7) & spr_rom_right(7) &
-                                spr_rom_left(8) & spr_rom_right(8) 
-                                  when sprite_i.a(14 downto 13) = "10" else
-                                spr_rom_left(9) & spr_rom_right(9) &
-                                spr_rom_left(10) & spr_rom_right(10) &
-                                spr_rom_left(11) & spr_rom_right(11);
-
-  end block BLK_GFX_ROMS;
-
-  BLK_VRAM : block
-    signal vram_a   : std_logic_vector(10 downto 0);
-    alias cram_a    : std_logic_vector(10 downto 0) is vram_a;
-  begin
-  
-    vram_a <= cpu_a(10 downto 0) when PLATFORM_VARIANT = "kungfum" else
-              cpu_a(11 downto 1);
-              
-    vram_inst : entity work.dpram
-      generic map
-      (
-        init_file		=> "",
-        widthad_a		=> 11
-      )
-      port map
-      (
-        clock_b			=> clk_sys,
-        address_b		=> vram_a,
-        wren_b			=> vram_wr,
-        data_b			=> cpu_d_o,
-        q_b					=> vram_d_o,
-
-        clock_a			=> clk_video,
-        address_a		=> tilemap_i(1).map_a(10 downto 0),
-        wren_a			=> '0',
-        data_a			=> (others => 'X'),
-        q_a					=> tilemap_o(1).map_d(7 downto 0)
-      );
-    tilemap_o(1).map_d(15 downto 8) <= (others => '0');
-
-    cram_inst : entity work.dpram
-      generic map
-      (
-        init_file		=> "",
-        widthad_a		=> 11
-      )
-      port map
-      (
-        clock_b			=> clk_sys,
-        address_b		=> cram_a,
-        wren_b			=> cram_wr,
-        data_b			=> cpu_d_o,
-        q_b					=> cram_d_o,
-
-        clock_a			=> clk_video,
-        address_a		=> tilemap_i(1).attr_a(10 downto 0),
-        wren_a			=> '0',
-        data_a			=> (others => 'X'),
-        q_a					=> tilemap_o(1).attr_d(7 downto 0)
-      );
-    tilemap_o(1).attr_d(15 downto 8) <= (others => '0');
-    
-  end block BLK_VRAM;
- 
-  
-    wram_inst : entity work.spram
-      generic map
-      (
-      	widthad_a => 12
-      )
-      port map
-      (
-        clock				=> clk_sys,
-        address			=> cpu_a(11 downto 0),
-        data				=> cpu_d_o,
-        wren				=> wram_wr,
-        q						=> wram_d_o
-      );
-
-		
-  -- unused outputs
-
-  sprite_o.ld <= '0';
-  --graphics_o <= NULL_TO_GRAPHICS;
-  leds_o <= (others => '0');
-  
-end SYN;
--- a/Hardware/LodeRunner_MiST/rtl/platform_pkg.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/platform_pkg.vhd
@@ -1,76 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-library work;
-
-use work.platform_variant_pkg.all;
-use work.video_controller_pkg.all;
-package platform_pkg is
-
-	constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_VGA_640x480_60Hz;
-	constant PACE_CLK0_DIVIDE_BY              : natural := 3;
-	constant PACE_CLK0_MULTIPLY_BY            : natural := 5;   -- 24*5/3 = 40MHz
-	constant PACE_CLK1_DIVIDE_BY              : natural := 19;
-	constant PACE_CLK1_MULTIPLY_BY            : natural := 20; 	-- 24*20/19 = 25.263158MHz
-	constant PACE_VIDEO_H_SCALE       	      : integer := 1;
-	constant PACE_VIDEO_V_SCALE       	      : integer := 1;
-	constant PACE_VIDEO_H_SYNC_POLARITY       : std_logic := '0';
-	constant PACE_VIDEO_V_SYNC_POLARITY       : std_logic := '0';
-
--  constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_ARCADE_STD_336x240_60Hz;
--  constant PACE_CLK0_DIVIDE_BY              : natural := 1;
--  constant PACE_CLK0_MULTIPLY_BY            : natural := 1;   	-- 24*1/1 = 24MHz
--  constant PACE_CLK1_DIVIDE_BY              : natural := 57;
--  constant PACE_CLK1_MULTIPLY_BY            : natural := 17;  	-- 24*17/57 = 7.157895MHz
--  constant PACE_VIDEO_H_SCALE       	      : integer := 1;
--  constant PACE_VIDEO_V_SCALE       	      : integer := 1;
--  constant PACE_VIDEO_H_SYNC_POLARITY       : std_logic := '0';
--  constant PACE_VIDEO_V_SYNC_POLARITY       : std_logic := '0';
-  
-  --constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_CVBS_720x288p_50Hz;
-  --constant PACE_CLK0_DIVIDE_BY              : natural := 8;
-  --constant PACE_CLK0_MULTIPLY_BY            : natural := 9;   -- 24*9/8 = 27MHz
-  --constant PACE_CLK1_DIVIDE_BY              : natural := 16;
-  --constant PACE_CLK1_MULTIPLY_BY            : natural := 9;		-- 24*9/16 = 13.5MHz
-	--constant PACE_VIDEO_H_SCALE               : integer := 2;
-	--constant PACE_VIDEO_V_SCALE               : integer := 1;
-	--constant PACE_ENABLE_ADV724					      : std_logic := '1';
-	--constant USE_VIDEO_VBLANK_INTERRUPT 		  : boolean := false;
-
-	constant PACE_VIDEO_BORDER_RGB            : RGB_t := RGB_BLACK;
-
-	constant M62_VIDEO_H_SIZE				      : integer := 384;
-	constant M62_VIDEO_H_OFFSET           : integer := (512-M62_VIDEO_H_SIZE)/2;
-	constant M62_VIDEO_V_SIZE				      : integer := 256;
-	
-	constant PACE_VIDEO_NUM_BITMAPS		    : natural := 0;
-	constant PACE_VIDEO_NUM_TILEMAPS	    : natural := 1;
-	constant PACE_VIDEO_NUM_SPRITES 	    : natural := 32;
-	constant PACE_VIDEO_H_SIZE				    : integer := M62_VIDEO_H_SIZE;
-	constant PACE_VIDEO_V_SIZE				    : integer := M62_VIDEO_V_SIZE;
-	constant PACE_VIDEO_L_CROP            : integer := 0;
-	constant PACE_VIDEO_R_CROP            : integer := PACE_VIDEO_L_CROP;
-	constant PACE_VIDEO_PIPELINE_DELAY    : integer := 5;
-	
-	constant PACE_INPUTS_NUM_BYTES        : integer := 6;
-	
-	constant CLK0_FREQ_MHz		            : natural := 
-    27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY;
-	constant CPU_FREQ_MHz                 : natural := 3;
-  
-	constant M62_CPU_CLK_ENA_DIVIDE_BY    : natural := CLK0_FREQ_MHz / CPU_FREQ_MHz;
-	
-
-  
-  
-
-  type from_PLATFORM_IO_t is record
-    not_used  : std_logic;
-  end record;
-
-  type to_PLATFORM_IO_t is record
-    not_used  : std_logic;
-  end record;
-
-end;
--- a/Hardware/LodeRunner_MiST/rtl/roms/Roms.txt
+++ b/Hardware/LodeRunner_MiST/rtl/roms/Roms.txt
@@ -1,37 +0,0 @@
-ROM_START( ldrun )
-	ROM_REGION( 0x10000, "maincpu", 0 )
-	ROM_LOAD( "lr-a-4e",      0x0000, 0x2000, CRC(5d7e2a4d) SHA1(fe8aeff360f6c3a8606d67a8b95148c3c2ef7267) )
-	ROM_LOAD( "lr-a-4d",      0x2000, 0x2000, CRC(96f20473) SHA1(e400c43f3f32e12f68ca204c60bcebdb2b3da55d) )
-	ROM_LOAD( "lr-a-4b",      0x4000, 0x2000, CRC(b041c4a9) SHA1(77768b03ea2497e25c3e47b68a0eb2fe3e9aea35) )
-	ROM_LOAD( "lr-a-4a",      0x6000, 0x2000, CRC(645e42aa) SHA1(c806ffce7ece418bad86854c987f78c70c13e492) )
-
-	ROM_REGION( 0x10000, "irem_audio:iremsound", 0 )   /* 64k for the audio CPU (6803) */
-	ROM_LOAD( "lr-a-3f",      0xc000, 0x2000, CRC(7a96accd) SHA1(e94815dbfaabbb562df8f3298060aa6bd7825904) )
-	ROM_LOAD( "lr-a-3h",      0xe000, 0x2000, CRC(3f7f3939) SHA1(7ee25a21e74995bfb36ac11b45d384b33a6d8515) )
-
-	ROM_REGION( 0x6000, "gfx1", 0 )
-	ROM_LOAD( "lr-e-2d",      0x0000, 0x2000, CRC(24f9b58d) SHA1(e33224b910d37aaa85713b954c8dd50996245a8c) )    /* characters */
-	ROM_LOAD( "lr-e-2j",      0x2000, 0x2000, CRC(43175e08) SHA1(9dbafb27d46cf7df35f343a8753e8d91ea706993) )
-	ROM_LOAD( "lr-e-2f",      0x4000, 0x2000, CRC(e0317124) SHA1(b766bd21e2da1673d2054148f62d61c33c95d38e) )
-
-	ROM_REGION( 0x6000, "gfx2", 0 )
-	ROM_LOAD( "lr-b-4k",      0x0000, 0x2000, CRC(8141403e) SHA1(65fa6bc872fb07c71aacbbcc35cee766b2877896) )    /* sprites */
-	ROM_LOAD( "lr-b-3n",      0x2000, 0x2000, CRC(55154154) SHA1(35304676e1ab55adccdabdc766a4e0e0901d3cd0) )
-	ROM_LOAD( "lr-b-4c",      0x4000, 0x2000, CRC(924e34d0) SHA1(6a841419797a129235fc7d0405a5be55e8d703da) )
-
-	ROM_REGION( 0x20, "spr_height_prom", 0 )
-	ROM_LOAD( "lr-b-5p",      0x00, 0x20, CRC(e01f69e2) SHA1(0d00ef348025ea4a9c274a7e3dbb006217d8449d) )    /* sprite height, one entry per 32 */
-
-	ROM_REGION( 0x300, "spr_color_proms", 0 )
-	ROM_LOAD( "lr-b-1m",      0x0000, 0x0100, CRC(4bae1c25) SHA1(17a9e2567d9d648dca69510bb201f8af0738b068) )    /* sprite palette red component */
-	ROM_LOAD( "lr-b-1n",      0x0100, 0x0100, CRC(9cd3db94) SHA1(bff95965f946df0e4af1f99db5b2468bf1d4403f) )    /* sprite palette green component */
-	ROM_LOAD( "lr-b-1l",      0x0200, 0x0100, CRC(08d8cf9a) SHA1(a46213e0dc04e44b0544401eb341fd49eef331dd) )    /* sprite palette blue component */
-
-	ROM_REGION( 0x300, "chr_color_proms", 0 )
-	ROM_LOAD( "lr-e-3m",      0x0000, 0x0100, CRC(53040416) SHA1(2c6915164d1c31afc60a21b557abdf023d5b3f46) )    /* character palette red component */
-	ROM_LOAD( "lr-e-3l",      0x0100, 0x0100, CRC(67786037) SHA1(cd40dfd94295afe57139733752643cf48b8566b1) )    /* character palette green component */
-	ROM_LOAD( "lr-e-3n",      0x0200, 0x0100, CRC(5b716837) SHA1(e3ea250891fec43a97e92ac1c3a4fbb5ee2d4a4d) )    /* character palette blue component */
-
-	ROM_REGION( 0x100, "timing", 0 )
-	ROM_LOAD( "lr-b-6f",      0x000, 0x100, CRC(34d88d3c) SHA1(727f4c5cfff33538886fa0a29fd119aa085d7008) )    /* video timing - common to the other games */
-ROM_END
--- a/Hardware/LodeRunner_MiST/rtl/roms/battroad.zip
+++ b/Hardware/LodeRunner_MiST/rtl/roms/battroad.zip
--- a/Hardware/LodeRunner_MiST/rtl/roms/kungfum.zip
+++ b/Hardware/LodeRunner_MiST/rtl/roms/kungfum.zip
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun.zip
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun.zip
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-a-3f
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-a-3f
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-a-3h
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-a-3h
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-a-4a
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-a-4a
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-a-4b
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-a-4b
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-a-4d
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-a-4d
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-a-4e
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-a-4e
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-1l
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-1l
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-1m
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-1m
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-1n
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-1n
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-3n
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-3n
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-4c
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-4c
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-4k
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-4k
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-5p
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-5p
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-6f
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-b-6f
@@ -1 +0,0 @@
-
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-e-2d
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-e-2d
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-e-2f
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-e-2f
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-e-2j
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-e-2j
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-e-3l
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-e-3l
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-e-3m
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-e-3m
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-e-3n
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/lr-e-3n
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/make_proms.bat
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/make_proms.bat
@@ -1,11 +0,0 @@
-copy /b lr-a-4e + lr-a-4d + lr-a-4b + lr-a-4a prog.bin
-make_vhdl_prom.exe prog.bin prog.vhd
-
-make_vhdl_prom.exe lr-b-5p rom_sprite_high_new.vhd
-
-
-copy /b lr-a-3f + lr-a-3h snd.bin
-make_vhdl_prom.exe snd.bin snd_prg.vhd
-
-copy /b prog.bin + snd.bin LDRUNNER.ROM
-pause
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/make_vhdl_prom.exe
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/make_vhdl_prom.exe
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/prog.bin
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/prog.bin
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/prog.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/prog.vhd
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/rom_sprite_high.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/rom_sprite_high.vhd
@@ -1,24 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity rom_sprite_high is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(4 downto 0);
-	data : out std_logic_vector(3 downto 0)
-);
-end entity;
-
-architecture prom of rom_sprite_high is
-	type rom is array(0 to  31) of std_logic_vector(3 downto 0);
-	signal rom_data: rom := (
-		"0001","0001","0001","0001","0000","0000","0000","0000","0001","0001","0001","0001","0000","0000","0000","0000",
-		"0001","0001","0001","0001","0000","0000","0000","0000","0001","0001","0001","0001","0000","0000","0000","0000");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/rom_sprite_high_new.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/rom_sprite_high_new.vhd
@@ -1,24 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity rom_sprite_high_new is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(4 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of rom_sprite_high_new is
-	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"00",
-		X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"00");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/snd.bin
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/snd.bin
--- a/Hardware/LodeRunner_MiST/rtl/roms/ldrun/snd_prg.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/roms/ldrun/snd_prg.vhd
--- a/Hardware/LodeRunner_MiST/rtl/roms/lotlot.zip
+++ b/Hardware/LodeRunner_MiST/rtl/roms/lotlot.zip
--- a/Hardware/LodeRunner_MiST/rtl/roms/lr-b-3n.hex
+++ b/Hardware/LodeRunner_MiST/rtl/roms/lr-b-3n.hex
@@ -1,513 +0,0 @@
-:1000000000000000000000000000000000000000F0
-:1000100000000000000000000000000000000000E0
-:1000200000000000000000000000000000000000D0
-:1000300000000000000000000000000000000000C0
-:1000400000000000000000000000000000000003AD
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--- a/Hardware/LodeRunner_MiST/rtl/roms/nu/lr-a-4d.hex
+++ b/Hardware/LodeRunner_MiST/rtl/roms/nu/lr-a-4d.hex
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--- a/Hardware/LodeRunner_MiST/rtl/roms/nu/lr-a-4e.hex
+++ b/Hardware/LodeRunner_MiST/rtl/roms/nu/lr-a-4e.hex
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--- a/Hardware/LodeRunner_MiST/rtl/sprite_array.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/sprite_array.vhd
@@ -1,164 +0,0 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
-
-library work;
-use work.pace_pkg.all;
-use work.video_controller_pkg.all;
-use work.sprite_pkg.all;
-use work.platform_pkg.all;
-
-entity sprite_array is
-  generic
-  (
-    N_SPRITES   : integer;
-    DELAY       : integer
-  );
-	port
-	(
-		reset				: in std_logic;
-
-    -- register interface
-    reg_i       : in to_SPRITE_REG_t;
-
-    -- video control signals
-    video_ctl   : in from_VIDEO_CTL_t;
-
-    -- extra data
-    graphics_i  : in to_GRAPHICS_t;
-
-		-- sprite data
-    row_a       : out SPRITE_ROW_A_t;
-    row_d       : in SPRITE_ROW_D_t;
-
-    -- video data
-    rgb         : out RGB_t;
-    set         : out std_logic;
-    pri         : out std_logic;
-    spr0_set    : out std_logic
-	);
-end entity sprite_array;
-
-architecture SYN of sprite_array is
-
-	type reg_a_t is array (natural range <>) of from_SPRITE_REG_t;
-  type ctl_i_a_t is array (natural range <>) of to_SPRITE_CTL_t;
-  type ctl_o_a_t is array (natural range <>) of from_SPRITE_CTL_t;
-  
-	alias clk       : std_logic is video_ctl.clk;
-	alias clk_ena   : std_logic is video_ctl.clk_ena;
-	
-	signal reg_o    : reg_a_t(0 to N_SPRITES-1);
-  signal ctl_i    : ctl_i_a_t(0 to N_SPRITES-1);
-  signal ctl_o    : ctl_o_a_t(0 to N_SPRITES-1);
-	
-	signal ld_r     : std_logic_vector(N_SPRITES-1 downto 0);
-	
-begin
-
-	-- Sprite Data Load Arbiter
-	-- - enables each sprite controller during hblank
-	--   to allow loading of sprite row data into row buffer
-	process (clk, clk_ena, reset)
-		variable i : integer range 0 to N_SPRITES-1;
-	begin
-		if reset = '1' then
-			-- enable must be 1 clock behind address to latch data after fetch
-			--ld_r <= (N_SPRITES-1 => '1', others => '0');
-      -- make ISE 9.2.03i happy...
-			ld_r(ld_r'left) <= '1';
-			ld_r(ld_r'left-1 downto 0) <= (others => '0');
-			i := 0;
-		elsif rising_edge(clk) and clk_ena = '1' then
-			ld_r <= ld_r(ld_r'left-1 downto 0) & ld_r(ld_r'left);
-			if i = N_SPRITES-1 then
-			  i := 0;
-			else
-			  i := i + 1;
-			end if;
-      row_a <= ctl_o(i).a;
-		end if;
-	end process;
-
-  -- sprite row data fan-out
-  GEN_ROW_D : for i in 0 to N_SPRITES-1 generate
-    ctl_i(i).ld <= ld_r(i);
-    ctl_i(i).d <= row_d;
-  end generate GEN_ROW_D;
-  
-	-- Sprite Priority Encoder
-	-- - determines which sprite pixel (if any) is to be displayed
-	-- We can use a clocked process here because the tilemap
-	-- output is 1 clock behind at this point
-	process (clk, clk_ena)
-		variable spr_on_v 	: std_logic := '0';
-		variable spr_pri_v 	: std_logic := '0';
-	begin
-		if rising_edge(clk) and clk_ena = '1' then
-			spr_on_v := '0';
-			spr_pri_v := '0';
-			for i in 0 to N_SPRITES-1 loop
-				-- if highest priority = 0 and pixel on
-				if spr_pri_v = '0' and ctl_o(i).set = '1' then
-					-- if no sprite on or this priority = 1
-					if spr_on_v = '0' or reg_o(i).pri = '1' then
-						rgb <= ctl_o(i).rgb;
-						spr_on_v := '1';					    -- flag as sprite on
-						spr_pri_v := reg_o(i).pri;		-- store priority
-					end if;
-				end if;
-			end loop;
-		end if;
-		set <= spr_on_v;
-		pri <= spr_pri_v;
-	end process;
-
-	-- for NES, and perhaps others
-	-- it's actually more complicated than this
-	-- but it'll do for now...
-	spr0_set <= ctl_o(0).set;
-		
-	--
-	-- Component Instantiation
-	--
-	
-	GEN_REGS : for i in 0 to N_SPRITES-1 generate
-	
-		sptReg_inst : entity work.sptReg
-			generic map
-			(
-				INDEX			=> i
-			)
-			port map
-			(
-        reg_i           => reg_i,
-				reg_o           => reg_o(i)
-			);
-
-		sptCtl_inst : entity work.spritectl
-			generic map
-			(
-				INDEX			=> i,
-				DELAY     => DELAY
-			)
-			port map
-			(
-        -- sprite registers
-        reg_i       => reg_o(i),
-        
-        -- video control signals
-        video_ctl   => video_ctl,
-
-        -- sprite control signals
-        ctl_i       => ctl_i(i),
-        ctl_o       => ctl_o(i),
-
-        graphics_i  => graphics_i
-      );
-				
-	end generate GEN_REGS;
-	
-end SYN;
-
--- a/Hardware/LodeRunner_MiST/rtl/spritectl.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/spritectl.vhd
@@ -1,202 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.pace_pkg.all;
-use work.video_controller_pkg.all;
-use work.sprite_pkg.all;
--use work.project_pkg.all;
-use work.platform_pkg.all;    
-use work.platform_variant_pkg.all;
-
-entity spritectl is
-	generic
-	(
-		INDEX		: natural;
-		DELAY   : integer
-	);
-	port               
-	(
-    -- sprite registers
-    reg_i       : in from_SPRITE_REG_t;
-    
-    -- video control signals
-    video_ctl   : in from_VIDEO_CTL_t;
-
-    -- sprite control signals
-    ctl_i       : in to_SPRITE_CTL_t;
-    ctl_o       : out from_SPRITE_CTL_t;
-    
-		graphics_i  : in to_GRAPHICS_t
-	);
-end entity spritectl;
-
-architecture SYN of spritectl is
-
-  alias clk       : std_logic is video_ctl.clk;
-  alias clk_ena   : std_logic is video_ctl.clk_ena;
-  
-  signal flipData : std_logic_vector(47 downto 0);   -- flipped row data
-   
-  alias rgb       : RGB_t is ctl_o.rgb;
-  
-begin
-
-  flipData(47 downto 32) <= flip_1 (ctl_i.d(47 downto 32), reg_i.xflip);
-  flipData(31 downto 16) <= flip_1 (ctl_i.d(31 downto 16), reg_i.xflip);
-  flipData(15 downto 0) <= flip_1 (ctl_i.d(15 downto 0), reg_i.xflip);
-  
-	process (clk, clk_ena)
-
-   	variable rowStore : std_logic_vector(47 downto 0);  -- saved row of spt to show during visibile period
-		variable pel      : std_logic_vector(2 downto 0);
-    variable x        : unsigned(video_ctl.x'range);
-    variable y        : unsigned(video_ctl.y'range);
-    variable yMat     : boolean;      -- raster is between first and last line of sprite
-    variable xMat     : boolean;      -- raster in between left edge and end of line
-
-    variable height     : unsigned(6 downto 0);
-		-- the width of rowCount determines the scanline multipler
-		-- - eg.	(4 downto 0) is 1:1
-		-- 				(5 downto 0) is 2:1 (scan-doubling)
--  	variable rowCount : unsigned(3+PACE_VIDEO_V_SCALE downto 0);
--    alias row         : unsigned(4 downto 0) is 
--                          rowCount(rowCount'left downto rowCount'left-4);
-    variable rowCount   : unsigned(height'range);
-    alias row           : unsigned(rowCount'range) is rowCount;
-    -- which part of the sprite is being drawn
-    alias segment       : unsigned(1 downto 0) is rowCount(5 downto 4);
-    
-    variable prom_i     : integer range sprite_prom'range;
-    variable code       : std_logic_vector(9 downto 0);
-    variable pal_i      : std_logic_vector(7 downto 0);
-		variable pal_rgb    : pal_rgb_t;
-    
-  begin
-
-		if rising_edge(clk) then
-      if clk_ena = '1' then
-        if video_ctl.hblank = '1' then
-
-          x := unsigned(reg_i.x) - M62_VIDEO_H_OFFSET + PACE_VIDEO_PIPELINE_DELAY - 3;
-          y := 256 + 128 - 15 - unsigned(reg_i.y);
-
-          -- hande sprite height, placement
-          prom_i := to_integer(unsigned(reg_i.n(9 downto 5)));
-          code := reg_i.n(9 downto 0); -- default
-          case sprite_prom(prom_i) is
-            when 1 =>
-              -- double height
-              height := to_unsigned(2*16,height'length);
-              y := y - 16;
-            when 2 =>
-              -- quadruple height
-              height := to_unsigned(4*16,height'length);
-              y := y - 3*16;
-            when others =>
-              height := to_unsigned(16,height'length);
-          end case;
-          
-          -- do this 1st because we don't have many clocks
-          if y = unsigned(video_ctl.y) then
-            -- start counting sprite row
-            rowCount := (others => '0');
-            yMat := true;
-          elsif row = height then
-            yMat := false;				
-          end if;
-
-          case sprite_prom(prom_i) is
-            when 1 =>
-              -- double height
-              if reg_i.yflip = '1' then
-                code(0) := not segment(0);
-              else
-                code(0) := segment(0);
-              end if;
-            when 2 =>
-              -- quadruple height
-              if reg_i.yflip = '1' then
-                code(1 downto 0) := not std_logic_vector(segment);
-              else
-                code(1 downto 0) := std_logic_vector(segment);
-              end if;
-            when others =>
-              null;
-          end case;
-
-          xMat := false;
-          -- stop sprites wrapping from bottom of screen
-          if y = 0 then
-            yMat := false;
-          end if;
-          
-          -- sprites not visible before row 16				
-          if ctl_i.ld = '1' then
-            if yMat then
-              rowStore := flipData;			-- load sprite data
-            else
-              rowStore := (others => '0');
-            end if;
-          end if;
-              
-        end if; -- hblank='1'
-        
-        if video_ctl.stb = '1' then
-      
-          if x = unsigned(video_ctl.x) then
-            -- count up at left edge of sprite
-            rowCount := rowCount + 1;
-            -- start of sprite
-            --if unsigned(x) /= 0 and unsigned(x) < 240 then
-              xMat := true;
-            --end if;
-          end if;
-          
-          if xMat then
-            -- shift in next pixel
-            pel := rowStore(rowStore'left-32) & rowStore(rowStore'left-16) & rowStore(rowStore'left);
-            rowStore(47 downto 32) := rowStore(46 downto 32) & '0';
-            rowStore(31 downto 16) := rowStore(30 downto 16) & '0';
-            rowStore(15 downto 0) := rowStore(14 downto 0) & '0';
-          end if;
-
-        end if;
-
-        if PLATFORM_VARIANT = "ldrun" or
-            PLATFORM_VARIANT = "battroad" then
-          pal_i := '0' & reg_i.colour(3 downto 0) & pel;
-        else
-          pal_i := reg_i.colour(4 downto 0) & pel;
-        end if;
-        --pal_i := "000" & std_logic_vector(to_unsigned(INDEX,5));
-        pal_rgb := sprite_pal(to_integer(unsigned(pal_i)));
-        rgb.r <= pal_rgb(0) & "00";
-        rgb.g <= pal_rgb(1) & "00";
-        rgb.b <= pal_rgb(2) & "00";
-
-        -- set pixel transparency based on match
-        ctl_o.set <= '0';
-        if xMat and pel /= "000" then
-          if graphics_i.bit8(0)(4) = '1' then
-            ctl_o.set <= '1';
-          end if;
-        end if;
-
-      end if; -- clk_ena='1'
-    end if; -- rising_edge(clk)
-    
-    -- generate sprite data address
-    ctl_o.a(15) <= '0'; -- unused
-    ctl_o.a(14 downto 5) <= code;
-    ctl_o.a(4) <= '0'; -- dual-port RAM
-    if reg_i.yflip = '0' then
-      ctl_o.a(3 downto 0) <= std_logic_vector(row(3 downto 0));
-    else
-      ctl_o.a(3 downto 0) <=  not std_logic_vector(row(3 downto 0));
-    end if;
-
-  end process;
-
-end architecture SYN;
--- a/Hardware/LodeRunner_MiST/rtl/target_top.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/target_top.vhd
@@ -1,147 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.pace_pkg.all;
-use work.video_controller_pkg.all;
-use work.platform_pkg.all;
-
-entity target_top is port(
-      clock_50      		: in std_logic;
-		clock_vid      	: in std_logic;
-		clk_aud      		: in std_logic;
-		reset_in      		: in std_logic;
-      audio_out         : out std_logic_vector(11 downto 0);
-		usr_coin1      	: in std_logic;
-		usr_coin2     		: in std_logic;
-		usr_service     	: in std_logic;
-	   usr_start1      	: in std_logic;
-		usr_start2      	: in std_logic;
-	   p1_up      			: in std_logic;
-	   p1_dw      			: in std_logic;
-	   p1_lt      			: in std_logic;
-	   p1_rt      			: in std_logic;
-		p1_f1      			: in std_logic;
-		p1_f2      			: in std_logic;
-		
-	   p2_up      			: in std_logic;
-	   p2_dw      			: in std_logic;
-	   p2_lt      			: in std_logic;
-	   p2_rt      			: in std_logic;
-		p2_f1      			: in std_logic;
-		p2_f2      			: in std_logic;
-		
-      VGA_VS        		: out std_logic;
-      VGA_HS        		: out std_logic;
-      VGA_R         		: out std_logic_vector(3 downto 0);
-      VGA_G         		: out std_logic_vector(3 downto 0);
-      VGA_B         		: out std_logic_vector(3 downto 0);
-	   cpu_rom_addr      : out std_logic_vector(14 downto 0);
-	   cpu_rom_do        : in std_logic_vector(7 downto 0);
-		snd_rom_addr      : out std_logic_vector(13 downto 0);
-      snd_rom_do        : in std_logic_vector(7 downto 0)
-  );    
-end target_top;
-
-architecture SYN of target_top is 
-  
-  signal clkrst_i       : from_CLKRST_t;
-  signal buttons_i      : from_BUTTONS_t;
-  signal switches_i     : from_SWITCHES_t;
-  signal leds_o         : to_LEDS_t;
-  signal inputs_i       : from_INPUTS_t;
-  signal video_i        : from_VIDEO_t;
-  signal video_o        : to_VIDEO_t;
-  signal platform_i     : from_PLATFORM_IO_t;
-  signal platform_o     : to_PLATFORM_IO_t;
-  signal sound_data     : std_logic_vector(7 downto 0);
-
-begin
-	clkrst_i.clk(0) <= clock_50;
-	clkrst_i.clk(1) <= clock_vid;		
-	clkrst_i.arst <= reset_in;
-	clkrst_i.arst_n <= not clkrst_i.arst;
-
-GEN_RESETS : for i in 0 to 3 generate
-	process (clkrst_i.clk(i), clkrst_i.arst)
-		variable rst_r : std_logic_vector(2 downto 0) := (others => '0');
-			begin
-				if clkrst_i.arst = '1' then
-					rst_r := (others => '1');
-				elsif rising_edge(clkrst_i.clk(i)) then
-					rst_r := rst_r(rst_r'left-1 downto 0) & '0';
-				end if;
-				clkrst_i.rst(i) <= rst_r(rst_r'left);
-    end process;
-end generate GEN_RESETS;
-
- video_i.clk <= clkrst_i.clk(1);
- video_i.clk_ena <= '1';
- video_i.reset <= clkrst_i.rst(1);
- VGA_R <= video_o.rgb.r(9 downto 6);
- VGA_G <= video_o.rgb.g(9 downto 6);
- VGA_B <= video_o.rgb.b(9 downto 6);
- VGA_HS <= video_o.hsync;
- VGA_VS <= video_o.vsync;
-
--Sound_Board : entity work.Sound_Board
--	port map(
--		clock_E    		=> clk_aud,
--		areset     		=> clkrst_i.rst(1),
--		select_sound  	=> sound_data,
--		audio_out     	=> audio_out,
--		snd_rom_addr   => snd_rom_addr,
--      snd_rom_do     => snd_rom_do,
--		dbg_cpu_addr  	=> open
--	);
- 
-pace_inst : entity work.pace                                            
-	port map(
-		clkrst_i				=> clkrst_i,
-		buttons_i         => buttons_i,
-		switches_i        => switches_i,
-		inputs_i          => inputs_i,
-		video_i           => video_i,
-		video_o           => video_o,
-		sound_data_o 		=> sound_data,
-      platform_i        => platform_i,
-      platform_o        => platform_o,
-		cpu_rom_addr      => cpu_rom_addr,
-	   cpu_rom_do        => cpu_rom_do
-    );
-
-		inputs_i.jamma_n.coin(1) <= not usr_coin1;
-		inputs_i.jamma_n.coin(2) <= not usr_coin2;
-		inputs_i.jamma_n.service <= not usr_service;
-		inputs_i.jamma_n.p(1).start <= not usr_start1;
-		inputs_i.jamma_n.p(2).start <= not usr_start2;
-		
-		inputs_i.jamma_n.p(1).up <= not p1_up;
-		inputs_i.jamma_n.p(1).down <= not p1_dw;
-		inputs_i.jamma_n.p(1).left <= not p1_lt;
-		inputs_i.jamma_n.p(1).right <= not p1_rt;
-		inputs_i.jamma_n.p(1).button(1) <= not p1_f1; 
-		inputs_i.jamma_n.p(1).button(2) <= not p1_f2; 
-		inputs_i.jamma_n.p(1).button(3) <= '1';
-		inputs_i.jamma_n.p(1).button(4) <= '1';
-		inputs_i.jamma_n.p(1).button(5) <= '1';
-
-		inputs_i.jamma_n.p(2).up <= not p2_up;
-		inputs_i.jamma_n.p(2).down <= not p2_dw;
-		inputs_i.jamma_n.p(2).left <= not p2_lt;
-		inputs_i.jamma_n.p(2).right <= not p2_rt;		
-		inputs_i.jamma_n.p(2).button(1) <= not p2_f1; 
-		inputs_i.jamma_n.p(2).button(2) <= not p2_f2; 
-		inputs_i.jamma_n.p(2).button(3) <= '1';
-		inputs_i.jamma_n.p(2).button(4) <= '1';
-		inputs_i.jamma_n.p(2).button(5) <= '1';
- 
-	-- not currently wired to any inputs
-	inputs_i.jamma_n.coin_cnt <= (others => '1');
--	inputs_i.jamma_n.coin(2) <= '1';
--	inputs_i.jamma_n.service <= '1';
-	inputs_i.jamma_n.tilt <= '1';
-	inputs_i.jamma_n.test <= '1';
-end SYN;
--- a/Hardware/LodeRunner_MiST/rtl/tilemapctl.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/tilemapctl.vhd
@@ -1,106 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.pace_pkg.all;
--use work.project_pkg.all;
-use work.platform_pkg.all;
-use work.platform_variant_pkg.all;
-use work.video_controller_pkg.all;
-
--
--	Irem M62 Tilemap Controller
--
--	Tile data is 2 BPP.
--
-
-architecture TILEMAP_1 of tilemapCtl is
-
-  alias clk       : std_logic is video_ctl.clk;
-  alias clk_ena   : std_logic is video_ctl.clk_ena;
-  alias stb       : std_logic is video_ctl.stb;
-  alias hblank    : std_logic is video_ctl.hblank;
-  alias vblank    : std_logic is video_ctl.vblank;
-  
-  signal x        : std_logic_vector(video_ctl.x'range);
-  signal y        : std_logic_vector(video_ctl.y'range);
-  
-  alias rot_en    : std_logic is graphics_i.bit8(0)(0);
-  alias hscroll   : std_logic_vector(15 downto 0) is graphics_i.bit16(0);
-  
-begin
-
-  -- not used
-	ctl_o.map_a(ctl_o.map_a'left downto 11) <= (others => '0');
-  ctl_o.attr_a(ctl_o.attr_a'left downto 11) <= (others => '0');
-  ctl_o.tile_a(ctl_o.tile_a'left downto 13) <= (others => '0');
-
-  -- screen rotation
-  x <=  std_logic_vector(M62_VIDEO_H_OFFSET + unsigned(video_ctl.x)) when unsigned(y) < 6*8 else
-        std_logic_vector(M62_VIDEO_H_OFFSET + unsigned(video_ctl.x) + unsigned(hscroll(8 downto 0))); 
-        -- when rot_en = '0' else not video_ctl.y;
-  --y <= not video_ctl.y when rot_en = '0' else 32 + video_ctl.x;
-  y <= video_ctl.y; -- when rot_en = '0' else video_ctl.x;
-  
-  -- generate pixel
-  process (clk, clk_ena)
-
-    variable tile_d_r   : std_logic_vector(23 downto 0);
-    variable attr_d_r   : std_logic_vector(7 downto 0);
-		variable pel        : std_logic_vector(2 downto 0);
-    variable pal_i      : std_logic_vector(7 downto 0);
-		variable pal_rgb    : pal_rgb_t;
-
-  begin
-  
-  	if rising_edge(clk) then
-      if clk_ena = '1' then
-
-        -- 1st stage of pipeline
-        -- - set tilemap, attribute address
-        ctl_o.map_a(10 downto 6) <= y(7 downto 3);
-        ctl_o.map_a(5 downto 0) <= x(8 downto 3);
-        ctl_o.attr_a(10 downto 6) <= y(7 downto 3);
-        ctl_o.attr_a(5 downto 0) <= x(8 downto 3);
-
-        -- 2nd stage of pipeline
-        -- - set tile address
-        if x(2 downto 0) = "010" then
-          ctl_o.tile_a(12 downto 11) <= ctl_i.attr_d(7 downto 6);
-          ctl_o.tile_a(10 downto 3) <= ctl_i.map_d(7 downto 0);
-          ctl_o.tile_a(2 downto 0) <= y(2 downto 0);
-        end if;
-        
-        -- 3rd stage of pipeline
-        -- - read tile, attribute data from ROM
-        if x(2 downto 0) = "100" then
-          tile_d_r := ctl_i.tile_d(tile_d_r'range);
-          attr_d_r := ctl_i.attr_d(7 downto 0);
-        elsif stb = '1' then
-          tile_d_r := tile_d_r(tile_d_r'left-1 downto 0) & '0';
-        end if;
-
-        -- extract R,G,B from colour palette
-        pel := tile_d_r(tile_d_r'left-16) & tile_d_r(tile_d_r'left-8) & tile_d_r(tile_d_r'left);
-        pal_i := attr_d_r(4 downto 0) & pel;
-        pal_rgb := tile_pal(to_integer(unsigned(pal_i)));
-        ctl_o.rgb.r <= pal_rgb(0) & "00";
-        ctl_o.rgb.g <= pal_rgb(1) & "00";
-        ctl_o.rgb.b <= pal_rgb(2) & "00";
-        ctl_o.set <= '0'; -- default
--        if pel /= "000" then
--            pal_rgb(0)(7 downto 5) /= "000" or
--            pal_rgb(1)(7 downto 5) /= "000" or
--            pal_rgb(2)(7 downto 5) /= "000" then
-          if graphics_i.bit8(0)(3) = '1' then
-            ctl_o.set <= '1';
-          end if;
--        end if;
-
-      end if; -- clk_ena
-		end if; -- rising_edge_clk
-
-  end process;
-
-end architecture TILEMAP_1;
--- a/Hardware/LodeRunner_MiST/rtl/tilemapctl_e.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/tilemapctl_e.vhd
@@ -1,29 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.pace_pkg.all;
--use work.project_pkg.all;
-use work.platform_pkg.all;
-use work.video_controller_pkg.all;
-
-entity tilemapCtl is          
-  generic
-  (
-    DELAY       : integer
-  );
-  port               
-  (
-    reset				: in std_logic;
-
-    -- video control signals		
-    video_ctl   : in from_VIDEO_CTL_t;
-
-    -- tilemap controller signals
-    ctl_i       : in to_TILEMAP_CTL_t;
-    ctl_o       : out from_TILEMAP_CTL_t;
-
-    graphics_i  : in to_GRAPHICS_t
-  );
-end entity tilemapCtl;
--- a/Hardware/README.txt
+++ b/Hardware/README.txt
@@ -0,0 +1,13 @@
+Irem M62 Hardware
+=================
+
+Based on old PACE code by Mark McDougall(tcdev), enhanced by Gyorgy Szombathelyi in March 2020.
+
+Games supported:
+- Lode Runner 1-4
+- Kung Fu Master
+- Horizon
+- Battle Road
+- Spelunker 1-2
+- Kid Niki
+- Youjyudn
--- a/Hardware/LodeRunner_MiST/clean.bat
+++ b/Hardware/LodeRunner_MiST/clean.bat
--- a/Hardware/meta/Battle
+++ b/Hardware/meta/Battle
@@ -0,0 +1,139 @@
+<misterromdescription>
+    <name>Battle Road</name>
+    <mameversion>0216</mameversion>
+    <setname>battroad</setname>
+    <manufacturer>Irem</manufacturer>
+    <rbf>iremm62</rbf>
+    <rom index="1"><part>6</part></rom>
+    <rom index="0" zip="battroad.zip" md5="4d5de2720b53b64fb63beed407cbeb19" type="merged|nonmerged">
+      <!-- CPU1, 128k -->
+      <part name="br-a-4e.b"/>
+      <part name="br-a-4d.b"/>
+      <part name="br-a-4b.b"/>
+      <part name="br-a-4a"/>
+      <part repeat="0x8000">FF</part>
+
+      <part name="br-c-7c"/>
+      <part name="br-c-7l"/>
+      <part name="br-c-7d"/>
+      <part name="br-c-7b"/>
+      <part name="br-c-7a"/>
+      <part name="br-c-7k"/>
+      <part name="br-c-7k"/>
+      <part repeat="0x2000">FF</part>
+
+      <!-- SND CPU2, 64k -->
+      <part repeat="0xa000">FF</part>
+      <part name="br-a-3e"/>
+      <part name="br-a-3f"/>
+      <part name="br-a-3h"/>
+
+      <!-- GFX1, 128k -->
+      <group width="32">
+          <part name="br-c-6h"/>
+          <part name="br-c-6n"/>
+          <part name="br-c-6k"/>
+          <part name="br-c-6k"/>
+      </group>
+      <group width="32">
+          <part name="br-c-6h"/>
+          <part name="br-c-6n"/>
+          <part name="br-c-6k"/>
+          <part name="br-c-6k"/>
+      </group>
+      <group width="32">
+          <part name="br-c-6h"/>
+          <part name="br-c-6n"/>
+          <part name="br-c-6k"/>
+          <part name="br-c-6k"/>
+      </group>
+      <group width="32">
+          <part name="br-c-6h"/>
+          <part name="br-c-6n"/>
+          <part name="br-c-6k"/>
+          <part name="br-c-6k"/>
+      </group>
+
+      <!-- GFX2, 256k -->
+      <group width="32">
+          <part name="br-b-4k.a"/>
+          <part name="br-b-3n.a"/>
+          <part name="br-b-4c.a"/>
+          <part name="br-b-4c.a"/>
+      </group>
+      <group width="32">
+          <part name="br-b-4f.a"/>
+          <part name="br-b-4n.a"/>
+          <part name="br-b-4e.a"/>
+          <part name="br-b-4e.a"/>
+      </group>
+      <group width="32">
+          <part name="br-b-4k.a"/>
+          <part name="br-b-3n.a"/>
+          <part name="br-b-4c.a"/>
+          <part name="br-b-4c.a"/>
+      </group>
+      <group width="32">
+          <part name="br-b-4f.a"/>
+          <part name="br-b-4n.a"/>
+          <part name="br-b-4e.a"/>
+          <part name="br-b-4e.a"/>
+      </group>
+      <group width="32">
+          <part name="br-b-4k.a"/>
+          <part name="br-b-3n.a"/>
+          <part name="br-b-4c.a"/>
+          <part name="br-b-4c.a"/>
+      </group>
+      <group width="32">
+          <part name="br-b-4f.a"/>
+          <part name="br-b-4n.a"/>
+          <part name="br-b-4e.a"/>
+          <part name="br-b-4e.a"/>
+      </group>
+      <group width="32">
+          <part name="br-b-4k.a"/>
+          <part name="br-b-3n.a"/>
+          <part name="br-b-4c.a"/>
+          <part name="br-b-4c.a"/>
+      </group>
+      <group width="32">
+          <part name="br-b-4f.a"/>
+          <part name="br-b-4n.a"/>
+          <part name="br-b-4e.a"/>
+          <part name="br-b-4e.a"/>
+      </group>
+
+      <!-- GFX3, 64k -->
+      <group width="32">
+          <part name="br-c-1c"/>
+          <part name="br-c-1b"/>
+          <part name="br-c-1c"/>
+          <part name="br-c-1b"/>
+      </group>
+      <group width="32">
+          <part name="br-c-1c"/>
+          <part name="br-c-1b"/>
+          <part name="br-c-1c"/>
+          <part name="br-c-1b"/>
+      </group>
+
+      <!-- spr_color_proms, 3*256b -->
+      <part name="br-b-1m"/>
+      <part name="br-b-1n"/>
+      <part name="br-b-1l"/>
+
+      <!-- chr_color_proms, 3*256b -->
+      <part name="br-c-3j"/>
+      <part name="br-c-3l"/>
+      <part name="br-c-3k"/>
+
+      <!-- fg_color_proms, 3*256b br-c-1j -->
+      <part name="br-c-1j"/>
+      <part repeat="0x2e0">FF</part>
+
+      <!-- spr_height_prom -->
+      <part name="br-b-5p"/>
+
+    </rom>
+</misterromdescription>
--- a/Hardware/meta/Horizon.mra
+++ b/Hardware/meta/Horizon.mra
@@ -0,0 +1,99 @@
+<misterromdescription>
+    <name>Horizon</name>
+    <mameversion>0216</mameversion>
+    <setname>horizon</setname>
+    <manufacturer>Irem</manufacturer>
+    <rbf>iremm62</rbf>
+    <rom index="1"><part>5</part></rom>
+    <rom index="0" zip="horizon.zip" md5="573ef5ced961ede734cdde94153fcb7a" type="merged|nonmerged">
+      <!-- CPU1, 128k -->
+      <part name="hrza-4e"/>
+      <part name="hrza-4d"/>
+      <part name="hrza-4b"/>
+      <part name="hrza-4b"/>
+
+      <part name="hrza-4e"/>
+      <part name="hrza-4d"/>
+      <part name="hrza-4b"/>
+      <part name="hrza-4b"/>
+
+      <!-- SND CPU2, 64k -->
+      <part name="hrza-3f"/>
+      <part name="hrza-3f"/>
+      <part name="hrza-3f"/>
+      <part name="hrza-3f"/>
+
+      <!-- GFX1, 128k -->
+      <group width="32">
+          <part name="hrzd-4d"/>
+          <part name="hrzd-4c"/>
+          <part name="hrzd-4a"/>
+          <part name="hrzd-4a"/>
+      </group>
+      <group width="32">
+          <part name="hrzd-4d"/>
+          <part name="hrzd-4c"/>
+          <part name="hrzd-4a"/>
+          <part name="hrzd-4a"/>
+      </group>
+      <group width="32">
+          <part name="hrzd-4d"/>
+          <part name="hrzd-4c"/>
+          <part name="hrzd-4a"/>
+          <part name="hrzd-4a"/>
+      </group>
+      <group width="32">
+          <part name="hrzd-4d"/>
+          <part name="hrzd-4c"/>
+          <part name="hrzd-4a"/>
+          <part name="hrzd-4a"/>
+      </group>
+
+      <!-- GFX2, 256k -->
+      <group width="32">
+          <part name="hrzb-4k.00"/>
+          <part name="hrzb-3n.10"/>
+          <part name="hrzb-4c.20"/>
+          <part name="hrzb-4c.20"/>
+      </group>
+      <group width="32">
+          <part name="hrzb-4f.01"/>
+          <part name="hrzb-4n.11"/>
+          <part name="hrzb-4e.21"/>
+          <part name="hrzb-4e.21"/>
+      </group>
+
+      <group width="32">
+          <part name="hrzb-4k.00"/>
+          <part name="hrzb-3n.10"/>
+          <part name="hrzb-4c.20"/>
+          <part name="hrzb-4c.20"/>
+      </group>
+      <group width="32">
+          <part name="hrzb-4f.01"/>
+          <part name="hrzb-4n.11"/>
+          <part name="hrzb-4e.21"/>
+          <part name="hrzb-4e.21"/>
+      </group>
+
+      <!-- GFX3, 64k -->
+      <part repeat="0x10000">FF</part>
+
+      <!-- spr_color_proms, 3*256b -->
+      <part name="hrzb-1m.r"/>
+      <part name="hrzb-1n.g"/>
+      <part name="hrzb-1l.b"/>
+
+      <!-- chr_color_proms, 3*256b -->
+      <part name="hrzd-1d"/>
+      <part name="hrzd-1c"/>
+      <part name="hrzd-1e"/>
+
+      <!-- fg_color_proms, 3*256b -->
+      <part repeat="0x300">FF</part>
+
+      <!-- spr_height_prom -->
+      <part name="hrzb-5p"/>
+
+    </rom>
+</misterromdescription>
--- a/Arcade_MiST/IremM62
+++ b/Arcade_MiST/IremM62
@@ -0,0 +1,82 @@
+<misterromdescription>
+    <name>Kid Niki - Radical Ninja</name>
+    <mameversion>0216</mameversion>
+    <setname>kidniki</setname>
+    <manufacturer>Irem</manufacturer>
+    <rbf>iremm62</rbf>
+    <rom index="1"><part>7</part></rom>
+    <rom index="0" zip="kidniki.zip" md5="63cf7764a51bae694ce95dfe518a96f3" type="merged|nonmerged">
+      <!-- CPU1, 128k -->
+      <part name="ky_a-4e-g.bin"/>
+      <part name="dr03.4cd"/>
+      <part name="ky_t-8k-g.bin"/>
+      <part name="dr12.8l"/>
+
+      <!-- SND CPU2, 64k -->
+      <part repeat="0x4000">FF</part>
+      <part name="dr00.3a"/>
+      <part name="dr01.3cd"/>
+      <part name="dr02.3f"/>
+
+      <!-- GFX1, 128k -->
+      <group width="32">
+          <part name="dr06.2b"/>
+          <part name="dr07.2dc"/>
+          <part name="dr05.2a"/>
+          <part name="dr05.2a"/>
+      </group>
+
+      <!-- GFX2, 256k -->
+      <group width="32">
+          <part name="dr21.4k"/>
+          <part name="dr14.3p"/>
+          <part name="dr16.4cb"/>
+          <part name="dr16.4cb"/>
+      </group>
+      <group width="32">
+          <part name="dr19.4f"/>
+          <part name="dr24.4p"/>
+          <part name="dr18.4e"/>
+          <part name="dr18.4e"/>
+      </group>
+      <group width="32">
+          <part name="dr22.4l"/>
+          <part name="dr23.4nm"/>
+          <part name="dr17.4dc"/>
+          <part name="dr17.4dc"/>
+      </group>
+      <group width="32">
+          <part name="dr20.4jh"/>
+          <part name="dr13.3nm"/>
+          <part name="dr15.4a"/>
+          <part name="dr15.4a"/>
+      </group>
+
+      <!-- GFX3, 64k -->
+      <group width="32">
+          <part name="dr10.4n"/>
+          <part name="dr09.4m"/>
+          <part name="dr08.4l"/>
+          <part name="dr08.4l"/>
+      </group>
+
+      <!-- spr_color_proms, 3*256b -->
+      <part name="dr30.1m"/>
+      <part name="dr31.1n"/>
+      <part name="dr29.1l"/>
+
+      <!-- chr_color_proms, 3*256b -->
+      <part name="dr25.3f"/>
+      <part name="dr26.3h"/>
+      <part name="dr27.3j"/>
+
+      <!-- fg_color_proms, 3*256b -->
+      <part name="dr25.3f"/>
+      <part name="dr26.3h"/>
+      <part name="dr27.3j"/>
+
+      <!-- spr_height_prom -->
+      <part name="dr32.5p"/>
+
+    </rom>
+</misterromdescription>
--- a/Arcade_MiST/IremM62
+++ b/Arcade_MiST/IremM62
@@ -0,0 +1,121 @@
+<misterromdescription>
+    <name>Kung Fu Master</name>
+    <mameversion>0216</mameversion>
+    <setname>kungfum</setname>
+    <manufacturer>Irem</manufacturer>
+    <rbf>iremm62</rbf>
+    <rom index="1"><part>4</part></rom>
+    <rom index="0" zip="kungfum.zip" md5="e4dd9d396dd574a11189c2183cf4cead" type="merged|nonmerged">
+      <!-- CPU1, 128k -->
+      <part name="a-4e-c.bin"/>
+      <part name="a-4d-c.bin"/>
+      <part name="a-4e-c.bin"/>
+      <part name="a-4d-c.bin"/>
+      <part name="a-4e-c.bin"/>
+      <part name="a-4d-c.bin"/>
+      <part name="a-4e-c.bin"/>
+      <part name="a-4d-c.bin"/>
+
+      <!-- SND CPU2, 64k -->
+      <part repeat="0xa000">FF</part>
+      <part name="a-3e-.bin"/>
+      <part name="a-3f-.bin"/>
+      <part name="a-3h-.bin"/>
+
+      <!-- GFX1, 128k -->
+      <group width="32">
+          <part name="g-4c-a.bin"/>
+          <part name="g-4d-a.bin"/>
+          <part name="g-4e-a.bin"/>
+          <part name="g-4e-a.bin"/>
+      </group>
+      <group width="32">
+          <part name="g-4c-a.bin"/>
+          <part name="g-4d-a.bin"/>
+          <part name="g-4e-a.bin"/>
+          <part name="g-4e-a.bin"/>
+      </group>
+      <group width="32">
+          <part name="g-4c-a.bin"/>
+          <part name="g-4d-a.bin"/>
+          <part name="g-4e-a.bin"/>
+          <part name="g-4e-a.bin"/>
+      </group>
+      <group width="32">
+          <part name="g-4c-a.bin"/>
+          <part name="g-4d-a.bin"/>
+          <part name="g-4e-a.bin"/>
+          <part name="g-4e-a.bin"/>
+      </group>
+
+      <!-- GFX2, 256k -->
+      <group width="32">
+          <part name="b-4k-.bin"/>
+          <part name="b-3n-.bin"/>
+          <part name="b-4c-.bin"/>
+          <part name="b-4c-.bin"/>
+      </group>
+      <group width="32">
+          <part name="b-4f-.bin"/>
+          <part name="b-4n-.bin"/>
+          <part name="b-4e-.bin"/>
+          <part name="b-4e-.bin"/>
+      </group>
+      <group width="32">
+          <part name="b-4l-.bin"/>
+          <part name="b-4m-.bin"/>
+          <part name="b-4d-.bin"/>
+          <part name="b-4d-.bin"/>
+      </group>
+      <group width="32">
+          <part name="b-4h-.bin"/>
+          <part name="b-3m-.bin"/>
+          <part name="b-4a-.bin"/>
+          <part name="b-4a-.bin"/>
+      </group>
+      <group width="32">
+          <part name="b-4k-.bin"/>
+          <part name="b-3n-.bin"/>
+          <part name="b-4c-.bin"/>
+          <part name="b-4c-.bin"/>
+      </group>
+      <group width="32">
+          <part name="b-4f-.bin"/>
+          <part name="b-4n-.bin"/>
+          <part name="b-4e-.bin"/>
+          <part name="b-4e-.bin"/>
+      </group>
+      <group width="32">
+          <part name="b-4l-.bin"/>
+          <part name="b-4m-.bin"/>
+          <part name="b-4d-.bin"/>
+          <part name="b-4d-.bin"/>
+      </group>
+      <group width="32">
+          <part name="b-4h-.bin"/>
+          <part name="b-3m-.bin"/>
+          <part name="b-4a-.bin"/>
+          <part name="b-4a-.bin"/>
+      </group>
+
+      <!-- GFX3, 64k -->
+      <part repeat="0x10000">FF</part>
+
+      <!-- spr_color_proms, 3*256b -->
+      <part name="b-1m-.bin"/>
+      <part name="b-1n-.bin"/>
+      <part name="b-1l-.bin"/>
+
+      <!-- chr_color_proms, 3*256b -->
+      <part name="g-1j-.bin"/>
+      <part name="g-1f-.bin"/>
+      <part name="g-1h-.bin"/>
+
+      <!-- fg_color_proms, 3*256b -->
+      <part repeat="0x300">FF</part>
+
+      <!-- spr_height_prom -->
+      <part name="b-5f-.bin"/>
+
+    </rom>       
+</misterromdescription>
--- a/Arcade_MiST/IremM62
+++ b/Arcade_MiST/IremM62
@@ -0,0 +1,131 @@
+<misterromdescription>
+    <name>Lode Runner 2</name>
+    <mameversion>0216</mameversion>
+    <setname>ldrun2</setname>
+    <manufacturer>Irem</manufacturer>
+    <rbf>iremm62</rbf>
+    <rom index="1"><part>1</part></rom>
+    <rom index="0" zip="ldrun2.zip" md5="46dbb2c6765031bd796a2c62b64c4ba2" type="merged|nonmerged">
+      <!-- CPU1, 128k -->
+      <part name="lr2-a-4e.a"/>
+      <part name="lr2-a-4d"/>
+      <part name="lr2-a-4a.a"/>
+      <part name="lr2-a-4a"/>
+      <part name="lr2-h-1c.a"/>
+      <part name="lr2-h-1d.a"/>
+      <part name="lr2-h-1d.a"/>
+      <part name="lr2-h-1d.a"/>
+
+      <part name="lr2-a-4e.a"/>
+      <part name="lr2-a-4d"/>
+      <part name="lr2-a-4a.a"/>
+      <part name="lr2-a-4a"/>
+      <part name="lr2-h-1c.a"/>
+      <part name="lr2-h-1d.a"/>
+      <part name="lr2-h-1d.a"/>
+      <part name="lr2-h-1d.a"/>
+
+      <!-- SND CPU2, 64k -->
+      <part repeat="0xa000">FF</part>
+
+      <part name="lr2-a-3e"/>
+      <part name="lr2-a-3f"/>
+      <part name="lr2-a-3h"/>
+
+      <!-- GFX1, 128k -->
+      <group width="32">
+          <part name="lr2-h-1e"/>
+          <part name="lr2-h-1j"/>
+          <part name="lr2-h-1h"/>
+          <part name="lr2-h-1h"/>
+      </group>
+      <group width="32">
+          <part name="lr2-h-1e"/>
+          <part name="lr2-h-1j"/>
+          <part name="lr2-h-1h"/>
+          <part name="lr2-h-1h"/>
+      </group>
+      <group width="32">
+          <part name="lr2-h-1e"/>
+          <part name="lr2-h-1j"/>
+          <part name="lr2-h-1h"/>
+          <part name="lr2-h-1h"/>
+      </group>
+      <group width="32">
+          <part name="lr2-h-1e"/>
+          <part name="lr2-h-1j"/>
+          <part name="lr2-h-1h"/>
+          <part name="lr2-h-1h"/>
+      </group>
+
+      <!-- GFX2, 256k -->
+      <group width="32">
+          <part name="lr2-b-4k"/>
+          <part name="lr2-b-3n"/>
+          <part name="lr2-b-4c"/>
+          <part name="lr2-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lr2-b-4f"/>
+          <part name="lr2-b-4n"/>
+          <part name="lr2-b-4e"/>
+          <part name="lr2-b-4e"/>
+      </group>
+      <group width="32">
+          <part name="lr2-b-4k"/>
+          <part name="lr2-b-3n"/>
+          <part name="lr2-b-4c"/>
+          <part name="lr2-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lr2-b-4f"/>
+          <part name="lr2-b-4n"/>
+          <part name="lr2-b-4e"/>
+          <part name="lr2-b-4e"/>
+      </group>
+      <group width="32">
+          <part name="lr2-b-4k"/>
+          <part name="lr2-b-3n"/>
+          <part name="lr2-b-4c"/>
+          <part name="lr2-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lr2-b-4f"/>
+          <part name="lr2-b-4n"/>
+          <part name="lr2-b-4e"/>
+          <part name="lr2-b-4e"/>
+      </group>
+      <group width="32">
+          <part name="lr2-b-4k"/>
+          <part name="lr2-b-3n"/>
+          <part name="lr2-b-4c"/>
+          <part name="lr2-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lr2-b-4f"/>
+          <part name="lr2-b-4n"/>
+          <part name="lr2-b-4e"/>
+          <part name="lr2-b-4e"/>
+      </group>
+
+      <!-- GFX3, 64k -->
+      <part repeat="0x10000">FF</part>
+
+      <!-- spr_color_proms, 3*256b -->
+      <part name="lr2-b-1m"/>
+      <part name="lr2-b-1n"/>
+      <part name="lr2-b-1l"/>
+
+      <!-- chr_color_proms, 3*256b -->
+      <part name="lr2-h-3m"/>
+      <part name="lr2-h-3l"/>
+      <part name="lr2-h-3n"/>
+
+      <!-- fg_color_proms, 3*256b -->
+      <part repeat="0x300">FF</part>
+
+      <!-- spr_height_prom -->
+      <part name="lr2-b-5p"/>
+
+    </rom>
+</misterromdescription>
--- a/Arcade_MiST/IremM62
+++ b/Arcade_MiST/IremM62
@@ -0,0 +1,87 @@
+<misterromdescription>
+    <name>Lode Runner 3</name>
+    <mameversion>0216</mameversion>
+    <setname>ldrun3</setname>
+    <manufacturer>Irem</manufacturer>
+    <rbf>iremm62</rbf>
+    <rom index="1"><part>2</part></rom>
+    <rom index="0" zip="ldrun3.zip" md5="a32c8e0a4927c70199174dea1600e761" type="merged|nonmerged">
+      <!-- CPU1, 128k -->
+      <part name="lr3a4eb.bin"/>
+      <part name="lr3a4db.bin"/>
+      <part name="lr3a4bb.bin"/>
+      <part name="lr3a4bb.bin"/>
+
+      <part name="lr3a4eb.bin"/>
+      <part name="lr3a4db.bin"/>
+      <part name="lr3a4bb.bin"/>
+      <part name="lr3a4bb.bin"/>
+
+      <!-- SND CPU2, 64k -->
+      <part name="lr3-a-3d"/>
+      <part name="lr3-a-3f"/>
+
+      <part name="lr3-a-3d"/>
+      <part name="lr3-a-3f"/>
+
+      <!-- GFX1, 128k -->
+      <group width="32">
+          <part name="lr3-n-2a"/>
+          <part name="lr3-n-2c"/>
+          <part name="lr3-n-2b"/>
+          <part name="lr3-n-2b"/>
+      </group>
+      <group width="32">
+          <part name="lr3-n-2a"/>
+          <part name="lr3-n-2c"/>
+          <part name="lr3-n-2b"/>
+          <part name="lr3-n-2b"/>
+      </group>
+
+      <!-- GFX2, 256k -->
+      <group width="32">
+          <part name="lr3b4kb.bin"/>
+          <part name="lr3b3nb.bin"/>
+          <part name="snxb4cb.bin"/>
+          <part name="snxb4cb.bin"/>
+      </group>
+      <group width="32">
+          <part name="snxb4fb.bin"/>
+          <part name="snxb4nb.bin"/>
+          <part name="snxb4eb.bin"/>
+          <part name="snxb4eb.bin"/>
+      </group>
+      <group width="32">
+          <part name="lr3b4kb.bin"/>
+          <part name="lr3b3nb.bin"/>
+          <part name="snxb4cb.bin"/>
+          <part name="snxb4cb.bin"/>
+      </group>
+      <group width="32">
+          <part name="snxb4fb.bin"/>
+          <part name="snxb4nb.bin"/>
+          <part name="snxb4eb.bin"/>
+          <part name="snxb4eb.bin"/>
+      </group>
+
+      <!-- GFX3, 64k -->
+      <part repeat="0x10000">FF</part>
+
+      <!-- spr_color_proms, 3*256b -->
+      <part name="lr3-b-1m"/>
+      <part name="lr3-b-1n"/>
+      <part name="lr3-b-1l"/>
+
+      <!-- chr_color_proms, 3*256b -->
+      <part name="lr3-n-2l"/>
+      <part name="lr3-n-2k"/>
+      <part name="lr3-n-2m"/>
+
+      <!-- fg_color_proms, 3*256b -->
+      <part repeat="0x300">FF</part>
+
+      <!-- spr_height_prom -->
+      <part name="lr3-b-5p"/>
+
+    </rom>
+</misterromdescription>
--- a/Arcade_MiST/IremM62
+++ b/Arcade_MiST/IremM62
@@ -0,0 +1,85 @@
+<misterromdescription>
+    <name>Lode Runner 4</name>
+    <mameversion>0216</mameversion>
+    <setname>ldrun4</setname>
+    <manufacturer>Irem</manufacturer>
+    <rbf>iremm62</rbf>
+    <rom index="1"><part>3</part></rom>
+    <rom index="0" zip="ldrun4.zip" md5="cd633975a81980cefe104543024cc7ee" type="merged|nonmerged">
+      <!-- CPU1, 128k -->
+      <part name="lr4-a-4e"/>
+      <part name="lr4-a-4d.c"/>
+      <part name="lr4-v-4k"/>
+
+      <part name="lr4-a-4e"/>
+      <part name="lr4-a-4d.c"/>
+      <part name="lr4-v-4k"/>
+
+      <!-- SND CPU2, 64k -->
+      <part name="lr4-a-3d"/>
+      <part name="lr4-a-3f"/>
+
+      <part name="lr4-a-3d"/>
+      <part name="lr4-a-3f"/>
+
+      <!-- GFX1, 128k -->
+      <group width="32">
+          <part name="lr4-v-2b"/>
+          <part name="lr4-v-2d"/>
+          <part name="lr4-v-2c"/>
+          <part name="lr4-v-2c"/>
+      </group>
+      <group width="32">
+          <part name="lr4-v-2b"/>
+          <part name="lr4-v-2d"/>
+          <part name="lr4-v-2c"/>
+          <part name="lr4-v-2c"/>
+      </group>
+
+      <!-- GFX2, 256k -->
+      <group width="32">
+          <part name="lr4-b-4k"/>
+          <part name="lr4-b-3n"/>
+          <part name="lr4-b-4c"/>
+          <part name="lr4-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lr4-b-4f"/>
+          <part name="lr4-b-4n"/>
+          <part name="lr4-b-4e"/>
+          <part name="lr4-b-4e"/>
+      </group>
+      <group width="32">
+          <part name="lr4-b-4k"/>
+          <part name="lr4-b-3n"/>
+          <part name="lr4-b-4c"/>
+          <part name="lr4-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lr4-b-4f"/>
+          <part name="lr4-b-4n"/>
+          <part name="lr4-b-4e"/>
+          <part name="lr4-b-4e"/>
+      </group>
+
+      <!-- GFX3, 64k -->
+      <part repeat="0x10000">FF</part>
+
+      <!-- spr_color_proms, 3*256b -->
+      <part name="lr4-b-1m"/>
+      <part name="lr4-b-1n"/>
+      <part name="lr4-b-1l"/>
+
+      <!-- chr_color_proms, 3*256b -->
+      <part name="lr4-v-1m"/>
+      <part name="lr4-v-1n"/>
+      <part name="lr4-v-1p"/>
+
+      <!-- fg_color_proms, 3*256b -->
+      <part repeat="0x300">FF</part>
+
+      <!-- spr_height_prom -->
+      <part name="lr4-b-5p"/>
+
+    </rom>
+</misterromdescription>
--- a/Arcade_MiST/IremM62
+++ b/Arcade_MiST/IremM62
@@ -0,0 +1,133 @@
+<misterromdescription>
+    <name>Lode Runner</name>
+    <mameversion>0216</mameversion>
+    <setname>ldrun</setname>
+    <manufacturer>Irem</manufacturer>
+    <rbf>iremm62</rbf>
+    <rom index="1"><part>0</part></rom>
+    <rom index="0" zip="ldrun.zip" md5="dbd20cd8f5d2555911090e62e4621920" type="merged|nonmerged">
+      <!-- CPU1, 128k -->
+      <part name="lr-a-4e"/>
+      <part name="lr-a-4d"/>
+      <part name="lr-a-4b"/>
+      <part name="lr-a-4a"/>
+      <part name="lr-a-4e"/>
+      <part name="lr-a-4d"/>
+      <part name="lr-a-4b"/>
+      <part name="lr-a-4a"/>
+      <part name="lr-a-4e"/>
+      <part name="lr-a-4d"/>
+      <part name="lr-a-4b"/>
+      <part name="lr-a-4a"/>
+      <part name="lr-a-4e"/>
+      <part name="lr-a-4d"/>
+      <part name="lr-a-4b"/>
+      <part name="lr-a-4a"/>
+
+      <!-- SND CPU2, 64k -->
+      <part name="lr-a-3f"/>
+      <part name="lr-a-3h"/>
+      <part name="lr-a-3f"/>
+      <part name="lr-a-3h"/>
+      <part name="lr-a-3f"/>
+      <part name="lr-a-3h"/>
+      <part name="lr-a-3f"/>
+      <part name="lr-a-3h"/>
+
+      <!-- GFX1, 128k -->
+      <group width="32">
+          <part name="lr-e-2d"/>
+          <part name="lr-e-2j"/>
+          <part name="lr-e-2f"/>
+          <part name="lr-e-2f"/>
+      </group>
+      <group width="32">
+          <part name="lr-e-2d"/>
+          <part name="lr-e-2j"/>
+          <part name="lr-e-2f"/>
+          <part name="lr-e-2f"/>
+      </group>
+      <group width="32">
+          <part name="lr-e-2d"/>
+          <part name="lr-e-2j"/>
+          <part name="lr-e-2f"/>
+          <part name="lr-e-2f"/>
+      </group>
+      <group width="32">
+          <part name="lr-e-2d"/>
+          <part name="lr-e-2j"/>
+          <part name="lr-e-2f"/>
+          <part name="lr-e-2f"/>
+      </group>
+
+      <!-- GFX2, 256k -->
+      <group width="32">
+          <part name="lr-b-4k"/>
+          <part name="lr-b-3n"/>
+          <part name="lr-b-4c"/>
+          <part name="lr-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lr-b-4k"/>
+          <part name="lr-b-3n"/>
+          <part name="lr-b-4c"/>
+          <part name="lr-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lr-b-4k"/>
+          <part name="lr-b-3n"/>
+          <part name="lr-b-4c"/>
+          <part name="lr-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lr-b-4k"/>
+          <part name="lr-b-3n"/>
+          <part name="lr-b-4c"/>
+          <part name="lr-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lr-b-4k"/>
+          <part name="lr-b-3n"/>
+          <part name="lr-b-4c"/>
+          <part name="lr-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lr-b-4k"/>
+          <part name="lr-b-3n"/>
+          <part name="lr-b-4c"/>
+          <part name="lr-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lr-b-4k"/>
+          <part name="lr-b-3n"/>
+          <part name="lr-b-4c"/>
+          <part name="lr-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lr-b-4k"/>
+          <part name="lr-b-3n"/>
+          <part name="lr-b-4c"/>
+          <part name="lr-b-4c"/>
+      </group>
+
+      <!-- GFX3, 64k -->
+      <part repeat="0x10000">FF</part>
+
+      <!-- spr_color_proms, 3*256b -->
+      <part name="lr-b-1m"/>
+      <part name="lr-b-1n"/>
+      <part name="lr-b-1l"/>
+
+      <!-- chr_color_proms, 3*256b -->
+      <part name="lr-e-3m"/>
+      <part name="lr-e-3l"/>
+      <part name="lr-e-3n"/>
+
+      <!-- fg_color_proms, 3*256b -->
+      <part repeat="0x300">FF</part>
+
+      <!-- spr_height_prom -->
+      <part name="lr-b-5p"/>
+
+    </rom>
+</misterromdescription>
--- a/Arcade_MiST/IremM62
+++ b/Arcade_MiST/IremM62
@@ -0,0 +1,131 @@
+<misterromdescription>
+    <name>Lot Lot</name>
+    <mameversion>0216</mameversion>
+    <setname>lotlot</setname>
+    <manufacturer>Irem</manufacturer>
+    <rbf>iremm62</rbf>
+    <rom index="1"><part>8</part></rom>
+    <rom index="0" zip="lotlot.zip" md5="dbd20cd8f5d2555911090e62e4621920" type="merged|nonmerged">
+      <!-- CPU1, 128k -->
+      <part name="lot-a-4e"/>
+      <part name="lot-a-4d"/>
+      <part name="lot-a-4e"/>
+      <part name="lot-a-4d"/>
+      <part name="lot-a-4e"/>
+      <part name="lot-a-4d"/>
+      <part name="lot-a-4e"/>
+      <part name="lot-a-4d"/>
+
+      <!-- SND CPU2, 64k -->
+      <part repeat="8" name="lot-a-3h"/>
+
+      <!-- GFX1, 128k -->
+      <group width="32">
+          <part name="lot-k-4a"/>
+          <part name="lot-k-4c"/>
+          <part name="lot-k-4b"/>
+          <part name="lot-k-4b"/>
+      </group>
+      <group width="32">
+          <part name="lot-k-4a"/>
+          <part name="lot-k-4c"/>
+          <part name="lot-k-4b"/>
+          <part name="lot-k-4b"/>
+      </group>
+      <group width="32">
+          <part name="lot-k-4a"/>
+          <part name="lot-k-4c"/>
+          <part name="lot-k-4b"/>
+          <part name="lot-k-4b"/>
+      </group>
+      <group width="32">
+          <part name="lot-k-4a"/>
+          <part name="lot-k-4c"/>
+          <part name="lot-k-4b"/>
+          <part name="lot-k-4b"/>
+      </group>
+
+      <!-- GFX2, 256k -->
+      <group width="32">
+          <part name="lot-b-4k"/>
+          <part name="lot-b-3n"/>
+          <part name="lot-b-4c"/>
+          <part name="lot-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lot-b-4k"/>
+          <part name="lot-b-3n"/>
+          <part name="lot-b-4c"/>
+          <part name="lot-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lot-b-4k"/>
+          <part name="lot-b-3n"/>
+          <part name="lot-b-4c"/>
+          <part name="lot-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lot-b-4k"/>
+          <part name="lot-b-3n"/>
+          <part name="lot-b-4c"/>
+          <part name="lot-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lot-b-4k"/>
+          <part name="lot-b-3n"/>
+          <part name="lot-b-4c"/>
+          <part name="lot-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lot-b-4k"/>
+          <part name="lot-b-3n"/>
+          <part name="lot-b-4c"/>
+          <part name="lot-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lot-b-4k"/>
+          <part name="lot-b-3n"/>
+          <part name="lot-b-4c"/>
+          <part name="lot-b-4c"/>
+      </group>
+      <group width="32">
+          <part name="lot-b-4k"/>
+          <part name="lot-b-3n"/>
+          <part name="lot-b-4c"/>
+          <part name="lot-b-4c"/>
+      </group>
+
+      <!-- GFX3, 64k -->
+      <group width="32">
+          <part name="lot-k-4p"/>
+          <part name="lot-k-4l"/>
+          <part name="lot-k-4n"/>
+          <part name="lot-k-4n"/>
+      </group>
+      <group width="32">
+          <part name="lot-k-4p"/>
+          <part name="lot-k-4l"/>
+          <part name="lot-k-4n"/>
+          <part name="lot-k-4n"/>
+      </group>
+
+      <!-- spr_color_proms, 3*256b -->
+      <part name="lot-b-1m"/>
+      <part name="lot-b-1n"/>
+      <part name="lot-b-1l"/>
+
+      <!-- chr_color_proms, 3*256b -->
+      <part name="lot-k-2f"/>
+      <part name="lot-k-2e"/>
+      <part name="lot-k-2d"/>
+
+      <!-- fg_color_proms, 3*256b -->
+      <part name="lot-k-2l"/>
+      <part name="lot-k-2k"/>
+      <part name="lot-k-2j"/>
+
+      <!-- spr_height_prom -->
+      <part name="lot-b-5p"/>
+
+    </rom>
+</misterromdescription>
--- a/Hardware/meta/Spelunker
+++ b/Hardware/meta/Spelunker
@@ -0,0 +1,83 @@
+<misterromdescription>
+    <name>Spelunker 2</name>
+    <mameversion>0216</mameversion>
+    <setname>spelunk2</setname>
+    <manufacturer>Irem</manufacturer>
+    <rbf>iremm62</rbf>
+    <rom index="1"><part>0A</part></rom>
+    <rom index="0" zip="spelunk2.zip" md5="5052a1aaf3f39b0a40babfcc00e9652d" type="merged|nonmerged">
+      <!-- CPU1, 128k -->
+      <part name="sp2-a.4e"/>
+      <part name="sp2-a.4d"/>
+
+      <part name="sp2-r.7b"/>
+      <part repeat="0x4000">FF</part>
+
+      <part name="sp2-r.7d"/>
+      <part name="sp2-r.7c"/>
+
+      <!-- SND CPU2, 64k -->
+      <part repeat="0x8000">FF</part>
+      <part name="sp2-a.3d"/>
+      <part name="sp2-a.3f"/>
+
+      <!-- GFX1, 128k -->
+      <group width="32">
+          <part name="sp2-r.1d"/>
+          <part name="sp2-r.3b"/>
+          <part name="sp2-r.1b"/>
+          <part name="sp2-r.1b"/>
+      </group>
+
+      <!-- GFX2, 256k -->
+      <group width="32">
+          <part name="sp2-b.4k"/>
+          <part name="sp2-b.3n"/>
+          <part name="sp2-b.4c"/>
+          <part name="sp2-b.4c"/>
+      </group>
+      <group width="32">
+          <part name="sp2-b.4f"/>
+          <part name="sp2-b.4n"/>
+          <part name="sp2-b.4e"/>
+          <part name="sp2-b.4e"/>
+      </group>
+      <group width="32">
+          <part name="sp2-b.4k"/>
+          <part name="sp2-b.3n"/>
+          <part name="sp2-b.4c"/>
+          <part name="sp2-b.4c"/>
+      </group>
+      <group width="32">
+          <part name="sp2-b.4f"/>
+          <part name="sp2-b.4n"/>
+          <part name="sp2-b.4e"/>
+          <part name="sp2-b.4e"/>
+      </group>
+
+      <!-- GFX3, 64k -->
+      <group width="32">
+          <part name="sp2-r.4p"/>
+          <part name="sp2-r.4m"/>
+          <part name="sp2-r.4l"/>
+          <part name="sp2-r.4l"/>
+      </group>
+
+      <!-- spr_color_proms, 3*256b -->
+      <part name="sp2-b.1m"/>
+      <part name="sp2-b.1n"/>
+      <part name="sp2-b.1l"/>
+
+      <!-- chr_color_proms, 3*256b -->
+      <part name="sp2-r.1k"/>
+      <part name="sp2-r.2k"/>
+
+      <!-- fg_color_proms, 3*256b -->
+      <part name="sp2-r.2j"/>
+      <part repeat="0x200">FF</part>
+
+      <!-- spr_height_prom -->
+      <part name="sp2-b.5p"/>
+
+    </rom>
+</misterromdescription>
--- a/Hardware/meta/Spelunker.mra
+++ b/Hardware/meta/Spelunker.mra
@@ -0,0 +1,89 @@
+<misterromdescription>
+    <name>Spelunker</name>
+    <mameversion>0216</mameversion>
+    <setname>spelunkr</setname>
+    <manufacturer>Irem</manufacturer>
+    <rbf>iremm62</rbf>
+    <rom index="1"><part>9</part></rom>
+    <rom index="0" zip="spelunkr.zip" md5="ec64e30638077a75ff9f6698494057fc" type="merged|nonmerged">
+      <!-- CPU1, 128k -->
+      <part name="spra.4e"/>
+      <part name="spra.4d"/>
+      <part repeat="0x8000">FF</part>
+      <part name="sprm.7c"/>
+      <part name="sprm.7b"/>
+      <part repeat="0x8000">FF</part>
+
+      <!-- SND CPU2, 64k -->
+      <part repeat="0x8000">FF</part>
+      <part name="spra.3d"/>
+      <part name="spra.3f"/>
+
+      <!-- GFX1, 128k -->
+      <group width="32">
+          <part name="sprm.1d"/>
+          <part name="sprm.3c"/>
+          <part name="sprm.1c"/>
+          <part name="sprm.1c"/>
+      </group>
+      <group width="32">
+          <part name="sprm.1e"/>
+          <part name="sprm.3b"/>
+          <part name="sprm.1b"/>
+          <part name="sprm.1b"/>
+      </group>
+
+      <!-- GFX2, 256k -->
+      <group width="32">
+          <part name="sprb.4k"/>
+          <part name="sprb.3p"/>
+          <part name="sprb.4c"/>
+          <part name="sprb.4c"/>
+      </group>
+      <group width="32">
+          <part name="sprb.4f"/>
+          <part name="sprb.4p"/>
+          <part name="sprb.4e"/>
+          <part name="sprb.4e"/>
+      </group>
+      <group width="32">
+          <part name="sprb.4k"/>
+          <part name="sprb.3p"/>
+          <part name="sprb.4c"/>
+          <part name="sprb.4c"/>
+      </group>
+      <group width="32">
+          <part name="sprb.4f"/>
+          <part name="sprb.4p"/>
+          <part name="sprb.4e"/>
+          <part name="sprb.4e"/>
+      </group>
+
+      <!-- GFX3, 64k -->
+      <group width="32">
+          <part name="sprm.4m"/>
+          <part name="sprm.4l"/>
+          <part name="sprm.4p"/>
+          <part name="sprm.4p"/>
+      </group>
+
+      <!-- spr_color_proms, 3*256b -->
+      <part name="sprb.1m"/>
+      <part name="sprb.1n"/>
+      <part name="sprb.1l"/>
+
+      <!-- chr_color_proms, 3*256b -->
+      <part name="sprm.2k"/>
+      <part name="sprm.2j"/>
+      <part name="sprm.2h"/>
+
+      <!-- fg_color_proms, 3*256b -->
+      <part name="sprm.2k"/>
+      <part name="sprm.2j"/>
+      <part name="sprm.2h"/>
+
+      <!-- spr_height_prom -->
+      <part name="sprb.5p"/>
+
+    </rom>
+</misterromdescription>
--- a/Hardware/meta/Youjyudn.mra
+++ b/Hardware/meta/Youjyudn.mra
@@ -0,0 +1,83 @@
+<misterromdescription>
+    <name>Youjyudn</name>
+    <mameversion>0216</mameversion>
+    <setname>youjyudn</setname>
+    <manufacturer>Irem</manufacturer>
+    <rbf>iremm62</rbf>
+    <rom index="1"><part>0B</part></rom>
+    <rom index="0" zip="youjyudn.zip" md5="88142ed9adb6ffff9643cc7fa6bae82b" type="merged|nonmerged">
+      <!-- CPU1, 128k -->
+      <part name="yju_a4eb.bin"/>
+      <part name="yju_a4db.bin"/>
+      <part repeat="0x8000">FF</part>
+
+      <part name="yju_p4cb.0"/>
+      <part name="yju_p4eb.1"/>
+      <part repeat="0x8000">FF</part>
+
+      <!-- SND CPU2, 64k -->
+      <part repeat="0xC000">FF</part>
+      <part name="yju_a3fb.bin"/>
+
+      <!-- GFX1, 128k -->
+      <group width="32">
+          <part name="yju_p3bb.0"/>
+          <part name="yju_p1bb.1"/>
+          <part name="yju_p1cb.2"/>
+          <part name="yju_p1cb.2"/>
+      </group>
+
+      <!-- GFX2, 256k -->
+      <group width="32">
+          <part name="yju_b4ka.00"/>
+          <part name="yju_b3na.10"/>
+          <part name="yju_b4ca.20"/>
+          <part name="yju_b4ca.20"/>
+      </group>
+      <group width="32">
+          <part name="yju_b4fa.01"/>
+          <part name="yju_b4na.11"/>
+          <part name="yju_b4ea.21"/>
+          <part name="yju_b4ea.21"/>
+      </group>
+      <group width="32">
+          <part name="yju_b4ka.00"/>
+          <part name="yju_b3na.10"/>
+          <part name="yju_b4ca.20"/>
+          <part name="yju_b4ca.20"/>
+      </group>
+      <group width="32">
+          <part name="yju_b4fa.01"/>
+          <part name="yju_b4na.11"/>
+          <part name="yju_b4ea.21"/>
+          <part name="yju_b4ea.21"/>
+      </group>
+
+      <!-- GFX3, 64k -->
+      <group width="32">
+          <part name="yju_p4pb.0"/>
+          <part name="yju_p4mb.1"/>
+          <part name="yju_p4lb.2"/>
+          <part name="yju_p4lb.2"/>
+      </group>
+
+      <!-- spr_color_proms, 3*256b -->
+      <part name="yju_b1ma.r"/>
+      <part name="yju_b1na.g"/>
+      <part name="yju_b1la.b"/>
+
+      <!-- chr_color_proms, 3*256b -->
+      <part name="yju_p2jb.bpr"/>
+      <part name="yju_p2kb.bpr"/>
+      <part name="yju_p2hb.bpr"/>
+
+      <!-- fg_color_proms, 3*256b -->
+      <part name="yju_p2jb.bpr"/>
+      <part name="yju_p2kb.bpr"/>
+      <part name="yju_p2hb.bpr"/>
+
+      <!-- spr_height_prom -->
+      <part name="yju_b-5p.bpr"/>
+
+    </rom>
+</misterromdescription>
--- a/Hardware/LodeRunner_MiST/rtl/Graphics.VHD
+++ b/Hardware/LodeRunner_MiST/rtl/Graphics.VHD
@@ -9,10 +9,16 @@ use work.video_controller_pkg.all;
 use work.sprite_pkg.all;
 --use work.project_pkg.all;
 use work.platform_pkg.all;
+use work.platform_variant_pkg.all;

 entity Graphics is
  port
  (
+    hwsel           : in HWSEL_t;
+    hires           : in std_logic;
+    palmode         : in std_logic;
+    sprite_prom     : in prom_a(0 to 31);
+
    bitmap_ctl_i    : in to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
    bitmap_ctl_o    : out from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
    tilemap_ctl_i   : in to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
@@ -21,20 +27,21 @@ entity Graphics is
    sprite_reg_i    : in to_SPRITE_REG_t;
    sprite_ctl_i    : in to_SPRITE_CTL_t;
    sprite_ctl_o    : out from_SPRITE_CTL_t;
-		spr0_hit				: out std_logic;
-    
+    spr0_hit        : out std_logic;
+    sprite_rgb      : in RGB_t;
+
    graphics_i      : in to_GRAPHICS_t;
    graphics_o      : out from_GRAPHICS_t;

-		video_i					: in from_VIDEO_t;
-		video_o					: out to_VIDEO_t
+    video_i         : in from_VIDEO_t;
+    video_o         : out to_VIDEO_t
  );

 end Graphics;

 architecture SYN of Graphics is

-	alias clk 					    : std_logic is video_i.clk;
+  alias clk               : std_logic is video_i.clk;

  signal from_video_ctl   : from_VIDEO_CTL_t;
  signal bitmap_ctl_o_s   : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
@@ -43,21 +50,21 @@ architecture SYN of Graphics is
  signal sprite_pri       : std_logic;


-	signal rgb_data			    : RGB_t;
+  signal rgb_data         : RGB_t;
  -- before OSD is mixed in
  signal video_o_s        : to_VIDEO_t;
-  
+
 begin

  -- dodgy OSD transparency...
-	video_o.clk <= video_o_s.clk;
+  video_o.clk <= video_o_s.clk;
  video_o.rgb.r <= 	video_o_s.rgb.r;
  video_o.rgb.g <=  video_o_s.rgb.g;
  video_o.rgb.b <= 	video_o_s.rgb.b;
-	video_o.hsync <= video_o_s.hsync;
-	video_o.vsync <= video_o_s.vsync;
-	video_o.hblank <= video_o_s.hblank;
-	video_o.vblank <= video_o_s.vblank;
+  video_o.hsync <= video_o_s.hsync;
+  video_o.vsync <= video_o_s.vsync;
+  video_o.hblank <= video_o_s.hblank;
+  video_o.vblank <= video_o_s.vblank;

  graphics_o.y <= from_video_ctl.y;
  -- should this be the 'real' vblank or the 'active' vblank?
@@ -65,38 +72,24 @@ begin
  graphics_o.hblank <= video_o_s.hblank;
  graphics_o.vblank <= video_o_s.vblank;
  --graphics_o.vblank <= from_video_ctl.vblank;
-    
-  pace_video_controller_inst : entity work.pace_video_controller
-    generic map
-    (
-      CONFIG		  => PACE_VIDEO_CONTROLLER_TYPE,
-      DELAY       => PACE_VIDEO_PIPELINE_DELAY,
-      H_SIZE      => PACE_VIDEO_H_SIZE,
-      V_SIZE      => PACE_VIDEO_V_SIZE,
-      L_CROP      => PACE_VIDEO_L_CROP,
-      R_CROP      => PACE_VIDEO_R_CROP,
-      H_SCALE     => PACE_VIDEO_H_SCALE,
-      V_SCALE     => PACE_VIDEO_V_SCALE,
-      H_SYNC_POL  => PACE_VIDEO_H_SYNC_POLARITY,
-      V_SYNC_POL  => PACE_VIDEO_V_SYNC_POLARITY,
-      BORDER_RGB  => PACE_VIDEO_BORDER_RGB
-    )
+
+  iremm62_video_controller_inst : entity work.iremm62_video_controller
    port map
    (
      -- clocking etc
      video_i         => video_i,
-      
-			-- register interface
-			reg_i.h_scale	=> "000",
-			reg_i.v_scale 	=> "000",
+      hwsel           => hwsel,
+      palmode         => palmode,
+      hires           => hires,
+
      -- video data signals (in)
-      rgb_i		    		=> rgb_data,
+      rgb_i           => rgb_data,

      -- video control signals (out)
      video_ctl_o     => from_video_ctl,

      -- VGA signals (out)
-      video_o     		=> video_o_s
+      video_o         => video_o_s
    );

  pace_video_mixer_inst : entity work.pace_video_mixer
@@ -104,7 +97,7 @@ begin
    (
        bitmap_ctl_o  => bitmap_ctl_o_s,
        tilemap_ctl_o => tilemap_ctl_o_s,
-        sprite_rgb    => sprite_ctl_o_s.rgb,
+        sprite_rgb    => sprite_rgb,
        sprite_set    => sprite_ctl_o_s.set,
        sprite_pri    => sprite_pri,
        
@@ -113,141 +106,148 @@ begin
        rgb_o         => rgb_data
    );
    
-	GEN_NO_BITMAPS : if PACE_VIDEO_NUM_BITMAPS = 0 generate
+  GEN_NO_BITMAPS : if PACE_VIDEO_NUM_BITMAPS = 0 generate
    --bitmap_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0');
-	end generate GEN_NO_BITMAPS;
-	
-	GEN_BITMAP_1 : if PACE_VIDEO_NUM_BITMAPS > 0 generate
-	
-	  forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_1)
+  end generate GEN_NO_BITMAPS;
+
+  GEN_BITMAP_1 : if PACE_VIDEO_NUM_BITMAPS > 0 generate
+
+    forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_1)
      generic map
      (
        DELAY         => PACE_VIDEO_PIPELINE_DELAY
      )
-	    port map
-	    (
-				reset					=> video_i.reset,
-				
-				video_ctl     => from_video_ctl,
+      port map
+      (
+        reset         => video_i.reset,

-	      ctl_i         => bitmap_ctl_i(1),
-	      ctl_o         => bitmap_ctl_o_s(1),
+        video_ctl     => from_video_ctl,
+
+        ctl_i         => bitmap_ctl_i(1),
+        ctl_o         => bitmap_ctl_o_s(1),

        graphics_i    => graphics_i
-	    );
-		end generate GEN_BITMAP_1;
+      );
+  end generate GEN_BITMAP_1;

-	GEN_BITMAP_2 : if PACE_VIDEO_NUM_BITMAPS > 1 generate
+  GEN_BITMAP_2 : if PACE_VIDEO_NUM_BITMAPS > 1 generate

-	  forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_2)
+    forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_2)
      generic map
      (
        DELAY         => PACE_VIDEO_PIPELINE_DELAY
      )
-	    port map
-	    (
-				reset					=> video_i.reset,
-				
-				video_ctl     => from_video_ctl,
+      port map
+      (
+        reset         => video_i.reset,

-	      ctl_i         => bitmap_ctl_i(2),
-	      ctl_o         => bitmap_ctl_o_s(2),
+        video_ctl     => from_video_ctl,
+
+        ctl_i         => bitmap_ctl_i(2),
+        ctl_o         => bitmap_ctl_o_s(2),

        graphics_i    => graphics_i
-	    );
+     );
      
  end generate GEN_BITMAP_2;

-	GEN_BITMAP_3 : if PACE_VIDEO_NUM_BITMAPS > 2 generate
+  GEN_BITMAP_3 : if PACE_VIDEO_NUM_BITMAPS > 2 generate

-	  forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_3)
+    forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_3)
      generic map
      (
        DELAY         => PACE_VIDEO_PIPELINE_DELAY
      )
-	    port map
-	    (
-				reset					=> video_i.reset,
-				
-				video_ctl     => from_video_ctl,
+      port map
+      (
+        reset         => video_i.reset,

-	      ctl_i         => bitmap_ctl_i(3),
-	      ctl_o         => bitmap_ctl_o_s(3),
+        video_ctl     => from_video_ctl,
+
+        ctl_i         => bitmap_ctl_i(3),
+        ctl_o         => bitmap_ctl_o_s(3),

        graphics_i    => graphics_i
-	    );
+      );
      
  end generate GEN_BITMAP_3;
  
  bitmap_ctl_o <= bitmap_ctl_o_s;
  
-	GEN_NO_TILEMAPS : if PACE_VIDEO_NUM_TILEMAPS = 0 generate
+  GEN_NO_TILEMAPS : if PACE_VIDEO_NUM_TILEMAPS = 0 generate
    --tilemap_ctl_o_s(1) <= ((others => '0'), (others => '0'), (others => '0'), 
    --                      (others => (others => '0')), '0');
-	end generate GEN_NO_TILEMAPS;
-	
-	GEN_TILEMAP_1 : if PACE_VIDEO_NUM_TILEMAPS > 0 generate
-	
-	  foreground_mapctl_inst : entity work.tilemapCtl(TILEMAP_1)
+  end generate GEN_NO_TILEMAPS;
+
+  GEN_TILEMAP_1 : if PACE_VIDEO_NUM_TILEMAPS > 0 generate
+
+    foreground_mapctl_inst : entity work.tilemapCtl(TILEMAP_1)
      generic map
      (
        DELAY         => PACE_VIDEO_PIPELINE_DELAY
      )
-	    port map
-	    (
-				reset					=> video_i.reset,
-				
-				video_ctl     => from_video_ctl,
+      port map
+      (
+        reset         => video_i.reset,
+        hwsel         => hwsel,
+        hires         => hires,

-				ctl_i         => tilemap_ctl_i(1),
-				ctl_o         => tilemap_ctl_o_s(1),
+        video_ctl     => from_video_ctl,
+
+        ctl_i         => tilemap_ctl_i(1),
+        ctl_o         => tilemap_ctl_o_s(1),

        graphics_i    => graphics_i
-	    );
+      );

-		end generate GEN_TILEMAP_1;
+  end generate GEN_TILEMAP_1;

-	GEN_TILEMAP_2 : if PACE_VIDEO_NUM_TILEMAPS > 1 generate
-	
-	  background_mapctl_inst : entity work.tilemapCtl(TILEMAP_2)
+  GEN_TILEMAP_2 : if PACE_VIDEO_NUM_TILEMAPS > 1 generate
+
+    background_mapctl_inst : entity work.tilemapCtl(TILEMAP_2)
      generic map
      (
        DELAY         => PACE_VIDEO_PIPELINE_DELAY
      )
-	    port map
-	    (
-				reset					=> video_i.reset,
-				
-				video_ctl     => from_video_ctl,
+      port map
+      (
+        reset         => video_i.reset,
+        hwsel         => hwsel,
+        hires         => hires,

-				ctl_i         => tilemap_ctl_i(2),
-				ctl_o         => tilemap_ctl_o_s(2),
+        video_ctl     => from_video_ctl,
+
+        ctl_i         => tilemap_ctl_i(2),
+        ctl_o         => tilemap_ctl_o_s(2),

        graphics_i    => graphics_i
-	    );
+      );

-		end generate GEN_TILEMAP_2;
+  end generate GEN_TILEMAP_2;
    
  tilemap_ctl_o <= tilemap_ctl_o_s;

-	GEN_NO_SPRITES : if PACE_VIDEO_NUM_SPRITES = 0 generate
-    sprite_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0');
+  GEN_NO_SPRITES : if PACE_VIDEO_NUM_SPRITES = 0 generate
+    sprite_ctl_o_s <= ((others => '0'), '0', (others => '0'));
    sprite_pri <= '0';
    spr0_hit <= '0';
-	end generate GEN_NO_SPRITES;
-	
-	GEN_SPRITES : if PACE_VIDEO_NUM_SPRITES > 0 generate
-	
-		sprites_inst : sprite_array
+  end generate GEN_NO_SPRITES;
+
+  GEN_SPRITES : if PACE_VIDEO_NUM_SPRITES > 0 generate
+
+    sprites_inst : sprite_array
      generic map
      (
        N_SPRITES     => PACE_VIDEO_NUM_SPRITES,
        DELAY         => PACE_VIDEO_PIPELINE_DELAY
      )
-			port map
-			(
-				reset				  => video_i.reset,
-  
+      port map
+      (
+        reset         => video_i.reset,
+        sprite_prom   => sprite_prom,
+
+        hwsel         => hwsel,
+        hires         => hires,
        -- register interface
        reg_i         => sprite_reg_i,

@@ -256,18 +256,17 @@ begin

        graphics_i    => graphics_i,

-				row_a         => sprite_ctl_o_s.a,
-				row_d         => sprite_ctl_i.d,
-				
-				rgb					  => sprite_ctl_o_s.rgb,
-				set           => sprite_ctl_o_s.set,
-				pri           => sprite_pri,
-				spr0_set	    => spr0_hit
-			);
+        row_a         => sprite_ctl_o_s.a,
+        row_d         => sprite_ctl_i.d,

-	end generate GEN_SPRITES;
+        pal_a         => sprite_ctl_o_s.pal_a,
+        set           => sprite_ctl_o_s.set,
+        pri           => sprite_pri,
+        spr0_set      => spr0_hit
+      );
+
+  end generate GEN_SPRITES;

  sprite_ctl_o <= sprite_ctl_o_s;

-
 end SYN;
--- a/Hardware/LodeRunner_MiST/rtl/Inputs.VHD
+++ b/Hardware/LodeRunner_MiST/rtl/Inputs.VHD
@@ -5,20 +5,20 @@ library work;
 use work.pace_pkg.all;

 entity inputs is
-	generic
-	(
+  generic
+  (
    NUM_DIPS        : integer := 8;
-		NUM_INPUTS 			: integer := 2;
-		CLK_1US_DIV			: natural := 30
-	);
+    NUM_INPUTS      : integer := 2;
+    CLK_1US_DIV     : natural := 30
+  );
  port
  (
    clk             : in std_logic;                               
    reset           : in std_logic;                                                          
-		jamma		        : in from_JAMMA_t;
-		
-		dips		        : in std_logic_vector(NUM_DIPS-1 downto 0);
-		inputs	        : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1)
+    jamma           : in from_JAMMA_t;
+
+    dips            : in std_logic_vector(NUM_DIPS-1 downto 0);
+    inputs          : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1)
  );
 end entity inputs;

@@ -33,19 +33,18 @@ begin


  inputmapper_inst : entity work.inputmapper
-		generic map
-		(
+    generic map
+    (
      NUM_DIPS    => NUM_DIPS,
-			NUM_INPUTS	=> NUM_INPUTS
-		)
+      NUM_INPUTS  => NUM_INPUTS
+    )
    port map
    (
      clk       => clk,
      rst_n     => reset_n,
-		jamma		  => jamma,
-		dips		  => dips,
-      inputs	  => inputs
+      jamma     => jamma,
+      dips      => dips,
+      inputs    => inputs
    );

-    
 end architecture SYN;
--- a/Hardware/LodeRunner_MiST/rtl/LodeRunner_MiST.sv
+++ b/Hardware/LodeRunner_MiST/rtl/LodeRunner_MiST.sv
@@ -1,12 +1,12 @@
-module LodeRunner_MiST(
-	output        LED,						
+module IremM62_MiST(
+	output        LED,
 	output  [5:0] VGA_R,
 	output  [5:0] VGA_G,
 	output  [5:0] VGA_B,
 	output        VGA_HS,
 	output        VGA_VS,
 	output        AUDIO_L,
-	output        AUDIO_R,	
+	output        AUDIO_R,
 	input         SPI_SCK,
 	output        SPI_DO,
 	input         SPI_DI,
@@ -30,9 +30,13 @@ module LodeRunner_MiST(

 `include "rtl/build_id.v" 

-localparam CONF_STR = {      
-	"LDRUNNER;ROM;",
+`define CORE_NAME "LDRUN"
+wire [6:0] core_mod;
+
+localparam CONF_STR = {
+	`CORE_NAME,";;",
 	"O2,Rotate Controls,Off,On;",
+	"O1,Video Timings,Original,PAL 50Hz;",
 	"O34,Scanlines,Off,25%,50%,75%;",
 	"O5,Blending,Off,On;",
 	"O6,Service,Off,On;",
@@ -40,20 +44,51 @@ localparam CONF_STR = {
 	"V,v1.0.",`BUILD_DATE
 };

+wire       palmode   = status[1];
+wire       rotate    = status[2];
+wire [1:0] scanlines = status[4:3];
+wire       blend     = status[5];
+wire       service   = status[6];

+reg  [1:0] orientation = 2'b10;
+
+always @(*) begin
+  orientation = 2'b10;
+  case (core_mod)
+  7'h0: ;// LDRUN
+  7'h1: ;// LDRUN2
+  7'h2: ;// LDRUN3
+  7'h3: ;// LDRUN4
+  7'h4: ;// KUNGFUM
+  7'h5: ;// HORIZON
+  7'h6: // BATTROAD
+  begin
+    orientation = 2'b11;
+  end
+  7'h7: ;// KIDNIKI
+  7'h8: ;// LOTLOT
+  7'h9: ;// SPELUNKR
+  7'hA: ;// SPELUNK2
+  7'hB: // YOUJYUDN
+  begin
+    orientation = 2'b01;
+  end
+  default: ;
+  endcase
+end

 assign LED = ~ioctl_downl;
 assign SDRAM_CLK = clk_sd;
 assign SDRAM_CKE = 1; 

-wire clk_sys, clk_aud, clk_sd, clk_vid;
+wire clk_sys, clk_vid, clk_aud, clk_sd;
 wire pll_locked;
 pll_mist pll(
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_sys),
-	.c1(clk_vid),
-	.c2(clk_sd),
+	.c0(clk_sd),
+	.c1(clk_sys),
+	.c2(clk_vid),
 	.c3(clk_aud),
 	.locked(pll_locked)
 	);
@@ -65,23 +100,61 @@ wire  [7:0] joystick_0;
 wire  [7:0] joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
-wire [11:0] audio;
-wire        hs, vs;
-wire        blankn = 1'b1;//todo
-wire  [3:0] g,b,r;
+wire        no_csync;
 wire        key_pressed;
 wire  [7:0] key_code;
 wire        key_strobe;

-wire [14:0] rom_addr;
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
+	.core_mod       (core_mod       ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+wire [16:0] rom_addr;
 wire [15:0] rom_do;

-wire [13:0] snd_addr;
+wire [17:0] snd_addr;
+wire [15:0] snd_rom_addr;
 wire [15:0] snd_do;
+wire        snd_vma;

-
-wire [14:0] sp_addr;
+wire [14:0] chr1_addr;
+wire [31:0] chr1_do;
+wire [15:0] sp_addr;
 wire [31:0] sp_do;
+wire [14:0] chr2_addr;
+wire [31:0] chr2_do;
+
+/* ROM structure
+00000-1FFFF CPU1 128k
+20000-2FFFF CPU2  64k
+30000-4FFFF GFX1 128k
+50000-8FFFF GFX2 256k
+
+90000-9FFFF GFX3  64k
+A0000-A02FF spr_color_proms 3*256b
+A0300-A05FF chr_color_proms 3*256b
+A0600-A08FF fg_color_proms  3*256b
+A0900-A091F spr_height_prom 32b
+*/

 wire        ioctl_downl;
 wire  [7:0] ioctl_index;
@@ -90,7 +163,7 @@ wire [24:0] ioctl_addr;
 wire  [7:0] ioctl_dout;

 data_io data_io(
-	.clk_sys       ( clk_sd       ),
+	.clk_sys       ( clk_sys      ),
 	.SPI_SCK       ( SPI_SCK      ),
 	.SPI_SS2       ( SPI_SS2      ),
 	.SPI_DI        ( SPI_DI       ),
@@ -101,13 +174,15 @@ data_io data_io(
 	.ioctl_dout    ( ioctl_dout   )
 );

-wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h10000; //todo
+wire [24:0] sp_ioctl_addr = ioctl_addr - 20'h30000;
+wire clkref;

 reg port1_req, port2_req;
 sdram sdram(
 	.*,
 	.init_n        ( pll_locked   ),
-	.clk           ( clk_sd      ),
+	.clk           ( clk_sd       ),
+	.clkref        ( clkref       ),

 	// port1 used for main + sound CPU
 	.port1_req     ( port1_req    ),
@@ -118,35 +193,44 @@ sdram sdram(
 	.port1_d       ( {ioctl_dout, ioctl_dout} ),
 	.port1_q       ( ),

-	.cpu1_addr     ( ioctl_downl ? 16'hffff : {2'b00, rom_addr[14:1]} ),
+	.cpu1_addr     ( ioctl_downl ? 17'h1ffff : {1'b0, rom_addr[16:1]} ),
 	.cpu1_q        ( rom_do ),
-	.cpu2_addr     ( ioctl_downl ? 16'hffff : (16'h4000 + snd_addr[13:1]) ),
+	.cpu2_addr     ( ioctl_downl ? 17'h1ffff : snd_addr[17:1] ),
 	.cpu2_q        ( snd_do ),

 	// port2 for sprite graphics
 	.port2_req     ( port2_req ),
 	.port2_ack     ( ),
-	.port2_a       ( {sp_ioctl_addr[23:16], sp_ioctl_addr[13:0], sp_ioctl_addr[15]} ), // merge sprite roms to 32-bit wide words
-	.port2_ds      ( {sp_ioctl_addr[14], ~sp_ioctl_addr[14]} ),
+	.port2_a       ( sp_ioctl_addr[23:1] ),
+	.port2_ds      ( {sp_ioctl_addr[0], ~sp_ioctl_addr[0]} ),
 	.port2_we      ( ioctl_downl ),
 	.port2_d       ( {ioctl_dout, ioctl_dout} ),
 	.port2_q       ( ),

-	.sp_addr       ( ioctl_downl ? 15'h7fff : sp_addr ),
-	.sp_q          ( sp_do )
+	.chr1_addr     ( chr1_addr ),
+	.chr1_q        ( chr1_do   ),
+	.chr2_addr     ( 17'h18000 + chr2_addr ),
+	.chr2_q        ( chr2_do   ),
+	.sp_addr       ( 16'h8000 + sp_addr ),
+	.sp_q          ( sp_do     )
 );

 // ROM download controller
-always @(posedge clk_sd) begin
+always @(posedge clk_sys) begin
 	reg        ioctl_wr_last = 0;
+	reg        snd_vma_r, snd_vma_r2;

 	ioctl_wr_last <= ioctl_wr;
 	if (ioctl_downl) begin
 		if (~ioctl_wr_last && ioctl_wr) begin
 			port1_req <= ~port1_req;
-			port2_req <= ~port2_req;
+			if (ioctl_addr >= 20'h30000) port2_req <= ~port2_req;
 		end
 	end
+
+	// async clock domain crossing here (clk_snd -> clk_sys)
+	snd_vma_r <= snd_vma; snd_vma_r2 <= snd_vma_r;
+	if (snd_vma_r2) snd_addr <= snd_rom_addr + 18'h20000;
 end

 // reset signal generation
@@ -165,15 +249,22 @@ always @(posedge clk_sys) begin

 end

+wire [11:0] audio;
+wire        hs, vs;
+wire        blankn = 1'b1;//todo
+wire  [3:0] g,b,r;
+
 target_top target_top(
-   .clock_50(clk_sys),//40MHz
-	.clock_vid(clk_vid),//25.263158MHz
+	.clock_sys(clk_sys),//24 MHz
+	.vid_clk_en(clkref),
 	.clk_aud(clk_aud),//0.895MHz
 	.reset_in(reset),
+	.hwsel(core_mod),
+	.palmode(palmode),
 	.audio_out(audio),
 	.usr_coin1(m_coin1),
 	.usr_coin2(m_coin2),
-	.usr_service(status[6]),
+	.usr_service(service),
 	.usr_start1(m_one_player),
 	.usr_start2(m_two_players),
 	.p1_up(m_up),
@@ -188,19 +279,31 @@ target_top target_top(
 	.p2_rt(m_right2),
 	.p2_f1(m_fire2A),
 	.p2_f2(m_fire2B),
-   .VGA_VS(hs),
-   .VGA_HS(vs),
-   .VGA_R(r),
-   .VGA_G(g),
-   .VGA_B(b),
+	.VGA_VS(vs),
+	.VGA_HS(hs),
+	.VGA_R(r),
+	.VGA_G(g),
+	.VGA_B(b),
+
+	.dl_addr(ioctl_addr - 20'hA0000),
+	.dl_data(ioctl_dout),
+	.dl_wr(ioctl_wr),
+
 	.cpu_rom_addr(rom_addr),
 	.cpu_rom_do( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
-	.snd_rom_addr(snd_addr),
-   .snd_rom_do(snd_addr[0] ? snd_do[15:8] : snd_do[7:0])
-  ); 
+	.snd_rom_addr(snd_rom_addr),
+	.snd_rom_do(snd_rom_addr[0] ? snd_do[15:8] : snd_do[7:0]),
+	.snd_vma(snd_vma),
+	.gfx1_addr(chr1_addr),
+	.gfx1_do(chr1_do),
+	.gfx3_addr(chr2_addr),
+	.gfx3_do(chr2_do),
+	.gfx2_addr(sp_addr),
+	.gfx2_do(sp_do)
+  );

-mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(9)) mist_video(
-	.clk_sys        ( clk_sys          ),
+mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(11)) mist_video(
+	.clk_sys        ( clk_vid          ),
 	.SPI_SCK        ( SPI_SCK          ),
 	.SPI_SS3        ( SPI_SS3          ),
 	.SPI_DI         ( SPI_DI           ),
@@ -214,33 +317,13 @@ mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(9)) mist_video(
 	.VGA_B          ( VGA_B            ),
 	.VGA_VS         ( VGA_VS           ),
 	.VGA_HS         ( VGA_HS           ),
-	.rotate         ( { 1'b1, status[2] } ),
-	.ce_divider     ( 1'b1                ),
-	.scandoubler_disable( 1),//scandoublerD ),
-	.scanlines      ( status[4:3]        ),
-	.blend          ( status[5]            ),
-	.ypbpr          ( ypbpr            )
-	);
-
-user_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-user_io(
-	.clk_sys        (clk_sys        ),
-	.conf_str       (CONF_STR       ),
-	.SPI_CLK        (SPI_SCK        ),
-	.SPI_SS_IO      (CONF_DATA0     ),
-	.SPI_MISO       (SPI_DO         ),
-	.SPI_MOSI       (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches       (switches       ),
-	.scandoubler_disable (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.key_strobe     (key_strobe     ),
-	.key_pressed    (key_pressed    ),
-	.key_code       (key_code       ),
-	.joystick_0     (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
+	.rotate         ( { 1'b1, rotate } ),
+	.ce_divider     ( 1'b1             ),
+	.scandoubler_disable( scandoublerD ),
+	.scanlines      ( scanlines        ),
+	.blend          ( blend            ),
+	.ypbpr          ( ypbpr            ),
+	.no_csync       ( no_csync         )
 	);

 wire dac_o;
@@ -267,8 +350,8 @@ arcade_inputs inputs (
 	.key_code    ( key_code    ),
 	.joystick_0  ( joystick_0  ),
 	.joystick_1  ( joystick_1  ),
-	.rotate      ( status[2]   ),
-	.orientation ( 2'b10       ),
+	.rotate      ( rotate      ),
+	.orientation ( orientation ),
 	.joyswap     ( 1'b0        ),
 	.oneplayer   ( 1'b1        ),
 	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
--- a/Hardware/LodeRunner_MiST/rtl/Sound_Board.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/Sound_Board.vhd
@@ -1,4 +1,5 @@
 ---------------------------------------------------------------------------------
+-- Irem M62 sound board, based on
 -- Moon patrol sound board by Dar (darfpga@aol.fr)
 -- http://darfpga.blogspot.fr
 ---------------------------------------------------------------------------------
@@ -10,13 +11,15 @@
 -- 6800/01 compatible CPU core 
 -- GNU public license - December 2002 : John E. Kent
 ---------------------------------------------------------------------------------
+-- jt5205 hardware by Jose Tejada (@topapate)
+---------------------------------------------------------------------------------
 -- Educational use only
 -- Do not redistribute synthetized file with roms
 -- Do not redistribute roms whatever the form
 -- Use at your own risk
 ---------------------------------------------------------------------------------
 -- Version 0.0 -- 24/11/2017 -- 
--		    initial version
+--    initial version
 ---------------------------------------------------------------------------------

 library ieee;
@@ -31,8 +34,9 @@ port(

 select_sound : in std_logic_vector(7 downto 0);
 audio_out    : out std_logic_vector(11 downto 0);
- snd_rom_addr      : out std_logic_vector(13 downto 0);
- snd_rom_do        : in std_logic_vector(7 downto 0);
+ snd_rom_addr : out std_logic_vector(15 downto 0);
+ snd_rom_do   : in std_logic_vector(7 downto 0);
+ snd_vma      : out std_logic;

 dbg_cpu_addr : out std_logic_vector(15 downto 0)
 );
@@ -67,6 +71,19 @@ architecture struct of Sound_Board is
    );
  end component;

+  component jt5205
+  port (
+    rst         : in  std_logic;
+    clk         : in  std_logic;
+    cen         : in  std_logic;
+    sel         : in  std_logic_vector(1 downto 0); -- s pin
+    din         : in  std_logic_vector(3 downto 0);
+    sound       : out signed(11 downto 0);
+    irq         : out std_logic;
+    vclk_o      : out std_logic
+    );
+  end component;
+
 signal reset      : std_logic := '1';
 signal reset_cnt  : integer range 0 to 1000000 := 1000000;

@@ -76,6 +93,7 @@ architecture struct of Sound_Board is
 signal cpu_rw     : std_logic;
 signal cpu_irq    : std_logic;
 signal cpu_nmi    : std_logic;
+ signal cpu_vma    : std_logic;
 
 signal irqraz_cs : std_logic;
 signal irqraz_we : std_logic;
@@ -112,48 +130,22 @@ architecture struct of Sound_Board is
 signal port2_data  : std_logic_vector(7 downto 0);
 signal port2_ddr   : std_logic_vector(7 downto 0);
 signal port2_in    : std_logic_vector(7 downto 0);
- 
+
+ signal adpcm_ce    : std_logic;
 signal adpcm_cs    : std_logic;
- signal adpcm_we    : std_logic;
+ signal adpcm_0_we  : std_logic;
+ signal adpcm_1_we  : std_logic;
 signal adpcm_0_di  : std_logic_vector(3 downto 0);
+ signal adpcm_1_di  : std_logic_vector(3 downto 0);

 signal select_sound_r : std_logic_vector(7 downto 0);

- signal audio : std_logic_vector(12 downto 0);
+ signal adpcm_0_out : signed(11 downto 0);
+ signal adpcm_1_out : signed(11 downto 0);
+ signal adpcm_vclk  : std_logic;

- type t_step_size is array(0 to 48) of integer range 0 to 1552;
- constant step_size : t_step_size := (
-    16,   17,   19,   21,   23,   25,   28,   31,
-    34,   37,   41,   45,   50,   55,   60,   66,
-    73,   80,   88,   97,  107,  118,  130,  143,
-	157,  173,  190,  209,  230,  253,  279,  307,
-	337,  371,  408,  449,  494,  544,  598,  658,
-	724,  796,  876,  963, 1060, 1166, 1282, 1411, 1552);
-	
- type t_delta_step is array(0 to 7) of integer range -1 to 8;	
- constant delta_step : t_delta_step := (-1,-1,-1,-1,2,4,6,8);
+ signal audio       : std_logic_vector(12 downto 0);

- signal adpcm_vclk  : std_logic := '0';
- signal adpcm_signal : integer range -16384 to 16383 := 0; 
-
-- adpcm algorithm (4bits) [no pcm here]
--
--   val    : input value 3bits (0 - 7 : b2b1b0)
--   sign   : input value sign  (4th bit : 0=>sign=1 ,1=>sign=-1)
--
--   step   : internal data, init = 0
--   signal : output value, init = 0;
--
--   for each new val (and sign) :
--   |
--   | step_size = 16*1.1^(step)
--   | delta     = sign * (step_size/8 + step_size/4*b0 + step_size/2*b1 + step_size*b2)
--   | signal    = signal + delta
--   | step      = step + delta_step(val)
--   |
--   | signal is then limited between -2048..2047
--   | step   is then limited between     0..48
- 
 begin

 dbg_cpu_addr <= cpu_addr;
@@ -161,54 +153,55 @@ dbg_cpu_addr <= cpu_addr;
 -- cs
 wram_cs   <= '1' when cpu_addr(15 downto  7) = X"00"&'1' else '0'; -- 0080-00FF
 ports_cs  <= '1' when cpu_addr(15 downto  4) = X"000"    else '0'; -- 0000-000F
-adpcm_cs  <= '1' when cpu_addr(14 downto 11) = "0001"    else '0'; -- 0800-0FFF / 8800-8FFF
-irqraz_cs <= '1' when cpu_addr(14 downto 12) = "001"     else '0'; -- 1000-1FFF / 9000-9FFF
-rom_cs    <= '1' when cpu_addr(14 downto 12) = "111"     else '0'; -- 7000-7FFF / F000-FFFF
-	
+adpcm_cs  <= '1' when cpu_addr(15 downto 14) = "00" and cpu_addr(11) = '1' and cpu_addr(1 downto 0) /= "00" else '0'; -- 0801-0802
+irqraz_cs <= '1' when cpu_addr(15 downto 14) = "00" and cpu_addr(11) = '1' and cpu_addr(1 downto 0)  = "00" else '0'; -- 0800
+rom_cs    <= '1' when cpu_addr(15 downto 14) /= "00"     else '0'; -- 4000-FFFF
+
 -- write enables
-wram_we <=   '1' when cpu_rw = '0' and wram_cs =   '1' else '0';
-ports_we <=  '1' when cpu_rw = '0' and ports_cs =  '1' else '0';
-adpcm_we <=  '1' when cpu_rw = '0' and adpcm_cs =  '1' else '0';
-irqraz_we <= '1' when cpu_rw = '0' and irqraz_cs = '1' else '0';
+wram_we    <= '1' when cpu_rw = '0' and wram_cs =   '1' else '0';
+ports_we   <= '1' when cpu_rw = '0' and ports_cs =  '1' else '0';
+adpcm_0_we <= '1' when cpu_rw = '0' and adpcm_cs =  '1' and cpu_addr(0) = '1' else '0';
+adpcm_1_we <= '1' when cpu_rw = '0' and adpcm_cs =  '1' and cpu_addr(1) = '1' else '0';
+irqraz_we  <= '1' when cpu_rw = '0' and irqraz_cs = '1' else '0';

 -- mux cpu in data between roms/io/wram
 cpu_di <=
-	wram_do when wram_cs = '1' else
-	port1_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"0" else
-	port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else
-	port1_in  when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else
-	port2_in  when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
-	rom_do when rom_cs = '1' else X"55";
+  wram_do when wram_cs = '1' else
+  port1_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"0" else
+  port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else
+  port1_in  when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else
+  port2_in  when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
+  snd_rom_do when rom_cs = '1' else X"55";

 process (clock_E)
 begin
-	if rising_edge(clock_E) then
-		reset <= '0';
-		if reset_cnt /= 0 then
-			reset_cnt <= reset_cnt - 1;
-			reset <= '1';
-		end if;
-		if areset = '1' then
-		   reset_cnt <= 1000000;
-		end if;
-	end if;
+  if rising_edge(clock_E) then
+    reset <= '0';
+    if reset_cnt /= 0 then
+      reset_cnt <= reset_cnt - 1;
+      reset <= '1';
+    end if;
+    if areset = '1' then
+     reset_cnt <= 1000000;
+    end if;
+  end if;
 end process;

 -- irq to cpu
 process (reset, clock_E)
 begin
-	if reset='1' then
-		cpu_irq <= '0';
-		select_sound_r(7) <= '1';
-	elsif rising_edge(clock_E) then
-		select_sound_r <= select_sound;
-		if select_sound_r(7) = '0' then
-			cpu_irq  <= '1';
-		end if;
-		if irqraz_we = '1' then
-			cpu_irq  <= '0';
-		end if;
-	end if;
+  if reset='1' then
+    cpu_irq <= '0';
+    select_sound_r(7) <= '0';
+  elsif rising_edge(clock_E) then
+    select_sound_r <= select_sound;
+    if select_sound_r(7) = '0' then
+      cpu_irq  <= '1';
+    end if;
+    if irqraz_we = '1' then
+      cpu_irq  <= '0';
+    end if;
+  end if;
 end process;

 -- cpu nmi
@@ -249,113 +242,82 @@ begin
 	if reset='1' then
 		adpcm_0_di <= (others=>'0');
 	elsif rising_edge(clock_E) then
-			if adpcm_cs = '1' and adpcm_we = '1' then
-				if cpu_addr(1) = '0' then adpcm_0_di  <= cpu_do(3 downto 0); end if;
+			if adpcm_cs = '1' and adpcm_0_we = '1' then
+				adpcm_0_di  <= cpu_do(3 downto 0);
+			end if;
+			if adpcm_cs = '1' and adpcm_1_we = '1' then
+				adpcm_1_di  <= cpu_do(3 downto 0);
 			end if;
 	end if;
 end process;

-- adcpm clocks and computation -- make 24kHz and vclk 8/6/4kHz
-adpcm_clocks : process(clock_E, ay1_port_b_do)
-	variable clock_div_a : integer range 0 to 148 := 0;
-	variable clock_div_b : integer range 0 to 5 := 0;
-	variable step   : integer range  0 to 48;
-	variable step_n : integer range -1 to 48+8;
-   variable sz : integer range 0 to 1552;
-	variable dn : integer range -32768 to 32767;
-	variable adpcm_signal_n : integer range -32768 to 32767;
+-- 384 kHz clock enable
+process( reset, clock_E )
+  variable CLK_SUM : integer;
 begin
-	if rising_edge(clock_E) then
-		if clock_div_a = 37 then   -- 24kHz
-			clock_div_a := 0;
-			
-			case ay1_port_b_do(3 downto 2) is				
-			when "00" => if clock_div_b = 5 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if;  -- 4kHz
-			when "01" => if clock_div_b = 2 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if;  -- 8kHz
-			when "10" => if clock_div_b = 3 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if;  -- 6kHz
-			when others => null;
-			end case;
-							
-			if clock_div_b = 0 then adpcm_vclk <= '1'; else adpcm_vclk <= '0'; end if;
-		else
-			clock_div_a := clock_div_a + 1;			
-		end if;
-			
-		if ay1_port_b_do(0) = '1' then
-			step := 0;
-			adpcm_signal <= 0;
-		else
-		
-			if clock_div_b = 0 then
-			case clock_div_a is
-			
-			when 0 => -- it's time to get new nibble (adpcm_0_di)
-							
-				sz := step_size(step);
-				dn := sz/8;
-				if adpcm_0_di(0) = '1' then dn := dn + sz/4; end if;
-				if adpcm_0_di(1) = '1' then dn := dn + sz/2; end if;
-				if adpcm_0_di(2) = '1' then dn := dn + sz  ; end if;
-				
-				if adpcm_0_di(3) = '1' then
-					dn := -dn;	
-				end if;
-								
-				step_n := step + delta_step(to_integer(unsigned(adpcm_0_di(2 downto 0))));
-			
-			when 4 => 
-			
-				adpcm_signal_n := adpcm_signal + dn;
-			
-				if step_n > 48 then step := 48; else step := step_n; end if;
-				if step_n < 0  then step := 0;  else step := step_n; end if;
-				
-			when 8 =>
-			
-				if adpcm_signal_n >  2040 then adpcm_signal <=  2040; else adpcm_signal <= adpcm_signal_n; end if;
-				if adpcm_signal_n < -2040 then adpcm_signal <= -2040; else adpcm_signal <= adpcm_signal_n; end if;
-			
-			when others => null;
-			
-			end case;
-			end if;
-			
-		end if;
-	end if;
+  if reset = '1' then
+    CLK_SUM := 0;
+    adpcm_ce <= '0';
+  elsif rising_edge(clock_E) then
+    adpcm_ce <= '0';
+    CLK_SUM := CLK_SUM + 384;
+    if CLK_SUM >= 895 then
+      CLK_SUM := CLK_SUM - 895;
+      adpcm_ce <= '1';
+    end if;
+  end if;
 end process;

+-- MSM5205 ADPCM decoder chips
+adpcm_0 : jt5205
+port map (
+  rst   => ay1_port_b_do(0),
+  clk   => clock_E,
+  cen   => adpcm_ce,
+  sel   => ay1_port_b_do(3 downto 2),
+  din   => adpcm_0_di,
+  sound => adpcm_0_out,
+  irq   => open,
+  vclk_o=> adpcm_vclk
+  );
+
+adpcm_1 : jt5205
+port map (
+  rst   => ay1_port_b_do(1),
+  clk   => clock_E,
+  cen   => adpcm_ce,
+  sel   => ay1_port_b_do(3 downto 2),
+  din   => adpcm_1_di,
+  sound => adpcm_1_out,
+  irq   => open,
+  vclk_o=> open
+  );
+
 -- audio mux
-audio <= ("000"&ay1_audio) + ("000"&ay2_audio) + ('0'&std_logic_vector(to_unsigned((adpcm_signal)+2048,12)));
+audio <= ("00"&ay1_audio&'0') + ("00"&ay2_audio&'0') + std_logic_vector(not adpcm_0_out(11)&adpcm_0_out(10 downto 0)) + std_logic_vector(not adpcm_1_out(11)&adpcm_1_out(10 downto 0));
 audio_out <= audio(12 downto 1);
-				 
+ 
 -- microprocessor 6800/01/03
 main_cpu : entity work.cpu68
 port map(	
-	clk      => clock_E,   -- E clock input (falling edge)
-	rst      => reset,    -- reset input (active high)
-	rw       => cpu_rw,   -- read not write output
-	vma      => open,     -- valid memory address (active high)
-	address  => cpu_addr, -- address bus output
-	data_in  => cpu_di,   -- data bus input
-	data_out => cpu_do,   -- data bus output
-	hold     => '0',      -- hold input (active high) extend bus cycle
-	halt     => '0',      -- halt input (active high) grants DMA
-	irq      => cpu_irq,  -- interrupt request input (active high)
-	nmi      => cpu_nmi,  -- non maskable interrupt request input (active high)
-	test_alu => open,
-	test_cc  => open
+ clk      => clock_E,   -- E clock input (falling edge)
+ rst      => reset,    -- reset input (active high)
+ rw       => cpu_rw,   -- read not write output
+ vma      => cpu_vma,  -- valid memory address (active high)
+ address  => cpu_addr, -- address bus output
+ data_in  => cpu_di,   -- data bus input
+ data_out => cpu_do,   -- data bus output
+ hold     => '0',      -- hold input (active high) extend bus cycle
+ halt     => '0',      -- halt input (active high) grants DMA
+ irq      => cpu_irq,  -- interrupt request input (active high)
+ nmi      => cpu_nmi,  -- non maskable interrupt request input (active high)
+ test_alu => open,
+ test_cc  => open
 );

-rom_cpu : entity work.snd_prg
-port map(
-	clk   => clock_E,   -- E clock input (falling edge)
-	addr  => cpu_addr(13 downto 0),
-	data  => rom_do
-);
+snd_vma <= rom_cs and cpu_vma;
+snd_rom_addr <= cpu_addr(15 downto 0);

-- snd_rom_addr <= cpu_addr(13 downto 0);
-
- 
 -- cpu wram
 cpu_ram : entity work.spram
 generic map( widthad_a => 7)
--- a/Hardware/LodeRunner_MiST/rtl/YM2149.sv
+++ b/Hardware/LodeRunner_MiST/rtl/YM2149.sv
@@ -79,7 +79,6 @@ reg env_reset;
 always @(posedge CLK) begin
 	if(RESET) begin
 		ymreg     <= '{default:0};
-		ymreg[7]  <= '1;
 		addr      <= '0;
 		env_reset <= 0;
 	end else begin
@@ -115,8 +114,8 @@ always_comb begin
 			11: dout = ymreg[11];
 			12: dout = ymreg[12];
 			13: dout = ymreg[13][3:0];
-			14: dout = ymreg[7][6] ? ymreg[14] : IOA_in;
-			15: dout = ymreg[7][7] ? ymreg[15] : IOB_in;
+			14: dout = ymreg[7][6] ? ymreg[14] | IOA_in : IOA_in;
+			15: dout = ymreg[7][7] ? ymreg[15] | IOA_in : IOB_in;
 		endcase
 	end
 end
--- a/Hardware/LodeRunner_MiST/rtl/bitmapctl_e.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/bitmapctl_e.vhd
@@ -16,7 +16,7 @@ entity bitmapCtl is
  );
  port               
  (
-    reset					: in std_logic;
+    reset         : in std_logic;

    -- video control signals		
    video_ctl     : in from_VIDEO_CTL_t;
--- a/Hardware/LodeRunner_MiST/rtl/build_id.tcl
+++ b/Hardware/LodeRunner_MiST/rtl/build_id.tcl
--- a/Hardware/rtl/clk_div.vhd
+++ b/Hardware/rtl/clk_div.vhd
@@ -0,0 +1,39 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clk_div is
+  generic
+  (
+    DIVISOR   : natural
+  );
+  port
+  (
+    clk       : in std_logic;
+    reset     : in std_logic;
+
+    clk_en    : out std_logic
+  );
+end clk_div;
+
+architecture SYN of clk_div is
+
+begin
+
+  process (clk, reset)
+    variable count : integer range 0 to DIVISOR-1;
+  begin
+    if reset = '1' then
+      count := 0;
+      clk_en <= '0';
+    elsif rising_edge(clk) then
+      clk_en <= '0';
+      if count = DIVISOR-1 then
+        clk_en <= '1';
+        count := 0;
+      else
+        count := count + 1;
+      end if;
+    end if;
+  end process;
+
+end SYN;
--- a/Hardware/LodeRunner_MiST/rtl/dpram.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/dpram.vhd
@@ -7,25 +7,27 @@ USE altera_mf.all;
 ENTITY dpram IS
 	GENERIC
 	(
-		init_file			: string := "";
+		init_file     : string := "";
 		--numwords_a		: natural;
-		widthad_a			: natural;
-		width_a				: natural := 8;
-    outdata_reg_a : string := "UNREGISTERED";
-    outdata_reg_b : string := "UNREGISTERED"
+		widthad_a     : natural;
+		width_a       : natural := 8;
+		widthad_b     : natural;
+		width_b       : natural := 8;
+		outdata_reg_a : string := "UNREGISTERED";
+		outdata_reg_b : string := "UNREGISTERED"
 	);
 	PORT
 	(
 		address_a		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-		address_b		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0);
 		clock_a		: IN STD_LOGIC ;
 		clock_b		: IN STD_LOGIC ;
 		data_a		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
 		wren_a		: IN STD_LOGIC  := '1';
 		wren_b		: IN STD_LOGIC  := '1';
 		q_a		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-		q_b		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+		q_b		: OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0)
 	);
 END dpram;

@@ -33,7 +35,7 @@ END dpram;
 ARCHITECTURE SYN OF dpram IS

 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);



@@ -72,17 +74,17 @@ ARCHITECTURE SYN OF dpram IS
 			wren_b	: IN STD_LOGIC ;
 			clock1	: IN STD_LOGIC ;
 			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-			address_b	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0);
 			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-			q_b	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
 			data_a	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-			data_b	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+			data_b	: IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0)
 	);
 	END COMPONENT;

 BEGIN
 	q_a    <= sub_wire0(width_a-1 DOWNTO 0);
-	q_b    <= sub_wire1(width_a-1 DOWNTO 0);
+	q_b    <= sub_wire1(width_b-1 DOWNTO 0);

 	altsyncram_component : altsyncram
 	GENERIC MAP (
@@ -96,19 +98,19 @@ BEGIN
 		intended_device_family => "Cyclone III",
 		lpm_type => "altsyncram",
 		numwords_a => 2**widthad_a,
-		numwords_b => 2**widthad_a,
+		numwords_b => 2**widthad_b,
 		operation_mode => "BIDIR_DUAL_PORT",
 		outdata_aclr_a => "NONE",
 		outdata_aclr_b => "NONE",
 		outdata_reg_a => outdata_reg_a,
-		outdata_reg_b => outdata_reg_a,
+		outdata_reg_b => outdata_reg_b,
 		power_up_uninitialized => "FALSE",
 		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
 		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
 		widthad_a => widthad_a,
-		widthad_b => widthad_a,
+		widthad_b => widthad_b,
 		width_a => width_a,
-		width_b => width_a,
+		width_b => width_b,
 		width_byteena_a => 1,
 		width_byteena_b => 1,
 		wrcontrol_wraddress_reg_b => "CLOCK1"
--- a/Hardware/rtl/history/history.db
+++ b/Hardware/rtl/history/history.db
--- a/Hardware/LodeRunner_MiST/rtl/input_mapper.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/input_mapper.vhd
@@ -6,21 +6,21 @@ library work;
 use work.pace_pkg.all;

 entity inputmapper is
-	generic
-	(
+  generic
+  (
    NUM_DIPS    : integer := 8;
-		NUM_INPUTS  : integer := 2
-	);
-	port
-	(
+    NUM_INPUTS  : integer := 2
+  );
+  port
+  (
    clk       : in std_logic;
    rst_n     : in std_logic;
-    jamma			: in from_JAMMA_t;
+    jamma     : in from_JAMMA_t;

    -- user outputs
-    dips			: in	std_logic_vector(NUM_DIPS-1 downto 0);
-    inputs		: out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1)
-	);
+    dips      : in std_logic_vector(NUM_DIPS-1 downto 0);
+    inputs    : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1)
+  );
 end inputmapper;

 architecture SYN of inputmapper is
@@ -28,7 +28,7 @@ architecture SYN of inputmapper is
 begin

  process (clk, rst_n)
-    variable jamma_v	: from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1);
+    variable jamma_v : from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1);
  begin

       -- note: all inputs are active LOW
@@ -45,27 +45,27 @@ begin
        jamma_v(0).d(1) := jamma.p(2).start;
        jamma_v(0).d(2) := '1';--jamma.service;
        jamma_v(0).d(3) := jamma.coin(1);
-		  --unused
-		  --unused
-		  --unused
-		  --unused
-		  
+      --unused
+      --unused
+      --unused
+      --unused
+
        jamma_v(1).d(0) := jamma.p(1).right;
        jamma_v(1).d(1) := jamma.p(1).left;
        jamma_v(1).d(2) := jamma.p(1).down;
        jamma_v(1).d(3) := jamma.p(1).up;
-		  --unused
+      --unused
        jamma_v(1).d(5) := jamma.p(1).button(2);
-		  --unused
+      --unused
        jamma_v(1).d(7) := jamma.p(1).button(1);
-		  
-		  jamma_v(2).d(0) := jamma.p(2).right;
+
+        jamma_v(2).d(0) := jamma.p(2).right;
        jamma_v(2).d(1) := jamma.p(2).left;
        jamma_v(2).d(2) := jamma.p(2).down;
        jamma_v(2).d(3) := jamma.p(2).up;
-		  jamma_v(2).d(4) := jamma.coin(2);
+        jamma_v(2).d(4) := jamma.coin(2);
        jamma_v(2).d(5) := jamma.p(2).button(2);
-		  --unused
+        --unused
        jamma_v(2).d(7) := jamma.p(2).button(1);
      end if; -- rising_edge (clk)

--- a/Hardware/rtl/iremm62_video_controller.vhd
+++ b/Hardware/rtl/iremm62_video_controller.vhd
@@ -0,0 +1,146 @@
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.video_controller_pkg.all;
+use work.platform_variant_pkg.all;
+
+entity iremm62_video_controller is
+  port
+  (
+    -- clocking etc
+    video_i       : in from_VIDEO_t;
+    hwsel         : in HWSEL_t;
+    palmode       : in std_logic;
+    hires         : in std_logic;
+
+    -- video input data
+    rgb_i         : in RGB_t;
+
+    -- control signals (out)
+    video_ctl_o   : out from_VIDEO_CTL_t;
+
+    -- video output control & data
+    video_o       : out to_VIDEO_t
+  );
+end iremm62_video_controller;
+
+architecture SYN of iremm62_video_controller is
+
+  alias clk       : std_logic is video_i.clk;
+  alias clk_ena   : std_logic is video_i.clk_ena;
+  alias reset     : std_logic is video_i.reset;
+ 
+  signal hcnt                   : unsigned(9 downto 0);
+  signal vcnt                   : unsigned(8 downto 0);
+  signal hsync                  : std_logic;
+  signal vsync                  : std_logic;
+  signal hblank                 : std_logic; -- hblank mux
+  signal hblank1                : std_logic; -- normal hblank
+  signal hblank2                : std_logic; -- shifted hblank for some games
+  signal vblank                 : std_logic;
+begin
+
+  -------------------
+  -- Video scanner --
+  -------------------
+  --  hcnt [x080..x0FF-x100..x1FF] => 128+256 = 384 pixels,  384/6.144Mhz => 1 line is 62.5us (16.000KHz) (lores)
+  --  hcnt [x080..x0FF-x100..x27F] => 128+384 = 512 pixels,  512/8.192Mhz => 1 line is 62.5us (16.000KHz) (hires)
+  --  vcnt [x0E6..x0FF-x100..x1FF] =>  26+256 = 282 lines, 1 frame is 260 x 62.5us = 17.625ms (56.74Hz)
+
+  process (reset, clk, clk_ena)
+  begin
+    if reset='1' then
+      hcnt  <= (others=>'0');
+      vcnt  <= '0'&X"FC";
+    elsif rising_edge(clk) and clk_ena = '1'then
+      hcnt <= hcnt + 1;
+      if (hires = '0' and hcnt = "01"&x"FF") or hcnt = "10"&x"7F" then
+        hcnt <= "00"&x"80";
+        vcnt <= vcnt + 1;
+        if vcnt = '1'&x"FF" then
+          if palmode = '1' then
+            vcnt <= '0'&x"C8";  -- 312 lines/PAL 50 Hz
+          else
+            vcnt <= '0'&x"E6";  -- from M52 schematics
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process (reset, clk, clk_ena)
+  begin
+    if reset = '1' then
+      hsync <= '0';
+      vsync <= '0';
+      hblank1 <= '1';
+      hblank2 <= '1';
+      vblank <= '1';
+    elsif rising_edge(clk) and clk_ena = '1' then
+      -- display blank
+      if hcnt = "00"&x"FF" then
+        hblank1 <= '0';
+        if vcnt = '1'&x"00" then
+          vblank <= '0';
+        end if;
+      end if;
+      if (hires = '0' and hcnt = "01"&x"FF") or hcnt = "10"&x"7F" then
+        hblank1 <= '1';
+      end if;
+      -- alternate blanking to hide hscroll garbage
+      if hcnt = "01"&x"07" then
+        hblank2 <= '0';
+      end if;
+      if hcnt = "00"&x"87" then
+        hblank2 <= '1';
+        if vcnt = '1'&x"FF" then
+          vblank <= '1';
+        end if;
+      end if;
+
+      -- display sync
+      if hcnt = "00"&x"8B" then
+        hsync <= '1';
+        if vcnt = '0'&x"F2" then
+          vsync <= '1';
+        end if;
+      end if;
+      if hcnt = "00"&x"B1" then
+        hsync <= '0';
+        if vcnt = '0'&x"F4" then
+          vsync <= '0';
+        end if;
+      end if;
+
+      -- registered rgb output
+      if hblank = '1' or vblank = '1' then
+        video_o.rgb <= RGB_BLACK;
+      else
+        video_o.rgb <= rgb_i;
+      end if;
+
+    end if;
+  end process;
+
+  video_o.hsync <= hsync;
+  video_o.vsync <= vsync;
+  hblank <= hblank2 when hwsel = HW_KIDNIKI else hblank1;
+  video_o.hblank <= hblank;
+  video_o.vblank <= vblank;
+  video_ctl_o.stb <= '1';
+  video_ctl_o.x <= '0'&std_logic_vector(hcnt);
+  video_ctl_o.y <= "00"&std_logic_vector(vcnt);
+  -- blank signal goes to tilemap/spritectl
+  video_ctl_o.hblank <= hblank;
+  video_ctl_o.vblank <= vblank;
+
+  -- pass-through for tile/bitmap & sprite controllers
+  video_ctl_o.clk <= clk;
+  video_ctl_o.clk_ena <= clk_ena;
+
+  -- for video DACs and TFT output
+  video_o.clk <= clk;
+
+end SYN;
--- a/Hardware/rtl/jt5205/LICENSE
+++ b/Hardware/rtl/jt5205/LICENSE
@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
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+GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
+USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
+DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
+PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
+EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGES.
+
+  17. Interpretation of Sections 15 and 16.
+
+  If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+                     END OF TERMS AND CONDITIONS
+
+            How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <https://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+  If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+    <program>  Copyright (C) <year>  <name of author>
+    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+  You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+<https://www.gnu.org/licenses/>.
+
+  The GNU General Public License does not permit incorporating your program
+into proprietary programs.  If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.  But first, please read
+<https://www.gnu.org/licenses/why-not-lgpl.html>.
--- a/Hardware/rtl/jt5205/README.md
+++ b/Hardware/rtl/jt5205/README.md
@@ -0,0 +1,29 @@
+# jt5205 hardware by Jose Tejada (@topapate)
+
+You can show your appreciation through
+* [Patreon](https://patreon.com/topapate), by supporting releases
+* [Paypal](https://paypal.me/topapate), with a donation
+
+JT5205 is an ADPCM sound source written in Verilog, fully compatible with OKI MSM5205.
+
+## Port Description
+
+Name     | Direction | Width | Purpose
+---------|-----------|-------|--------------------------------------
+rst      | input     |       | active-high asynchronous reset signal
+clk      | input     |       | clock
+cen      | input     |       | clock enable.
+sel      | input     | 2     | selects the data rate
+din      | input     | 4     | input data
+sound    | output    | 12    | signed sound output
+
+## Usage
+
+This is a pin-to-pin compatible module with OKI MSM5205. If you are just going to use it on a retro core you don't need to know the internals of it just hook it up and be sure that the effective clock rate, i.e. clk&cen signal, is the intended 384kHz (or whatever your system needs).
+
+If you hear a periodic noise when there should be no output, check whether your target system was leaving the MSM5205 halted at reset when no output was needed. If The part is not reset it will keep processing the output and a constant 0 input will produce a repetitive noise.
+
+## FPGA arcade cores using this module:
+
+* [Double Dragon](https://github.com/jotego/jtdd), by the same author
+* [Tora e no michi](https://github.com/jotego/jt_gng), by the same author
--- a/Hardware/rtl/jt5205/jt5205.qip
+++ b/Hardware/rtl/jt5205/jt5205.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt5205.v            ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt5205_adpcm.v      ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt5205_timing.v     ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt5205_interpol2x.v ]
+
+
--- a/Hardware/rtl/jt5205/jt5205.v
+++ b/Hardware/rtl/jt5205/jt5205.v
@@ -0,0 +1,67 @@
+/*  This file is part of JT5205.
+    JT5205 program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JT5205 program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JT5205.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 30-10-2019 */
+
+module jt5205(
+    input                  rst,
+    input                  clk,
+    input                  cen /* direct_enable */,        
+    input         [ 1:0]   sel,        // s pin
+    input         [ 3:0]   din,
+    output signed [11:0]   sound,
+    // This output pin is not part of MSM5205 I/O
+    // It helps integrating the system as it produces
+    // a strobe
+    // at the internal clock divider pace
+    output                 irq,
+    output                 vclk_o
+);
+
+wire               cen_lo, cen_mid;
+wire signed [11:0] raw;
+
+assign irq=cen_lo; // Notice that irq is active even if rst is high. This is
+    // important for games such as Tora e no michi.
+
+jt5205_timing u_timing(
+    .clk    ( clk       ),
+    .cen    ( cen       ),
+    .sel    ( sel       ),
+    .cen_lo ( cen_lo    ),
+    .cen_mid( cen_mid   ),
+    .cenb_lo(           ),
+    .vclk_o (vclk_o     )
+);
+
+jt5205_adpcm u_adpcm(
+    .rst    ( rst       ),
+    .clk    ( clk       ),
+    .cen_lo ( cen_lo    ),
+    .cen_hf ( cen       ),
+    .din    ( din       ),
+    .sound  ( raw       )
+);
+
+jt5205_interpol2x u_interpol(
+    .rst    ( rst       ),
+    .clk    ( clk       ),
+    .cen_mid( cen_mid   ),
+    .din    ( raw       ),
+    .dout   ( sound     )
+);
+
+endmodule
--- a/Hardware/rtl/jt5205/jt5205_adpcm.v
+++ b/Hardware/rtl/jt5205/jt5205_adpcm.v
@@ -0,0 +1,108 @@
+/*  This file is part of JT5205.
+    JT5205 program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JT5205 program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JT5205.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 30-10-2019 */
+
+module jt5205_adpcm(
+    input                      rst,
+    input                      clk,
+    (* direct_enable *) input  cen_hf,
+    (* direct_enable *) input  cen_lo,
+    input             [ 3:0]   din,
+    output reg signed [11:0]   sound
+);
+
+reg [ 5:0] delta_idx, idx_inc;
+reg [10:0] delta[0:48];
+
+reg [11:0] dn, qn;
+reg        up;
+reg [ 2:0] factor;
+reg [ 3:0] din_copy;
+reg [ 5:0] next_idx;
+reg signed [12:0] unlim;
+
+always @(posedge clk, posedge rst) begin
+    if( rst ) begin
+        factor    <= 3'd0;
+        up        <= 1'b0;
+        next_idx  <= 6'd0;
+        dn        <= 12'd0;
+        qn        <= 12'd0;
+    end else if(cen_hf) begin
+        up <= cen_lo;
+        if( up ) begin
+            factor   <= din_copy[2:0];
+            dn       <= { 1'b0, delta[delta_idx] };
+            qn       <= { 1'd0, delta[delta_idx]>>3};
+            next_idx <= din_copy[2] ? (delta_idx+idx_inc) : (delta_idx-6'd1);
+        end else begin
+            if(factor[2]) begin
+                qn <= qn + dn;
+            end
+            dn     <= dn>>1;
+            factor <= factor<<1;
+            if( next_idx>6'd48)
+                next_idx <= din_copy[2] ? 6'd48 : 6'd0;
+        end
+    end
+end
+
+function signed [12:0] extend;
+    input signed [11:0] a;
+    extend = { a[11], a };
+endfunction
+
+always @(*) begin
+    unlim = din_copy[3] ? extend(sound) - {1'b0,qn} :
+                          extend(sound) + {1'b0,qn};
+end
+
+wire signed [12:0] lim_pos =  13'd2047;
+wire signed [12:0] lim_neg = -13'd2048;
+
+wire ovp = unlim>lim_pos;
+wire ovn = unlim<lim_neg;
+
+always @(posedge clk, posedge rst) begin
+    if( rst ) begin
+        delta_idx <= 6'd0;
+        sound     <= -12'd2;
+        din_copy  <= 4'd0;
+    end else if(cen_lo) begin
+        case( din[1:0] )
+            2'd0: idx_inc <= 6'd2;
+            2'd1: idx_inc <= 6'd4;
+            2'd2: idx_inc <= 6'd6;
+            2'd3: idx_inc <= 6'd8;
+        endcase
+        din_copy  <= din;
+        delta_idx <= next_idx;
+        sound     <= ovp ? 12'd2047 : ovn ? -12'd2048 : unlim[11:0];
+    end
+end
+
+initial begin
+delta[ 0] = 11'd0016; delta[ 1] = 11'd0017; delta[ 2] = 11'd0019; delta[ 3] = 11'd0021; delta[ 4] = 11'd0023; delta[ 5] = 11'd0025; delta[ 6] = 11'd0028; 
+delta[ 7] = 11'd0031; delta[ 8] = 11'd0034; delta[ 9] = 11'd0037; delta[10] = 11'd0041; delta[11] = 11'd0045; delta[12] = 11'd0050; delta[13] = 11'd0055; 
+delta[14] = 11'd0060; delta[15] = 11'd0066; delta[16] = 11'd0073; delta[17] = 11'd0080; delta[18] = 11'd0088; delta[19] = 11'd0097; delta[20] = 11'd0107; 
+delta[21] = 11'd0118; delta[22] = 11'd0130; delta[23] = 11'd0143; delta[24] = 11'd0157; delta[25] = 11'd0173; delta[26] = 11'd0190; delta[27] = 11'd0209; 
+delta[28] = 11'd0230; delta[29] = 11'd0253; delta[30] = 11'd0279; delta[31] = 11'd0307; delta[32] = 11'd0337; delta[33] = 11'd0371; delta[34] = 11'd0408; 
+delta[35] = 11'd0449; delta[36] = 11'd0494; delta[37] = 11'd0544; delta[38] = 11'd0598; delta[39] = 11'd0658; delta[40] = 11'd0724; delta[41] = 11'd0796; 
+delta[42] = 11'd0876; delta[43] = 11'd0963; delta[44] = 11'd1060; delta[45] = 11'd1166; delta[46] = 11'd1282; delta[47] = 11'd1411; delta[48] = 11'd1552; 
+end
+
+endmodule
--- a/Hardware/rtl/jt5205/jt5205_interpol2x.v
+++ b/Hardware/rtl/jt5205/jt5205_interpol2x.v
@@ -0,0 +1,43 @@
+/*  This file is part of JT5205.
+    JT5205 program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JT5205 program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JT5205.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 30-12-2019 */
+
+// Simple 2x interpolator
+// Reduces HF content without altering too much the
+// original sound
+
+module jt5205_interpol2x(
+    input                      rst,
+    input                      clk,
+    (* direct_enable *) input  cen_mid,
+    input      signed [11:0]   din,
+    output reg signed [11:0]   dout
+);
+
+reg signed [11:0] last;
+
+always @(posedge clk, posedge rst) begin
+    if(rst) begin
+        last <= 12'd0;
+        dout <= 12'd0;
+    end else if(cen_mid) begin
+        last <= din;
+        dout <= (last>>>1)+(din>>>1);
+    end
+end
+
+endmodule
--- a/Hardware/rtl/jt5205/jt5205_timing.v
+++ b/Hardware/rtl/jt5205/jt5205_timing.v
@@ -0,0 +1,69 @@
+/*  This file is part of JT5205.
+    JT5205 program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JT5205 program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JT5205.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 30-10-2019 */
+
+module jt5205_timing(
+    input             clk,
+    (* direct_enable *) input cen,
+    input      [ 1:0] sel,        // s pin
+    output            cen_lo,
+    output            cenb_lo,
+    output            cen_mid,
+    output reg        vclk_o
+);
+
+reg [6:0] cnt=7'd0;
+reg       pre=1'b0, preb=1'b0;
+reg [6:0] lim;
+
+always @(posedge clk) begin
+    case(sel)
+        2'd0: lim <= 7'd95;
+        2'd1: lim <= 7'd63;
+        2'd2: lim <= 7'd47;
+        2'd3: lim <= 7'd1;
+    endcase
+end
+
+always @(posedge clk) begin
+
+    if (lim == 1) begin
+      cnt <= 1'b0;
+      vclk_o <= 1'b0;
+    end
+    if(cen) begin
+        if (lim != 1) cnt <= cnt + 7'd1;
+
+        pre    <= 1'b0;
+        preb   <= 1'b0;
+        if(cnt==lim) begin
+            vclk_o <= 1'b1;
+            cnt <= 7'd0;
+            pre <= 1'b1;
+        end
+        if(cnt==(lim>>1)) begin
+          preb <=1'b1;
+          vclk_o <= 1'b0;
+        end
+    end
+end
+
+assign cen_lo  = pre &cen;
+assign cenb_lo = preb&cen;
+assign cen_mid = (pre|preb)&cen;
+
+endmodule
--- a/Hardware/rtl/pace.vhd
+++ b/Hardware/rtl/pace.vhd
@@ -0,0 +1,197 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+use work.platform_pkg.all;
+use work.platform_variant_pkg.all;
+--use work.project_pkg.all;
+
+entity PACE is
+  port
+  (
+    -- clocks and resets
+    clkrst_i        : in from_CLKRST_t;
+    cpu_clk_en_i    : in std_logic;
+
+    -- hardware variant
+    hwsel           : in HWSEL_t;
+    palmode         : in std_logic;
+    hires           : in std_logic;
+
+    -- misc I/O
+    buttons_i       : in from_BUTTONS_t;
+    switches_i      : in from_SWITCHES_t;
+    leds_o          : out to_LEDS_t;
+
+    -- controller inputs
+    inputs_i        : in from_INPUTS_t;
+
+    -- video
+    video_i         : in from_VIDEO_t;
+    video_o         : out to_VIDEO_t;
+    sound_data_o    : out std_logic_vector(7 downto 0);
+
+    -- custom i/o
+    -- project_i       : in from_PROJECT_IO_t;
+    -- project_o       : out to_PROJECT_IO_t;
+    platform_i      : in from_PLATFORM_IO_t;
+    platform_o      : out to_PLATFORM_IO_t;
+
+    dl_addr         : in std_logic_vector(11 downto 0);
+    dl_data         : in std_logic_vector(7 downto 0);
+    dl_wr           : in std_logic;
+
+    cpu_rom_addr    : out std_logic_vector(16 downto 0);
+    cpu_rom_do      : in std_logic_vector(7 downto 0);
+    gfx1_addr       : out std_logic_vector(17 downto 2);
+    gfx1_do         : in std_logic_vector(31 downto 0);
+    gfx2_addr       : out std_logic_vector(17 downto 2);
+    gfx2_do         : in std_logic_vector(31 downto 0);
+    gfx3_addr       : out std_logic_vector(17 downto 2);
+    gfx3_do         : in std_logic_vector(31 downto 0)
+  );
+end entity PACE;
+
+architecture SYN of PACE is
+
+  alias clk_sys         : std_logic is clkrst_i.clk(0);
+
+  constant CLK_1US_COUNTS : integer := 
+    integer(27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY);
+
+  signal mapped_inputs    : from_MAPPED_INPUTS_t(0 to PACE_INPUTS_NUM_BYTES-1);
+
+  signal to_tilemap_ctl   : to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+  signal from_tilemap_ctl : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+
+  signal to_bitmap_ctl    : to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+  signal from_bitmap_ctl  : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+
+  signal to_sprite_reg    : to_SPRITE_REG_t;
+  signal to_sprite_ctl    : to_SPRITE_CTL_t;
+  signal to_sprite_ctl2   : to_SPRITE_CTL_t;
+  signal from_sprite_ctl  : from_SPRITE_CTL_t;
+  signal spr0_hit         : std_logic;
+
+  signal to_graphics      : to_GRAPHICS_t;
+  signal from_graphics    : from_GRAPHICS_t;
+  signal sprite_prom      : prom_a(0 to 31);
+  signal sprite_no        : integer range 0 to PACE_VIDEO_NUM_SPRITES-1;
+  signal sprite_rgb       : RGB_t;
+
+begin
+
+  inputs_inst : entity work.inputs
+    generic map
+    (
+      NUM_DIPS        => PACE_NUM_SWITCHES,
+      NUM_INPUTS      => PACE_INPUTS_NUM_BYTES,
+      CLK_1US_DIV     => CLK_1US_COUNTS
+    )
+    port map
+    (
+      clk             => clkrst_i.clk(0),
+      reset           => clkrst_i.rst(0),
+      jamma           => inputs_i.jamma_n,
+
+      dips            => switches_i,
+      inputs          => mapped_inputs
+    );
+
+  platform_inst : entity work.platform
+    generic map
+    (
+      NUM_INPUT_BYTES => PACE_INPUTS_NUM_BYTES
+    )
+    port map
+    (
+      -- clocking and reset
+      clkrst_i        => clkrst_i,
+      cpu_clk_en_i    => cpu_clk_en_i,
+
+      hwsel           => hwsel,
+
+      -- misc inputs and outputs
+      buttons_i       => buttons_i,
+      switches_i      => switches_i,
+      leds_o          => leds_o,
+      sound_data_o    => sound_data_o,
+      -- controller inputs
+      inputs_i        => mapped_inputs,
+
+      -- graphics
+      bitmap_i        => from_bitmap_ctl,
+      bitmap_o        => to_bitmap_ctl,
+      
+      tilemap_i       => from_tilemap_ctl,
+      tilemap_o       => to_tilemap_ctl,
+      
+      sprite_reg_o    => to_sprite_reg,
+      sprite_i        => from_sprite_ctl,
+      sprite_o        => to_sprite_ctl,
+      spr0_hit        => spr0_hit,
+      sprite_rgb      => sprite_rgb,
+      graphics_i      => from_graphics,
+      graphics_o      => to_graphics,
+
+      -- custom i/o
+--      project_i       => project_i,
+--      project_o       => project_o,
+      platform_i      => platform_i,
+      platform_o      => platform_o,
+
+      dl_addr         => dl_addr,
+      dl_data         => dl_data,
+      dl_wr           => dl_wr,
+
+      cpu_rom_addr    => cpu_rom_addr,
+      cpu_rom_do      => cpu_rom_do,
+      gfx1_addr       => gfx1_addr,
+      gfx1_do         => gfx1_do,
+      gfx2_addr       => gfx2_addr,
+      gfx2_do         => gfx2_do,
+      gfx3_addr       => gfx3_addr,
+      gfx3_do         => gfx3_do
+    );
+
+  graphics_inst : entity work.Graphics                                    
+    Port Map
+    (
+      hwsel           => hwsel,
+      hires           => hires,
+      palmode         => palmode,
+      sprite_prom     => sprite_prom,
+
+      bitmap_ctl_i    => to_bitmap_ctl,
+      bitmap_ctl_o    => from_bitmap_ctl,
+
+      tilemap_ctl_i   => to_tilemap_ctl,
+      tilemap_ctl_o   => from_tilemap_ctl,
+
+      sprite_reg_i    => to_sprite_reg,
+      sprite_ctl_i    => to_sprite_ctl,
+      sprite_ctl_o    => from_sprite_ctl,
+      spr0_hit        => spr0_hit,
+      sprite_rgb      => sprite_rgb,
+      
+      graphics_i      => to_graphics,
+      graphics_o      => from_graphics,
+      -- video (incl. clk)
+      video_i           => video_i,
+      video_o           => video_o
+    );
+
+  process(clk_sys) begin
+    if rising_edge(clk_sys) then
+      -- 900-91F
+      if dl_wr = '1' and dl_addr(11 downto 5) = x"9"&"000" then
+        sprite_prom(to_integer(unsigned(dl_addr(4 downto 0)))) <= to_integer(unsigned(dl_data(1 downto 0)));
+      end if;
+    end if;
+  end process;
+end SYN;
--- a/Hardware/LodeRunner_MiST/rtl/pace_pkg.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/pace_pkg.vhd
@@ -6,9 +6,9 @@ library work;

 package pace_pkg is

-	--  
-	-- PACE constants which *MUST* be defined
-	--
+  --  
+  -- PACE constants which *MUST* be defined
+  --

  type PACETargetType is
  (
@@ -51,26 +51,26 @@ package pace_pkg is
    PACE_TARGET_S6M_A0
  );

-	type PACEFpgaVendor_t is
-	(
-		PACE_FPGA_VENDOR_ALTERA,
-		PACE_FPGA_VENDOR_XILINX,
-		PACE_FPGA_VENDOR_LATTICE
-	);
+  type PACEFpgaVendor_t is
+  (
+    PACE_FPGA_VENDOR_ALTERA,
+    PACE_FPGA_VENDOR_XILINX,
+    PACE_FPGA_VENDOR_LATTICE
+  );

-	type PACEFpgaFamily_t is
-	(
-		PACE_FPGA_FAMILY_CYCLONE1,
-		PACE_FPGA_FAMILY_CYCLONE2,
-		PACE_FPGA_FAMILY_CYCLONE3,
-		PACE_FPGA_FAMILY_CYCLONE4,
-		PACE_FPGA_FAMILY_CYCLONE5,
-		PACE_FPGA_FAMILY_CYCLONE6,
-		PACE_FPGA_FAMILY_STRATIX_III,
-		PACE_FPGA_FAMILY_SPARTAN3,
-		PACE_FPGA_FAMILY_SPARTAN3A,
-		PACE_FPGA_FAMILY_SPARTAN3E
-	);
+  type PACEFpgaFamily_t is
+  (
+    PACE_FPGA_FAMILY_CYCLONE1,
+    PACE_FPGA_FAMILY_CYCLONE2,
+    PACE_FPGA_FAMILY_CYCLONE3,
+    PACE_FPGA_FAMILY_CYCLONE4,
+    PACE_FPGA_FAMILY_CYCLONE5,
+    PACE_FPGA_FAMILY_CYCLONE6,
+    PACE_FPGA_FAMILY_STRATIX_III,
+    PACE_FPGA_FAMILY_SPARTAN3,
+    PACE_FPGA_FAMILY_SPARTAN3A,
+    PACE_FPGA_FAMILY_SPARTAN3E
+  );

  type PACEJamma_t is
  (
@@ -82,7 +82,7 @@ package pace_pkg is

  -- Types

-	type ByteArrayType is array (natural range <>) of std_logic_vector(7 downto 0);
+  type ByteArrayType is array (natural range <>) of std_logic_vector(7 downto 0);

  type from_CLKRST_t is record
    arst      : std_logic;
@@ -103,30 +103,30 @@ package pace_pkg is
  constant PACE_NUM_LEDS      : natural := 18;
  subtype to_LEDS_t is std_logic_vector(PACE_NUM_LEDS-1 downto 0);
  
-	--
-	-- JAMMA interface data structures
-	-- - note: all signals are active LOW
-	--
+  --
+  -- JAMMA interface data structures
+  -- - note: all signals are active LOW
+  --

-	type from_JAMMA_player_t is record
-		start			: std_logic;
-		up				: std_logic;
-		down			: std_logic;
-		left			: std_logic;
-		right			: std_logic;
-		button		: std_logic_vector(1 to 5);
-	end record;
+  type from_JAMMA_player_t is record
+    start     : std_logic;
+    up        : std_logic;
+    down      : std_logic;
+    left      : std_logic;
+    right     : std_logic;
+    button    : std_logic_vector(1 to 5);
+  end record;

-	type from_JAMMA_player_a is array (natural range <>) of from_JAMMA_player_t;
-	
-	type from_JAMMA_t is record
-		coin_cnt	: std_logic_vector(1 to 2);
-		service		: std_logic;
-		tilt			: std_logic;
-		test			: std_logic;
-		coin			: std_logic_vector(1 to 2);
-		p					: from_JAMMA_player_a(1 to 2);
-	end record;
+  type from_JAMMA_player_a is array (natural range <>) of from_JAMMA_player_t;
+
+  type from_JAMMA_t is record
+    coin_cnt  : std_logic_vector(1 to 2);
+    service   : std_logic;
+    tilt      : std_logic;
+    test      : std_logic;
+    coin      : std_logic_vector(1 to 2);
+    p         : from_JAMMA_player_a(1 to 2);
+  end record;

  --
  -- INPUTS
@@ -134,7 +134,7 @@ package pace_pkg is
  subtype analogue_in_t is std_logic_vector(9 downto 0);
  type analogue_in_a is array (natural range <>) of analogue_in_t;
  
-	type from_INPUTS_t is record
+  type from_INPUTS_t is record
    ps2_kclk  : std_logic;
    ps2_kdat  : std_logic;
    ps2_mclk  : std_logic;
@@ -150,38 +150,38 @@ package pace_pkg is
  
  type from_MAPPED_INPUTS_t is array (natural range <>) of in8_t;
  
-	--
-	-- SRAM interface data structure
-	--
-	type from_SRAM_t is record
-		d					: std_logic_vector(31 downto 0);
-	end record;
-	
-	type to_SRAM_t is record
-		a					: std_logic_vector(23 downto 0);
-		d					: std_logic_vector(31 downto 0);
-		be				: std_logic_vector(3 downto 0);
-		cs				: std_logic;
-		oe				: std_logic;
-		we				: std_logic;
-	end record;
+  --
+  -- SRAM interface data structure
+  --
+  type from_SRAM_t is record
+    d         : std_logic_vector(31 downto 0);
+  end record;
+
+  type to_SRAM_t is record
+    a         : std_logic_vector(23 downto 0);
+    d         : std_logic_vector(31 downto 0);
+    be        : std_logic_vector(3 downto 0);
+    cs        : std_logic;
+    oe        : std_logic;
+    we        : std_logic;
+  end record;

  function NULL_TO_SRAM return to_SRAM_t;
-	
-	--
-	-- FLASH interface data structure
-	--
-	type from_FLASH_t is record
-		d					: std_logic_vector(15 downto 0);
-	end record;
-	
-	type to_FLASH_t is record
-		a					: std_logic_vector(21 downto 0);
-		d					: std_logic_vector(15 downto 0);
-		we				: std_logic;
-		cs				: std_logic;
-		oe				: std_logic;
-	end record;
+
+  --
+  -- FLASH interface data structure
+  --
+  type from_FLASH_t is record
+    d         : std_logic_vector(15 downto 0);
+  end record;
+  
+  type to_FLASH_t is record
+    a         : std_logic_vector(21 downto 0);
+    d         : std_logic_vector(15 downto 0);
+    we        : std_logic;
+    cs        : std_logic;
+    oe        : std_logic;
+  end record;

  function NULL_TO_FLASH return to_FLASH_t;

@@ -250,7 +250,7 @@ package pace_pkg is

  function NULL_TO_SOUND return to_SOUND_t;
  
- 	--
+  --
  -- OSD interface data structure
  --
  type from_OSD_t is record
@@ -268,13 +268,13 @@ package pace_pkg is

  function NULL_TO_OSD return to_OSD_t;

-	-- create a constant that automatically determines 
-	-- whether this is simulation or synthesis
-	constant IN_SIMULATION : BOOLEAN := false
-	-- synthesis translate_off
-	or true
-	-- synthesis translate_on
-	;
-	constant IN_SYNTHESIS : boolean := not IN_SIMULATION;
-	
-end;
+  -- create a constant that automatically determines 
+  -- whether this is simulation or synthesis
+  constant IN_SIMULATION : BOOLEAN := false
+  -- synthesis translate_off
+  or true
+  -- synthesis translate_on
+  ;
+  constant IN_SYNTHESIS : boolean := not IN_SIMULATION;
+
+ end;
--- a/Hardware/LodeRunner_MiST/rtl/pace_pkg_body.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/pace_pkg_body.vhd
--- a/Hardware/rtl/platform.vhd
+++ b/Hardware/rtl/platform.vhd
@@ -0,0 +1,997 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+use work.platform_pkg.all;
+use work.platform_variant_pkg.all;
+--use work.project_pkg.all;
+
+entity platform is
+  generic
+  (
+    NUM_INPUT_BYTES   : integer
+  );
+  port
+  (
+    -- clocking and reset
+    clkrst_i        : in from_CLKRST_t;
+    cpu_clk_en_i    : in std_logic;
+
+    hwsel           : in HWSEL_t;
+
+    -- misc I/O
+    buttons_i       : in from_BUTTONS_t;
+    switches_i      : in from_SWITCHES_t;
+    leds_o          : out to_LEDS_t;
+
+    -- controller inputs
+    inputs_i        : in from_MAPPED_INPUTS_t(0 to NUM_INPUT_BYTES-1);
+
+    -- graphics
+    
+    bitmap_i        : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+    bitmap_o        : out to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+    
+    tilemap_i       : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+    tilemap_o       : out to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+
+    sprite_reg_o    : out to_SPRITE_REG_t;
+    sprite_i        : in from_SPRITE_CTL_t;
+    sprite_o        : out to_SPRITE_CTL_t;
+    spr0_hit        : in std_logic;
+    sprite_rgb      : out RGB_t;
+
+    -- various graphics information
+    graphics_i      : in from_GRAPHICS_t;
+    graphics_o      : out to_GRAPHICS_t;
+    sound_data_o    : out std_logic_vector(7 downto 0);
+
+    -- custom i/o
+--    project_i       : in from_PROJECT_IO_t;
+--    project_o       : out to_PROJECT_IO_t;
+    platform_i      : in from_PLATFORM_IO_t;
+    platform_o      : out to_PLATFORM_IO_t;
+
+    dl_addr         : in std_logic_vector(11 downto 0);
+    dl_data         : in std_logic_vector(7 downto 0);
+    dl_wr           : in std_logic;
+
+    cpu_rom_addr    : out std_logic_vector(16 downto 0);
+    cpu_rom_do      : in std_logic_vector(7 downto 0);
+    gfx1_addr       : out std_logic_vector(17 downto 2);
+    gfx1_do         : in std_logic_vector(31 downto 0);
+    gfx2_addr       : out std_logic_vector(17 downto 2);
+    gfx2_do         : in std_logic_vector(31 downto 0);
+    gfx3_addr       : out std_logic_vector(17 downto 2);
+    gfx3_do         : in std_logic_vector(31 downto 0)
+  );
+
+end platform;
+
+architecture SYN of platform is
+
+  alias clk_sys         : std_logic is clkrst_i.clk(0);
+  alias rst_sys         : std_logic is clkrst_i.rst(0);
+  alias clk_video       : std_logic is clkrst_i.clk(1);
+
+  -- cpu signals  
+  signal cpu_clk_en     : std_logic;
+  signal cpu_a          : std_logic_vector(15 downto 0);
+  signal cpu_d_i        : std_logic_vector(7 downto 0);
+  signal cpu_d_o        : std_logic_vector(7 downto 0);
+  signal cpu_mem_wr     : std_logic;
+  signal cpu_io_rd      : std_logic;
+  signal cpu_io_wr      : std_logic;
+  signal cpu_irq        : std_logic;
+  signal cpu_intack     : std_logic;
+
+  -- ROM signals        
+  signal rom_cs         : std_logic;
+--  signal rom_d_o        : std_logic_vector(7 downto 0);
+  
+  -- keyboard signals
+
+  -- VRAM signals       
+  signal vram_cs        : std_logic;
+  signal vram_wr        : std_logic;
+  signal vram_d_o       : std_logic_vector(7 downto 0);
+
+  signal snd_cs         : std_logic;
+
+  -- RAM signals        
+  signal wram_cs        : std_logic;
+  signal wram_wr        : std_logic;
+  signal wram_d_o       : std_logic_vector(7 downto 0);
+
+  -- CRAM/SPRITE signals        
+  signal cram_cs        : std_logic;
+  signal cram_wr        : std_logic;
+  signal cram_d_o       : std_logic_vector(7 downto 0);
+  signal sprite_cs      : std_logic;
+
+  -- text RAM
+  signal textram_a      : std_logic_vector(11 downto 0);
+  signal textram_cs     : std_logic;
+  signal textram_wr     : std_logic;
+  signal textram_d_o    : std_logic_vector(7 downto 0);
+  signal textram_q      : std_logic_vector(15 downto 0);
+
+  -- misc signals      
+  signal in_cs          : std_logic;
+  signal in_d_o         : std_logic_vector(7 downto 0);
+  signal pal_r_wr       : std_logic;
+  signal pal_g_wr       : std_logic;
+  signal pal_b_wr       : std_logic;
+  signal sp_pal_r_wr    : std_logic;
+  signal sp_pal_g_wr    : std_logic;
+  signal sp_pal_b_wr    : std_logic;
+  signal sprite_pal_a   : std_logic_vector(7 downto 0);
+  signal tilemap1_pal_a : std_logic_vector(7 downto 0);
+  signal pal_r_q        : std_logic_vector(7 downto 0);
+  signal pal_g_q        : std_logic_vector(7 downto 0);
+  signal pal_b_q        : std_logic_vector(7 downto 0);
+
+  signal pal2_r_wr      : std_logic;
+  signal pal2_g_wr      : std_logic;
+  signal pal2_b_wr      : std_logic;
+  signal pal2_r_q       : std_logic_vector(7 downto 0);
+  signal pal2_g_q       : std_logic_vector(7 downto 0);
+  signal pal2_b_q       : std_logic_vector(7 downto 0);
+  signal tilemap2_pal_a : std_logic_vector(7 downto 0);
+
+  -- other signals
+  signal rst_platform   : std_logic;
+  signal pause          : std_logic;
+  signal rot_en         : std_logic;
+
+  -- Lode Runner 2,4
+  signal ld2_bankr1     : std_logic_vector(5 downto 0);
+  signal ld2_bankr2     : std_logic_vector(7 downto 0);
+  signal ld24_bank       : std_logic;
+
+  -- Lode Runner 3
+  signal ld3_prot5_cs   : std_logic;
+  signal ld3_prot7_cs   : std_logic;
+
+  -- Kidniki, Battle Road
+  signal kidniki_bank   : std_logic_vector(3 downto 0);
+  signal kidniki_gfxbank: std_logic;
+
+  signal spelunk2_palbank : std_logic_vector(1 downto 0);
+  signal spelunkr_palbank : std_logic;
+  signal spelunk2_bank1   : std_logic_vector(1 downto 0);
+
+begin
+
+  -- handle special keys
+  process (clk_sys, rst_sys)
+    variable spec_keys_r  : std_logic_vector(7 downto 0);
+    alias spec_keys       : std_logic_vector(7 downto 0) is inputs_i(PACE_INPUTS_NUM_BYTES-1).d;
+    variable layer_en     : std_logic_vector(4 downto 0);
+  begin
+    if rst_sys = '1' then
+      rst_platform <= '0';
+      pause <= '0';
+      rot_en <= '0';  -- to default later
+      spec_keys_r := (others => '0');
+      layer_en := "11111";
+    elsif rising_edge(clk_sys) then
+      rst_platform <= spec_keys(0);
+      if spec_keys_r(1) = '0' and spec_keys(1) = '1' then
+        pause <= not pause;
+      end if;
+      if spec_keys_r(2) = '0' and spec_keys(2) = '1' then
+        rot_en <= not rot_en;
+        if layer_en = "11111" then
+          layer_en := "00001";
+        elsif layer_en = "10000" then
+          layer_en := "11111";
+        else
+          layer_en := layer_en(3 downto 0) & layer_en(4);
+        end if;
+      end if;
+      spec_keys_r := spec_keys;
+    end if;
+    graphics_o.bit8(0)(4 downto 0) <= layer_en;
+  end process;
+  
+  --graphics_o.bit8(0)(0) <= rot_en;
+  
+  -- chip select logic
+  -- ROM $0000-$7FFF
+  --     $0000-$9FFF - LDRUN2, KIDNIKI, SPELUNKR, SPELUNK2
+  --     $0000-$BFFF - LDRUN3,4, HORIZON, YOUJYUDN
+  --     $A000-$BFFF - BATTROAD
+  rom_cs <=     '1' when STD_MATCH(cpu_a,  "0---------------") else 
+                '1' when (hwsel = HW_LDRUN2 or hwsel = HW_KIDNIKI or hwsel = HW_SPELUNKR or hwsel = HW_SPELUNK2) and cpu_a(15 downto 13) = "100" else
+                '1' when (hwsel = HW_LDRUN3 or hwsel = HW_LDRUN4 or hwsel = HW_HORIZON or hwsel = HW_YOUJYUDN) and cpu_a(15 downto 14) = "10" else
+                '1' when hwsel = HW_BATTROAD and cpu_a(15 downto 13) = "101" else
+                '0';
+
+  -- SPRITE $C000-$C0FF
+  --        $C000-$C1FF - HORIZON
+  sprite_cs <=  '1' when cpu_a(15 downto 8) = x"C0" else
+                '1' when cpu_a(15 downto 9) = x"C"&"000" and hwsel = HW_HORIZON else
+                '0';
+
+  -- VRAM/CRAM $D000-$DFFF, $A000-$AFFF - KIDNIKI, $A000-$BFFF - SPELUNKR, SPELUNK2
+  vram_cs <=    '1' when hwsel = HW_KUNGFUM and
+                          STD_MATCH(cpu_a, X"D"&"0-----------") else
+                '1' when hwsel = HW_KIDNIKI and
+                          STD_MATCH(cpu_a, X"A"&"-----------0") else
+                '1' when (hwsel = HW_SPELUNKR or hwsel = HW_SPELUNK2) and
+                          STD_MATCH(cpu_a,  "101------------0") else
+                '1' when hwsel /= HW_KUNGFUM and hwsel /= HW_KIDNIKI and
+                          STD_MATCH(cpu_a, X"D"&"-----------0") else
+                '0';
+  cram_cs <=    '1' when hwsel = HW_KUNGFUM and
+                          STD_MATCH(cpu_a, X"D"&"1-----------") else
+                '1' when hwsel = HW_KIDNIKI and
+                          STD_MATCH(cpu_a, X"A"&"-----------1") else
+                '1' when (hwsel = HW_SPELUNKR or hwsel = HW_SPELUNK2) and
+                          STD_MATCH(cpu_a,  "101------------1") else
+                '1' when hwsel /= HW_KUNGFUM and hwsel /= HW_KIDNIKI and
+                          STD_MATCH(cpu_a, X"D"&"-----------1") else
+                '0';
+
+  -- Text RAM $C800-$CFFF - BATTROAD, SPELUNKR, SPELUNK2, YOUJYUDN $D000-$DFFF - KIDNIKI, $A000-$AFFF - LOTLOT
+  textram_cs <= '1' when (hwsel = HW_BATTROAD or hwsel = HW_SPELUNKR or hwsel = HW_SPELUNK2 or hwsel = HW_YOUJYUDN) and
+                          cpu_a(15 downto 11) = x"C"&'1' else
+                '1' when hwsel = HW_KIDNIKI and
+                          cpu_a(15 downto 12) = x"D" else
+                '1' when hwsel = HW_LOTLOT and
+                          cpu_a(15 downto 12) = x"A" else
+                '0';
+
+  -- RAM $E000-$EFFF
+  wram_cs <=    '1' when STD_MATCH(cpu_a, X"E"&"------------") else '0';
+
+  -- OUTPUT $XX00
+  snd_cs <=      '1' when cpu_a(7 downto 0) = X"00" else '0';
+
+  -- INPUTS (I/O) $00-$04
+  in_cs <=      '1' when STD_MATCH(cpu_a(7 downto 0), X"0"&"00--") else 
+                '1' when STD_MATCH(cpu_a(7 downto 0), X"04") else
+                '0';
+
+  -- Lode Runner 3 protection
+  ld3_prot5_cs <= '1' when hwsel = HW_LDRUN3 and cpu_a = x"c800" else '0';
+  ld3_prot7_cs <= '1' when hwsel = HW_LDRUN3 and (cpu_a = x"cc00" or cpu_a = x"cfff") else '0';
+
+  process (clk_sys, rst_sys) begin
+    if rst_sys = '1' then
+      sound_data_o <= X"00";
+    elsif rising_edge(clk_sys) then
+      if cpu_clk_en = '1' and cpu_io_wr = '1' and snd_cs = '1' then
+        sound_data_o <= cpu_d_o;
+      end if;
+    end if; 
+  end process;
+
+  -- memory read mux
+  cpu_d_i <=  in_d_o when (cpu_io_rd = '1' and in_cs = '1') else
+              x"05" when ld3_prot5_cs = '1' else
+              x"07" when ld3_prot7_cs = '1' else
+              cpu_rom_do when rom_cs = '1' else
+              vram_d_o when vram_cs = '1' else
+              cram_d_o when cram_cs = '1' else
+              wram_d_o when wram_cs = '1' else
+              textram_d_o when textram_cs = '1' else
+              (others => '1');
+
+  -- memory block write signals 
+  vram_wr <= vram_cs and cpu_mem_wr;
+  cram_wr <= cram_cs and cpu_mem_wr;
+  wram_wr <= wram_cs and cpu_mem_wr;
+  textram_wr <= textram_cs and cpu_mem_wr;
+
+  -- sprite registers
+  sprite_reg_o.clk <= clk_sys;
+  sprite_reg_o.clk_ena <= cpu_clk_en_i;
+  sprite_reg_o.a <= cpu_a(8 downto 0)  when hwsel = HW_HORIZON else '0' & cpu_a(7 downto 0);
+  sprite_reg_o.d <= cpu_d_o;
+  sprite_reg_o.wr <= sprite_cs and cpu_mem_wr;
+
+  --
+  -- COMPONENT INSTANTIATION
+  --
+
+  BLK_CPU : block
+    signal cpu_rst        : std_logic;
+  begin
+    -- gated CPU signals
+    cpu_clk_en <= cpu_clk_en_i and not pause;
+    cpu_rst <= rst_sys or rst_platform;
+    
+    cpu_inst : entity work.Z80                                                
+      port map
+      (
+        clk     => clk_sys,                                   
+        clk_en  => cpu_clk_en,
+        reset   => cpu_rst,
+
+        addr    => cpu_a,
+        datai   => cpu_d_i,
+        datao   => cpu_d_o,
+
+        mem_rd  => open,
+        mem_wr  => cpu_mem_wr,
+        io_rd   => cpu_io_rd,
+        io_wr   => cpu_io_wr,
+
+        intreq  => cpu_irq,
+        intvec  => cpu_d_i,
+        intack  => cpu_intack,
+        nmi     => '0'
+      );
+
+    cpu_rom_addr <= 
+      '0' & "10" & ld24_bank & cpu_a(12 downto 0) when hwsel = HW_LDRUN2 and cpu_a(15) = '1' else
+      '0' & '1'  & ld24_bank & cpu_a(13 downto 0) when hwsel = HW_LDRUN4 and cpu_a(15) = '1' else
+      '1' & kidniki_bank(2 downto 0) & cpu_a(12 downto 0) when hwsel = HW_BATTROAD and cpu_a(15 downto 13) = "101" else
+      (kidniki_bank(3 downto 0) + "100") & cpu_a(12 downto 0) when hwsel = HW_KIDNIKI and cpu_a(15 downto 13) = "100" and kidniki_bank(3 downto 2) /= "11" else
+      "10" & kidniki_bank(1 downto 0) & cpu_a(12 downto 0) when hwsel = HW_SPELUNKR and cpu_a(15 downto 13) = "100" else
+      "010" & spelunk2_bank1 & cpu_a(11 downto 0) when hwsel = HW_SPELUNK2 and cpu_a(15 downto 12) = x"8" else
+      '1' & kidniki_bank & cpu_a(11 downto 0) when hwsel = HW_SPELUNK2 and cpu_a(15 downto 12) = x"9" else
+      "10" & kidniki_bank(0) & cpu_a(13 downto 0) when hwsel = HW_YOUJYUDN and cpu_a(15 downto 14) = "10" else
+      '0' & cpu_a(15 downto 0);
+
+    -- Lode Runner 2 bank switching - some kind of protection, only the level number is used to select bank 0 or 1 at $8000
+    -- writes to $80 (level number)
+    -- writes to $81 (unknown, from a table)
+    -- reads from $80 (number of times from a table)
+    process (clk_sys, rst_sys)
+    begin
+      if rst_sys = '1' then
+        ld2_bankr1 <= (others => '0');
+        ld2_bankr2 <= (others => '0');
+        ld24_bank <= '0';
+        kidniki_bank <= (others => '0');
+        kidniki_gfxbank <= '0';
+        spelunkr_palbank <= '0';
+        spelunk2_bank1 <= (others => '0');
+      elsif rising_edge(clk_sys) then
+        if cpu_clk_en = '1' and cpu_io_wr = '1' then
+          case cpu_a(7 downto 0) is
+            when X"80" => ld2_bankr1 <= cpu_d_o(5 downto 0);
+            when X"81" => ld2_bankr2 <= cpu_d_o;
+            when X"83" => if hwsel = HW_BATTROAD or hwsel = HW_YOUJYUDN then kidniki_bank <= cpu_d_o(3 downto 0); end if;
+            when X"84" => if hwsel = HW_KIDNIKI then kidniki_gfxbank <= cpu_d_o(0); end if;
+            -- Kidniki banks: 0-7, C-F, 8-B not used
+            when X"85" => if hwsel = HW_KIDNIKI then kidniki_bank <= cpu_d_o(3) & (not cpu_d_o(3) and cpu_d_o(2)) & cpu_d_o(1 downto 0); end if;
+            when others => null;
+          end case;
+        end if;
+
+        if cpu_clk_en = '1' and cpu_io_rd = '1' and cpu_a(7 downto 0) = x"80" then
+          if ld2_bankr1 = 6 or ld2_bankr1 = 8 or ld2_bankr1 = 12 or ld2_bankr1 = 13 or ld2_bankr1 = 14 or ld2_bankr1 = 15 or ld2_bankr1 = 16 or
+             ld2_bankr1 = 21 or ld2_bankr1 >= 23
+          then
+            ld24_bank <= '1';
+          else
+            ld24_bank <= '0';
+          end if;
+        end if;
+
+        if cpu_clk_en = '1' and cpu_mem_wr = '1' then
+          if cpu_a = x"c800" and hwsel = HW_LDRUN4 then
+            ld24_bank <= cpu_d_o(0);
+          end if;
+          if cpu_a = x"d003" and hwsel = HW_SPELUNK2 then
+            kidniki_bank <= cpu_d_o(5 downto 2);
+            spelunk2_bank1 <= cpu_d_o(7 downto 6);
+          end if;
+          if cpu_a = x"d004" and hwsel = HW_SPELUNKR then
+            kidniki_bank(1 downto 0) <= cpu_d_o(1 downto 0);
+          end if;
+          if cpu_a = x"d005" and hwsel = HW_SPELUNKR then
+            spelunkr_palbank <= cpu_d_o(0);
+          end if;
+        end if;
+
+      end if;
+    end process;
+  end block BLK_CPU;
+
+  BLK_INTERRUPTS : block
+  
+    signal vblank_r     : std_logic;
+
+  begin
+
+    -- generate INT
+    process (clk_sys, rst_sys)
+    begin
+      if rst_sys = '1' then
+        cpu_irq <= '0';
+      elsif rising_edge(clk_sys) then
+        vblank_r <= graphics_i.vblank;
+        if vblank_r = '0' and graphics_i.vblank = '1' then
+          cpu_irq <= '1';
+        end if;
+        if cpu_intack = '1' then
+          cpu_irq <= '0';
+        end if;
+      end if;
+    end process;
+
+  end block BLK_INTERRUPTS;
+
+  BLK_INPUTS : block
+  begin
+    in_d_o <= inputs_i(0).d when cpu_a(2 downto 0) = "000" else
+              inputs_i(1).d when cpu_a(2 downto 0) = "001" else
+              inputs_i(2).d when cpu_a(2 downto 0) = "010" else
+              inputs_i(3).d when cpu_a(2 downto 0) = "011" else
+              inputs_i(4).d;
+  end block BLK_INPUTS;
+  
+  BLK_SCROLL : block
+    signal m62_hscroll  : std_logic_vector(15 downto 0);
+    signal m62_vscroll  : std_logic_vector(15 downto 0);
+    signal m62_vscroll2 : std_logic_vector(15 downto 0);
+    signal m62_topbottom_mask: std_logic;
+    signal scrollram_d_o  : std_logic_vector(15 downto 0);
+    signal scrollram_wr   : std_logic;
+  begin
+    horizon_scrollram_inst : entity work.dpram
+    generic map
+    (
+      init_file  => "",
+      widthad_a  => 5,
+      width_a    => 16,
+      widthad_b  => 6,
+      width_b    => 8
+    )
+    port map
+    (
+      clock_b    => clk_sys,
+      address_b  => cpu_a(5 downto 0),
+      wren_b     => scrollram_wr,
+      data_b     => cpu_d_o,
+      q_b        => open,
+
+      clock_a    => clk_video,
+      address_a  => tilemap_i(1).map_a(10 downto 6),
+      wren_a     => '0',
+      data_a     => (others => 'X'),
+      q_a        => scrollram_d_o
+    );
+
+    scrollram_wr <= '1' when cpu_mem_wr = '1' and cpu_a(15 downto 6) = X"C8"&"00" else '0';
+
+    process (clk_sys, rst_sys)
+    begin
+      if rst_sys = '1' then
+        m62_hscroll <= (others => '0');
+        m62_vscroll <= (others => '0');
+        m62_vscroll2 <= (others => '0');
+        m62_topbottom_mask <= '0';
+        spelunk2_palbank <= "00";
+      elsif rising_edge(clk_sys) then
+        if hwsel = HW_LOTLOT then
+          m62_hscroll <= std_logic_vector(to_signed(-64, m62_hscroll'length));
+          m62_vscroll <= std_logic_vector(to_unsigned(32, m62_vscroll'length));
+        end if;
+        if cpu_clk_en = '1' and cpu_mem_wr = '1' then
+          case cpu_a is
+            when X"A000" =>
+              if hwsel = HW_KUNGFUM then
+                m62_hscroll(7 downto 0) <= cpu_d_o;
+              end if;
+            when X"B000" =>
+              if hwsel = HW_KUNGFUM then
+                m62_hscroll(15 downto 8) <= cpu_d_o;
+              end if;
+            when x"D000" =>
+              if hwsel = HW_SPELUNKR or hwsel = HW_SPELUNK2 then
+                m62_vscroll(7 downto 0) <= cpu_d_o;
+              end if;
+            when x"D001" =>
+              if hwsel = HW_SPELUNKR then
+                m62_vscroll(15 downto 8) <= cpu_d_o;
+              end if;
+              if hwsel = HW_SPELUNK2 then
+                m62_hscroll(7 downto 0) <= cpu_d_o;
+              end if;
+            when x"D002" =>
+              if hwsel = HW_SPELUNKR then
+                m62_hscroll(7 downto 0) <= cpu_d_o;
+              end if;
+              if hwsel = HW_SPELUNK2 then
+                m62_vscroll(8) <= cpu_d_o(0);
+                m62_hscroll(8) <= cpu_d_o(1);
+                spelunk2_palbank <= cpu_d_o(3 downto 2);
+              end if;
+            when x"D003" =>
+              if hwsel = HW_SPELUNKR then
+                m62_hscroll(15 downto 8) <= cpu_d_o;
+              end if;
+            when others =>
+              null;
+          end case;
+        end if; -- cpu_wr
+
+        if cpu_clk_en = '1' and cpu_io_wr = '1' then
+          -- background 1 vscroll
+          if (hwsel = HW_LDRUN3 or hwsel = HW_BATTROAD) and cpu_a(7 downto 0) = x"80" then
+            m62_vscroll(7 downto 0) <= cpu_d_o;
+          end if;
+          -- background 1 hscroll
+          if (hwsel = HW_LDRUN4 and cpu_a(7 downto 0) = x"82") or
+             ((hwsel = HW_BATTROAD or hwsel = HW_KIDNIKI) and cpu_a(7 downto 0) = x"81") or 
+						 (hwsel = HW_YOUJYUDN and cpu_a(7 downto 0) = x"80") then
+            m62_hscroll(15 downto 8) <= cpu_d_o;
+          end if;
+          if (hwsel = HW_LDRUN4 and cpu_a(7 downto 0) = x"83") or
+             (hwsel = HW_BATTROAD and cpu_a(7 downto 0) = x"82") or
+             (hwsel = HW_KIDNIKI and cpu_a(7 downto 0) = x"80") or
+						 (hwsel = HW_YOUJYUDN and cpu_a(7 downto 0) = x"81") then
+            m62_hscroll(7 downto 0) <= cpu_d_o;
+          end if;
+          if hwsel = HW_LDRUN3 and cpu_a(7 downto 0) = x"81" then
+            m62_topbottom_mask <= cpu_d_o(0);
+          end if;
+          -- backrground 2 vscroll
+          if hwsel = HW_KIDNIKI and cpu_a(7 downto 0) = x"82" then
+            m62_vscroll2(7 downto 0) <= cpu_d_o;
+          end if;
+          if hwsel = HW_KIDNIKI and cpu_a(7 downto 0) = x"83" then
+            m62_vscroll2(15 downto 8) <= cpu_d_o;
+          end if;
+
+        end if;
+      end if; -- rising_edge(clk_sys)
+    end process;
+    graphics_o.bit16(0) <= scrollram_d_o when hwsel = HW_HORIZON else m62_hscroll;
+    graphics_o.bit16(1) <= m62_vscroll;
+    graphics_o.bit16(2) <= m62_vscroll2;
+  end block BLK_SCROLL;
+
+
+  BLK_GFX_ROMS : block
+  
+    type gfx_rom_d_a is array(M62_CHAR_ROM'range) of std_logic_vector(7 downto 0);
+    signal chr_rom_d      : gfx_rom_d_a;
+    type spr_rom_d_a is array(0 to 11) of std_logic_vector(7 downto 0);
+    signal spr_rom        : spr_rom_d_a;
+    
+  begin
+
+    -- external background ROMs
+    gfx1_addr <= 
+      '0' & tilemap_i(1).tile_a(14 downto 0) when hwsel = HW_SPELUNKR or hwsel = HW_SPELUNK2 or hwsel = HW_YOUJYUDN else 
+      '0' & kidniki_gfxbank & tilemap_i(1).tile_a(13 downto 0);
+
+    tilemap_o(1).tile_d(23 downto 0) <= gfx1_do(7 downto 0) & gfx1_do(15 downto 8) & gfx1_do(23 downto 16);
+
+    gfx3_addr <= '0' & tilemap_i(2).tile_a(14 downto 0);
+
+    tilemap_o(2).tile_d(23 downto 0) <= gfx3_do(7 downto 0) & gfx3_do(15 downto 8) & gfx3_do(23 downto 16);
+
+    -- internal background ROMs
+--    GEN_CHAR_ROMS : for i in M62_CHAR_ROM'range generate
+--      char_rom_inst : entity work.sprom
+--        generic map
+--        (
+--          init_file  => "./roms/" &
+--                          M62_CHAR_ROM(i) & ".hex",
+--          widthad_a  => 13
+--        )
+--        port map
+--        (
+--          clock      => clk_video,
+--          address    => tilemap_i(1).tile_a(12 downto 0),
+--          q          => chr_rom_d(i)
+--        );
+--    end generate GEN_CHAR_ROMS;
+--
+--    tilemap_o(1).tile_d(23 downto 0) <= chr_rom_d(0) & chr_rom_d(1) & chr_rom_d(2);
+
+    -- external sprite ROMs
+    gfx2_addr <= sprite_i.a(15 downto 0);
+    sprite_o.d(23 downto 0) <= gfx2_do(7 downto 0) & gfx2_do(15 downto 8) & gfx2_do(23 downto 16);
+
+    -- internal sprite ROMs
+--    GEN_SPRITE_ROMS : for i in M62_SPRITE_ROM'range generate
+--      sprite_rom_inst : entity work.sprom
+--        generic map
+--        (
+--          init_file  => "./roms/" &
+--                          M62_SPRITE_ROM(i) & ".hex",
+--          widthad_a  => 13
+--        )
+--        port map
+--        (
+--          clock                 => clk_video,
+--          address(12 downto 5)  => sprite_i.a(12 downto 5),
+--          address(4 downto 0)   => sprite_i.a(4 downto 0),
+--          q                     => spr_rom(i)
+--        );
+--    end generate GEN_SPRITE_ROMS;
+--
+--    sprite_o.d(sprite_o.d'left downto 24) <= (others => '0');
+--    sprite_o.d(23 downto 0) <=  spr_rom(0) & 
+--                                spr_rom(1) &
+--                                spr_rom(2)
+--                                  when sprite_i.a(14 downto 13) = "00" else
+--                                spr_rom(3) &
+--                                spr_rom(4) &
+--                                spr_rom(5) 
+--                                  when sprite_i.a(14 downto 13) = "01" else
+--                                spr_rom(6) &
+--                                spr_rom(7) &
+--                                spr_rom(8)
+--                                  when sprite_i.a(14 downto 13) = "10" else
+--                                spr_rom(9) &
+--                                spr_rom(10) &
+--                                spr_rom(11);
+
+  end block BLK_GFX_ROMS;
+
+  BLK_VRAM : block
+    signal vram_a   : std_logic_vector(11 downto 0);
+    alias cram_a    : std_logic_vector(11 downto 0) is vram_a;
+  begin
+
+    textram_a <= '0' & cpu_a(10 downto 0) when hwsel = HW_BATTROAD or hwsel = HW_SPELUNKR or hwsel = HW_SPELUNK2 or hwsel = HW_YOUJYUDN else cpu_a(11 downto 0);
+
+    vram_a <= '0' & cpu_a(10 downto 0) when hwsel = HW_KUNGFUM else
+              cpu_a(12 downto 1) when hwsel = HW_SPELUNKR or hwsel = HW_SPELUNK2 else
+              '0' & cpu_a(11 downto 1);
+
+    vram_inst : entity work.dpram
+      generic map
+      (
+        init_file  => "",
+        widthad_a  => 12,
+        widthad_b  => 12
+      )
+      port map
+      (
+        clock_b    => clk_sys,
+        address_b  => vram_a,
+        wren_b     => vram_wr,
+        data_b     => cpu_d_o,
+        q_b        => vram_d_o,
+
+        clock_a    => clk_video,
+        address_a  => tilemap_i(1).map_a(11 downto 0),
+        wren_a     => '0',
+        data_a     => (others => 'X'),
+        q_a        => tilemap_o(1).map_d(7 downto 0)
+      );
+    tilemap_o(1).map_d(15 downto 8) <= (others => '0');
+
+    cram_inst : entity work.dpram
+      generic map
+      (
+        init_file  => "",
+        widthad_a  => 12,
+        widthad_b  => 12
+      )
+      port map
+      (
+        clock_b     => clk_sys,
+        address_b   => cram_a,
+        wren_b      => cram_wr,
+        data_b      => cpu_d_o,
+        q_b         => cram_d_o,
+
+        clock_a     => clk_video,
+        address_a   => tilemap_i(1).attr_a(11 downto 0),
+        wren_a      => '0',
+        data_a      => (others => 'X'),
+        q_a         => tilemap_o(1).attr_d(7 downto 0)
+      );
+    tilemap_o(1).attr_d(15 downto 8) <= (others => '0');
+
+    textram_inst : entity work.dpram
+      generic map
+      (
+        init_file  => "",
+        widthad_a  => 11,
+        width_a    => 16,
+        widthad_b  => 12,
+        width_b    => 8
+      )
+      port map
+      (
+        clock_b    => clk_sys,
+        address_b  => textram_a,
+        wren_b     => textram_wr,
+        data_b     => cpu_d_o,
+        q_b        => textram_d_o,
+
+        clock_a    => clk_video,
+        address_a  => tilemap_i(2).map_a(10 downto 0),
+        wren_a     => '0',
+        data_a     => (others => 'X'),
+        q_a        => textram_q
+      );
+
+    tilemap_o(2).attr_d(7 downto 0) <= textram_q(15 downto 8);
+    tilemap_o(2).map_d(7 downto 0) <= textram_q(7 downto 0);
+
+  end block BLK_VRAM;
+
+  wram_inst : entity work.spram
+    generic map
+    (
+      widthad_a => 12
+    )
+    port map
+    (
+      clock     => clk_sys,
+      address   => cpu_a(11 downto 0),
+      data      => cpu_d_o,
+      wren      => wram_wr,
+      q         => wram_d_o
+    );
+
+  -- tilemap 1 palette address
+  tilemap1_pal_a <= spelunkr_palbank & tilemap_i(1).pal_a(6 downto 0) when hwsel = HW_SPELUNKR else
+                    spelunk2_palbank(0) & tilemap_i(1).pal_a(6 downto 0) when hwsel = HW_SPELUNK2 and tilemap_i(2).set = '0' else
+                    spelunk2_palbank(0) & tilemap_i(2).pal_a(6 downto 0) when hwsel = HW_SPELUNK2 and tilemap_i(2).set = '1' else
+                    '0' & tilemap_i(1).pal_a(6 downto 0) when hwsel = HW_BATTROAD else
+                    tilemap_i(1).pal_a(7 downto 0);
+
+  -- Spelunk2 uses 512 entries/palette in an odd way: 
+  -- - red and green are stored in the first two ROMs, using the first and second half bytes
+  -- - blue is stored in the third and fourth ROMs, using the second half byte
+
+  tilemap_o(1).rgb.r(9 downto 2) <= pal_g_q(3 downto 0) & pal_g_q(3 downto 0) when hwsel = HW_SPELUNK2 and spelunk2_palbank(1) = '1' else
+                                    pal_r_q(3 downto 0) & pal_r_q(3 downto 0);
+  tilemap_o(1).rgb.g(9 downto 2) <= pal_r_q(7 downto 4) & pal_r_q(7 downto 4) when hwsel = HW_SPELUNK2 and spelunk2_palbank(1) = '0' else
+                                    pal_g_q(7 downto 4) & pal_g_q(7 downto 4) when hwsel = HW_SPELUNK2 and spelunk2_palbank(1) = '1' else
+                                    pal_g_q(3 downto 0) & pal_g_q(3 downto 0);
+  tilemap_o(1).rgb.b(9 downto 2) <= pal2_r_q(3 downto 0) & pal2_r_q(3 downto 0) when hwsel = HW_SPELUNK2 and spelunk2_palbank(1) = '1' else
+                                    pal_b_q(3 downto 0) & pal_b_q(3 downto 0);
+
+  -- tilemap 1 palettes
+  pal_r : entity work.dpram
+    generic map
+    (
+      init_file  => "",
+      widthad_a  => 8,
+      widthad_b  => 8
+    )
+    port map
+    (
+      clock_b     => clk_sys,
+      address_b   => dl_addr(7 downto 0),
+      wren_b      => pal_r_wr,
+      data_b      => dl_data,
+      q_b         => open,
+
+      clock_a     => not clk_video,
+      address_a   => tilemap1_pal_a,
+      wren_a      => '0',
+      data_a      => (others => 'X'),
+      q_a         => pal_r_q
+    );
+  pal_r_wr <= '1' when dl_wr = '1' and dl_addr(11 downto 8) = x"3" else '0';  -- 300-3FF
+
+  pal_g : entity work.dpram
+    generic map
+    (
+      init_file  => "",
+      widthad_a  => 8,
+      widthad_b  => 8
+    )
+    port map
+    (
+      clock_b     => clk_sys,
+      address_b   => dl_addr(7 downto 0),
+      wren_b      => pal_g_wr,
+      data_b      => dl_data,
+      q_b         => open,
+
+      clock_a     => not clk_video,
+      address_a   => tilemap1_pal_a,
+      wren_a      => '0',
+      data_a      => (others => 'X'),
+      q_a         => pal_g_q
+    );
+  pal_g_wr <= '1' when dl_wr = '1' and dl_addr(11 downto 8) = x"4" else '0';  -- 400-4FF
+
+  pal_b : entity work.dpram
+    generic map
+    (
+      init_file  => "",
+      widthad_a  => 8,
+      widthad_b  => 8
+    )
+    port map
+    (
+      clock_b     => clk_sys,
+      address_b   => dl_addr(7 downto 0),
+      wren_b      => pal_b_wr,
+      data_b      => dl_data,
+      q_b         => open,
+
+      clock_a     => not clk_video,
+      address_a   => tilemap1_pal_a,
+      wren_a      => '0',
+      data_a      => (others => 'X'),
+      q_a         => pal_b_q
+    );
+  pal_b_wr <= '1' when dl_wr = '1' and dl_addr(11 downto 8) = x"5" else '0';  -- 500-5FF
+
+  -- tilemap 2 palette address
+  -- Use this for Spelunk2's second blue ROM, too
+  tilemap2_pal_a <= spelunk2_palbank(0) & tilemap_i(1).pal_a(6 downto 0) when hwsel = HW_SPELUNK2 else
+                    '1' & tilemap_i(2).pal_a(6 downto 0) when hwsel = HW_YOUJYUDN else
+                    tilemap_i(2).pal_a(7 downto 0);
+
+  tilemap_o(2).rgb.r(9 downto 2) <= pal2_r_q(7 downto 6) & pal2_r_q(7 downto 6) & pal2_r_q(7 downto 6) & pal2_r_q(7 downto 6) when hwsel = HW_BATTROAD else
+                                    tilemap_o(1).rgb.r(9 downto 2) when hwsel = HW_SPELUNK2 else
+                                    pal2_r_q(3 downto 0) & pal2_r_q(3 downto 0);
+  tilemap_o(2).rgb.g(9 downto 2) <= pal2_r_q(5 downto 3) & pal2_r_q(5 downto 3) & pal2_r_q(5 downto 4) when hwsel = HW_BATTROAD else
+                                    tilemap_o(1).rgb.g(9 downto 2) when hwsel = HW_SPELUNK2 else
+                                    pal2_g_q(3 downto 0) & pal2_g_q(3 downto 0);
+  tilemap_o(2).rgb.b(9 downto 2) <= pal2_r_q(2 downto 0) & pal2_r_q(2 downto 0) & pal2_r_q(2 downto 1) when hwsel = HW_BATTROAD else
+                                    tilemap_o(1).rgb.b(9 downto 2) when hwsel = HW_SPELUNK2 else
+                                    pal2_b_q(3 downto 0) & pal2_b_q(3 downto 0);
+
+  -- tilemap 2 palettes
+  pal2_r : entity work.dpram
+    generic map
+    (
+      init_file  => "",
+      widthad_a  => 8,
+      widthad_b  => 8
+    )
+    port map
+    (
+      clock_b     => clk_sys,
+      address_b   => dl_addr(7 downto 0),
+      wren_b      => pal2_r_wr,
+      data_b      => dl_data,
+      q_b         => open,
+
+      clock_a     => not clk_video,
+      address_a   => tilemap2_pal_a,
+      wren_a      => '0',
+      data_a      => (others => 'X'),
+      q_a         => pal2_r_q
+    );
+  pal2_r_wr <= '1' when dl_wr = '1' and dl_addr(11 downto 8) = x"6" else '0';  -- 600-6FF
+
+  pal2_g : entity work.dpram
+    generic map
+    (
+      init_file  => "",
+      widthad_a  => 8,
+      widthad_b  => 8
+    )
+    port map
+    (
+      clock_b     => clk_sys,
+      address_b   => dl_addr(7 downto 0),
+      wren_b      => pal2_g_wr,
+      data_b      => dl_data,
+      q_b         => open,
+
+      clock_a     => not clk_video,
+      address_a   => tilemap2_pal_a,
+      wren_a      => '0',
+      data_a      => (others => 'X'),
+      q_a         => pal2_g_q
+    );
+  pal2_g_wr <= '1' when dl_wr = '1' and dl_addr(11 downto 8) = x"7" else '0';  -- 700-7FF
+
+  pal2_b : entity work.dpram
+    generic map
+    (
+      init_file  => "",
+      widthad_a  => 8,
+      widthad_b  => 8
+    )
+    port map
+    (
+      clock_b     => clk_sys,
+      address_b   => dl_addr(7 downto 0),
+      wren_b      => pal2_b_wr,
+      data_b      => dl_data,
+      q_b         => open,
+
+      clock_a     => not clk_video,
+      address_a   => tilemap2_pal_a,
+      wren_a      => '0',
+      data_a      => (others => 'X'),
+      q_a         => pal2_b_q
+    );
+  pal2_b_wr <= '1' when dl_wr = '1' and dl_addr(11 downto 8) = x"8" else '0';  -- 800-8FF
+
+  -- sprite palette address
+  sprite_pal_a <= '0' & sprite_i.pal_a(6 downto 0) when
+                    hwsel = HW_LDRUN or
+                    hwsel = HW_LDRUN2 or
+                    hwsel = HW_LDRUN3 or
+                    hwsel = HW_LDRUN4 or
+                    hwsel = HW_BATTROAD
+                  else sprite_i.pal_a;
+
+  -- sprite palettes
+  sp_pal_r : entity work.dpram
+    generic map
+    (
+      init_file  => "",
+      widthad_a  => 8,
+      widthad_b  => 8
+    )
+    port map
+    (
+      clock_b     => clk_sys,
+      address_b   => dl_addr(7 downto 0),
+      wren_b      => sp_pal_r_wr,
+      data_b      => dl_data(3 downto 0) & dl_data(3 downto 0),
+      q_b         => open,
+
+      clock_a     => not clk_video,
+      address_a   => sprite_pal_a,
+      wren_a      => '0',
+      data_a      => (others => '0'),
+      q_a         => sprite_rgb.r(9 downto 2)
+    );
+  sp_pal_r_wr <= '1' when dl_wr = '1' and dl_addr(11 downto 8) = x"0" else '0';  -- 000-0FF
+
+  sp_pal_g : entity work.dpram
+    generic map
+    (
+      init_file  => "",
+      widthad_a  => 8,
+      widthad_b  => 8
+    )
+    port map
+    (
+      clock_b     => clk_sys,
+      address_b   => dl_addr(7 downto 0),
+      wren_b      => sp_pal_g_wr,
+      data_b      => dl_data(3 downto 0) & dl_data(3 downto 0),
+      q_b         => open,
+
+      clock_a     => not clk_video,
+      address_a   => sprite_pal_a,
+      wren_a      => '0',
+      data_a      => (others => '0'),
+      q_a         => sprite_rgb.g(9 downto 2)
+    );
+  sp_pal_g_wr <= '1' when dl_wr = '1' and dl_addr(11 downto 8) = x"1" else '0';  -- 100-1FF
+
+  sp_pal_b : entity work.dpram
+    generic map
+    (
+      init_file  => "",
+      widthad_a  => 8,
+      widthad_b  => 8
+    )
+    port map
+    (
+      clock_b     => clk_sys,
+      address_b   => dl_addr(7 downto 0),
+      wren_b      => sp_pal_b_wr,
+      data_b      => dl_data(3 downto 0) & dl_data(3 downto 0),
+      q_b         => open,
+
+      clock_a     => not clk_video,
+      address_a   => sprite_pal_a,
+      wren_a      => '0',
+      data_a      => (others => '0'),
+      q_a         => sprite_rgb.b(9 downto 2)
+    );
+  sp_pal_b_wr <= '1' when dl_wr = '1' and dl_addr(11 downto 8) = x"2" else '0';  -- 200-2FF
+
+  -- unused outputs
+
+  sprite_o.ld <= '0';
+  --graphics_o <= NULL_TO_GRAPHICS;
+  leds_o <= (others => '0');
+  
+end SYN;
--- a/Hardware/rtl/platform_pkg.vhd
+++ b/Hardware/rtl/platform_pkg.vhd
@@ -0,0 +1,74 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+
+use work.platform_variant_pkg.all;
+use work.video_controller_pkg.all;
+package platform_pkg is
+
+--  constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_VGA_640x480_60Hz;
+--  constant PACE_CLK0_DIVIDE_BY              : natural := 3;
+--  constant PACE_CLK0_MULTIPLY_BY            : natural := 5;   -- 24*5/3 = 40MHz
+--  constant PACE_CLK1_DIVIDE_BY              : natural := 19;
+--  constant PACE_CLK1_MULTIPLY_BY            : natural := 20; 	-- 24*20/19 = 25.263158MHz
+--  constant PACE_VIDEO_H_SCALE       	      : integer := 1;
+--  constant PACE_VIDEO_V_SCALE       	      : integer := 1;
+--  constant PACE_VIDEO_H_SYNC_POLARITY       : std_logic := '0';
+--  constant PACE_VIDEO_V_SYNC_POLARITY       : std_logic := '0';
+
+--  constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_ARCADE_STD_336x240_60Hz;
+--  constant PACE_CLK0_DIVIDE_BY              : natural := 19;
+--  constant PACE_CLK0_MULTIPLY_BY            : natural := 20;  -- 27*20/19 = 24MHz
+--  constant PACE_CLK1_DIVIDE_BY              : natural := 19;
+--  constant PACE_CLK1_MULTIPLY_BY            : natural := 5;   -- 27*5/19 = 7.157895MHz
+--  constant PACE_VIDEO_H_SCALE       	      : integer := 1;
+--  constant PACE_VIDEO_V_SCALE       	      : integer := 1;
+--  constant PACE_VIDEO_H_SYNC_POLARITY       : std_logic := '0';
+--  constant PACE_VIDEO_V_SYNC_POLARITY       : std_logic := '0';
+
+  constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_IREMM62;
+  constant PACE_CLK0_DIVIDE_BY              : natural := 9;
+  constant PACE_CLK0_MULTIPLY_BY            : natural := 8;   -- 27*8/9 = 24MHz
+  constant PACE_CLK1_DIVIDE_BY              : natural := 27;
+  constant PACE_CLK1_MULTIPLY_BY            : natural := 8;   -- 27*8/9 = 24MHz
+  constant PACE_VIDEO_H_SCALE               : integer := 1;
+  constant PACE_VIDEO_V_SCALE               : integer := 1;
+  constant PACE_ENABLE_ADV724               : std_logic := '1';
+  constant USE_VIDEO_VBLANK_INTERRUPT       : boolean := false;
+  constant PACE_VIDEO_H_SYNC_POLARITY       : std_logic := '1';
+  constant PACE_VIDEO_V_SYNC_POLARITY       : std_logic := '1';
+
+  constant PACE_VIDEO_BORDER_RGB            : RGB_t := RGB_BLACK;
+
+--  constant M62_VIDEO_H_SIZE                 : integer := 384;
+--  constant M62_VIDEO_H_OFFSET               : integer := (512-M62_VIDEO_H_SIZE)/2;
+  constant M62_VIDEO_V_SIZE                 : integer := 256;
+
+  constant PACE_VIDEO_NUM_BITMAPS           : natural := 0;
+  constant PACE_VIDEO_NUM_TILEMAPS          : natural := 2;
+  constant PACE_VIDEO_NUM_SPRITES           : natural := 64;
+--  constant PACE_VIDEO_H_SIZE                : integer := M62_VIDEO_H_SIZE;
+  constant PACE_VIDEO_V_SIZE                : integer := M62_VIDEO_V_SIZE;
+  constant PACE_VIDEO_L_CROP                : integer := 8;
+  constant PACE_VIDEO_R_CROP                : integer := 8;
+  constant PACE_VIDEO_PIPELINE_DELAY        : integer := 5;
+
+  constant PACE_INPUTS_NUM_BYTES            : integer := 6;
+
+  constant CLK0_FREQ_MHz                    : natural := 
+    27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY;
+  constant CPU_FREQ_MHz                     : natural := 3;
+
+  constant M62_CPU_CLK_ENA_DIVIDE_BY    : natural := CLK0_FREQ_MHz / CPU_FREQ_MHz;
+
+  type from_PLATFORM_IO_t is record
+    not_used  : std_logic;
+  end record;
+
+  type to_PLATFORM_IO_t is record
+    not_used  : std_logic;
+  end record;
+
+end;
--- a/Hardware/LodeRunner_MiST/rtl/platform_variant_pkg.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/platform_variant_pkg.vhd
@@ -9,8 +9,21 @@ use work.platform_pkg.all;
 package platform_variant_pkg is


-  constant PLATFORM_VARIANT             : string := "ldrun";
-  
+  constant HW_LDRUN    : integer := 0;
+  constant HW_LDRUN2   : integer := 1;
+  constant HW_LDRUN3   : integer := 2;
+  constant HW_LDRUN4   : integer := 3;
+  constant HW_KUNGFUM  : integer := 4;
+  constant HW_HORIZON  : integer := 5;
+  constant HW_BATTROAD : integer := 6;
+  constant HW_KIDNIKI  : integer := 7;
+  constant HW_LOTLOT   : integer := 8;
+  constant HW_SPELUNKR : integer := 9;
+  constant HW_SPELUNK2 : integer := 10;
+  constant HW_YOUJYUDN : integer := 11;
+
+  subtype HWSEL_t is integer range 0 to 11;
+
  type rom_a is array (natural range <>) of string;
  
  constant M62_ROM                      : rom_a(0 to 3) := 
@@ -36,11 +49,11 @@ package platform_variant_pkg is
                                            2 => "lr-b-4c"
                                          );

-	type pal_rgb_t is array (0 to 2) of std_logic_vector(7 downto 0);
-	type pal_a is array (natural range <>) of pal_rgb_t;
+  type pal_rgb_t is array (0 to 2) of std_logic_vector(7 downto 0);
+  type pal_a is array (natural range <>) of pal_rgb_t;

-	constant tile_pal : pal_a(0 to 255) :=
-	(
+  constant tile_pal : pal_a(0 to 255) :=
+  (
    17 => (0=>"00000011", 1=>"11111111", 2=>"11111111"),  -- 03FFFF
    25 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
    33 => (0=>"11111111", 1=>"11111111", 2=>"11111111"),  -- FFFFFF
@@ -200,11 +213,11 @@ package platform_variant_pkg is
    251 => (0=>"10110111", 1=>"01110000", 2=>"01100010"),  -- B77062
    252 => (0=>"11001100", 1=>"01110000", 2=>"10000100"),  -- CC7084
    253 => (0=>"11110000", 1=>"10100110", 2=>"10010100"),  -- F0A694
-		others => (others => "00000011")
+    others => (others => "00000011")
  );
                                          
-	constant sprite_pal : pal_a(0 to 255) :=
-	(
+  constant sprite_pal : pal_a(0 to 255) :=
+  (
    1 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
    2 => (0=>"00000011", 1=>"11111111", 2=>"00000011"),  -- 03FF03
    3 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
@@ -411,30 +424,50 @@ package platform_variant_pkg is
    253 => (0=>"11111111", 1=>"11111111", 2=>"11111111"),  -- FFFFFF
    254 => (0=>"00000011", 1=>"10010100", 2=>"00000011"),  -- 039403
    255 => (0=>"11110000", 1=>"11110000", 2=>"11110000"),  -- F0F0F0
-		others => (others => "00000011")
-	);
+    others => (others => "00000011")
+  );

  -- table of sprite heights
  type prom_a is array (natural range <>) of integer range 0 to 3;
-  constant sprite_prom : prom_a(0 to 31) :=
-  (
-    4 => 0,
-    5 => 0,
-    6 => 0,
-    7 => 0,
-    12 => 0,
-    13 => 0,
-    14 => 0,
-    15 => 0,
-    20 => 0,
-    21 => 0,
-    22 => 0,
-    23 => 0,
-    28 => 0,
-    29 => 0,
-    30 => 0,
-    31 => 0,
-    others => 1
-  );
-  
+
+-- ldrun
+--  constant sprite_prom : prom_a(0 to 31) :=
+--  (
+--    4 => 0,
+--    5 => 0,
+--    6 => 0,
+--    7 => 0,
+--    12 => 0,
+--    13 => 0,
+--    14 => 0,
+--    15 => 0,
+--    20 => 0,
+--    21 => 0,
+--    22 => 0,
+--    23 => 0,
+--    28 => 0,
+--    29 => 0,
+--    30 => 0,
+--    31 => 0,
+--    others => 1
+--  );
+
+-- kungfum
+--  constant sprite_prom : prom_a(0 to 31) :=
+--  (
+--    0 => 0,
+--    1 => 0,
+--    8 => 0,
+--    9 => 0,
+--    12 => 2,
+--    13 => 2,
+--    14 => 2,
+--    15 => 2,
+--    16 => 0,
+--    21 => 0,
+--    23 => 0,
+--    24 => 0,
+--    27 => 0,
+--    others => 1
+--  );
 end package platform_variant_pkg;
--- a/Hardware/LodeRunner_MiST/rtl/pll_mist.qip
+++ b/Hardware/LodeRunner_MiST/rtl/pll_mist.qip
--- a/Hardware/LodeRunner_MiST/rtl/pll_mist.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/pll_mist.vhd
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************


--Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -164,17 +164,17 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 27,
+		clk0_divide_by => 3,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 40,
+		clk0_multiply_by => 8,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 43,
+		clk1_divide_by => 9,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 40,
+		clk1_multiply_by => 8,
 		clk1_phase_shift => "0",
-		clk2_divide_by => 3,
+		clk2_divide_by => 9,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 8,
+		clk2_multiply_by => 16,
 		clk2_phase_shift => "0",
 		clk3_divide_by => 5400,
 		clk3_duty_cycle => 50,
@@ -262,16 +262,16 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "43"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "3"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
 -- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.116280"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "72.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "72.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "48.000000"
 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.895000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
@@ -301,18 +301,18 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "40"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "8"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "44"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "11"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
 -- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.26315800"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "72.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "72.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "48.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89500000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
@@ -369,17 +369,17 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "40"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "43"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "16"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5400"
 -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- a/Hardware/LodeRunner_MiST/rtl/sdram.sv
+++ b/Hardware/LodeRunner_MiST/rtl/sdram.sv
@@ -37,6 +37,7 @@ module sdram (
 	// cpu/chipset interface
 	input             init_n,     // init signal after FPGA config to initialize RAM
 	input             clk,        // sdram clock
+	input             clkref,     // sync the state machine to clkref rising edge

 	input             port1_req,
 	output reg        port1_ack,
@@ -46,9 +47,9 @@ module sdram (
 	input      [15:0] port1_d,
 	output reg [15:0] port1_q,

-	input      [16:1] cpu1_addr,
+	input      [17:1] cpu1_addr,
 	output reg [15:0] cpu1_q,
-	input      [16:1] cpu2_addr,
+	input      [17:1] cpu2_addr,
 	output reg [15:0] cpu2_q,

 	input             port2_req,
@@ -59,10 +60,16 @@ module sdram (
 	input      [15:0] port2_d,
 	output reg [31:0] port2_q,
 	
-	input      [16:2] sp_addr,
+	input      [19:2] chr1_addr,
+	output reg [31:0] chr1_q,
+	input      [19:2] chr2_addr,
+	output reg [31:0] chr2_q,
+	input      [19:2] sp_addr,
 	output reg [31:0] sp_q
 );

+parameter  MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
+
 localparam RASCAS_DELAY   = 3'd2;   // tRCD=20ns -> 2 cycles@<100MHz
 localparam BURST_LENGTH   = 3'b001; // 000=1, 001=2, 010=4, 011=8
 localparam ACCESS_TYPE    = 1'b0;   // 0=sequential, 1=interleaved
@@ -72,8 +79,8 @@ localparam NO_WRITE_BURST = 1'b1;   // 0= write burst enabled, 1=only single acc

 localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; 

-// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
-localparam RFRSH_CYCLES = 10'd842;
+// 64ms/8192 rows = 7.8us
+localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;

 // ---------------------------------------------------------------------
 // ------------------------ cycle state machine ------------------------
@@ -83,30 +90,37 @@ localparam RFRSH_CYCLES = 10'd842;
 SDRAM state machine for 2 bank interleaved access
 1 word burst, CL2
 cmd issued  registered
- 0 RAS0     cas1 - data0 read burst terminated
- 1          ras0
- 2          data1 returned
- 3 CAS0     data1 returned
+ 0 RAS0     data1 returned
+ 1          ras0 - data1 returned
+ 2
+ 3 CAS0
 4 RAS1     cas0
 5          ras1
 6 CAS1     data0 returned
+ 7          cas1 - data0 read burst terminated
+ 8
 */

-localparam STATE_RAS0      = 3'd0;   // first state in cycle
-localparam STATE_RAS1      = 3'd4;   // Second ACTIVE command after RAS0 + tRRD (15ns)
+localparam STATE_RAS0      = 4'd0;   // first state in cycle
+localparam STATE_RAS1      = 4'd4;   // Second ACTIVE command after RAS0 + tRRD (15ns)
 localparam STATE_CAS0      = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
 localparam STATE_CAS1      = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
-localparam STATE_READ0     = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
-localparam STATE_READ1     = 3'd3;
-localparam STATE_DS1b      = 3'd0;
-localparam STATE_READ1b    = 3'd4;
-localparam STATE_LAST      = 3'd6;
+localparam STATE_READ0     = STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
+localparam STATE_READ1     = 4'd1;
+localparam STATE_DS1b      = 4'd7;
+localparam STATE_READ1b    = 4'd2;
+localparam STATE_LAST      = 4'd8;

-reg [2:0] t;
+reg [3:0] t;

 always @(posedge clk) begin
-	t <= t + 1'd1;
+	reg clkref_d;
+	clkref_d <= clkref;
+
+//	t <= t + 1'd1;
+	if ((~clkref_d && clkref && t == 4'd2) || (t != 4'd2)) t <= t + 1'd1;
 	if (t == STATE_LAST) t <= STATE_RAS0;
+//	if (~clkref_d & clkref) t <= STATE_RAS0;
 end

 // ---------------------------------------------------------------------
@@ -152,8 +166,8 @@ assign SDRAM_nWE  = sd_cmd[0];

 reg [24:1] addr_latch[2];
 reg [24:1] addr_latch_next[2];
-reg [16:1] addr_last[2];
-reg [16:2] addr_last2[2];
+reg [17:1] addr_last[2];
+reg [19:2] addr_last2[4];
 reg [15:0] din_latch[2];
 reg  [1:0] oe_latch;
 reg  [1:0] we_latch;
@@ -162,14 +176,16 @@ reg  [1:0] ds[2];
 reg        port1_state;
 reg        port2_state;

-localparam PORT_NONE  = 2'd0;
-localparam PORT_CPU1  = 2'd1;
-localparam PORT_CPU2  = 2'd2;
-localparam PORT_SP    = 2'd1;
-localparam PORT_REQ   = 2'd3;
+localparam PORT_NONE  = 3'd0;
+localparam PORT_CPU1  = 3'd1;
+localparam PORT_CPU2  = 3'd2;
+localparam PORT_SP    = 3'd1;
+localparam PORT_CHR1  = 3'd2;
+localparam PORT_CHR2  = 3'd3;
+localparam PORT_REQ   = 3'd4;

-reg  [1:0] next_port[2];
-reg  [1:0] port[2];
+reg  [2:0] next_port[2];
+reg  [2:0] port[2];

 reg        refresh;
 reg [10:0] refresh_cnt;
@@ -185,10 +201,10 @@ always @(*) begin
 		addr_latch_next[0] = { 1'b0, port1_a };
 	end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
 		next_port[0] = PORT_CPU1;
-		addr_latch_next[0] = { 8'd0, cpu1_addr };
+		addr_latch_next[0] = { 7'd0, cpu1_addr };
 	end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
 		next_port[0] = PORT_CPU2;
-		addr_latch_next[0] = { 8'd0, cpu2_addr };
+		addr_latch_next[0] = { 7'd0, cpu2_addr };
 	end else begin
 		next_port[0] = PORT_NONE;
 		addr_latch_next[0] = addr_latch[0];
@@ -202,7 +218,13 @@ always @(*) begin
 		addr_latch_next[1] = { 1'b1, port2_a };
 	end else if (sp_addr != addr_last2[PORT_SP]) begin
 		next_port[1] = PORT_SP;
-		addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
+		addr_latch_next[1] = { 1'b1, 4'd0, sp_addr, 1'b0 };
+	end else if (chr1_addr != addr_last2[PORT_CHR1]) begin
+		next_port[1] = PORT_CHR1;
+		addr_latch_next[1] = { 1'b1, 4'd0, chr1_addr, 1'b0 };
+	end else if (chr2_addr != addr_last2[PORT_CHR2]) begin
+		next_port[1] = PORT_CHR2;
+		addr_latch_next[1] = { 1'b1, 4'd0, chr2_addr, 1'b0 };
 	end else begin
 		next_port[1] = PORT_NONE;
 		addr_latch_next[1] = addr_latch[1];
@@ -249,7 +271,7 @@ always @(posedge clk) begin
 				sd_cmd <= CMD_ACTIVE;
 				SDRAM_A <= addr_latch_next[0][22:10];
 				SDRAM_BA <= addr_latch_next[0][24:23];
-				addr_last[next_port[0]] <= addr_latch_next[0][16:1];
+				addr_last[next_port[0]] <= addr_latch_next[0][17:1];
 				if (next_port[0] == PORT_REQ) begin
 					{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
 					ds[0] <= port1_ds;
@@ -273,7 +295,7 @@ always @(posedge clk) begin
 				sd_cmd <= CMD_ACTIVE;
 				SDRAM_A <= addr_latch_next[1][22:10];
 				SDRAM_BA <= addr_latch_next[1][24:23];
-				addr_last2[next_port[1]] <= addr_latch_next[1][16:2];
+				addr_last2[next_port[1]] <= addr_latch_next[1][19:2];
 				if (next_port[1] == PORT_REQ) begin
 					{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
 					ds[1] <= port2_ds;
@@ -327,8 +349,10 @@ always @(posedge clk) begin

 		if(t == STATE_READ1 && oe_latch[1]) begin
 			case(port[1])
-				PORT_REQ:	port2_q[15:0] <= sd_din;
-				PORT_SP :    sp_q[15:0] <= sd_din;
+				PORT_REQ : port2_q[15:0] <= sd_din;
+				PORT_SP  :    sp_q[15:0] <= sd_din;
+				PORT_CHR1:  chr1_q[15:0] <= sd_din;
+				PORT_CHR2:  chr2_q[15:0] <= sd_din;
 				default: ;
 			endcase;
 		end
@@ -337,8 +361,10 @@ always @(posedge clk) begin

 		if(t == STATE_READ1b && oe_latch[1]) begin
 			case(port[1])
-				PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
-				PORT_SP : begin    sp_q[31:16] <= sd_din; end
+				PORT_REQ  : begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
+				PORT_SP   : begin    sp_q[31:16] <= sd_din; end
+				PORT_CHR1 : begin  chr1_q[31:16] <= sd_din; end
+				PORT_CHR2 : begin  chr2_q[31:16] <= sd_din; end
 				default: ;
 			endcase;
 		end
--- a/Hardware/LodeRunner_MiST/rtl/spram.vhd
+++ b/Hardware/LodeRunner_MiST/rtl/spram.vhd
--- a/Show More
+++ b/Show More