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https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-11 23:43:09 +00:00
Added fade-in and fade-out to wave sound.
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@ -42,12 +42,19 @@ reg [23:0] data_size;
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reg [27:0] START_ADDR;
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reg [7:0] W_SAMPL_LSB;
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reg [15:0] W_SAMPL_L;
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reg [15:0] W_SAMPL_R;
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reg signed [15:0] W_SAMPL_L;
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reg signed [15:0] W_SAMPL_R;
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reg [31:0] sum;
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wire[31:0] sum_next = sum + ( stereo ? {sample_rate,1'b0} : sample_rate);
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reg signed [9:0] volume;
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reg signed [8:0] voldelay;
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reg signed [24:0] scaled_l;
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reg signed [24:0] scaled_r;
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reg playing;
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wire stereo = num_channels==16'h2 ? 1'b1 : 1'b0;
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reg channel_toggle;
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@ -145,7 +152,7 @@ always@(posedge I_CLK) begin
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W_DMA_ADDR <= W_DMA_ADDR + 1'd1;
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end
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if(read_done && ce_sample && !I_PAUSE) begin
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if(read_done && ce_sample && playing) begin
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read_done <= 0;
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channel_toggle<=~channel_toggle;
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W_DMA_EN <= ~(W_DMA_ADDR >= END_ADDR);
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@ -159,14 +166,47 @@ always@(posedge I_CLK) begin
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end
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end
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if(I_RST || I_PAUSE || !W_DMA_EN) begin
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if(I_RST || !playing || !W_DMA_EN) begin
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W_SAMPL_L <= 0;
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W_SAMPL_R <= 0;
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end
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end
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assign O_ADDR = W_DMA_ADDR;
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assign O_PCM_L = W_SAMPL_L;
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assign O_PCM_R = W_SAMPL_R;
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always @(posedge I_CLK) begin
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if(ce_sample) begin
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voldelay <= voldelay + 1;
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end
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end
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always @(posedge I_CLK) begin
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if(&voldelay && ce_sample) begin
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if(I_PAUSE) begin
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if(volume[8:0]!=9'h0) begin
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volume<={volume[9:2],2'b00}-9'h4;
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end else begin
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playing <=1'b0;
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end
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end else begin
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playing <=1'b1;
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if(!volume[8]) begin
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volume<=volume+7'b1;
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end
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end
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end
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if(I_RST) begin
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volume <= 9'b0;
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end
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scaled_l <= W_SAMPL_L * volume;
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scaled_r <= W_SAMPL_R * volume;
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end
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assign O_PCM_L = scaled_l[24:9];
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assign O_PCM_R = scaled_r[24:9];
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endmodule
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