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add 65c02 CPU Core

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Marcel
2022-06-20 17:28:35 +02:00
parent 8ab2f87611
commit 6fe7618dcf
8 changed files with 7451 additions and 0 deletions
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common/CPU/65C02/core.vhd Normal file
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-- VHDL Entity r65c02_tc.core.symbol
--
-- Created:
-- by - jens.Domain Users (ENTW-7HPZ200)
-- at - 11:09:21 08/01/13
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity core is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
ce : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
-- Declarations
end core ;
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.8 2013/08/01 11:00:00 jens
-- - Change Block names to lower case
-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong. Adding a priority encoder.
--
-- Revision 1.7 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
--
-- Revision 1.6 2009/01/04 10:20:47 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 09:23:10 eda
-- - Delete unused nets and blocks (same as R6502_TC)
-- - Rename blocks
--
-- Revision 1.4 2009/01/03 16:53:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
--
-- VHDL Architecture r65c02_tc.core.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 12:00:34 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
library r65c02_tc;
architecture struct of core is
-- Architecture declarations
-- Internal signal declarations
signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
signal adr_o_i : std_logic_vector(15 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal adr_sp_o_i : std_logic_vector(15 downto 0);
signal ch_a_o_i : std_logic_vector(7 downto 0);
signal ch_b_o_i : std_logic_vector(7 downto 0);
signal d_alu_n_o_i : std_logic;
signal d_alu_o_i : std_logic_vector(7 downto 0);
signal d_alu_or_o_i : std_logic;
signal d_alu_prio_o_i : std_logic_vector(7 downto 0);
signal d_regs_in_o_i : std_logic_vector(7 downto 0);
signal d_regs_out_o_i : std_logic_vector(7 downto 0);
signal ld_o_i : std_logic_vector(1 downto 0);
signal ld_pc_o_i : std_logic;
signal ld_sp_o_i : std_logic;
signal load_regs_o_i : std_logic;
signal nmi_o_i : std_logic;
signal offset_o_i : std_logic_vector(15 downto 0);
signal q_a_o_i : std_logic_vector(7 downto 0);
signal q_x_o_i : std_logic_vector(7 downto 0);
signal q_y_o_i : std_logic_vector(7 downto 0);
signal reg_0flag_o_i : std_logic;
signal reg_1flag_o_i : std_logic;
signal reg_7flag_o_i : std_logic;
signal rst_nmi_o_i : std_logic;
signal sel_pc_in_o_i : std_logic;
signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
signal sel_rb_in_o_i : std_logic_vector(1 downto 0);
signal sel_rb_out_o_i : std_logic_vector(1 downto 0);
signal sel_reg_o_i : std_logic_vector(1 downto 0);
signal sel_sp_as_o_i : std_logic;
signal sel_sp_in_o_i : std_logic;
signal var_shift_data_o_i : std_logic_vector(7 downto 0);
-- Component Declarations
component fsm_execution_unit
port (
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_alu_prio_i : in std_logic_vector (7 downto 0);
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic ;
nmi_i : in std_logic ;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic ;
reg_0flag_i : in std_logic ;
reg_1flag_i : in std_logic ;
reg_7flag_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
ce : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic ;
ld_sp_o : out std_logic ;
load_regs_o : out std_logic ;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic ;
rst_nmi_o : out std_logic ;
sel_pc_in_o : out std_logic ;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic ;
sel_sp_in_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
);
end component;
component fsm_intnmi
port (
clk_clk_i : in std_logic ;
nmi_n_i : in std_logic ;
rst_nmi_i : in std_logic ;
rst_rst_n_i : in std_logic ;
ce : in std_logic ;
nmi_o : out std_logic
);
end component;
component reg_pc
port (
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic ;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_n_i : in std_logic ;
sel_pc_in_i : in std_logic ;
sel_pc_val_i : in std_logic_vector (1 downto 0);
ce : in std_logic;
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0)
);
end component;
component reg_sp
port (
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic ;
ld_low_i : in std_logic ;
ld_sp_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_sp_as_i : in std_logic ;
sel_sp_in_i : in std_logic ;
ce : in std_logic ;
adr_sp_o : out std_logic_vector (15 downto 0)
);
end component;
component regbank_axy
port (
clk_clk_i : in std_logic ;
d_regs_in_i : in std_logic_vector (7 downto 0);
load_regs_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_rb_in_i : in std_logic_vector (1 downto 0);
sel_rb_out_i : in std_logic_vector (1 downto 0);
sel_reg_i : in std_logic_vector (1 downto 0);
ce : in std_logic ;
d_regs_out_o : out std_logic_vector (7 downto 0);
q_a_o : out std_logic_vector (7 downto 0);
q_x_o : out std_logic_vector (7 downto 0);
q_y_o : out std_logic_vector (7 downto 0)
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : fsm_execution_unit use entity r65c02_tc.fsm_execution_unit;
for all : fsm_intnmi use entity r65c02_tc.fsm_intnmi;
for all : reg_pc use entity r65c02_tc.reg_pc;
for all : reg_sp use entity r65c02_tc.reg_sp;
for all : regbank_axy use entity r65c02_tc.regbank_axy;
-- pragma synthesis_on
begin
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
-- eb1 1
var_shift_data_o_i <= x"01";
-- ModuleWare code(v1.12) for instance 'U_11' of 'add'
u_11combo_proc: process (ch_a_o_i, ch_b_o_i)
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
variable temp_carry : std_logic;
begin
temp_din0 := '0' & ch_a_o_i;
temp_din1 := '0' & ch_b_o_i;
temp_carry := '0';
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
d_alu_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8);
reg_0flag_o_i <= temp_sum(8) ;
end process u_11combo_proc;
-- ModuleWare code(v1.12) for instance 'U_8' of 'inv'
reg_1flag_o_i <= not(d_alu_or_o_i);
-- ModuleWare code(v1.12) for instance 'U_9' of 'inv'
reg_7flag_o_i <= not(d_alu_n_o_i);
-- ModuleWare code(v1.12) for instance 'U_10' of 'inv'
d_alu_n_o_i <= not(d_alu_o_i(7));
-- ModuleWare code(v1.12) for instance 'U_5' of 'lshift'
u_5combo_proc : process (var_shift_data_o_i, ch_a_o_i)
variable temp_shift : std_logic_vector (3 downto 0);
variable temp_dout : std_logic_vector (7 downto 0);
variable temp_din : std_logic_vector (7 downto 0);
begin
temp_din := (others=> 'X');
temp_shift := ch_a_o_i(3 downto 0);
temp_din := var_shift_data_o_i;
for i in 0 to 3 loop
if (i < 3) then
if (temp_shift(i) = '1') then
temp_dout := (others => '0');
temp_dout(7 downto 2**i) := temp_din(7 - 2**i downto 0);
elsif (temp_shift(i) = '0') then
temp_dout := temp_din;
else
temp_dout := (others => 'X');
end if;
else
if (temp_shift(i) = '1') then
temp_dout := (others => '0');
elsif (temp_shift(i) = '0') then
temp_dout := temp_din;
else
temp_dout := (others => 'X');
end if;
end if;
temp_din := temp_dout;
end loop;
d_alu_prio_o_i <= temp_dout;
end process u_5combo_proc;
-- ModuleWare code(v1.12) for instance 'U_7' of 'por'
d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7);
-- Instance port mappings.
U_4 : fsm_execution_unit
port map (
adr_nxt_pc_i => adr_nxt_pc_o_i,
adr_pc_i => adr_pc_o_i,
adr_sp_i => adr_sp_o_i,
clk_clk_i => clk_clk_i,
d_alu_i => d_alu_o_i,
d_alu_prio_i => d_alu_prio_o_i,
d_i => d_i,
d_regs_out_i => d_regs_out_o_i,
irq_n_i => irq_n_i,
nmi_i => nmi_o_i,
q_a_i => q_a_o_i,
q_x_i => q_x_o_i,
q_y_i => q_y_o_i,
rdy_i => rdy_i,
reg_0flag_i => reg_0flag_o_i,
reg_1flag_i => reg_1flag_o_i,
reg_7flag_i => reg_7flag_o_i,
rst_rst_n_i => rst_rst_n_i,
so_n_i => so_n_i,
ce => ce,
a_o => a_o,
adr_o => adr_o_i,
ch_a_o => ch_a_o_i,
ch_b_o => ch_b_o_i,
d_o => d_o,
d_regs_in_o => d_regs_in_o_i,
ld_o => ld_o_i,
ld_pc_o => ld_pc_o_i,
ld_sp_o => ld_sp_o_i,
load_regs_o => load_regs_o_i,
offset_o => offset_o_i,
rd_o => rd_o,
rst_nmi_o => rst_nmi_o_i,
sel_pc_in_o => sel_pc_in_o_i,
sel_pc_val_o => sel_pc_val_o_i,
sel_rb_in_o => sel_rb_in_o_i,
sel_rb_out_o => sel_rb_out_o_i,
sel_reg_o => sel_reg_o_i,
sel_sp_as_o => sel_sp_as_o_i,
sel_sp_in_o => sel_sp_in_o_i,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
);
U_3 : fsm_intnmi
port map (
clk_clk_i => clk_clk_i,
nmi_n_i => nmi_n_i,
ce => ce,
rst_nmi_i => rst_nmi_o_i,
rst_rst_n_i => rst_rst_n_i,
nmi_o => nmi_o_i
);
U_0 : reg_pc
port map (
adr_i => adr_o_i,
clk_clk_i => clk_clk_i,
ce => ce,
ld_i => ld_o_i,
ld_pc_i => ld_pc_o_i,
offset_i => offset_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_pc_in_i => sel_pc_in_o_i,
sel_pc_val_i => sel_pc_val_o_i,
adr_nxt_pc_o => adr_nxt_pc_o_i,
adr_pc_o => adr_pc_o_i
);
U_1 : reg_sp
port map (
adr_low_i => adr_o_i(7 DOWNTO 0),
clk_clk_i => clk_clk_i,
ce => ce,
ld_low_i => ld_o_i(0),
ld_sp_i => ld_sp_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_sp_as_i => sel_sp_as_o_i,
sel_sp_in_i => sel_sp_in_o_i,
adr_sp_o => adr_sp_o_i
);
U_2 : regbank_axy
port map (
clk_clk_i => clk_clk_i,
ce => ce,
d_regs_in_i => d_regs_in_o_i,
load_regs_i => load_regs_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_rb_in_i => sel_rb_in_o_i,
sel_rb_out_i => sel_rb_out_o_i,
sel_reg_i => sel_reg_o_i,
d_regs_out_o => d_regs_out_o_i,
q_a_o => q_a_o_i,
q_x_o => q_x_o_i,
q_y_o => q_y_o_i
);
end struct;

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-- VHDL Entity r65c02_tc.fsm_intnmi.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 12:35:56 10.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity fsm_intnmi is
port(
clk_clk_i : in std_logic;
nmi_n_i : in std_logic;
rst_nmi_i : in std_logic;
rst_rst_n_i : in std_logic;
ce : in std_logic;
nmi_o : out std_logic
);
-- Declarations
end fsm_intnmi ;
-- (C) 2008 - 2013 Jens Gutschmidt
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.8 2018/09/01 18:07:00 jens
-- - NMI = '0' need at least 1 cycles for correct
-- operation now (2 cycles in the past)
--
-- Revision 1.7 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
--
-- Revision 1.6 2009/01/04 10:20:47 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 09:23:10 eda
-- - Delete unused nets and blocks (same as R6502_TC)
-- - Rename blocks
--
-- Revision 1.4 2009/01/03 16:53:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
--
-- VHDL Architecture r65c02_tc.fsm_intnmi.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 12:35:56 10.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2013 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of fsm_intnmi is
type state_type is (
idle,
idle1,
IMP
);
-- State vector declaration
attribute state_vector : string;
attribute state_vector of fsm : architecture is "current_state";
-- Declare current and next state signals
signal current_state : state_type;
signal next_state : state_type;
-- Declare any pre-registered internal signals
signal nmi_o_cld : std_logic ;
begin
-----------------------------------------------------------------
clocked_proc : process (
clk_clk_i,
ce,
rst_rst_n_i
)
-----------------------------------------------------------------
begin
if (rst_rst_n_i = '0') then
current_state <= idle;
-- Default Reset Values
nmi_o_cld <= '0';
elsif (clk_clk_i'event and clk_clk_i = '1' and ce = '1') then
current_state <= next_state;
-- Default Assignment To Internals
nmi_o_cld <= '0';
-- Combined Actions
case current_state is
when idle1 =>
if (nmi_n_i = '0') then
nmi_o_cld <= '1';
end if;
when IMP =>
nmi_o_cld <= '1';
if (rst_nmi_i = '1') then
nmi_o_cld <= '0';
end if;
when others =>
null;
end case;
end if;
end process clocked_proc;
-----------------------------------------------------------------
nextstate_proc : process (
current_state,
nmi_n_i,
rst_nmi_i
)
-----------------------------------------------------------------
begin
case current_state is
when idle =>
if (nmi_n_i = '1') then
next_state <= idle1;
else
next_state <= idle;
end if;
when idle1 =>
if (nmi_n_i = '0') then
next_state <= IMP;
else
next_state <= idle1;
end if;
when IMP =>
if (rst_nmi_i = '1') then
next_state <= idle;
else
next_state <= IMP;
end if;
when others =>
next_state <= idle;
end case;
end process nextstate_proc;
-- Concurrent Statements
-- Clocked output assignments
nmi_o <= nmi_o_cld;
end fsm;

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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) core.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) fsm_execution_unit.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) fsm_intnmi.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) r65c02_tc.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) reg_pc.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) reg_sp.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) regbank_axy.vhd]

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common/CPU/65C02/r65c02_tc.vhd Normal file
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-- VHDL Entity r65c02_tc.r65c02_tc.symbol
--
-- Created:
-- by - remoteghost.UNKNOWN (ENTW-7HPZ200)
-- at - 10:24:26 07/21/13
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity r65c02_tc is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
ce : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
-- Declarations
end r65c02_tc ;
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.52 2018/09/10 12:14:00 jens
-- - RESET generates SYNC now, 1 dead cycle delayed
-- Revision 1.52 RC 2018/09/09 03:00:00 jens
-- - ADC / SBC flags and A like R65C02 now
-- Revision 1.52 BETA 2018/09/05 19:35:00 jens
-- - BBRx/BBSx internal cycles like real 65C02 now
-- - Bug Fix ADC and SBC in decimal mode (all op codes -
-- 1 cycle is missing
-- - Bug Fix ADC and SBC in decimal mode (all op codes -
-- "Overflow" flag was computed wrong)
-- Revision 1.52 BETA 2018/09/02 18:49:00 jens
-- - Interrupt NMI and IRQ processing via FETCH stage now
-- Revision 1.52 BETA 2018/08/30 15:39:00 jens
-- - Interrupt priority order is now: BRQ - NMI - IRQ
-- - Performance improvements on-going (Mealy -> Moore)
-- Revision 1.52 BETA 2018/08/23 20:27:00 jens
-- - Bug Fixes All Branch Instructions
-- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA)
-- 3 cycles now if branch forward occur and the branch
-- instruction lies on a xxFEh location.
-- (BBR, BBS) 6 cycles now if branch forward occur and the
-- branch instruction lies on a xxFDh location.
-- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now
-- - Bug Fix Now all cycles are delayable (WR and internal)
--
-- Revision 1.51 RC 2014/04/19 14:44:00 jens
-- (never submitted to opencores)
-- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH.
-- When the ABS address data bytes cross the page
-- boundary (e.g. $02FE JMP hhll reads hh from
-- $02FF and ll from $0200, instead $02FF and $0300)
--
-- Revision 1.5 RC 2013/08/01 11:00:00 jens
-- - Change Block name to lower case
-- - Bug Fix CMP (IND) - wrongly decoded as function AND
-- - Bug Fix BRK should clear decimal flag in P Reg
-- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address
-- - Bug Fix Unknown Ops - Used always 1b2c NOP ($EA) - new NOPs created
-- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong)
-- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed
-- - Bug Fix RTI - should increment stack pointer
-- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates.
-- - Bug Fix ADC and SBC (all sub codes - "Overflow" flag was computed wrong)
-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong
--
-- Revision 1.4 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
-- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH)
--
-- Revision 1.3 2009/01/04 10:20:50 eda
-- Changes for cosmetic issues only
--
-- Revision 1.2 2009/01/04 09:23:12 eda
-- - Delete unused nets and blocks (same as R6502_TC)
-- - Rename blocks
-- - Re-arrage FSM symbols in block FSM_Execution_Unit
--
-- Revision 1.1 2009/01/03 16:36:48 eda
-- -- no description --
--
--
--
-- VHDL Architecture r65c02_tc.r65c02_tc.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 12:21:16 10.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
library r65c02_tc;
architecture struct of r65c02_tc is
-- Architecture declarations
-- Internal signal declarations
-- Component Declarations
component core
port (
clk_clk_i : in std_logic ;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic ;
nmi_n_i : in std_logic ;
rdy_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
ce : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : core use entity r65c02_tc.core;
-- pragma synthesis_on
begin
-- Instance port mappings.
U_0 : core
port map (
clk_clk_i => clk_clk_i,
d_i => d_i,
irq_n_i => irq_n_i,
nmi_n_i => nmi_n_i,
rdy_i => rdy_i,
rst_rst_n_i => rst_rst_n_i,
so_n_i => so_n_i,
ce => ce,
a_o => a_o,
d_o => d_o,
rd_o => rd_o,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
);
end struct;

238
common/CPU/65C02/reg_pc.vhd Normal file
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@@ -0,0 +1,238 @@
-- VHDL Entity r65c02_tc.reg_pc.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 11:59:59 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity reg_pc is
port(
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_n_i : in std_logic;
sel_pc_in_i : in std_logic;
sel_pc_val_i : in std_logic_vector (1 downto 0);
ce : in std_logic;
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0)
);
-- Declarations
end reg_pc ;
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.7 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
--
-- Revision 1.6 2009/01/04 10:20:47 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 09:23:10 eda
-- - Delete unused nets and blocks (same as R6502_TC)
-- - Rename blocks
--
-- Revision 1.4 2009/01/03 16:53:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
--
-- VHDL Architecture r65c02_tc.reg_pc.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 11:59:59 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture struct of reg_pc is
-- Architecture declarations
-- Internal signal declarations
signal adr_pc_high_o_i : std_logic_vector(7 downto 0);
signal adr_pc_low_o_i : std_logic_vector(7 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal ci_o_i : std_logic;
signal cout_pc_o_i : std_logic;
signal load3_o_i : std_logic;
signal load_o_i : std_logic;
signal offset_high_o_i : std_logic_vector(7 downto 0);
signal offset_low_o_i : std_logic_vector(7 downto 0);
signal val_o_i : std_logic_vector(7 downto 0);
signal val_one : std_logic_vector(7 downto 0);
signal val_zero : std_logic_vector(7 downto 0);
-- Implicit buffer signal declarations
signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0);
signal adr_pc_o_internal : std_logic_vector (15 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff'
signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_3' of 'split'
signal mw_U_3temp_din : std_logic_vector(15 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'split'
signal mw_U_5temp_din : std_logic_vector(15 downto 0);
begin
-- ModuleWare code(v1.12) for instance 'U_2' of 'add'
u_2combo_proc: process (adr_pc_low_o_i, val_o_i)
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
variable temp_carry : std_logic;
begin
temp_din0 := '0' & adr_pc_low_o_i;
temp_din1 := '0' & val_o_i;
temp_carry := '0';
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 downto 0),8);
cout_pc_o_i <= temp_sum(8) ;
end process u_2combo_proc;
-- ModuleWare code(v1.12) for instance 'U_11' of 'add'
u_11combo_proc: process (adr_pc_high_o_i, offset_high_o_i, ci_o_i)
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
variable temp_carry : std_logic;
begin
temp_din0 := '0' & adr_pc_high_o_i;
temp_din1 := '0' & offset_high_o_i;
temp_carry := ci_o_i;
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 downto 0),8);
end process u_11combo_proc;
-- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, ce, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1' and ce = '1') then
if (load_o_i = '1') then
mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
end if;
end if;
end process u_0seq_proc;
-- ModuleWare code(v1.12) for instance 'U_4' of 'adff'
adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
u_4seq_proc: process (clk_clk_i, ce, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_4reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1' and ce = '1') then
if (load3_o_i = '1') then
mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
end if;
end if;
end process u_4seq_proc;
-- ModuleWare code(v1.12) for instance 'U_6' of 'and'
load_o_i <= ld_pc_i and ld_i(0);
-- ModuleWare code(v1.12) for instance 'U_7' of 'and'
load3_o_i <= ld_pc_i and ld_i(1);
-- ModuleWare code(v1.12) for instance 'U_10' of 'and'
ci_o_i <= cout_pc_o_i and ld_pc_i;
-- ModuleWare code(v1.12) for instance 'U_1' of 'constval'
val_zero <= "00000000";
-- ModuleWare code(v1.12) for instance 'U_9' of 'constval'
val_one <= "00000001";
-- ModuleWare code(v1.12) for instance 'U_8' of 'mux'
u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i)
begin
case sel_pc_in_i is
when '0' => adr_pc_o_i <= adr_pc_o_internal;
when '1' => adr_pc_o_i <= adr_i;
when others => adr_pc_o_i <= (others => 'X');
end case;
end process u_8combo_proc;
-- ModuleWare code(v1.12) for instance 'U_13' of 'mux'
u_13combo_proc: process(val_one, val_zero, offset_low_o_i,
sel_pc_val_i)
begin
case sel_pc_val_i is
when "00" => val_o_i <= val_one;
when "01" => val_o_i <= val_zero;
when "10" => val_o_i <= offset_low_o_i;
when "11" => val_o_i <= val_zero;
when others => val_o_i <= (others => 'X');
end case;
end process u_13combo_proc;
-- ModuleWare code(v1.12) for instance 'U_3' of 'split'
mw_U_3temp_din <= adr_pc_o_i;
u_3combo_proc: process (mw_U_3temp_din)
variable temp_din: std_logic_vector(15 downto 0);
begin
temp_din := mw_U_3temp_din(15 downto 0);
adr_pc_low_o_i <= temp_din(7 downto 0);
adr_pc_high_o_i <= temp_din(15 downto 8);
end process u_3combo_proc;
-- ModuleWare code(v1.12) for instance 'U_5' of 'split'
mw_U_5temp_din <= offset_i;
u_5combo_proc: process (mw_U_5temp_din)
variable temp_din: std_logic_vector(15 downto 0);
begin
temp_din := mw_U_5temp_din(15 downto 0);
offset_low_o_i <= temp_din(7 downto 0);
offset_high_o_i <= temp_din(15 downto 8);
end process u_5combo_proc;
-- Instance port mappings.
-- Implicit buffered output assignments
adr_nxt_pc_o <= adr_nxt_pc_o_internal;
adr_pc_o <= adr_pc_o_internal;
end struct;

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common/CPU/65C02/reg_sp.vhd Normal file
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-- VHDL Entity r65c02_tc.reg_sp.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 12:04:08 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity reg_sp is
port(
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic;
ld_low_i : in std_logic;
ld_sp_i : in std_logic;
rst_rst_n_i : in std_logic;
sel_sp_as_i : in std_logic;
sel_sp_in_i : in std_logic;
ce : in std_logic;
adr_sp_o : out std_logic_vector (15 downto 0)
);
-- Declarations
end reg_sp ;
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.7 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
--
-- Revision 1.6 2009/01/04 10:20:47 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 09:23:10 eda
-- - Delete unused nets and blocks (same as R6502_TC)
-- - Rename blocks
--
-- Revision 1.4 2009/01/03 16:53:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
--
-- VHDL Architecture r65c02_tc.reg_sp.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 12:04:08 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture struct of reg_sp is
-- Architecture declarations
-- Internal signal declarations
signal adr_sp_low_o_i : std_logic_vector(7 downto 0);
signal load_o_i : std_logic;
signal result_low1_o_i : std_logic_vector(7 downto 0);
signal result_low_o_i : std_logic_vector(7 downto 0);
signal sp_as_n_o_i : std_logic;
signal val_one : std_logic_vector(7 downto 0);
-- Implicit buffer signal declarations
signal adr_sp_o_internal : std_logic_vector (15 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
begin
-- ModuleWare code(v1.12) for instance 'U_11' of 'addsub'
u_11combo_proc: process (adr_sp_low_o_i, val_one, sp_as_n_o_i)
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
variable temp_carry : std_logic;
begin
temp_din0 := '0' & adr_sp_low_o_i;
temp_din1 := '0' & val_one;
temp_carry := '0';
if (sp_as_n_o_i = '1') then
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
else
temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
end if;
result_low_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8);
end process u_11combo_proc;
-- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, ce, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1' and ce = '1') then
if (load_o_i = '1') then
mw_U_0reg_cval <= result_low1_o_i;
end if;
end if;
end process u_0seq_proc;
-- ModuleWare code(v1.12) for instance 'U_6' of 'and'
load_o_i <= ld_sp_i and ld_low_i;
-- ModuleWare code(v1.12) for instance 'U_3' of 'buff'
adr_sp_o_internal(15 DOWNTO 8) <= val_one;
-- ModuleWare code(v1.12) for instance 'U_4' of 'constval'
val_one <= "00000001";
-- ModuleWare code(v1.12) for instance 'U_2' of 'inv'
sp_as_n_o_i <= not(sel_sp_as_i);
-- ModuleWare code(v1.12) for instance 'U_8' of 'mux'
u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i)
begin
case sel_sp_in_i is
when '0' => result_low1_o_i <= result_low_o_i;
when '1' => result_low1_o_i <= adr_low_i;
when others => result_low1_o_i <= (others => 'X');
end case;
end process u_8combo_proc;
-- ModuleWare code(v1.12) for instance 'U_10' of 'tap'
adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0);
-- Instance port mappings.
-- Implicit buffered output assignments
adr_sp_o <= adr_sp_o_internal;
end struct;

208
common/CPU/65C02/regbank_axy.vhd Normal file
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@@ -0,0 +1,208 @@
-- VHDL Entity r65c02_tc.regbank_axy.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 20:45:48 27.08.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity regbank_axy is
port(
clk_clk_i : in std_logic;
d_regs_in_i : in std_logic_vector (7 downto 0);
load_regs_i : in std_logic;
rst_rst_n_i : in std_logic;
sel_rb_in_i : in std_logic_vector (1 downto 0);
sel_rb_out_i : in std_logic_vector (1 downto 0);
sel_reg_i : in std_logic_vector (1 downto 0);
ce : in std_logic;
d_regs_out_o : out std_logic_vector (7 downto 0);
q_a_o : out std_logic_vector (7 downto 0);
q_x_o : out std_logic_vector (7 downto 0);
q_y_o : out std_logic_vector (7 downto 0)
);
-- Declarations
end regbank_axy ;
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.7 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
--
-- Revision 1.6 2009/01/04 10:20:47 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 09:23:10 eda
-- - Delete unused nets and blocks (same as R6502_TC)
-- - Rename blocks
--
-- Revision 1.4 2009/01/03 16:53:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
--
-- VHDL Architecture r65c02_tc.regbank_axy.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 12:04:48 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture struct of regbank_axy is
-- Architecture declarations
-- Internal signal declarations
signal ld : std_logic_vector(2 downto 0);
signal load1_o_i : std_logic;
signal load2_o_i : std_logic;
signal load_o_i : std_logic;
signal q_mux_o_i : std_logic_vector(7 downto 0);
signal val_zero : std_logic_vector(7 downto 0);
-- Implicit buffer signal declarations
signal q_a_o_internal : std_logic_vector (7 downto 0);
signal q_x_o_internal : std_logic_vector (7 downto 0);
signal q_y_o_internal : std_logic_vector (7 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff'
signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'adff'
signal mw_U_5reg_cval : std_logic_vector(7 downto 0);
begin
-- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
q_a_o_internal <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, ce, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1' and ce = '1') then
if (load_o_i = '1') then
mw_U_0reg_cval <= q_mux_o_i;
end if;
end if;
end process u_0seq_proc;
-- ModuleWare code(v1.12) for instance 'U_4' of 'adff'
q_x_o_internal <= mw_U_4reg_cval;
u_4seq_proc: process (clk_clk_i, ce, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_4reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1' and ce = '1') then
if (load1_o_i = '1') then
mw_U_4reg_cval <= q_mux_o_i;
end if;
end if;
end process u_4seq_proc;
-- ModuleWare code(v1.12) for instance 'U_5' of 'adff'
q_y_o_internal <= mw_U_5reg_cval;
u_5seq_proc: process (clk_clk_i, ce, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_5reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1' and ce = '1') then
if (load2_o_i = '1') then
mw_U_5reg_cval <= q_mux_o_i;
end if;
end if;
end process u_5seq_proc;
-- ModuleWare code(v1.12) for instance 'U_6' of 'and'
load_o_i <= load_regs_i and ld(0);
-- ModuleWare code(v1.12) for instance 'U_7' of 'and'
load1_o_i <= load_regs_i and ld(1);
-- ModuleWare code(v1.12) for instance 'U_8' of 'and'
load2_o_i <= load_regs_i and ld(2);
-- ModuleWare code(v1.12) for instance 'U_11' of 'constval'
val_zero <= "00000000";
-- ModuleWare code(v1.12) for instance 'U_1' of 'decoder1'
u_1combo_proc: process (sel_reg_i)
begin
ld <= (others => '0');
case sel_reg_i is
when "00" => ld(0) <= '1';
when "01" => ld(1) <= '1';
when "10" => ld(2) <= '1';
when others => ld <= (others => '0');
end case;
end process u_1combo_proc;
-- ModuleWare code(v1.12) for instance 'U_2' of 'mux'
u_2combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal,
val_zero, sel_rb_out_i)
begin
case sel_rb_out_i is
when "00" => d_regs_out_o <= q_a_o_internal;
when "01" => d_regs_out_o <= q_x_o_internal;
when "10" => d_regs_out_o <= q_y_o_internal;
when "11" => d_regs_out_o <= val_zero;
when others => d_regs_out_o <= (others => 'X');
end case;
end process u_2combo_proc;
-- ModuleWare code(v1.12) for instance 'U_3' of 'mux'
u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal,
d_regs_in_i, sel_rb_in_i)
begin
case sel_rb_in_i is
when "00" => q_mux_o_i <= q_a_o_internal;
when "01" => q_mux_o_i <= q_y_o_internal;
when "10" => q_mux_o_i <= q_x_o_internal;
when "11" => q_mux_o_i <= d_regs_in_i;
when others => q_mux_o_i <= (others => 'X');
end case;
end process u_3combo_proc;
-- Instance port mappings.
-- Implicit buffered output assignments
q_a_o <= q_a_o_internal;
q_x_o <= q_x_o_internal;
q_y_o <= q_y_o_internal;
end struct;