github.com/Gehstock.Mist_FPGA
1
0
Fork 0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-05-08 00:46:41 +00:00
Code Issues Releases Wiki Activity

Delete Mister Files

Browse Source
This commit is contained in:
Marcel
2023-07-08 15:50:52 +02:00
parent bcad377841
commit 74a2bf0cc7
589 changed files with 0 additions and 188811 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/.gitignore vendored
View File

@@ -1,40 +0,0 @@
db
greybox_tmp
incremental_db
output_files
simulation
hc_output
scaler
hps_isw_handoff
vip
*_sim
.qsys_edit
PLLJ_PLLSPE_INFO.txt
*.bak
*.orig
*.rej
*.qdf
*.rpt
*.smsg
*.summary
*.done
*.jdi
*.pin
*.sof
*.qws
*.ppf
*.ddb
build_id.v
c5_pin_model_dump.txt
*.sopcinfo
*.csv
*.f
*.cmp
*.sip
*.spd
*.bsf
*~
*.xml
*_netlist
*.cdf
**/.DS_Store

36
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/clean.bat
View File

@@ -1,36 +0,0 @@
@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
for /d %%i in (sys\*_sim) do rmdir /s /q "%%i"
for /d %%i in (rtl\*_sim) do rmdir /s /q "%%i"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del *.cdf
del *.rpt
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

31
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/demonwld.qpf
View File

@@ -1,31 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 16:22:54 May 10, 2023
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "20.1"
DATE = "16:22:54 May 10, 2023"
# Revisions
PROJECT_REVISION = "demonwld"

108
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/demonwld.qsf
View File

@@ -1,108 +0,0 @@
# --------------------------------------------------------------------------
#
# MiSTer project
#
# WARNING WARNING WARNING:
# Do not add files to project in Quartus IDE! It will mess this file!
# Add the files manually to files.qip file.
#
# --------------------------------------------------------------------------
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE OFF
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE BALANCED
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS OFF
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
set_global_assignment -name SEED 1
set_global_assignment -name VERILOG_MACRO "MISTER_FB=1"
#enable it only if 8bit indexed mode is used in core
#set_global_assignment -name VERILOG_MACRO "MISTER_FB_PALETTE=1"
#do not enable DEBUG_NOHDMI in release!
#set_global_assignment -name VERILOG_MACRO "MISTER_DEBUG_NOHDMI=1"
# disable bilinear filtering when downscaling
#set_global_assignment -name VERILOG_MACRO "MISTER_DOWNSCALE_NN=1"
# disable adaptive scanline filtering
#set_global_assignment -name VERILOG_MACRO "MISTER_DISABLE_ADAPTIVE=1"
# Enable YC / Composite output
set_global_assignment -name VERILOG_MACRO "MISTER_ENABLE_YC=1"
#enable dimming during pause
set_global_assignment -name VERILOG_MACRO "PAUSE_OUTPUT_DIM=1"
source sys/sys.tcl
source sys/sys_analog.tcl
source files.qip
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name SYNTHESIS_EFFORT FAST
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL NORMAL
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
set_global_assignment -name SDC_FILE demonwld.sdc
set_global_assignment -name SYSTEMVERILOG_FILE demonwld.sv
set_global_assignment -name QIP_FILE rtl/t80/T80.qip
set_global_assignment -name QIP_FILE rtl/fx68k/fx68k.qip
set_global_assignment -name QIP_FILE rtl/jtopl/jt26.qip
set_global_assignment -name QIP_FILE rtl/TMS320C1X/TMS320C1X.qip
set_global_assignment -name VERILOG_FILE rtl/video_timing.v
set_global_assignment -name QIP_FILE sys/pll_q17.qip
set_global_assignment -name QIP_FILE sys/pll_hdmi.qip
set_global_assignment -name QIP_FILE sys/pll_audio.qip
set_global_assignment -name QIP_FILE sys/pll_cfg.qip
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name VERILOG_FILE rtl/pause.v
set_global_assignment -name VERILOG_FILE rtl/mem/rom_controller.v
set_global_assignment -name VERILOG_FILE rtl/mem/tile_cache.v
set_global_assignment -name VERILOG_FILE rtl/mem/cache.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/chip_select.v
set_global_assignment -name VHDL_FILE rtl/mem/math.vhd
set_global_assignment -name VHDL_FILE rtl/mem/segment.vhd
set_global_assignment -name VHDL_FILE rtl/mem/download_buffer.vhd
set_global_assignment -name VHDL_FILE rtl/mem/sdram.vhd
set_global_assignment -name VHDL_FILE rtl/mem/dual_port_ram.vhd
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

234
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/demonwld.sdc
View File

@@ -1,234 +0,0 @@
## Generated SDC file "demonwld.sdc"
## Copyright (C) 2020 Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions
## and other software and tools, and any partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Intel Program License
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel FPGA IP License Agreement, or other applicable license
## agreement, including, without limitation, that your use is for
## the sole purpose of programming logic devices manufactured by
## Intel and sold by Intel or its authorized distributors. Please
## refer to the applicable agreement for further details, at
## https://fpgasoftware.intel.com/eula.
## VENDOR "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
## DATE "Mon Jun 05 18:32:43 2023"
##
## DEVICE "5CSEBA6U23I7"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}]
create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}]
create_clock -name {FPGA_CLK3_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK3_50}]
create_clock -name {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk} -period 10.000 -waveform { 0.000 5.000 } [get_pins -compatibility_mode {*|h2f_user0_clk}]
create_clock -name {spi_sck} -period 10.000 -waveform { 0.000 5.000 } [get_pins -compatibility_mode {spi|sclk_out}]
create_clock -name {hdmi_sck} -period 100.000 -waveform { 0.000 50.000 } [get_pins -compatibility_mode {hdmi_i2c|out_clk}]
#**************************************************************
# Create Generated Clock
#**************************************************************
create_generated_clock -name {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk} -source [get_pins {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 3 -master_clock {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]} [get_pins {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}]
create_generated_clock -name {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]} -source [get_pins {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin}] -duty_cycle 50/1 -multiply_by 4563 -divide_by 512 -master_clock {FPGA_CLK1_50} [get_pins {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]}]
create_generated_clock -name {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 4279 -divide_by 512 -master_clock {FPGA_CLK3_50} [get_pins {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]
create_generated_clock -name {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 17 -master_clock {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|pll|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {emu|pll|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 14 -divide_by 2 -master_clock {FPGA_CLK2_50} [get_pins {emu|pll|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]
create_generated_clock -name {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 5 -master_clock {emu|pll|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 5 -phase -1285560/14285 -master_clock {emu|pll|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
set_clock_uncertainty -rise_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
set_clock_uncertainty -rise_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
set_clock_uncertainty -fall_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
set_clock_uncertainty -fall_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -rise_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -rise_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -rise_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -rise_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -fall_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.180
set_clock_uncertainty -fall_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.170
set_clock_uncertainty -fall_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -fall_from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 0.280
set_clock_uncertainty -rise_from [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {pll_audio|pll_audio_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -rise_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -rise_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -hold 0.080
set_clock_uncertainty -rise_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -fall_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -setup 0.200
set_clock_uncertainty -rise_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -fall_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -hold 0.080
set_clock_uncertainty -fall_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -rise_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -rise_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -hold 0.080
set_clock_uncertainty -fall_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -fall_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -setup 0.200
set_clock_uncertainty -fall_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -fall_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -hold 0.080
set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] 0.060
set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] 0.060
set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] 0.060
set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] 0.060
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060
set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060
set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1_50}] -rise_to [get_clocks {FPGA_CLK1_50}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1_50}] -rise_to [get_clocks {FPGA_CLK1_50}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1_50}] -fall_to [get_clocks {FPGA_CLK1_50}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1_50}] -fall_to [get_clocks {FPGA_CLK1_50}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1_50}] -rise_to [get_clocks {FPGA_CLK1_50}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1_50}] -rise_to [get_clocks {FPGA_CLK1_50}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1_50}] -fall_to [get_clocks {FPGA_CLK1_50}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1_50}] -fall_to [get_clocks {FPGA_CLK1_50}] -hold 0.060
#**************************************************************
# Set Input Delay
#**************************************************************
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -exclusive -group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] -group [get_clocks { pll_audio|pll_audio_inst|altera_pll_i|*[0].*|divclk}] -group [get_clocks { spi_sck}] -group [get_clocks { hdmi_sck}] -group [get_clocks { *|h2f_user0_clk}] -group [get_clocks { FPGA_CLK1_50 }] -group [get_clocks { FPGA_CLK2_50 }] -group [get_clocks { FPGA_CLK3_50 }]
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -to [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
set_false_path -from [get_ports {KEY*}]
set_false_path -from [get_ports {BTN_*}]
set_false_path -to [get_ports {LED_*}]
set_false_path -to [get_ports {VGA_*}]
set_false_path -to [get_ports {AUDIO_SPDIF}]
set_false_path -to [get_ports {AUDIO_L}]
set_false_path -to [get_ports {AUDIO_R}]
set_false_path -to [get_keepers {cfg[*]}]
set_false_path -from [get_keepers {cfg[*]}]
set_false_path -from [get_keepers {VSET[*]}]
set_false_path -to [get_keepers {wcalc[*] hcalc[*]}]
set_false_path -to [get_keepers {hdmi_width[*] hdmi_height[*]}]
set_false_path -to [get_keepers {*_osd|v_cnt*}]
set_false_path -to [get_keepers {*_osd|v_osd_start*}]
set_false_path -to [get_keepers {*_osd|v_info_start*}]
set_false_path -to [get_keepers {*_osd|h_osd_start*}]
set_false_path -from [get_keepers {*_osd|v_osd_start*}]
set_false_path -from [get_keepers {*_osd|v_info_start*}]
set_false_path -from [get_keepers {*_osd|h_osd_start*}]
set_false_path -from [get_keepers {*_osd|rot*}]
set_false_path -from [get_keepers {*_osd|dsp_width*}]
set_false_path -to [get_keepers {*_osd|half}]
set_false_path -to [get_keepers {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}]
set_false_path -from [get_keepers {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}]
set_false_path -to [get_keepers {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]}]
set_false_path -from [get_keepers {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]}]
set_false_path -to [get_keepers {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}]
set_false_path -from [get_keepers {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}]
set_false_path -from [get_keepers {aflt_* acx* acy* areset* arc*}]
set_false_path -from [get_keepers {vs_line*}]
set_false_path -from [get_keepers {ascal|o_ihsize*}]
set_false_path -from [get_keepers {ascal|o_ivsize*}]
set_false_path -from [get_keepers {ascal|o_format*}]
set_false_path -from [get_keepers {ascal|o_hdown}]
set_false_path -from [get_keepers {ascal|o_vdown}]
set_false_path -from [get_keepers {ascal|o_hmin* ascal|o_hmax* ascal|o_vmin* ascal|o_vmax*}]
set_false_path -from [get_keepers {ascal|o_hdisp* ascal|o_vdisp*}]
set_false_path -from [get_keepers {ascal|o_htotal* ascal|o_vtotal*}]
set_false_path -from [get_keepers {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*}]
set_false_path -from [get_keepers {ascal|o_hsize* ascal|o_vsize*}]
set_false_path -from [get_keepers {mcp23009|sd_cd}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -setup -start -from [get_keepers {*fx68k:*|Ir[*]}] -to [get_keepers {*fx68k:*|microAddr[*]}] 2
set_multicycle_path -hold -start -from [get_keepers {*fx68k:*|Ir[*]}] -to [get_keepers {*fx68k:*|microAddr[*]}] 1
set_multicycle_path -setup -start -from [get_keepers {*fx68k:*|Ir[*]}] -to [get_keepers {*fx68k:*|nanoAddr[*]}] 2
set_multicycle_path -hold -start -from [get_keepers {*fx68k:*|Ir[*]}] -to [get_keepers {*fx68k:*|nanoAddr[*]}] 1
set_multicycle_path -setup -start -from [get_keepers {*|nanoLatch[*]}] -to [get_keepers {*|excUnit|alu|pswCcr[*]}] 2
set_multicycle_path -hold -start -from [get_keepers {*|nanoLatch[*]}] -to [get_keepers {*|excUnit|alu|pswCcr[*]}] 1
set_multicycle_path -setup -start -from [get_keepers {*|excUnit|alu|oper[*]}] -to [get_keepers {*|excUnit|alu|pswCcr[*]}] 2
set_multicycle_path -hold -start -from [get_keepers {*|excUnit|alu|oper[*]}] -to [get_keepers {*|excUnit|alu|pswCcr[*]}] 1
set_multicycle_path -setup -end -to [get_keepers {*_osd|osd_vcnt*}] 2
set_multicycle_path -hold -end -to [get_keepers {*_osd|osd_vcnt*}] 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

71
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/dev/mra/Demons World - Horror Story (Set 1).mra
View File

@@ -1,71 +0,0 @@
<misterromdescription>
<name>Demon's World / Horror Story (Set 1)</name>
<setname>demonwld</setname>
<rbf>demonwld</rbf>
<mameversion>0254</mameversion>
<year>1990</year>
<manufacturer>Toaplan</manufacturer>
<players>2</players>
<joystick>8-way</joystick>
<rotation>Horizontal</rotation>
<region>Japan</region>
<switches default="00,00,00,00,00,00,00,00">
<!-- DSWA -->
<dip name="Screen Rotation" bits="1" ids="Off,On"/>
<dip name="Test Mode" bits="2" ids="Off,On"/>
<dip name="Attract Sound" bits="3" ids="On,Off"/>
<dip name="Coin 1" bits="4,5" ids="1/1,2/1,3/1,4/1"/>
<dip name="Coin 2" bits="6,7" ids="1/2,1/3,1/4,1/6"/>
<!-- DSWB -->
<dip name="Game Difficulty" bits="8,9" ids="B,A,C,D"/>
<dip name="Extend" bits="10,11" ids="30k/100k,50k/100k,100k,None"/>
<dip name="Player" bits="12,13" ids="3,5,2,1"/>
<dip name="No Hit" bits="14" ids="Off,On"/>
<!-- TJUMP -->
<dip name="Region" bits="16" ids="Japan/Taito Corp,Toaplan"/>
</switches>
<buttons names="Shot,Jump,-,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,Start"/>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" zip="demonwld.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="o16-10.v2" crc="ca8194f3" map="01"/>
<part name="o16-09.v2" crc="7baea7ba" map="10"/>
</interleave>
<part repeat="0x40000">FF</part>
<!-- gfx1 - starts at 0x80000 -->
<interleave output="32">
<part name="rom05" crc="6506c982" map="0001"/>
<part name="rom07" crc="a3a0d993" map="0010"/>
<part name="rom06" crc="4fc5e5f3" map="0100"/>
<part name="rom08" crc="eb53ab09" map="1000"/>
</interleave>
<part repeat="0x80000"> FF</part>
<!-- gfx2 - starts at 0x180000 -->
<interleave output="32">
<part name="rom01" crc="1b3724e9" map="0001"/>
<part name="rom02" crc="7b20a44d" map="0010"/>
<part name="rom03" crc="2cacdcd0" map="0100"/>
<part name="rom04" crc="76fd3201" map="1000"/>
</interleave>
<!-- audiocpu - starts at 0x200000 -->
<part name="rom11.v2" crc="dbe08c85"/>
<!-- dsp - starts at 0x208000 -->
<interleave output="16">
<part name="dsp_21.bin" crc="2d135376" map="01"/>
<part name="dsp_22.bin" crc="79389a71" map="10"/>
</interleave>
<!-- Total 0x209000 bytes - 2084 kBytes -->
</rom>
</misterromdescription>

71
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/dev/mra/_alternatives/_Demon's World/Demons World - Horror Story (Set 2).mra
View File

@@ -1,71 +0,0 @@
<misterromdescription>
<name>Demon's World / Horror Story (Set 2)</name>
<setname>demonwld</setname>
<rbf>demonwld</rbf>
<mameversion>0254</mameversion>
<year>1989</year>
<manufacturer>Toaplan</manufacturer>
<players>2</players>
<joystick>8-way</joystick>
<rotation>Horizontal</rotation>
<region>Japan</region>
<switches default="00,00,00,00,00,00,00,00">
<!-- DSWA -->
<dip name="Screen Rotation" bits="1" ids="Off,On"/>
<dip name="Test Mode" bits="2" ids="Off,On"/>
<dip name="Attract Sound" bits="3" ids="On,Off"/>
<dip name="Coin 1" bits="4,5" ids="1/1,2/1,3/1,4/1"/>
<dip name="Coin 2" bits="6,7" ids="1/2,1/3,1/4,1/6"/>
<!-- DSWB -->
<dip name="Game Difficulty" bits="8,9" ids="B,A,C,D"/>
<dip name="Extend" bits="10,11" ids="30k/100k,50k/100k,100k,None"/>
<dip name="Player" bits="12,13" ids="3,5,2,1"/>
<dip name="No Hit" bits="14" ids="Off,On"/>
<!-- TJUMP -->
<dip name="Region" bits="16" ids="Japan/Taito Corp,Toaplan"/>
</switches>
<buttons names="Shot,Jump,-,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,Start"/>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" zip="demonwld1.zip|demonwld.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="o16n-10.bin" crc="fc38aeaa" map="01"/>
<part name="o16n-09.bin" crc="74f66643" map="10"/>
</interleave>
<part repeat="0x40000"> FF</part>
<!-- gfx1 - starts at 0x80000 -->
<interleave output="32">
<part name="rom05" crc="6506c982" map="0001"/>
<part name="rom07" crc="a3a0d993" map="0010"/>
<part name="rom06" crc="4fc5e5f3" map="0100"/>
<part name="rom08" crc="eb53ab09" map="1000"/>
</interleave>
<part repeat="0x80000"> FF</part>
<!-- gfx2 - starts at 0x180000 -->
<interleave output="32">
<part name="rom01" crc="1b3724e9" map="0001"/>
<part name="rom02" crc="7b20a44d" map="0010"/>
<part name="rom03" crc="2cacdcd0" map="0100"/>
<part name="rom04" crc="76fd3201" map="1000"/>
</interleave>
<!-- audiocpu - starts at 0x200000 -->
<part name="o16-11.bin" crc="dbe08c85"/>
<!-- dsp - starts at 0x208000 -->
<interleave output="16">
<part name="dsp_21.bin" crc="2d135376" map="01"/>
<part name="dsp_22.bin" crc="79389a71" map="10"/>
</interleave>
<!-- Total 0x209000 bytes - 2084 kBytes -->
</rom>
</misterromdescription>

71
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/dev/mra/_alternatives/_Demon's World/Demons World - Horror Story (Set 3).mra
View File

@@ -1,71 +0,0 @@
<misterromdescription>
<name>Demon's World / Horror Story (Set 3)</name>
<setname>demonwld2</setname>
<rbf>demonwld</rbf>
<mameversion>0254</mameversion>
<year>1989</year>
<manufacturer>Toaplan</manufacturer>
<players>2</players>
<joystick>8-way</joystick>
<rotation>Horizontal</rotation>
<region>Japan</region>
<switches default="00,00,00,00,00,00,00,00">
<!-- DSWA -->
<dip name="Screen Rotation" bits="1" ids="Off,On"/>
<dip name="Test Mode" bits="2" ids="Off,On"/>
<dip name="Attract Sound" bits="3" ids="On,Off"/>
<dip name="Coin 1" bits="4,5" ids="1/1,2/1,3/1,4/1"/>
<dip name="Coin 2" bits="6,7" ids="1/2,1/3,1/4,1/6"/>
<!-- DSWB -->
<dip name="Game Difficulty" bits="8,9" ids="B,A,C,D"/>
<dip name="Extend" bits="10,11" ids="30k/100k,50k/100k,100k,None"/>
<dip name="Player" bits="12,13" ids="3,5,2,1"/>
<dip name="No Hit" bits="14" ids="Off,On"/>
<!-- TJUMP -->
<dip name="Region" bits="16,17" ids="Japan/Taito Corp,US/Taito America,World/Taito Japan,US/Toaplan"/>
</switches>
<buttons names="Shot,Jump,-,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,Start"/>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" zip="demonwld2.zip|demonwld.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="o16-10.rom" crc="036ee46c" map="01"/>
<part name="o16-09.rom" crc="bed746e3" map="10"/>
</interleave>
<part repeat="0x40000"> FF</part>
<!-- gfx1 - starts at 0x80000 -->
<interleave output="32">
<part name="rom05" crc="6506c982" map="0001"/>
<part name="rom07" crc="a3a0d993" map="0010"/>
<part name="rom06" crc="4fc5e5f3" map="0100"/>
<part name="rom08" crc="eb53ab09" map="1000"/>
</interleave>
<part repeat="0x80000"> FF</part>
<!-- gfx2 - starts at 0x180000 -->
<interleave output="32">
<part name="rom01" crc="1b3724e9" map="0001"/>
<part name="rom02" crc="7b20a44d" map="0010"/>
<part name="rom03" crc="2cacdcd0" map="0100"/>
<part name="rom04" crc="76fd3201" map="1000"/>
</interleave>
<!-- audiocpu - starts at 0x200000 -->
<part name="rom11" crc="397eca1b"/>
<!-- dsp - starts at 0x208000 -->
<interleave output="16">
<part name="dsp_21.bin" crc="2d135376" map="01"/>
<part name="dsp_22.bin" crc="79389a71" map="10"/>
</interleave>
<!-- Total 0x209000 bytes - 2084 kBytes -->
</rom>
</misterromdescription>

71
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/dev/mra/_alternatives/_Demon's World/Demons World - Horror Story (Set 4).mra
View File

@@ -1,71 +0,0 @@
<misterromdescription>
<name>Demon's World / Horror Story (Set 4)</name>
<setname>demonwld3</setname>
<rbf>demonwld</rbf>
<mameversion>0254</mameversion>
<year>1989</year>
<manufacturer>Toaplan</manufacturer>
<players>2</players>
<joystick>8-way</joystick>
<rotation>Horizontal</rotation>
<region>Japan</region>
<switches default="00,00,00,00,00,00,00,00">
<!-- DSWA -->
<dip name="Screen Rotation" bits="1" ids="Off,On"/>
<dip name="Test Mode" bits="2" ids="Off,On"/>
<dip name="Attract Sound" bits="3" ids="On,Off"/>
<dip name="Coin 1" bits="4,5" ids="1/1,2/1,3/1,4/1"/>
<dip name="Coin 2" bits="6,7" ids="1/2,1/3,1/4,1/6"/>
<!-- DSWB -->
<dip name="Game Difficulty" bits="8,9" ids="B,A,C,D"/>
<dip name="Extend" bits="10,11" ids="30k/100k,50k/100k,100k,None"/>
<dip name="Player" bits="12,13" ids="3,5,2,1"/>
<dip name="No Hit" bits="14" ids="Off,On"/>
<!-- TJUMP -->
<dip name="Region" bits="16,17" ids="Japan/Taito Corp,US/Taito America,World/Taito Japan,US/Toaplan"/>
</switches>
<buttons names="Shot,Jump,-,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,Start"/>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" zip="demonwld3.zip|demonwld.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="o16-10-2.bin" crc="84ee5218" map="01"/>
<part name="o16-09-2.bin" crc="cf474cb2" map="10"/>
</interleave>
<part repeat="0x40000"> FF</part>
<!-- gfx1 - starts at 0x80000 -->
<interleave output="32">
<part name="rom05" crc="6506c982" map="0001"/>
<part name="rom07" crc="a3a0d993" map="0010"/>
<part name="rom06" crc="4fc5e5f3" map="0100"/>
<part name="rom08" crc="eb53ab09" map="1000"/>
</interleave>
<part repeat="0x80000"> FF</part>
<!-- gfx2 - starts at 0x180000 -->
<interleave output="32">
<part name="rom01" crc="1b3724e9" map="0001"/>
<part name="rom02" crc="7b20a44d" map="0010"/>
<part name="rom03" crc="2cacdcd0" map="0100"/>
<part name="rom04" crc="76fd3201" map="1000"/>
</interleave>
<!-- audiocpu - starts at 0x200000 -->
<part name="rom11" crc="397eca1b"/>
<!-- dsp - starts at 0x208000 -->
<interleave output="16">
<part name="dsp_21.bin" crc="2d135376" map="01"/>
<part name="dsp_22.bin" crc="79389a71" map="10"/>
</interleave>
<!-- Total 0x209000 bytes - 2084 kBytes -->
</rom>
</misterromdescription>

71
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/dev/mra/_alternatives/_Demon's World/Demons World - Horror Story (Set 5).mra
View File

@@ -1,71 +0,0 @@
<misterromdescription>
<name>Demon's World / Horror Story (Set 5)</name>
<setname>demonwld4</setname>
<rbf>demonwld</rbf>
<mameversion>0254</mameversion>
<year>1989</year>
<manufacturer>Toaplan</manufacturer>
<players>2</players>
<joystick>8-way</joystick>
<rotation>Horizontal</rotation>
<region>Japan</region>
<switches default="00,00,00,00,00,00,00,00">
<!-- DSWA -->
<dip name="Screen Rotation" bits="1" ids="Off,On"/>
<dip name="Test Mode" bits="2" ids="Off,On"/>
<dip name="Attract Sound" bits="3" ids="On,Off"/>
<dip name="Coin 1" bits="4,5" ids="1/1,2/1,3/1,4/1"/>
<dip name="Coin 2" bits="6,7" ids="1/2,1/3,1/4,1/6"/>
<!-- DSWB -->
<dip name="Game Difficulty" bits="8,9" ids="B,A,C,D"/>
<dip name="Extend" bits="10,11" ids="30k/100k,50k/100k,100k,None"/>
<dip name="Player" bits="12,13" ids="3,5,2,1"/>
<dip name="No Hit" bits="14" ids="Off,On"/>
<!-- TJUMP -->
<dip name="Region" bits="16,17" ids="Japan/Taito Corp,US/Taito America,World/Taito Japan,US/Toaplan"/>
</switches>
<buttons names="Shot,Jump,-,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,Start"/>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" zip="demonwld4.zip|demonwld.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="o16-10.bin" crc="6f7468e0" map="01"/>
<part name="o16-09.bin" crc="a572f5f7" map="10"/>
</interleave>
<part repeat="0x40000"> FF</part>
<!-- gfx1 - starts at 0x80000 -->
<interleave output="32">
<part name="rom05" crc="6506c982" map="0001"/>
<part name="rom07" crc="a3a0d993" map="0010"/>
<part name="rom06" crc="4fc5e5f3" map="0100"/>
<part name="rom08" crc="eb53ab09" map="1000"/>
</interleave>
<part repeat="0x80000"> FF</part>
<!-- gfx2 - starts at 0x180000 -->
<interleave output="32">
<part name="rom01" crc="1b3724e9" map="0001"/>
<part name="rom02" crc="7b20a44d" map="0010"/>
<part name="rom03" crc="2cacdcd0" map="0100"/>
<part name="rom04" crc="76fd3201" map="1000"/>
</interleave>
<!-- audiocpu - starts at 0x200000 -->
<part name="rom11" crc="397eca1b"/>
<!-- dsp - starts at 0x208000 -->
<interleave output="16">
<part name="dsp_21.bin" crc="2d135376" map="01"/>
<part name="dsp_22.bin" crc="79389a71" map="10"/>
</interleave>
<!-- Total 0x209000 bytes - 2084 kBytes -->
</rom>
</misterromdescription>

636
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/dev/stp1.stp
View File

File diff suppressed because one or more lines are too long

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Artwork/horror-story101.jpg
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 1001 KiB

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Artwork/horror-story102.jpg
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 574 KiB

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Out Zone (TP-015C)/Out Zone (TCP-015C)/PXL_20220131_034746408.jpg
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 3.1 MiB

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Out Zone (TP-015C)/Zero Wing/1 - CG0hSFG.jpg
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 3.3 MiB

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Out Zone (TP-015C)/Zero Wing/2 - QHaxXRl.jpg
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 3.7 MiB

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Out Zone (TP-015C)/Zero Wing/3 - rFlWtWq.jpg
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 3.8 MiB

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Out Zone (TP-015C)/Zero Wing/4 - XhrRfrr.jpg
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 3.3 MiB

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Out Zone (TP-015C)/Zero Wing/5 - ycb8UDb.jpg
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 4.1 MiB

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Out Zone (TP-015C)/Zero Wing/6 - WFY0QAw.jpg
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 3.5 MiB

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Out Zone (TP-015C)/Zero Wing/7 - BjNSo7Z.jpg
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 4.0 MiB

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Out Zone (TP-015C)/Zero Wing/8 - QDJ8zqu.jpg
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 3.7 MiB

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Out Zone (TP-015C)/outzone_50MHz.sr
View File

Binary file not shown.

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Out Zone (TP-015C)/outzone_Hz.png
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 80 KiB

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Out Zone (TP-015C)/outzone_KHz.png
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 58 KiB

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/Schematics/Out Zone Schematics.pdf
View File

Binary file not shown.

57996
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/TMS32010/TMS32010_Users_Guide_1985.pdf
View File

File diff suppressed because one or more lines are too long

BIN
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/doc/TMS32010/tms320c10fnl.pdf
View File

Binary file not shown.

25
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/files.qip
View File

@@ -1,25 +0,0 @@
set_global_assignment -name SDC_FILE demonwld.sdc
set_global_assignment -name SYSTEMVERILOG_FILE demonwld.sv
set_global_assignment -name QIP_FILE rtl/t80/T80.qip
set_global_assignment -name QIP_FILE rtl/fx68k/fx68k.qip
set_global_assignment -name QIP_FILE rtl/jtopl/jt26.qip
set_global_assignment -name QIP_FILE rtl/TMS320C1X/TMS320C1X.qip
set_global_assignment -name VERILOG_FILE rtl/video_timing.v
set_global_assignment -name QIP_FILE sys/pll_q17.qip
set_global_assignment -name QIP_FILE sys/pll_hdmi.qip
set_global_assignment -name QIP_FILE sys/pll_cfg.qip
set_global_assignment -name QIP_FILE sys/pll_audio.qip
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name VERILOG_FILE rtl/pause.v
set_global_assignment -name VERILOG_FILE rtl/mem/rom_controller.v
set_global_assignment -name VERILOG_FILE rtl/mem/tile_cache.v
set_global_assignment -name VERILOG_FILE rtl/mem/cache.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/chip_select.v
set_global_assignment -name VHDL_FILE rtl/mem/math.vhd
set_global_assignment -name VHDL_FILE rtl/mem/segment.vhd
set_global_assignment -name VHDL_FILE rtl/mem/download_buffer.vhd
set_global_assignment -name VHDL_FILE rtl/mem/sdram.vhd
set_global_assignment -name VHDL_FILE rtl/mem/dual_port_ram.vhd
set_global_assignment -name VERILOG_FILE rtl/jtframe_mixer.v
set_global_assignment -name VERILOG_FILE rtl/jtframe_fir_mono.v

66
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/releases/Demons World - Horror Story (Set 3).mra
View File

@@ -1,66 +0,0 @@
<misterromdescription>
<name>Demon's World / Horror Story (Set 3)</name>
<setname>demonwld2</setname>
<rbf>demonwld</rbf>
<mameversion>0254</mameversion>
<year>1989</year>
<manufacturer>Toaplan</manufacturer>
<players>2</players>
<joystick>8-way</joystick>
<rotation>Horizontal</rotation>
<region>Japan</region>
<switches default="00,00,00,00,00,00,00,00">
<!-- DSWA -->
<dip name="Screen Rotation" bits="1" ids="Off,On"/>
<dip name="Test Mode" bits="2" ids="Off,On"/>
<dip name="Attract Sound" bits="3" ids="On,Off"/>
<dip name="Coin 1" bits="4,5" ids="1/1,2/1,3/1,4/1"/>
<dip name="Coin 2" bits="6,7" ids="1/2,1/3,1/4,1/6"/>
<!-- DSWB -->
<dip name="Game Difficulty" bits="8,9" ids="B,A,C,D"/>
<dip name="Extend" bits="10,11" ids="30k/100k,50k/100k,100k,None"/>
<dip name="Player" bits="12,13" ids="3,5,2,1"/>
<dip name="No Hit" bits="14" ids="Off,On"/>
<!-- TJUMP -->
<dip name="Region" bits="16,19" ids="Japan/Taito Corp,US/Taito America,World/Taito Japan,US/Toaplan"/>
</switches>
<buttons names="Shot,Jump,Rapid Shot,Slow Scroll,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start,Select"/>
<rom index="0" zip="demonwld2.zip|demonwld.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="o16-10.rom" crc="036ee46c" map="01"/>
<part name="o16-09.rom" crc="bed746e3" map="10"/>
</interleave>
<part repeat="0x40000"> FF</part>
<!-- gfx1 - starts at 0x80000 -->
<interleave output="32">
<part name="rom05" crc="6506c982" map="0001"/>
<part name="rom07" crc="a3a0d993" map="0010"/>
<part name="rom06" crc="4fc5e5f3" map="0100"/>
<part name="rom08" crc="eb53ab09" map="1000"/>
</interleave>
<part repeat="0x80000"> FF</part>
<!-- gfx2 - starts at 0x180000 -->
<interleave output="32">
<part name="rom01" crc="1b3724e9" map="0001"/>
<part name="rom02" crc="7b20a44d" map="0010"/>
<part name="rom03" crc="2cacdcd0" map="0100"/>
<part name="rom04" crc="76fd3201" map="1000"/>
</interleave>
<!-- audiocpu - starts at 0x200000 -->
<part name="rom11" crc="397eca1b"/>
<patch offset="0x0000145E">67 16</patch>
<patch offset="0x00001474">66 20</patch>
<patch offset="0x0000181C">4E 71</patch>
<patch offset="0x00001824">60 0A</patch>
<!-- Total 0x208000 bytes - 2084 kBytes -->
</rom>
</misterromdescription>

66
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/releases/_alternatives/_Demon's World/Demon's World - Horror Story (Set 1).mra
View File

@@ -1,66 +0,0 @@
<misterromdescription>
<name>Demon's World / Horror Story (Set 1)</name>
<setname>demonwld</setname>
<rbf>demonwld</rbf>
<mameversion>0254</mameversion>
<year>1990</year>
<manufacturer>Toaplan</manufacturer>
<players>2</players>
<joystick>8-way</joystick>
<rotation>Horizontal</rotation>
<region>Japan</region>
<switches default="00,00,00,00,00,00,00,00">
<!-- DSWA -->
<dip name="Screen Rotation" bits="1" ids="Off,On"/>
<dip name="Test Mode" bits="2" ids="Off,On"/>
<dip name="Attract Sound" bits="3" ids="On,Off"/>
<dip name="Coin 1" bits="4,5" ids="1/1,2/1,3/1,4/1"/>
<dip name="Coin 2" bits="6,7" ids="1/2,1/3,1/4,1/6"/>
<!-- DSWB -->
<dip name="Game Difficulty" bits="8,9" ids="B,A,C,D"/>
<dip name="Extend" bits="10,11" ids="30k/100k,50k/100k,100k,None"/>
<dip name="Player" bits="12,13" ids="3,5,2,1"/>
<dip name="No Hit" bits="14" ids="Off,On"/>
<!-- TJUMP -->
<dip name="Region" bits="16" ids="Japan/Taito Corp,Toaplan"/>
</switches>
<buttons names="Shot,Jump,Rapid Shot,Slow Scroll,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start,Select"/>
<rom index="0" zip="demonwld.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="o16-10.v2" crc="ca8194f3" map="01"/>
<part name="o16-09.v2" crc="7baea7ba" map="10"/>
</interleave>
<part repeat="0x40000">FF</part>
<!-- gfx1 - starts at 0x80000 -->
<interleave output="32">
<part name="rom05" crc="6506c982" map="0001"/>
<part name="rom07" crc="a3a0d993" map="0010"/>
<part name="rom06" crc="4fc5e5f3" map="0100"/>
<part name="rom08" crc="eb53ab09" map="1000"/>
</interleave>
<part repeat="0x80000"> FF</part>
<!-- gfx2 - starts at 0x180000 -->
<interleave output="32">
<part name="rom01" crc="1b3724e9" map="0001"/>
<part name="rom02" crc="7b20a44d" map="0010"/>
<part name="rom03" crc="2cacdcd0" map="0100"/>
<part name="rom04" crc="76fd3201" map="1000"/>
</interleave>
<!-- audiocpu - starts at 0x200000 -->
<part name="rom11.v2" crc="dbe08c85"/>
<patch offset="0x0000145E">67 16</patch>
<patch offset="0x00001474">66 20</patch>
<patch offset="0x00001430">4E 71</patch>
<patch offset="0x00001438">60 0A</patch>
<!-- Total 0x208000 bytes - 2080 kBytes -->
</rom>
</misterromdescription>

66
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/releases/_alternatives/_Demon's World/Demons World - Horror Story (Set 2).mra
View File

@@ -1,66 +0,0 @@
<misterromdescription>
<name>Demon's World / Horror Story (Set 2)</name>
<setname>demonwld1</setname>
<rbf>demonwld</rbf>
<mameversion>0254</mameversion>
<year>1989</year>
<manufacturer>Toaplan</manufacturer>
<players>2</players>
<joystick>8-way</joystick>
<rotation>Horizontal</rotation>
<region>Japan</region>
<switches default="00,00,00,00,00,00,00,00">
<!-- DSWA -->
<dip name="Screen Rotation" bits="1" ids="Off,On"/>
<dip name="Test Mode" bits="2" ids="Off,On"/>
<dip name="Attract Sound" bits="3" ids="On,Off"/>
<dip name="Coin 1" bits="4,5" ids="1/1,2/1,3/1,4/1"/>
<dip name="Coin 2" bits="6,7" ids="1/2,1/3,1/4,1/6"/>
<!-- DSWB -->
<dip name="Game Difficulty" bits="8,9" ids="B,A,C,D"/>
<dip name="Extend" bits="10,11" ids="30k/100k,50k/100k,100k,None"/>
<dip name="Player" bits="12,13" ids="3,5,2,1"/>
<dip name="No Hit" bits="14" ids="Off,On"/>
<!-- TJUMP -->
<dip name="Region" bits="16" ids="Japan/Taito Corp,Toaplan"/>
</switches>
<buttons names="Shot,Jump,Rapid Shot,Slow Scroll,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start,Select"/>
<rom index="0" zip="demonwld1.zip|demonwld.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="o16n-10.bin" crc="fc38aeaa" map="01"/>
<part name="o16n-09.bin" crc="74f66643" map="10"/>
</interleave>
<part repeat="0x40000"> FF</part>
<!-- gfx1 - starts at 0x80000 -->
<interleave output="32">
<part name="rom05" crc="6506c982" map="0001"/>
<part name="rom07" crc="a3a0d993" map="0010"/>
<part name="rom06" crc="4fc5e5f3" map="0100"/>
<part name="rom08" crc="eb53ab09" map="1000"/>
</interleave>
<part repeat="0x80000"> FF</part>
<!-- gfx2 - starts at 0x180000 -->
<interleave output="32">
<part name="rom01" crc="1b3724e9" map="0001"/>
<part name="rom02" crc="7b20a44d" map="0010"/>
<part name="rom03" crc="2cacdcd0" map="0100"/>
<part name="rom04" crc="76fd3201" map="1000"/>
</interleave>
<!-- audiocpu - starts at 0x200000 -->
<part name="o16-11.bin" crc="dbe08c85"/>
<patch offset="0x0000145E">67 16</patch>
<patch offset="0x00001474">66 20</patch>
<patch offset="0x00001430">4E 71</patch>
<patch offset="0x00001438">60 0A</patch>
<!-- Total 0x208000 bytes - 2084 kBytes -->
</rom>
</misterromdescription>

66
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/releases/_alternatives/_Demon's World/Demons World - Horror Story (Set 4).mra
View File

@@ -1,66 +0,0 @@
<misterromdescription>
<name>Demon's World / Horror Story (Set 4)</name>
<setname>demonwld3</setname>
<rbf>demonwld</rbf>
<mameversion>0254</mameversion>
<year>1989</year>
<manufacturer>Toaplan</manufacturer>
<players>2</players>
<joystick>8-way</joystick>
<rotation>Horizontal</rotation>
<region>Japan</region>
<switches default="00,00,00,00,00,00,00,00">
<!-- DSWA -->
<dip name="Screen Rotation" bits="1" ids="Off,On"/>
<dip name="Test Mode" bits="2" ids="Off,On"/>
<dip name="Attract Sound" bits="3" ids="On,Off"/>
<dip name="Coin 1" bits="4,5" ids="1/1,2/1,3/1,4/1"/>
<dip name="Coin 2" bits="6,7" ids="1/2,1/3,1/4,1/6"/>
<!-- DSWB -->
<dip name="Game Difficulty" bits="8,9" ids="B,A,C,D"/>
<dip name="Extend" bits="10,11" ids="30k/100k,50k/100k,100k,None"/>
<dip name="Player" bits="12,13" ids="3,5,2,1"/>
<dip name="No Hit" bits="14" ids="Off,On"/>
<!-- TJUMP -->
<dip name="Region" bits="16,19" ids="Japan/Taito Corp,US/Taito America,World/Taito Japan,US/Toaplan"/>
</switches>
<buttons names="Shot,Jump,Rapid Shot,Slow Scroll,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start,Select"/>
<rom index="0" zip="demonwld3.zip|demonwld.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="o16-10-2.bin" crc="84ee5218" map="01"/>
<part name="o16-09-2.bin" crc="cf474cb2" map="10"/>
</interleave>
<part repeat="0x40000"> FF</part>
<!-- gfx1 - starts at 0x80000 -->
<interleave output="32">
<part name="rom05" crc="6506c982" map="0001"/>
<part name="rom07" crc="a3a0d993" map="0010"/>
<part name="rom06" crc="4fc5e5f3" map="0100"/>
<part name="rom08" crc="eb53ab09" map="1000"/>
</interleave>
<part repeat="0x80000"> FF</part>
<!-- gfx2 - starts at 0x180000 -->
<interleave output="32">
<part name="rom01" crc="1b3724e9" map="0001"/>
<part name="rom02" crc="7b20a44d" map="0010"/>
<part name="rom03" crc="2cacdcd0" map="0100"/>
<part name="rom04" crc="76fd3201" map="1000"/>
</interleave>
<!-- audiocpu - starts at 0x200000 -->
<part name="rom11" crc="397eca1b"/>
<patch offset="0x0000184A">67 16</patch>
<patch offset="0x00001860">66 22</patch>
<patch offset="0x0000181C">4E 71</patch>
<patch offset="0x00001824">60 0A</patch>
<!-- Total 0x208000 bytes - 2084 kBytes -->
</rom>
</misterromdescription>

66
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/releases/_alternatives/_Demon's World/Demons World - Horror Story (Set 5).mra
View File

@@ -1,66 +0,0 @@
<misterromdescription>
<name>Demon's World / Horror Story (Set 5)</name>
<setname>demonwld4</setname>
<rbf>demonwld</rbf>
<mameversion>0254</mameversion>
<year>1989</year>
<manufacturer>Toaplan</manufacturer>
<players>2</players>
<joystick>8-way</joystick>
<rotation>Horizontal</rotation>
<region>Japan</region>
<switches default="00,00,00,00,00,00,00,00">
<!-- DSWA -->
<dip name="Screen Rotation" bits="1" ids="Off,On"/>
<dip name="Test Mode" bits="2" ids="Off,On"/>
<dip name="Attract Sound" bits="3" ids="On,Off"/>
<dip name="Coin 1" bits="4,5" ids="1/1,2/1,3/1,4/1"/>
<dip name="Coin 2" bits="6,7" ids="1/2,1/3,1/4,1/6"/>
<!-- DSWB -->
<dip name="Game Difficulty" bits="8,9" ids="B,A,C,D"/>
<dip name="Extend" bits="10,11" ids="30k/100k,50k/100k,100k,None"/>
<dip name="Player" bits="12,13" ids="3,5,2,1"/>
<dip name="No Hit" bits="14" ids="Off,On"/>
<!-- TJUMP -->
<dip name="Region" bits="16,19" ids="Japan/Taito Corp,US/Taito America,World/Taito Japan,US/Toaplan"/>
</switches>
<buttons names="Shot,Jump,Rapid Shot,Slow Scroll,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start,Select"/>
<rom index="0" zip="demonwld4.zip|demonwld.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="o16-10.bin" crc="6f7468e0" map="01"/>
<part name="o16-09.bin" crc="a572f5f7" map="10"/>
</interleave>
<part repeat="0x40000"> FF</part>
<!-- gfx1 - starts at 0x80000 -->
<interleave output="32">
<part name="rom05" crc="6506c982" map="0001"/>
<part name="rom07" crc="a3a0d993" map="0010"/>
<part name="rom06" crc="4fc5e5f3" map="0100"/>
<part name="rom08" crc="eb53ab09" map="1000"/>
</interleave>
<part repeat="0x80000"> FF</part>
<!-- gfx2 - starts at 0x180000 -->
<interleave output="32">
<part name="rom01" crc="1b3724e9" map="0001"/>
<part name="rom02" crc="7b20a44d" map="0010"/>
<part name="rom03" crc="2cacdcd0" map="0100"/>
<part name="rom04" crc="76fd3201" map="1000"/>
</interleave>
<!-- audiocpu - starts at 0x200000 -->
<part name="rom11" crc="397eca1b"/>
<patch offset="0x00001856">67 16</patch>
<patch offset="0x0000186C">66 22</patch>
<patch offset="0x00001828">4E 71</patch>
<patch offset="0x00001830">60 0A</patch>
<!-- Total 0x208000 bytes - 2084 kBytes -->
</rom>
</misterromdescription>

4
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/fx68k/fx68k.qip
View File

@@ -1,4 +0,0 @@
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) fx68k.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) fx68kAlu.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) uaddrPla.sv ]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) fx68k.sdc ]

9
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/fx68k/fx68k.sdc
View File

@@ -1,9 +0,0 @@
set_multicycle_path -start -setup -from [get_keepers *fx68k:*|Ir[*]] -to [get_keepers *fx68k:*|microAddr[*]] 2
set_multicycle_path -start -hold -from [get_keepers *fx68k:*|Ir[*]] -to [get_keepers *fx68k:*|microAddr[*]] 1
set_multicycle_path -start -setup -from [get_keepers *fx68k:*|Ir[*]] -to [get_keepers *fx68k:*|nanoAddr[*]] 2
set_multicycle_path -start -hold -from [get_keepers *fx68k:*|Ir[*]] -to [get_keepers *fx68k:*|nanoAddr[*]] 1
set_multicycle_path -start -setup -from {*|nanoLatch[*]} -to {*|excUnit|alu|pswCcr[*]} 2
set_multicycle_path -start -hold -from {*|nanoLatch[*]} -to {*|excUnit|alu|pswCcr[*]} 1
set_multicycle_path -start -setup -from {*|excUnit|alu|oper[*]} -to {*|excUnit|alu|pswCcr[*]} 2
set_multicycle_path -start -hold -from {*|excUnit|alu|oper[*]} -to {*|excUnit|alu|pswCcr[*]} 1

2697
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/fx68k/fx68k.sv
View File

File diff suppressed because it is too large Load Diff

87
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/fx68k/fx68k.txt
View File

@@ -1,87 +0,0 @@
FX68K
68000 cycle accurate core
Copyright (c) 2018 by Jorge Cwik
fx68k@fxatari.com
FX68K is a 68K cycle exact compatible core. In theory at least, it should be impossible to distinguish functionally from a real 68K processor.
On Cyclone families it uses just over 5,100 LEs and about 5KB internal ram, reaching a max clock frequency close to 40MHz. Some optimizations are still possible to implement and increase the performance.
The core is fully synchronous. Considerable effort was done to avoid any asynchronous logic.
Written in SystemVerilog.
The timing of the external bus signals is exactly as the original processor. The only feature that is not implemented yet is bus retry using the external HALT input signal.
It was designed to replace an actual chip on a real board. This wasn't yet tested however and not all necessary output enable control signals are fully implemented.
Copyright
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
Developer Notes
The core receives a clock that must be at least twice the frequency of the desired nominal speed. The core also receives two signals for masking both phases of the clock (PHI1 and PHI2). These signals are implemented as simple clock enable for all the flip flops used by the core. This way, the original clock frequency can be any multiple and it doesn't even need to be regular or constant.
These two signals are enPhi1 and enPhi2. They must be a single cycle pulse, and they don't need to be registered. Because they are actually used as clock enable, the output signals change one cycle later.
enPhi1 should be asserted one cycle before the high phase of the nominal clock, and enPhi2 one cycle before the low phase.
E.g., during a bus cycle, AS is asserted one cycle after enPhi1 is asserted, and AS is deasserted one cycle after enPhi2 is asserted. This follows the original bus timing that specify AS being asserted on the raising edge of the clock, and deasserted on the falling edge one.
All signals follow the original polarity and then most are low active.
extReset is external reset and is synchronous and high active. Hence is doesn't have to be registered.
pwrUp qualifies external reset as being a cold power up reset. If it is asserted, then extReset must be asserted as well. Most system don't need to distinguish between a cold and a warm reset at the CPU level. Then both signals can be always asserted together. The core does expect pwrUp to be asserted initially because there is no true asynchronous reset. The signal is high active.
Timing analysis
Microcode access is one of the slowest paths on the core. But the microcode output is not needed immediately. Use the following constraints to get a more accurate timing analysis. Note that the full path might need to be modified:
# Altera/Intel
set_multicycle_path -start -setup -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|microAddr[*]] 2
set_multicycle_path -start -hold -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|microAddr[*]] 1
set_multicycle_path -start -setup -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|nanoAddr[*]] 2
set_multicycle_path -start -hold -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|nanoAddr[*]] 1
# For Xilinx Vivado
set_multicycle_path -setup -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/nanoAddr_reg*/D] 2
set_multicycle_path -setup -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/microAddr_reg*/D] 2
set_multicycle_path -hold -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/nanoAddr_reg*/D] 1
set_multicycle_path -hold -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/microAddr_reg*/D] 1
The update of the CCR flags is also time critical. Some compilers might benefit with the following constraints, but this wasn't fully verified yet:
# Altera/Intel
# set_multicycle_path -start -setup -from [fx68k:fx68k|nanoLatch[*]]
# -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 2
# set_multicycle_path -start -setup -from [fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|oper[*]]
# -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 2
# set_multicycle_path -start -hold -from [fx68k:fx68k|nanoLatch[*]]
# -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 1
# set_multicycle_path -start -hold -from [fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|oper[*]]
# -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 1

843
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/fx68k/fx68kAlu.sv
View File

@@ -1,843 +0,0 @@
//
// FX 68K
//
// M68K cycle accurate, fully synchronous
// Copyright (c) 2018 by Jorge Cwik
//
// ALU
//
// altera message_off 10230
// altera message_off 10763
// altera message_off 10958
`timescale 1 ns / 1 ns
localparam MASK_NBITS = 5;
localparam
OP_AND = 1,
OP_SUB = 2, OP_SUBX = 3, OP_ADD = 4,
OP_EXT = 5, OP_SBCD = 6, OP_SUB0 = 7,
OP_OR = 8, OP_EOR = 9,
OP_SUBC = 10, OP_ADDC = 11, OP_ADDX = 12,
OP_ASL = 13,
OP_ASR = 14,
OP_LSL = 15,
OP_LSR = 16,
OP_ROL = 17,
OP_ROR = 18,
OP_ROXL = 19,
OP_ROXR = 20,
OP_SLAA = 21,
OP_ABCD = 22;
module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
input [15:0] ird,
input [2:0] aluColumn,
input [1:0] aluDataCtrl,
input aluAddrCtrl, alueClkEn, ftu2Ccr, init, finish, aluIsByte,
input [15:0] ftu,
input [15:0] alub,
input [15:0] iDataBus, input [15:0] iAddrBus,
output ze,
output reg [15:0] alue,
output reg [7:0] ccr,
output [15:0] aluOut);
`define ALU_ROW_01 16'h0002
`define ALU_ROW_02 16'h0004
`define ALU_ROW_03 16'h0008
`define ALU_ROW_04 16'h0010
`define ALU_ROW_05 16'h0020
`define ALU_ROW_06 16'h0040
`define ALU_ROW_07 16'h0080
`define ALU_ROW_08 16'h0100
`define ALU_ROW_09 16'h0200
`define ALU_ROW_10 16'h0400
`define ALU_ROW_11 16'h0800
`define ALU_ROW_12 16'h1000
`define ALU_ROW_13 16'h2000
`define ALU_ROW_14 16'h4000
`define ALU_ROW_15 16'h8000
// Bit positions for flags in CCR
localparam CF = 0, VF = 1, ZF = 2, NF = 3, XF = 4;
reg [15:0] aluLatch;
reg [4:0] pswCcr;
reg [4:0] ccrCore;
logic [15:0] result;
logic [4:0] ccrTemp;
reg coreH; // half carry latch
logic [15:0] subResult;
logic subHcarry;
logic subCout, subOv;
assign aluOut = aluLatch;
assign ze = ~ccrCore[ ZF]; // Check polarity !!!
//
// Control
// Signals derived from IRD *must* be registered on either T3 or T4
// Signals derived from nano rom can be registered on T4.
reg [15:0] row;
reg isArX; // Don't set Z
reg noCcrEn;
reg isByte;
reg [4:0] ccrMask;
reg [4:0] oper;
logic [15:0] aOperand, dOperand;
wire isCorf = ( aluDataCtrl == 2'b10);
wire [15:0] cRow;
wire cIsArX;
wire cNoCcrEn;
rowDecoder rowDecoder( .ird( ird), .row( cRow), .noCcrEn( cNoCcrEn), .isArX( cIsArX));
// Get Operation & CCR Mask from row/col
// Registering them on T4 increase performance. But slowest part seems to be corf !
wire [4:0] cMask;
wire [4:0] aluOp;
aluGetOp aluGetOp( .row, .col( aluColumn), .isCorf, .aluOp);
ccrTable ccrTable( .col( aluColumn), .row( row), .finish, .ccrMask( cMask));
// Inefficient, uCode could help !
wire shftIsMul = row[7];
wire shftIsDiv = row[1];
wire [31:0] shftResult;
reg [7:0] bcdLatch;
reg bcdCarry, bcdOverf;
reg isLong;
reg rIrd8;
logic isShift;
logic shftCin, shftRight, addCin;
// Register some decoded signals
always_ff @( posedge clk) begin
if( enT3) begin
row <= cRow;
isArX <= cIsArX;
noCcrEn <= cNoCcrEn;
rIrd8 <= ird[8];
isByte <= aluIsByte;
end
if( enT4) begin
// Decode if long shift
// MUL and DIV are long (but special !)
isLong <= (ird[7] & ~ird[6]) | shftIsMul | shftIsDiv;
ccrMask <= cMask;
oper <= aluOp;
end
end
always_comb begin
// Dest (addr) operand source
// If aluCsr (depends on column/row) addrbus is shifted !!
aOperand = (aluAddrCtrl ? alub : iAddrBus);
// Second (data,source) operand mux
case( aluDataCtrl)
2'b00: dOperand = iDataBus;
2'b01: dOperand = 'h0000;
2'b11: dOperand = 'hffff;
// 2'b10: dOperand = bcdResult;
2'b10: dOperand = 'X;
endcase
end
// Execution
// shift operand MSB. Input in ASR/ROL. Carry in right.
// Can't be registered because uses bus operands that aren't available early !
wire shftMsb = isLong ? alue[15] : (isByte ? aOperand[7] : aOperand[15]);
aluShifter shifter( .data( { alue, aOperand}),
.swapWords( shftIsMul | shftIsDiv),
.cin( shftCin), .dir( shftRight), .isByte( isByte), .isLong( isLong),
.result( shftResult));
wire [7:0] bcdResult;
wire bcdC, bcdV;
aluCorf aluCorf( .binResult( aluLatch[7:0]), .hCarry( coreH),
.bAdd( (oper != OP_SBCD) ), .cin( pswCcr[ XF]),
.bcdResult( bcdResult), .dC( bcdC), .ov( bcdV));
// BCD adjust is among the slowest processing on ALU !
// Precompute and register BCD result on T1
// We don't need to wait for execution buses because corf is always added to ALU previous result
always_ff @( posedge clk)
if( enT1) begin
bcdLatch <= bcdResult;
bcdCarry <= bcdC;
bcdOverf <= bcdV;
end
// Adder carry in selector
always_comb
begin
case( oper)
OP_ADD, OP_SUB: addCin = 1'b0;
OP_SUB0: addCin = 1'b1; // NOT = 0 - op - 1
OP_ADDC,OP_SUBC: addCin = ccrCore[ CF];
OP_ADDX,OP_SUBX: addCin = pswCcr[ XF];
default: addCin = 1'bX;
endcase
end
// Shifter carry in and direction selector
always_comb begin
case( oper)
OP_LSL, OP_ASL, OP_ROL, OP_ROXL, OP_SLAA: shftRight = 1'b0;
OP_LSR, OP_ASR, OP_ROR, OP_ROXR: shftRight = 1'b1;
default: shftRight = 1'bX;
endcase
case( oper)
OP_LSR,
OP_ASL,
OP_LSL: shftCin = 1'b0;
OP_ROL,
OP_ASR: shftCin = shftMsb;
OP_ROR: shftCin = aOperand[0];
OP_ROXL,
OP_ROXR:
if( shftIsMul)
shftCin = rIrd8 ? pswCcr[NF] ^ pswCcr[VF] : pswCcr[ CF];
else
shftCin = pswCcr[ XF];
OP_SLAA: shftCin = aluColumn[1]; // col4 -> 0, col 6-> 1
default: shftCin = 'X;
endcase
end
// ALU operation selector
always_comb begin
// sub is DATA - ADDR
mySubber( aOperand, dOperand, addCin,
(oper == OP_ADD) | (oper == OP_ADDC) | (oper == OP_ADDX),
isByte, subResult, subCout, subOv);
isShift = 1'b0;
case( oper)
OP_AND: result = aOperand & dOperand;
OP_OR: result = aOperand | dOperand;
OP_EOR: result = aOperand ^ dOperand;
OP_EXT: result = { {8{aOperand[7]}}, aOperand[7:0]};
OP_SLAA,
OP_ASL, OP_ASR,
OP_LSL, OP_LSR,
OP_ROL, OP_ROR,
OP_ROXL, OP_ROXR:
begin
result = shftResult[15:0];
isShift = 1'b1;
end
OP_ADD,
OP_ADDC,
OP_ADDX,
OP_SUB,
OP_SUBC,
OP_SUB0,
OP_SUBX: result = subResult;
OP_ABCD,
OP_SBCD: result = { 8'hXX, bcdLatch};
default: result = 'X;
endcase
end
task mySubber;
input [15:0] inpa, inpb;
input cin, bAdd, isByte;
output reg [15:0] result;
output cout, ov;
// Not very efficient!
logic [16:0] rtemp;
logic rm,sm,dm,tsm;
begin
if( isByte)
begin
rtemp = bAdd ? { 1'b0, inpb[7:0]} + { 1'b0, inpa[7:0]} + cin:
{ 1'b0, inpb[7:0] } - { 1'b0, inpa[7:0]} - cin;
result = { {8{ rtemp[7]}}, rtemp[7:0]};
cout = rtemp[8];
end
else begin
rtemp = bAdd ? { 1'b0, inpb } + { 1'b0, inpa} + cin:
{ 1'b0, inpb } - { 1'b0, inpa} - cin;
result = rtemp[ 15:0];
cout = rtemp[16];
end
rm = isByte ? rtemp[7] : rtemp[15];
dm = isByte ? inpb[ 7] : inpb[ 15];
tsm = isByte ? inpa[ 7] : inpa[ 15];
sm = bAdd ? tsm : ~tsm;
ov = (sm & dm & ~rm) | (~sm & ~dm & rm);
// Store half carry for bcd correction
subHcarry = inpa[4] ^ inpb[4] ^ rtemp[4];
end
endtask
// CCR flags process
always_comb begin
ccrTemp[XF] = pswCcr[XF]; ccrTemp[CF] = 0; ccrTemp[VF] = 0;
// Not on all operators
ccrTemp[ ZF] = isByte ? ~(| result[7:0]) : ~(| result);
ccrTemp[ NF] = isByte ? result[7] : result[15];
unique case( oper)
OP_EXT:
// Division overflow.
if( aluColumn == 5) begin
ccrTemp[VF] = 1'b1;
ccrTemp[NF] = 1'b1; ccrTemp[ ZF] = 1'b0;
end
OP_SUB0, // used by NOT
OP_OR,
OP_EOR:
begin
ccrTemp[CF] = 0; ccrTemp[VF] = 0;
end
OP_AND:
begin
// ROXL/ROXR indeed copy X to C in column 1 (OP_AND), executed before entering the loop.
// Needed when rotate count is zero, the ucode with the ROX operator never reached.
// C must be set to the value of X, X remains unaffected.
if( (aluColumn == 1) & (row[11] | row[8]))
ccrTemp[CF] = pswCcr[XF];
else
ccrTemp[CF] = 0;
ccrTemp[VF] = 0;
end
// Assumes col 3 of DIV use C and not X !
// V will be set in other cols (2/3) of DIV
OP_SLAA: ccrTemp[ CF] = aOperand[15];
OP_LSL,OP_ROXL:
begin
ccrTemp[ CF] = shftMsb;
ccrTemp[ XF] = shftMsb;
ccrTemp[ VF] = 1'b0;
end
OP_LSR,OP_ROXR:
begin
// 0 Needed for mul, or carry gets in high word
ccrTemp[ CF] = shftIsMul ? 1'b0 : aOperand[0];
ccrTemp[ XF] = aOperand[0];
// Not relevant for MUL, we clear it at mulm6 (1f) anyway.
// Not that MUL can never overlow!
ccrTemp[ VF] = 0;
// Z is checking here ALU (low result is actually in ALUE).
// But it is correct, see comment above.
end
OP_ASL:
begin
ccrTemp[ XF] = shftMsb; ccrTemp[ CF] = shftMsb;
// V set if msb changed on any shift.
// Otherwise clear previously on OP_AND (col 1i).
ccrTemp[ VF] = pswCcr[VF] | (shftMsb ^
(isLong ? alue[15-1] : (isByte ? aOperand[7-1] : aOperand[15-1])) );
end
OP_ASR:
begin
ccrTemp[ XF] = aOperand[0]; ccrTemp[ CF] = aOperand[0];
ccrTemp[ VF] = 0;
end
// X not changed on ROL/ROR !
OP_ROL: ccrTemp[ CF] = shftMsb;
OP_ROR: ccrTemp[ CF] = aOperand[0];
OP_ADD,
OP_ADDC,
OP_ADDX,
OP_SUB,
OP_SUBC,
OP_SUBX:
begin
ccrTemp[ CF] = subCout;
ccrTemp[ XF] = subCout;
ccrTemp[ VF] = subOv;
end
OP_ABCD,
OP_SBCD:
begin
ccrTemp[ XF] = bcdCarry;
ccrTemp[ CF] = bcdCarry;
ccrTemp[ VF] = bcdOverf;
end
endcase
end
// Core and psw latched at the same cycle
// CCR filter
// CCR out mux for Z & C flags
// Z flag for 32-bit result
// Not described, but should be used also for instructions
// that clear but not set Z (ADDX/SUBX/ABCD, etc)!
logic [4:0] ccrMasked;
always_comb begin
ccrMasked = (ccrTemp & ccrMask) | (pswCcr & ~ccrMask);
// if( finish | isCorf | isArX) // No need to check specicially for isCorf as they always have the "finish" flag anyway
if( finish | isArX)
ccrMasked[ ZF] = ccrTemp[ ZF] & pswCcr[ ZF];
end
always_ff @( posedge clk) begin
if( enT3) begin
// Update latches from ALU operators
if( (| aluColumn)) begin
aluLatch <= result;
coreH <= subHcarry;
// Update CCR core
if( (| aluColumn))
ccrCore <= ccrTemp; // Most bits not really used
end
if( alueClkEn)
alue <= iDataBus;
else if( isShift & (| aluColumn))
alue <= shftResult[31:16];
end
// CCR
// Originally on T3-T4 edge pulse !!
// Might be possible to update on T4 (but not after T0) from partial result registered on T3, it will increase performance!
if( pwrUp)
pswCcr <= '0;
else if( enT3 & ftu2Ccr)
pswCcr <= ftu[4:0];
else if( enT3 & ~noCcrEn & (finish | init))
pswCcr <= ccrMasked;
end
assign ccr = { 3'b0, pswCcr};
endmodule
// add bcd correction factor
// It would be more efficient to merge add/sub with main ALU !!!
module aluCorf( input [7:0] binResult, input bAdd, input cin, input hCarry,
output [7:0] bcdResult, output dC, output logic ov);
reg [8:0] htemp;
reg [4:0] hNib;
wire lowC = hCarry | (bAdd ? gt9( binResult[ 3:0]) : 1'b0);
wire highC = cin | (bAdd ? (gt9( htemp[7:4]) | htemp[8]) : 1'b0);
always_comb begin
if( bAdd) begin
htemp = { 1'b0, binResult} + (lowC ? 4'h6 : 4'h0);
hNib = htemp[8:4] + (highC ? 4'h6 : 4'h0);
ov = hNib[3] & ~binResult[7];
end
else begin
htemp = { 1'b0, binResult} - (lowC ? 4'h6 : 4'h0);
hNib = htemp[8:4] - (highC ? 4'h6 : 4'h0);
ov = ~hNib[3] & binResult[7];
end
end
assign bcdResult = { hNib[ 3:0], htemp[3:0]};
assign dC = hNib[4] | cin;
// Nibble > 9
function gt9 (input [3:0] nib);
begin
gt9 = nib[3] & (nib[2] | nib[1]);
end
endfunction
endmodule
module aluShifter( input [31:0] data,
input isByte, input isLong, swapWords,
input dir, input cin,
output logic [31:0] result);
// output reg cout
logic [31:0] tdata;
// size mux, put cin in position if dir == right
always_comb begin
tdata = data;
if( isByte & dir)
tdata[8] = cin;
else if( !isLong & dir)
tdata[16] = cin;
end
always_comb begin
// Reverse alu/alue position for MUL & DIV
// Result reversed again
if( swapWords & dir)
result = { tdata[0], tdata[31:17], cin, tdata[15:1]};
else if( swapWords)
result = { tdata[30:16], cin, tdata[14:0], tdata[31]};
else if( dir)
result = { cin, tdata[31:1]};
else
result = { tdata[30:0], cin};
end
endmodule
// Get current OP from row & col
module aluGetOp( input [15:0] row, input [2:0] col, input isCorf,
output logic [4:0] aluOp);
always_comb begin
aluOp = 'X;
unique case( col)
1: aluOp = OP_AND;
5: aluOp = OP_EXT;
default:
unique case( 1'b1)
row[1]:
unique case( col)
2: aluOp = OP_SUB;
3: aluOp = OP_SUBC;
4,6: aluOp = OP_SLAA;
endcase
row[2]:
unique case( col)
2: aluOp = OP_ADD;
3: aluOp = OP_ADDC;
4: aluOp = OP_ASR;
endcase
row[3]:
unique case( col)
2: aluOp = OP_ADDX;
3: aluOp = isCorf ? OP_ABCD : OP_ADD;
4: aluOp = OP_ASL;
endcase
row[4]:
aluOp = ( col == 4) ? OP_LSL : OP_AND;
row[5],
row[6]:
unique case( col)
2: aluOp = OP_SUB;
3: aluOp = OP_SUBC;
4: aluOp = OP_LSR;
endcase
row[7]: // MUL
unique case( col)
2: aluOp = OP_SUB;
3: aluOp = OP_ADD;
4: aluOp = OP_ROXR;
endcase
row[8]:
// OP_AND For EXT.L
// But would be more efficient to change ucode and use column 1 instead of col3 at ublock extr1!
unique case( col)
2: aluOp = OP_EXT;
3: aluOp = OP_AND;
4: aluOp = OP_ROXR;
endcase
row[9]:
unique case( col)
2: aluOp = OP_SUBX;
3: aluOp = OP_SBCD;
4: aluOp = OP_ROL;
endcase
row[10]:
unique case( col)
2: aluOp = OP_SUBX;
3: aluOp = OP_SUBC;
4: aluOp = OP_ROR;
endcase
row[11]:
unique case( col)
2: aluOp = OP_SUB0;
3: aluOp = OP_SUB0;
4: aluOp = OP_ROXL;
endcase
row[12]: aluOp = OP_ADDX;
row[13]: aluOp = OP_EOR;
row[14]: aluOp = (col == 4) ? OP_EOR : OP_OR;
row[15]: aluOp = (col == 3) ? OP_ADD : OP_OR; // OP_ADD used by DBcc
endcase
endcase
end
endmodule
// Decodes IRD into ALU row (1-15)
// Slow, but no need to optimize for speed since IRD is latched at least two CPU cycles before it is used
// We also register the result after combining with column from nanocode
//
// Many opcodes are not decoded because they either don't do any ALU op,
// or use only columns 1 and 5 that are the same for all rows.
module rowDecoder( input [15:0] ird,
output logic [15:0] row, output noCcrEn, output logic isArX);
// Addr or data register direct
wire eaRdir = (ird[ 5:4] == 2'b00);
// Addr register direct
wire eaAdir = (ird[ 5:3] == 3'b001);
wire size11 = ird[7] & ird[6];
always_comb begin
case( ird[15:12])
'h4,
'h9,
'hd:
isArX = row[10] | row[12];
default:
isArX = 1'b0;
endcase
end
always_comb begin
unique case( ird[15:12])
'h4: begin
if( ird[8])
row = `ALU_ROW_06; // chk (or lea)
else case( ird[11:9])
'b000: row = `ALU_ROW_10; // negx
'b001: row = `ALU_ROW_04; // clr
'b010: row = `ALU_ROW_05; // neg
'b011: row = `ALU_ROW_11; // not
'b100: row = (ird[7]) ? `ALU_ROW_08 : `ALU_ROW_09; // nbcd/swap/ext(or pea)
'b101: row = `ALU_ROW_15; // tst & tas
default: row = 0;
endcase
end
'h0: begin
if( ird[8]) // dynamic bit
row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13;
else case( ird[ 11:9])
'b000: row = `ALU_ROW_14; // ori
'b001: row = `ALU_ROW_04; // andi
'b010: row = `ALU_ROW_05; // subi
'b011: row = `ALU_ROW_02; // addi
'b100: row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13; // static bit
'b101: row = `ALU_ROW_13; // eori
'b110: row = `ALU_ROW_06; // cmpi
default: row = 0;
endcase
end
// MOVE
// move.b originally also rows 5 & 15. Only because IRD bit 14 is not decoded.
// It's the same for move the operations performed by MOVE.B
'h1,'h2,'h3: row = `ALU_ROW_02;
'h5:
if( size11)
row = `ALU_ROW_15; // As originally and easier to decode
else
row = ird[8] ? `ALU_ROW_05 : `ALU_ROW_02; // addq/subq
'h6: row = 0; //bcc/bra/bsr
'h7: row = `ALU_ROW_02; // moveq
'h8:
if( size11) // div
row = `ALU_ROW_01;
else if( ird[8] & eaRdir) // sbcd
row = `ALU_ROW_09;
else
row = `ALU_ROW_14; // or
'h9:
if( ird[8] & ~size11 & eaRdir)
row = `ALU_ROW_10; // subx
else
row = `ALU_ROW_05; // sub/suba
'hb:
if( ird[8] & ~size11 & ~eaAdir)
row = `ALU_ROW_13; // eor
else
row = `ALU_ROW_06; // cmp/cmpa/cmpm
'hc:
if( size11)
row = `ALU_ROW_07; // mul
else if( ird[8] & eaRdir) // abcd
row = `ALU_ROW_03;
else
row = `ALU_ROW_04; // and
'hd:
if( ird[8] & ~size11 & eaRdir)
row = `ALU_ROW_12; // addx
else
row = `ALU_ROW_02; // add/adda
'he:
begin
reg [1:0] stype;
if( size11) // memory shift/rotate
stype = ird[ 10:9];
else // register shift/rotate
stype = ird[ 4:3];
case( {stype, ird[8]})
0: row = `ALU_ROW_02; // ASR
1: row = `ALU_ROW_03; // ASL
2: row = `ALU_ROW_05; // LSR
3: row = `ALU_ROW_04; // LSL
4: row = `ALU_ROW_08; // ROXR
5: row = `ALU_ROW_11; // ROXL
6: row = `ALU_ROW_10; // ROR
7: row = `ALU_ROW_09; // ROL
endcase
end
default: row = 0;
endcase
end
// Decode opcodes that don't affect flags
// ADDA/SUBA ADDQ/SUBQ MOVEA
assign noCcrEn =
// ADDA/SUBA
( ird[15] & ~ird[13] & ird[12] & size11) |
// ADDQ/SUBQ to An
( (ird[15:12] == 4'h5) & eaAdir) |
// MOVEA
( (~ird[15] & ~ird[14] & ird[13]) & ird[8:6] == 3'b001);
endmodule
// Row/col CCR update table
module ccrTable(
input [2:0] col, input [15:0] row, input finish,
output logic [MASK_NBITS-1:0] ccrMask);
localparam
KNZ00 = 5'b01111, // ok coz operators clear them
KKZKK = 5'b00100,
KNZKK = 5'b01100,
KNZ10 = 5'b01111, // Used by OP_EXT on divison overflow
KNZ0C = 5'b01111, // Used by DIV. V should be 0, but it is ok:
// DIVU: ends with quotient - 0, so V & C always clear.
// DIVS: ends with 1i (AND), again, V & C always clear.
KNZVC = 5'b01111,
XNKVC = 5'b11011, // Used by BCD instructions. Don't modify Z at all at the binary operation. Only at the BCD correction cycle
CUPDALL = 5'b11111,
CUNUSED = 5'bxxxxx;
logic [MASK_NBITS-1:0] ccrMask1;
always_comb begin
unique case( col)
1: ccrMask = ccrMask1;
2,3:
unique case( 1'b1)
row[1]: ccrMask = KNZ0C; // DIV, used as 3n in col3
row[3], // ABCD
row[9]: // SBCD/NBCD
ccrMask = (col == 2) ? XNKVC : CUPDALL;
row[2],
row[5],
row[10], // SUBX/NEGX
row[12]: ccrMask = CUPDALL; // ADDX
row[6], // CMP
row[7], // MUL
row[11]: ccrMask = KNZVC; // NOT
row[4],
row[8], // Not used in col 3
row[13],
row[14]: ccrMask = KNZ00;
row[15]: ccrMask = 5'b0; // TAS/Scc, not used in col 3
// default: ccrMask = CUNUSED;
endcase
4:
unique case( row)
// 1: DIV, only n (4n & 6n)
// 14: BCLR 4n
// 6,12,13,15 // not used
`ALU_ROW_02,
`ALU_ROW_03, // ASL (originally ANZVA)
`ALU_ROW_04,
`ALU_ROW_05: ccrMask = CUPDALL; // Shifts (originally ANZ0A)
`ALU_ROW_07: ccrMask = KNZ00; // MUL (originally KNZ0A)
`ALU_ROW_09,
`ALU_ROW_10: ccrMask = KNZ00; // RO[lr] (originally KNZ0A)
`ALU_ROW_08, // ROXR (originally ANZ0A)
`ALU_ROW_11: ccrMask = CUPDALL; // ROXL (originally ANZ0A)
default: ccrMask = CUNUSED;
endcase
5: ccrMask = row[1] ? KNZ10 : 5'b0;
default: ccrMask = CUNUSED;
endcase
end
// Column 1 (AND)
always_comb begin
if( finish)
ccrMask1 = row[7] ? KNZ00 : KNZKK;
else
ccrMask1 = row[13] | row[14] ? KKZKK : KNZ00;
end
endmodule

1024
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/fx68k/microrom.mem
View File

File diff suppressed because it is too large Load Diff

336
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/fx68k/nanorom.mem
View File

@@ -1,336 +0,0 @@
00000000000000000000000000000000000000000000000010000000000000000000
00000000000000000000000000000000000000000000000010000000000000000000
00000000000000000000000000000000000000000000000010000000000000000000
00000000000000000000000000001000000110011100000000000000101001000001
00100001000000011000010001001000000110100000000001000000011001001001
00000001100000000010100000001000000110000000001001000000001001001001
00100000000000011000010001000000000101000000000010000000100001010000
11000001000000000000000000001000000100010000000001000000000001010001
00100001000000011000010000000000000000000000000101000000000000010000
01000001011000000000100000000110010001000000001100000000110100011000
01000001011000000000100000000110010001000000001100000001100100011000
00100001000000011000010000000000000100000000000001000000000001010000
10100100001000011000001000010000101001110000000001000100110010100001
01000000000000000000000010000000010100000000001000110001000000000000
00100001000000011000000000110010100100011111010001100000000001000000
00100010000000011000000000000000100010000100000000010100000100000011
00000001011000000000000001000110000000000000000010000000000100000000
00000000000000000000000000001000000100000000000001000000000001010001
00000001100000000010100000001000000110000000001001010000001001001001
00101000000000001000010000000000000000000000000010000000000000000000
01100010000000011000010010000000010100000000001000110001000000000000
00000000000000000000000010010010100000000000000100110010000000000000
00100000000000011000010001001000000110000000001001010000001001001001
00000000000000000000001000000000100100000000000000110010000001011000
00010010000000000100100000001000000100000000000010000000000001010001
00100010000000011100000000000000000001100000000010001000100000000000
00010010000000000100000000000000010001100000000010000000000000000000
00000000000000000000000000011001100110100000010001000000011011010001
10100010110000000000000000000000100000010000010010000100000100000000
10000000000000000000000000001000000100010000000001000000000001000001
00100000000000011001000000011010000110000000001001000000001001001001
00010011000000000000101000010000001001000000010101000000100000110000
00000001000000000001010000000000000000000000000101100000000000010000
00100010000000011000001000001000100110000000000001000000000001010001
00000001000000000010100001010000001001000000010110000000100000110000
01000001000000000000000000000000000001101010001100000000110000000000
00110100000000000100000100000000000000000000000010000000000000000000
00000000000100100000100000000000010000000000000000000001000000011000
01110101000000000100100000100010000001100000000000000000110100001010
00100010000000011010000100000000100010000100000000010100000100000011
11000001000000000000000000001000000100010000000001000000000001010001
01010011000000000100100000100010000001100000000000000000110100001010
11000001000000000000000000001001100110110000000001000000011011000001
01001001110000000000001000001000001000000000000101000000000000100001
00000000000000000000100000100010010000000000000000110001000100000010
00010000110000000001010000000000000000011100000010000000000000011000
01010001110000000001000000011010100100000000000001000000000001000001
00000000000000000000000001000000000100000000001100010000000001010000
00001000000000011001001000001000000110100000000001000100000011010001
01010001110000000001010000001000001000000000000101000000000000110001
10100010110100100100000001000000000001110000000010000000110000010000
00000000000100000000000000000010100001001010000101100000100000010000
00010000110000000001000000000000100000000000010010000100000100000000
10000000000000000000000000001000000100010000000001000000000001000001
00000001000000000000000001000000001001000000000101000000100000100000
00010010000000000000100000001010101000000000000101000000000000110001
10100000000100111000000000100001100010111010000101100000011010010010
00100000000000011000000000110010100110000000010000100000001101000010
00010010000000001100000000000000000000000000000010000000000000000000
11000001000000000000001000011101100100010000000001000000000001000001
00010100000000000100000100000000000000000000000010000000000000000000
10100010110000000100001000000000100000010000010010000100000010000000
00100000000100111000000000000000100000010010000101000100000100010010
00100010000000011000000000000000100010000100000000010100000100000011
00100010100000011001010000010000100100000000001110000100001000000000
00000000000100000000000000000010100000001010000101000000000000010000
00100010100000011001000000010010100100000000001110000100001000000000
00000001000000000000010000000000100000000000010101000100000010010000
00000000000100100000000000100010000000000100000000110001000100011010
00100000000000011000000000010000100110000000011000100000001001000000
00000000000100100000100000100010010000000000000000110001000100011010
00000000011000000000000000000110000000000000001110000000110100111000
00011000000000011001001000001000000100000000000001000000000001010001
00100010000000011100000000000000000001100000000010001000100000000000
00110000100000001000000100000000100000000000000010000100000100000000
00000000000100000000000000000010100001000000000101100000100000010000
10100010110000000100001000010001100000010000000010000000000000000000
01000001000000000000000000000000000000000000000101000000000000010000
10000000000000000000000000001000000100010000000001000000000001000001
00000000000000000000000000001000001000000000000101000000000000110001
00001000110000000000001000000000000000000000000010000000000000000000
00010010000000001100000000000000000000000000000010000000000000000000
00010000000000001010000100000000110001000000000010000100011000000000
01010001000000011000001000000000000001100000000000000000110000000000
00001100000000011000001000100001000010100000000101110000000000000011
01000000000000000000000010000000010100000000001000110000000001000000
11000001000000000000000000001000001000010000000101000000000000100001
00000000000000000000000000001000000100011100000001100000000001000001
00000000000000000000000000000000000000000000000101100000000000000000
00000000000100000000000000000000100000000000000101000100000100010000
11101011000000000000000000000000000000010000000010000000000000000000
01100001000000011001000000011010100100000000000001000000000001000001
01100010000000011000010010000000010100000000001000110000000001000000
00000000000000000000000010010010100000000000010100110000000100000000
01000001000000000000010000011001101000000000000101000100001000110001
00100000000100111100000000000000000010000010000100100010001000010000
00010010000000000000000000000010110100000000001110000000000000011000
00000000000000000000001000010000100100000000011100110010000001011000
00000000000100000000000000010000111000000000010101000100011000110000
00000000011000000010100000000110000100000000001101110000000101000000
00000000000000000000000000000000000000000000000010000000000000000000
00000001000000000000000000000000010101001010001101000000100001010000
00000001000000000000010000000000100000000000000101000100001000010000
01110101000000010000001000000000000001100000000000000000110000000000
01000001000000000000000010000000010100001010001000110001000000000000
00100010000000011000000000011010101010000000010101000000001100110001
00100001000000011000010001010000000100000000010000010000000001010000
01000001000000000000010000000000100000000110000101000000000000010000
01000001000000000000000010000000010100001010001000110001000000000000
00100000000000011000010001010001000000000000011010000000000010001000
00000001000000000000000001010000000100000000010001110000000001000000
00010010000000001000000000011010101000000000000101000000000000110001
00000000000000000000000000001000001000000000000101000000000000110001
00010010000000000001100000000010000000000000000101100000000000000000
00010010000000000001000000000010000100000000000101100000000000000000
00100010000000011100000000001000001000000000000101000000000000100001
00000001000000000001010000000000001010100000000110000000011000101000
00000001100000000000100000000000000000000000000101000000000000010000
00010010000000000000101000001001000100000000001001000000000011010001
11110101001000000100000000000000000000010000000010000000000000000000
00000000000000000000010000001001101000000000000101000010000010110001
00000000000000000000010000000000100000000110000101100000000000000000
00100010100000001001100000000010000010000100001000000000001000001000
00100010100000001001000000000010000110000100001000000000001000001000
00010010000000001000010000000000000000000000001110000000000000011000
00110100000100101100000000000000000001100000000001100000110000010000
01110101000000001000000100000000111000000000010010000100000100000000
01000000000000000000010000010000100110000000011100100000000001011000
11010011000000000000101000001001000100010000001001000000000011010001
11110101001000000000000000000000100000010000000010000100000100000000
01110101000000000100000000000000010000000000010010001000000001000000
01110101000000000000000000000000110000000000010010001100000101000000
01110101000000000000000000000000110000000000010010001100011001000000
01110000000000011100000000000000000001100000001101000000110000000000
00010000000000001000000000000010100000000000000010000000000000000000
00010010000000000100000100000000010001000000000010000000000000000000
01000000000000000000010000010000100110000000011100100010001001011000
00100000000000011000010000000000000100000000000000100000000001000000
00000001000000000000000000000000001000000000000101000000000000110000
00100001000000011100000001011001000110000000011000000000001011001001
01100001000000011000000000010010100110000000011100100000001101011000
01100001000000011000010000010010000010000000010101000000001100010000
00000000000000000000000100000000010010100000001100110001011000011000
01100001000000011000000000010000100110000000011000100000001001000000
00000000000000000000000000001000000100011100000001100000000001000001
00010010000000000000000000010010110110000000001110000010001000011000
01000001000000000000100000010010010000000000010000110001000100011000
00010010000000000000010000010000110110000000001110000010001000011000
01000001000000000000000010000000010100001010001000110000000001000000
01000001000000000000010000001000101000000110000101000000000000110001
00000001000000000000010000000000100000000000000101000100001000010000
00101000000000001000010000000000000000000000000010000000000000000000
00100010000000011000000000000000100000000000000010000100011000000000
00100010001000011010000000000000100000000000000010000100000100000000
11010011001000000100000000010000011000010000000010000000000000000000
00010010000000000100000000000000010000000000010010001000000001000000
00001000000000011000001000000000000000000000000101110000000000000011
00100010110000000000010000001000001000000000000101000000000000110001
00100010000000011000000000000000100010100000000010000000000000000000
00100000000000011000000000110001100100011111011001100000000011000010
00100000000000011000000000001000100110000000001001010000001001000001
01000001000000000000000000010000000100000000011100100000000001011000
00000000100000000010100000000000000001000000000101000000100000010000
00000001000000000000000000011001000100000000011001000000000011000001
00000000011000000010100001000110000101000000000000010000100101010000
00100001000000011100000001011001000100000000011001000000000011000001
01000000000000000000000000000000000101001010001101100000100001000000
00000000000100000000000000000000100001001010000101100100100100010000
00000000011000000000000000000010110110000000001100000000001101011000
01000001000000000000000000000001111001100000001010000000110010100000
00110010000000011000000000010010100010000000001110000010001000011000
11000001000000000000000000011001100110110000010001000000011011000001
00100000000000011010000000100001110000001100001010000000000010000010
00000000000000000000000000010000000100010101010001100000000001000000
01000000000000000000000000000000000010100000000010000000011000001000
00000001000000000000000000000000000001101010001101000000110000010000
10000000000000000000001000001101100100010000000001000000000001000001
01110101000000000000000000000000110000000000000010001100000101000000
11000001000000000000000000001000000100010000000001000000000001000001
00100010000000011000000000001001101000000010000101000010000010110001
00100010000100011000000000010010100000000000000101000000000000010000
11100101000000011100000000001001000100010000001001000000000011010001
00100100000100111000000000000000100000000000010101100100000100010000
00100010000100011000000000011010100100000000000000000000000001011001
00100000000000001000001000000000100000000000000010000100000010000000
00100010000000011100001000001000100100000000000001000100001001010001
00010010000000000100000100000000010001000000000010000000000000000000
10000000000000000000001000011101000100010000000001000000000001000001
00011000000000011000001000000000100010000000000010000000000000000000
01000000000000000000000000000000000100000000000001000000000001010000
01000000000000000000010000010000100110000000011100100000011001001000
00000000001000000010001000010001010000000000000010001000000000100000
11100101000000011100000000001000001000010000000101000000000000110001
01000001000000000000001000010001100000000000000010000000000000000000
00110100000000000000000000000000110000000000000010001100000101000000
10000000000000000000001000001000100100010000010001000100000011000001
01110101000000000100001000000001110000000000010010001000000001000000
10000000000000000000001000001000100100010000000001000100000011000001
00110100000000000000000000000000110000000000010010001100000101000000
00110100000000000000000000000000110000000000010010001100011001000000
01000000000000000000000000010000000110100000011100100000011001001000
00000000000100000000000000010000111000000000010101000100000100110010
00000000000100000000000000100010100001100000000001000000110000011000
01000000000000000000000000010010000110000000010000100000001101001000
00000000000000000000000000001000000110000000001001000000001001001001
01000000000000000000010000000001100000000000000101000010000010010000
01000000000000000000000000001000000110000000001001010000001001000001
00000001000000000000000000000000000001101010001101000000110000000000
11100101000000011000000000010000111001110000010010000100110100100000
00000000000000000000000000011010101010000000000101000010001000110001
11000001000000000000001000001101100100010000000001000000000001000001
00000000000000000000000100000000010000000000000001100001000000000000
00000000000000000000000000001001100100000000001001000000000011010001
11000001000000000000010000010001100000010000010010000000011010000000
00000000000000000000000000000000000000010110000010000000000000000000
00000000000000000000000000000000000000001100000000000001000000000000
00100010000000011000000000000000100010100000000010000000000000000000
00001000000000011000001000000000000000000000000101110000000000000011
10000000000000000000000000000000000000010000000010000000000000000000
00000000000000000000010000000000100010000000000010000010001000000000
00101000000000001000001000000000000000000000000010000000000000000000
01010011000000000000100000000010100001100000001100000000110000011000
00000001000010000000000001000000000000000000000101000000000000010000
00100010000000011000010000001101101000000000000101000000000000110001
00000000000000000000100000010010010000000000010000110001000100000000
01000000000000000000000000010000000100000000011100100000000001000000
00000000000000000000000100010010010000000000010000110001000100000000
01000000000000000000100000000000010000000000000001000000110000010000
01010011000000001000010000000000000001100000001100000000110000011000
01000001000000000000010000001001101000000000000101000000000000110001
00100100000100011001000000000000100000000000010101000100000100010000
01100010000000011000100000010010110010000000001100000000110000011000
00011000000000011000001000000000000000000000000101110000000000000011
00000000000000000000000000001000000100000000000001000000000001010001
00010010000000000100000100000000010001000000000010000000000000000000
00001010000000011000001000000000000000000000000101110000000000000011
00010010000000000000000000000001110100000010001110000010000010011000
01100010000000011000100000010010110010000000001100000001000000011000
01000000000000000000100000000010010000000000001100110001000100011000
00100010000100011000000001011010100100000000000001000000000001011001
00000001000000000000010000000001100001001010000101000000100000010000
00000000000000000000010000000000100101000110001110000000100001011000
00000000000000000000100000010010010000000000010000110001000100011000
01010011000000000000100000000001100001100010001100000010110010011000
01100011000000011000000000010010100100000000011101110000000001011000
00000000000100000001000000010000100100000000011101000100000101010000
00100010000100011000000001010010100100000000011100010000000001010000
00000001000000000000010000000000100000000001000101000100000010010000
00000001000000000000010000000001100000001111000101000000000000010000
00000000000000000000000000010010100000000110010101100000000100000000
00000111000000000000010000010000111000001000010110000100001000100000
01000000000000000000100000000001110000000000001001000000110010010000
01001011000000011000001000000000000001100000000000000000110000000000
00000000000000000000010000000000100010000000000101000000000000010000
10100100000000011100000000001000000100010000000001000000000001000001
00010000000000000000000000010000100100000010000010000000000000000000
00000000000000000000000000001000000100000010000000110010000001000001
01000000000000000000000000001001100100000000001001010000000011000001
00000000000000000000000000001001100100000000001001010000000011000001
00100000000000011000000000010010100010000000010101000000001100010000
00000000000100000000000000000000101000000000000101000100011000110000
00000000000100100000100000010010010000000000010000110001000100011000
01000000000000000000010000010001100000000000010101000010000010010000
00100001000000011100010100000000110010000000001110001000100000011000
00000000000000000000001000000000100000000110000101000000000000000000
00000110000000000000000000000000000000001000000010000000000000000000
01000000000000000000010000000000100100001010001100110010000001000000
01000000000000000000000000000000000100001010001100000000000001000000
01100001000000011000000000000000100001100010000000000000110000000000
01000001000000000000010000000000100000000110000101010000000000010000
00101000000000001000010000001000101010000000000101100000000000100001
10000110000000000000000000001000001000001000000101100000000000100001
00000000000000000000000000001000000100000000000001000000000001010001
00100010000100111000100000000000110010100000000001000000110000010000
00100100000100111100000000001000000100000000000001000000000001011001
00100011000000011000010100000000010000000000001110001000100000011000
00000000000000000000000000011001100110100000010001000000011011010001
00000000000000000000000000000000000000000000000010000000000000000000
00000000000100100000010001001000100100000000000001000000011001001001
00100100001000111100001000000000100010000000000101000000000000010000
01000001000000000000000000010001100000000010000010000000000000000000
00100010000000011010000000000000110100000000011110001100100100011000
11100101000000011100000100000000001000010000010101000000011010000000
00010000000000000000100000000000100001100010001100000000110000000000
00100010000100111000010001001000000100000000000000000000000001011001
00010000000000000010000000000000100100000010001110000000000000011000
11100011000000011100001000010101100000010000000101000000000000000000
00100000000000011000000000110010100100011111010001100000000001000000
10000000000100000000000000001000100110110000000001000000000001011001
11000001000000000000000000001001000100010000001001000000000011010001
00100100000100111100000000000000000000000000000101100000000000010000
10000000000100100000000001001001000100010000001001000000000011001001
11000001000000000000000000000000000000010000000010000000000000000000
00110100001100100000000000000000100000000000000101100100000100010000
00000001000001000000000001000000000000000000000101000000000000010000
00000001000010000000010001000000100000000000000101000100000010010000
00100000000100111000000000010000101000010111010101000100000100110010
11100101000000011100000000000000000000010000000010000000000000000000
11100101000000011000000000000000100000010000010010000100000100000000
00000000000000000000000000001000001000000000000101000000000000110001
00000000000000000000000000000000000000000000000010000000000000000000
00000000000000000000000000000000000000000000000010000000000000000000
00000000000000000000000000000000000000000000000010000000000000000000
00000001000000000000000000001000001001100000000001000000110000110001
00000001000001000000000001001000000100000000000001010000000001011001
00100000000000001000001000000000100000000000000010000100000010000000
11000001000000000000010000001001001000010000000101000000000000110001
00000000000110000000000001000000100000000000000101000100000100010000
00000000000101000000000001000000100000000000000101000100000100010000
00000000000010100000000001010000000100000000000101000000000000010000
00000000000101000000000001001010000100000000000001010000000001011001
11100101001000011100000000000000010000010000010010001000000000100000
00100000000000001000000000001000001000000000000110000000000000110001
00100000000000011000000000000000100000000100011100000101000100011000
00100000000000011000000000010000110100000000011100000101000100011000
01100011100000011000000100010010000000000000000101110000000000000011
01100010000000011000010100000000010000000000001100000001000000011000
10000000000100100000000001001000000100010000000001000000000001011001
01100010000000011000010100000010010000000000001100110001000100011000
01100011000000011000010000010000000100000000011101110000000001011000
00000000000000000000010000000000100000000110000101000000000000010000
00000000000000000000000000000000000000011100001110000000000000011000
10100000000000001000010000001000101000000110000101000000000000100001
00100000000000011000000000110001100100001111011001100000000011000010
00000001000000000000010000000001100001001010000101000010100010010000
00100010001000111000010000010000000100000000011101000000000001010000
00100100000100111100000000000000000000000000000101000000000000010000
00100010000100011000010001010000000100000000011100010000000001010000
01000001000000000000000100010000011000000000000010000000000000000000
00000000000000000000010000000000100010000000000101000010001000010000
00100000000100111000000000000000100000000010000100100000000000010000
00100010000000011000010000001000001000000000000101000000000000110001
00000001000000000000010000000000100000000000000101000100000010010000
00000000000000000000000000000000000000000000000010000000000000000000
00000000000000000000001000000000100100000000000000110010000001011000
00000000011000000000000000000010110110000000001100000000001101011000

2195
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/fx68k/uaddrPla.sv
View File

File diff suppressed because it is too large Load Diff

674
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/LICENSE
View File

@@ -1,674 +0,0 @@
GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The GNU General Public License is a free, copyleft license for
software and other kinds of works.
The licenses for most software and other practical works are designed
to take away your freedom to share and change the works. By contrast,
the GNU General Public License is intended to guarantee your freedom to
share and change all versions of a program--to make sure it remains free
software for all its users. We, the Free Software Foundation, use the
GNU General Public License for most of our software; it applies also to
any other work released this way by its authors. You can apply it to
your programs, too.
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
them if you wish), that you receive source code or can get it if you
want it, that you can change the software or use pieces of it in new
free programs, and that you know you can do these things.
To protect your rights, we need to prevent others from denying you
these rights or asking you to surrender the rights. Therefore, you have
certain responsibilities if you distribute copies of the software, or if
you modify it: responsibilities to respect the freedom of others.
For example, if you distribute copies of such a program, whether
gratis or for a fee, you must pass on to the recipients the same
freedoms that you received. You must make sure that they, too, receive
or can get the source code. And you must show them these terms so they
know their rights.
Developers that use the GNU GPL protect your rights with two steps:
(1) assert copyright on the software, and (2) offer you this License
giving you legal permission to copy, distribute and/or modify it.
For the developers' and authors' protection, the GPL clearly explains
that there is no warranty for this free software. For both users' and
authors' sake, the GPL requires that modified versions be marked as
changed, so that their problems will not be attributed erroneously to
authors of previous versions.
Some devices are designed to deny users access to install or run
modified versions of the software inside them, although the manufacturer
can do so. This is fundamentally incompatible with the aim of
protecting users' freedom to change the software. The systematic
pattern of such abuse occurs in the area of products for individuals to
use, which is precisely where it is most unacceptable. Therefore, we
have designed this version of the GPL to prohibit the practice for those
products. If such problems arise substantially in other domains, we
stand ready to extend this provision to those domains in future versions
of the GPL, as needed to protect the freedom of users.
Finally, every program is threatened constantly by software patents.
States should not allow patents to restrict development and use of
software on general-purpose computers, but in those that do, we wish to
avoid the special danger that patents applied to a free program could
make it effectively proprietary. To prevent this, the GPL assures that
patents cannot be used to render the program non-free.
The precise terms and conditions for copying, distribution and
modification follow.
TERMS AND CONDITIONS
0. Definitions.
"This License" refers to version 3 of the GNU General Public License.
"Copyright" also means copyright-like laws that apply to other kinds of
works, such as semiconductor masks.
"The Program" refers to any copyrightable work licensed under this
License. Each licensee is addressed as "you". "Licensees" and
"recipients" may be individuals or organizations.
To "modify" a work means to copy from or adapt all or part of the work
in a fashion requiring copyright permission, other than the making of an
exact copy. The resulting work is called a "modified version" of the
earlier work or a work "based on" the earlier work.
A "covered work" means either the unmodified Program or a work based
on the Program.
To "propagate" a work means to do anything with it that, without
permission, would make you directly or secondarily liable for
infringement under applicable copyright law, except executing it on a
computer or modifying a private copy. Propagation includes copying,
distribution (with or without modification), making available to the
public, and in some countries other activities as well.
To "convey" a work means any kind of propagation that enables other
parties to make or receive copies. Mere interaction with a user through
a computer network, with no transfer of a copy, is not conveying.
An interactive user interface displays "Appropriate Legal Notices"
to the extent that it includes a convenient and prominently visible
feature that (1) displays an appropriate copyright notice, and (2)
tells the user that there is no warranty for the work (except to the
extent that warranties are provided), that licensees may convey the
work under this License, and how to view a copy of this License. If
the interface presents a list of user commands or options, such as a
menu, a prominent item in the list meets this criterion.
1. Source Code.
The "source code" for a work means the preferred form of the work
for making modifications to it. "Object code" means any non-source
form of a work.
A "Standard Interface" means an interface that either is an official
standard defined by a recognized standards body, or, in the case of
interfaces specified for a particular programming language, one that
is widely used among developers working in that language.
The "System Libraries" of an executable work include anything, other
than the work as a whole, that (a) is included in the normal form of
packaging a Major Component, but which is not part of that Major
Component, and (b) serves only to enable use of the work with that
Major Component, or to implement a Standard Interface for which an
implementation is available to the public in source code form. A
"Major Component", in this context, means a major essential component
(kernel, window system, and so on) of the specific operating system
(if any) on which the executable work runs, or a compiler used to
produce the work, or an object code interpreter used to run it.
The "Corresponding Source" for a work in object code form means all
the source code needed to generate, install, and (for an executable
work) run the object code and to modify the work, including scripts to
control those activities. However, it does not include the work's
System Libraries, or general-purpose tools or generally available free
programs which are used unmodified in performing those activities but
which are not part of the work. For example, Corresponding Source
includes interface definition files associated with source files for
the work, and the source code for shared libraries and dynamically
linked subprograms that the work is specifically designed to require,
such as by intimate data communication or control flow between those
subprograms and other parts of the work.
The Corresponding Source need not include anything that users
can regenerate automatically from other parts of the Corresponding
Source.
The Corresponding Source for a work in source code form is that
same work.
2. Basic Permissions.
All rights granted under this License are granted for the term of
copyright on the Program, and are irrevocable provided the stated
conditions are met. This License explicitly affirms your unlimited
permission to run the unmodified Program. The output from running a
covered work is covered by this License only if the output, given its
content, constitutes a covered work. This License acknowledges your
rights of fair use or other equivalent, as provided by copyright law.
You may make, run and propagate covered works that you do not
convey, without conditions so long as your license otherwise remains
in force. You may convey covered works to others for the sole purpose
of having them make modifications exclusively for you, or provide you
with facilities for running those works, provided that you comply with
the terms of this License in conveying all material for which you do
not control copyright. Those thus making or running the covered works
for you must do so exclusively on your behalf, under your direction
and control, on terms that prohibit them from making any copies of
your copyrighted material outside their relationship with you.
Conveying under any other circumstances is permitted solely under
the conditions stated below. Sublicensing is not allowed; section 10
makes it unnecessary.
3. Protecting Users' Legal Rights From Anti-Circumvention Law.
No covered work shall be deemed part of an effective technological
measure under any applicable law fulfilling obligations under article
11 of the WIPO copyright treaty adopted on 20 December 1996, or
similar laws prohibiting or restricting circumvention of such
measures.
When you convey a covered work, you waive any legal power to forbid
circumvention of technological measures to the extent such circumvention
is effected by exercising rights under this License with respect to
the covered work, and you disclaim any intention to limit operation or
modification of the work as a means of enforcing, against the work's
users, your or third parties' legal rights to forbid circumvention of
technological measures.
4. Conveying Verbatim Copies.
You may convey verbatim copies of the Program's source code as you
receive it, in any medium, provided that you conspicuously and
appropriately publish on each copy an appropriate copyright notice;
keep intact all notices stating that this License and any
non-permissive terms added in accord with section 7 apply to the code;
keep intact all notices of the absence of any warranty; and give all
recipients a copy of this License along with the Program.
You may charge any price or no price for each copy that you convey,
and you may offer support or warranty protection for a fee.
5. Conveying Modified Source Versions.
You may convey a work based on the Program, or the modifications to
produce it from the Program, in the form of source code under the
terms of section 4, provided that you also meet all of these conditions:
a) The work must carry prominent notices stating that you modified
it, and giving a relevant date.
b) The work must carry prominent notices stating that it is
released under this License and any conditions added under section
7. This requirement modifies the requirement in section 4 to
"keep intact all notices".
c) You must license the entire work, as a whole, under this
License to anyone who comes into possession of a copy. This
License will therefore apply, along with any applicable section 7
additional terms, to the whole of the work, and all its parts,
regardless of how they are packaged. This License gives no
permission to license the work in any other way, but it does not
invalidate such permission if you have separately received it.
d) If the work has interactive user interfaces, each must display
Appropriate Legal Notices; however, if the Program has interactive
interfaces that do not display Appropriate Legal Notices, your
work need not make them do so.
A compilation of a covered work with other separate and independent
works, which are not by their nature extensions of the covered work,
and which are not combined with it such as to form a larger program,
in or on a volume of a storage or distribution medium, is called an
"aggregate" if the compilation and its resulting copyright are not
used to limit the access or legal rights of the compilation's users
beyond what the individual works permit. Inclusion of a covered work
in an aggregate does not cause this License to apply to the other
parts of the aggregate.
6. Conveying Non-Source Forms.
You may convey a covered work in object code form under the terms
of sections 4 and 5, provided that you also convey the
machine-readable Corresponding Source under the terms of this License,
in one of these ways:
a) Convey the object code in, or embodied in, a physical product
(including a physical distribution medium), accompanied by the
Corresponding Source fixed on a durable physical medium
customarily used for software interchange.
b) Convey the object code in, or embodied in, a physical product
(including a physical distribution medium), accompanied by a
written offer, valid for at least three years and valid for as
long as you offer spare parts or customer support for that product
model, to give anyone who possesses the object code either (1) a
copy of the Corresponding Source for all the software in the
product that is covered by this License, on a durable physical
medium customarily used for software interchange, for a price no
more than your reasonable cost of physically performing this
conveying of source, or (2) access to copy the
Corresponding Source from a network server at no charge.
c) Convey individual copies of the object code with a copy of the
written offer to provide the Corresponding Source. This
alternative is allowed only occasionally and noncommercially, and
only if you received the object code with such an offer, in accord
with subsection 6b.
d) Convey the object code by offering access from a designated
place (gratis or for a charge), and offer equivalent access to the
Corresponding Source in the same way through the same place at no
further charge. You need not require recipients to copy the
Corresponding Source along with the object code. If the place to
copy the object code is a network server, the Corresponding Source
may be on a different server (operated by you or a third party)
that supports equivalent copying facilities, provided you maintain
clear directions next to the object code saying where to find the
Corresponding Source. Regardless of what server hosts the
Corresponding Source, you remain obligated to ensure that it is
available for as long as needed to satisfy these requirements.
e) Convey the object code using peer-to-peer transmission, provided
you inform other peers where the object code and Corresponding
Source of the work are being offered to the general public at no
charge under subsection 6d.
A separable portion of the object code, whose source code is excluded
from the Corresponding Source as a System Library, need not be
included in conveying the object code work.
A "User Product" is either (1) a "consumer product", which means any
tangible personal property which is normally used for personal, family,
or household purposes, or (2) anything designed or sold for incorporation
into a dwelling. In determining whether a product is a consumer product,
doubtful cases shall be resolved in favor of coverage. For a particular
product received by a particular user, "normally used" refers to a
typical or common use of that class of product, regardless of the status
of the particular user or of the way in which the particular user
actually uses, or expects or is expected to use, the product. A product
is a consumer product regardless of whether the product has substantial
commercial, industrial or non-consumer uses, unless such uses represent
the only significant mode of use of the product.
"Installation Information" for a User Product means any methods,
procedures, authorization keys, or other information required to install
and execute modified versions of a covered work in that User Product from
a modified version of its Corresponding Source. The information must
suffice to ensure that the continued functioning of the modified object
code is in no case prevented or interfered with solely because
modification has been made.
If you convey an object code work under this section in, or with, or
specifically for use in, a User Product, and the conveying occurs as
part of a transaction in which the right of possession and use of the
User Product is transferred to the recipient in perpetuity or for a
fixed term (regardless of how the transaction is characterized), the
Corresponding Source conveyed under this section must be accompanied
by the Installation Information. But this requirement does not apply
if neither you nor any third party retains the ability to install
modified object code on the User Product (for example, the work has
been installed in ROM).
The requirement to provide Installation Information does not include a
requirement to continue to provide support service, warranty, or updates
for a work that has been modified or installed by the recipient, or for
the User Product in which it has been modified or installed. Access to a
network may be denied when the modification itself materially and
adversely affects the operation of the network or violates the rules and
protocols for communication across the network.
Corresponding Source conveyed, and Installation Information provided,
in accord with this section must be in a format that is publicly
documented (and with an implementation available to the public in
source code form), and must require no special password or key for
unpacking, reading or copying.
7. Additional Terms.
"Additional permissions" are terms that supplement the terms of this
License by making exceptions from one or more of its conditions.
Additional permissions that are applicable to the entire Program shall
be treated as though they were included in this License, to the extent
that they are valid under applicable law. If additional permissions
apply only to part of the Program, that part may be used separately
under those permissions, but the entire Program remains governed by
this License without regard to the additional permissions.
When you convey a copy of a covered work, you may at your option
remove any additional permissions from that copy, or from any part of
it. (Additional permissions may be written to require their own
removal in certain cases when you modify the work.) You may place
additional permissions on material, added by you to a covered work,
for which you have or can give appropriate copyright permission.
Notwithstanding any other provision of this License, for material you
add to a covered work, you may (if authorized by the copyright holders of
that material) supplement the terms of this License with terms:
a) Disclaiming warranty or limiting liability differently from the
terms of sections 15 and 16 of this License; or
b) Requiring preservation of specified reasonable legal notices or
author attributions in that material or in the Appropriate Legal
Notices displayed by works containing it; or
c) Prohibiting misrepresentation of the origin of that material, or
requiring that modified versions of such material be marked in
reasonable ways as different from the original version; or
d) Limiting the use for publicity purposes of names of licensors or
authors of the material; or
e) Declining to grant rights under trademark law for use of some
trade names, trademarks, or service marks; or
f) Requiring indemnification of licensors and authors of that
material by anyone who conveys the material (or modified versions of
it) with contractual assumptions of liability to the recipient, for
any liability that these contractual assumptions directly impose on
those licensors and authors.
All other non-permissive additional terms are considered "further
restrictions" within the meaning of section 10. If the Program as you
received it, or any part of it, contains a notice stating that it is
governed by this License along with a term that is a further
restriction, you may remove that term. If a license document contains
a further restriction but permits relicensing or conveying under this
License, you may add to a covered work material governed by the terms
of that license document, provided that the further restriction does
not survive such relicensing or conveying.
If you add terms to a covered work in accord with this section, you
must place, in the relevant source files, a statement of the
additional terms that apply to those files, or a notice indicating
where to find the applicable terms.
Additional terms, permissive or non-permissive, may be stated in the
form of a separately written license, or stated as exceptions;
the above requirements apply either way.
8. Termination.
You may not propagate or modify a covered work except as expressly
provided under this License. Any attempt otherwise to propagate or
modify it is void, and will automatically terminate your rights under
this License (including any patent licenses granted under the third
paragraph of section 11).
However, if you cease all violation of this License, then your
license from a particular copyright holder is reinstated (a)
provisionally, unless and until the copyright holder explicitly and
finally terminates your license, and (b) permanently, if the copyright
holder fails to notify you of the violation by some reasonable means
prior to 60 days after the cessation.
Moreover, your license from a particular copyright holder is
reinstated permanently if the copyright holder notifies you of the
violation by some reasonable means, this is the first time you have
received notice of violation of this License (for any work) from that
copyright holder, and you cure the violation prior to 30 days after
your receipt of the notice.
Termination of your rights under this section does not terminate the
licenses of parties who have received copies or rights from you under
this License. If your rights have been terminated and not permanently
reinstated, you do not qualify to receive new licenses for the same
material under section 10.
9. Acceptance Not Required for Having Copies.
You are not required to accept this License in order to receive or
run a copy of the Program. Ancillary propagation of a covered work
occurring solely as a consequence of using peer-to-peer transmission
to receive a copy likewise does not require acceptance. However,
nothing other than this License grants you permission to propagate or
modify any covered work. These actions infringe copyright if you do
not accept this License. Therefore, by modifying or propagating a
covered work, you indicate your acceptance of this License to do so.
10. Automatic Licensing of Downstream Recipients.
Each time you convey a covered work, the recipient automatically
receives a license from the original licensors, to run, modify and
propagate that work, subject to this License. You are not responsible
for enforcing compliance by third parties with this License.
An "entity transaction" is a transaction transferring control of an
organization, or substantially all assets of one, or subdividing an
organization, or merging organizations. If propagation of a covered
work results from an entity transaction, each party to that
transaction who receives a copy of the work also receives whatever
licenses to the work the party's predecessor in interest had or could
give under the previous paragraph, plus a right to possession of the
Corresponding Source of the work from the predecessor in interest, if
the predecessor has it or can get it with reasonable efforts.
You may not impose any further restrictions on the exercise of the
rights granted or affirmed under this License. For example, you may
not impose a license fee, royalty, or other charge for exercise of
rights granted under this License, and you may not initiate litigation
(including a cross-claim or counterclaim in a lawsuit) alleging that
any patent claim is infringed by making, using, selling, offering for
sale, or importing the Program or any portion of it.
11. Patents.
A "contributor" is a copyright holder who authorizes use under this
License of the Program or a work on which the Program is based. The
work thus licensed is called the contributor's "contributor version".
A contributor's "essential patent claims" are all patent claims
owned or controlled by the contributor, whether already acquired or
hereafter acquired, that would be infringed by some manner, permitted
by this License, of making, using, or selling its contributor version,
but do not include claims that would be infringed only as a
consequence of further modification of the contributor version. For
purposes of this definition, "control" includes the right to grant
patent sublicenses in a manner consistent with the requirements of
this License.
Each contributor grants you a non-exclusive, worldwide, royalty-free
patent license under the contributor's essential patent claims, to
make, use, sell, offer for sale, import and otherwise run, modify and
propagate the contents of its contributor version.
In the following three paragraphs, a "patent license" is any express
agreement or commitment, however denominated, not to enforce a patent
(such as an express permission to practice a patent or covenant not to
sue for patent infringement). To "grant" such a patent license to a
party means to make such an agreement or commitment not to enforce a
patent against the party.
If you convey a covered work, knowingly relying on a patent license,
and the Corresponding Source of the work is not available for anyone
to copy, free of charge and under the terms of this License, through a
publicly available network server or other readily accessible means,
then you must either (1) cause the Corresponding Source to be so
available, or (2) arrange to deprive yourself of the benefit of the
patent license for this particular work, or (3) arrange, in a manner
consistent with the requirements of this License, to extend the patent
license to downstream recipients. "Knowingly relying" means you have
actual knowledge that, but for the patent license, your conveying the
covered work in a country, or your recipient's use of the covered work
in a country, would infringe one or more identifiable patents in that
country that you have reason to believe are valid.
If, pursuant to or in connection with a single transaction or
arrangement, you convey, or propagate by procuring conveyance of, a
covered work, and grant a patent license to some of the parties
receiving the covered work authorizing them to use, propagate, modify
or convey a specific copy of the covered work, then the patent license
you grant is automatically extended to all recipients of the covered
work and works based on it.
A patent license is "discriminatory" if it does not include within
the scope of its coverage, prohibits the exercise of, or is
conditioned on the non-exercise of one or more of the rights that are
specifically granted under this License. You may not convey a covered
work if you are a party to an arrangement with a third party that is
in the business of distributing software, under which you make payment
to the third party based on the extent of your activity of conveying
the work, and under which the third party grants, to any of the
parties who would receive the covered work from you, a discriminatory
patent license (a) in connection with copies of the covered work
conveyed by you (or copies made from those copies), or (b) primarily
for and in connection with specific products or compilations that
contain the covered work, unless you entered into that arrangement,
or that patent license was granted, prior to 28 March 2007.
Nothing in this License shall be construed as excluding or limiting
any implied license or other defenses to infringement that may
otherwise be available to you under applicable patent law.
12. No Surrender of Others' Freedom.
If conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot convey a
covered work so as to satisfy simultaneously your obligations under this
License and any other pertinent obligations, then as a consequence you may
not convey it at all. For example, if you agree to terms that obligate you
to collect a royalty for further conveying from those to whom you convey
the Program, the only way you could satisfy both those terms and this
License would be to refrain entirely from conveying the Program.
13. Use with the GNU Affero General Public License.
Notwithstanding any other provision of this License, you have
permission to link or combine any covered work with a work licensed
under version 3 of the GNU Affero General Public License into a single
combined work, and to convey the resulting work. The terms of this
License will continue to apply to the part which is the covered work,
but the special requirements of the GNU Affero General Public License,
section 13, concerning interaction through a network will apply to the
combination as such.
14. Revised Versions of this License.
The Free Software Foundation may publish revised and/or new versions of
the GNU General Public License from time to time. Such new versions will
be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
Each version is given a distinguishing version number. If the
Program specifies that a certain numbered version of the GNU General
Public License "or any later version" applies to it, you have the
option of following the terms and conditions either of that numbered
version or of any later version published by the Free Software
Foundation. If the Program does not specify a version number of the
GNU General Public License, you may choose any version ever published
by the Free Software Foundation.
If the Program specifies that a proxy can decide which future
versions of the GNU General Public License can be used, that proxy's
public statement of acceptance of a version permanently authorizes you
to choose that version for the Program.
Later license versions may give you additional or different
permissions. However, no additional obligations are imposed on any
author or copyright holder as a result of your choosing to follow a
later version.
15. Disclaimer of Warranty.
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
16. Limitation of Liability.
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES.
17. Interpretation of Sections 15 and 16.
If the disclaimer of warranty and limitation of liability provided
above cannot be given local legal effect according to their terms,
reviewing courts shall apply local law that most closely approximates
an absolute waiver of all civil liability in connection with the
Program, unless a warranty or assumption of liability accompanies a
copy of the Program in return for a fee.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
state the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
Also add information on how to contact you by electronic and paper mail.
If the program does terminal interaction, make it output a short
notice like this when it starts in an interactive mode:
<program> Copyright (C) <year> <name of author>
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, your program's commands
might be different; for a GUI interface, you would use an "about box".
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
<https://www.gnu.org/licenses/>.
The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<https://www.gnu.org/licenses/why-not-lgpl.html>.

131
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/README.md
View File

@@ -1,131 +0,0 @@
# JTOPL FPGA Clone of Yamaha OPL hardware by Jose Tejada (@topapate)
You can show your appreciation through
* [Patreon](https://patreon.com/topapate), by supporting releases
* [Paypal](https://paypal.me/topapate), with a donation
JTOPL is an FM sound source written in Verilog, fully compatible with YM3526. This project will most likely grow to include other Yamaha chips of the OPL family.
## Features
The implementation tries to be as close to original hardware as possible. Low usage of FPGA resources has also been a design goal.
*Accuracy*
* Follows Y8950 block diagram by Yamaha
* Barrel shift registers used for configuration values
* Takes note of all known reverse engineered information, particularly die shots
* Accurate at sample level, and at internal cycle clock where reasonable
* Original architecture kept as much as possible
Some reference works used:
* [NukeYT's Nuked-OPLL](https://github.com/nukeykt/Nuked-OPLL)
* [Research by Andete](https://github.com/andete/ym2413)
* [Mitsutaka Okazaki's emu2413](https://github.com/digital-sound-antiques/emu2413)
*Modern Design for FPGA*
* Fully synchronous
* Clock enable input for easy integration
* Avoids bulky multiplexers
Directories:
* hdl -> all relevant RTL files, written in verilog
* ver -> test benches
* ver/verilator -> test bench that can play vgm files
## Usage
Although many files are shared, each chip has its own top level file to instantiate. There are YAML files for each one that detail the list of files used for each file. These files can be easily converted to whatever format you need, like .qip.
Not all the chips of OPL series are implemented yet, so take the following table as a plan which I am working on.
Chip | Top Level Cell | YAML file | Type | Patches | Implemented | Usage
--------|----------------|-------------|-------------|---------|--------------|------------------
YM3526 | jtopl.v | jt26.yaml | OPL | | Yes | Bubble Bobble
YM3812 | jtopl2.v | jtopl2.yaml | OPL2 | | Yes | Robocop
Y8950 | jt8950.v | jt8950.yaml | OPL+ADPCM | | Not yet | MSX-Audio
YM2413 | jt2413.v | jt2413.yaml | OPL-L | Yes | WIP | Pang!
YM2423 | - | - | OPL-LX | Yes | No plans | Atari ST FM cart
YMF281 | - | - | OPL-LLP | Yes | No plans | Pachinko
YMF262 | jt262.v | jt262.yaml | OPL3 | | Not yet |
### Chip differences
Chip | Type | EG bits | Features
---------|--------------|---------|-------------------------------
YM3526 | OPL | 9? | Basic OPL
YM2413 | OPLL | 7 | Removes depth options for vibrato/tremolo
Y8950 | OPL+ADPCM | 9? | Adds ADPCM
YM3812 | OPL2 | 9? | Adds waveform select. Four waveforms
YMF262 | OPL3 | 9 | No CSM. More operator modes, more channels
## Simulation
There are several simulation test benches in the **ver** folder. The most important one is in the **ver/verilator** folder. The simulation script is called with the shell script **go** in the same folder. The script will compile the file **test.cpp** together with other files and the design and will simulate the tune specificied with the -f command. It can read **vgm** tunes and generate .wav output of them.
### Tested Features
Each feature is tested with a given .jtt file in the **ver/verilator/tests** folder.
Feature | JTT File | Status (commit) | Remarks
---------------|-----------|-----------------|--------
TL | TL | |
EG rates | rates | |
fnum | fnum_abs | Passed 4a2c3cc | Checks absolute value of a note
FB | fb | Passed 6e6178d |
connection | mod | |
EG type | perc | |
All slots | slots | | no modulation
All slots | slots_mod | | Modulate some channels
KSL | ksl1/2/3 | Passed 4a2c3cc | See note*
AM | am | Passed fc6ad19 |
Vibratto | vib | Passed 44a540f |
CSM | | | Not implemented
OPL2 waves | tone_w? | Passed | Implemented
Keyboard split| | Untested b4345fa| Not implemented
Note* values don't match the app notes but implementation follows reverse engineering of OPLL and OPL3. Measuring from first note of an octave to last note of the next seems to fit better the table in the notes.
## Rhythm Instruments
They are bass drum, snare drum, tom-tom, high-hat, cymbals and top cymbals. Channels 6,7 and 8 are used for these instruments.
For patch-based OPL chips, there were specific values for each operator register of these instruments. However, for non-patched synthesizers, the user still had to enter register values. So it looks like the benefit from the rhythm feature was:
* Ability to enter more than one key-on command at once
* Noisy phase for three instruments
* Forced no modulation on 5 five instruments
Short name | Instrument | Slot | Phase | EG | Modulation |
-----------|------------|---------|---------|------|------------|
BD | Bass drum | 13 & 16 | | Drum | Normal |
HH | High hat | 14 | Special | Drum | No |
TOM | Tom tom | 15 | | Drum | No |
SD | Snare drum | 17 | Special | Drum | No |
TOP-CYM | Top cymbal | 18 | Special | Drum | No |
## Related Projects
Other sound chips from the same author (Verilog RTL)
Chip | Repository
-----------------------|------------
YM2203, YM2612, YM2610 | [JT12](https://github.com/jotego/jt12)
YM2151 | [JT51](https://github.com/jotego/jt51)
YM3526 | [JTOPL](https://github.com/jotego/jtopl)
YM2149 | [JT49](https://github.com/jotego/jt49)
sn76489an | [JT89](https://github.com/jotego/jt89)
OKI 6295 | [JT6295](https://github.com/jotego/jt6295)
OKI MSM5205 | [JT5205](https://github.com/jotego/jt5205)
Cycle accurate FM chips from Nuked (software emulation)
Chip | Repository
--------------------|------------------------
OPLL | [Nuked-OPLL](https://github.com/nukeykt/Nuked-OPLL)
OPL3 | [Nuked-OPL3](https://github.com/nukeykt/Nuked-OPL3)
YM3438 | [Nuked-OPN2](https://github.com/nukeykt/Nuked-OPN2)

212
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jt2413.v
View File

@@ -1,212 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 10-6-2020
*/
module jt2413(
input rst, // rst should be at least 6 clk&cen cycles long
input clk, // CPU clock
input cen, // optional clock enable, it not needed leave as 1'b1
input [ 7:0] din,
input addr,
input cs_n,
input wr_n,
// combined output
output signed [15:0] snd,
output sample
);
parameter OPL_TYPE=11;
wire cenop, write, zero;
wire [ 1:0] group;
wire [17:0] slot;
wire [ 3:0] trem;
// Phase
wire [ 8:0] fnum_I;
wire [ 2:0] block_I;
wire [ 3:0] mul_II;
wire [ 9:0] phase_IV;
wire pg_rst_II;
wire viben_I;
wire [ 2:0] vib_cnt;
// envelope configuration
wire en_sus_I; // enable sustain
wire [ 3:0] keycode_II;
wire [ 3:0] arate_I; // attack rate
wire [ 3:0] drate_I; // decay rate
wire [ 3:0] rrate_I; // release rate
wire [ 3:0] sl_I; // sustain level
wire ksr_II; // key scale rate - affects rates
wire [ 1:0] ksl_IV; // key scale level - affects amplitude
// envelope operation
wire keyon_I;
wire eg_stop;
// envelope number
wire amen_IV;
wire [ 5:0] tl_IV;
wire [ 9:0] eg_V;
// Global values
wire am_dep, vib_dep, rhy_en;
// Operator
wire [ 2:0] fb_I;
wire [ 1:0] wavsel_I;
wire op, con_I, op_out, con_out;
wire signed [12:0] op_result;
assign write = !cs_n && !wr_n;
assign eg_stop = 0;
assign sample = zero;
jtopll_mmr #(.OPL_TYPE(OPL_TYPE)) u_mmr(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ), // external clock enable
.cenop ( cenop ), // internal clock enable
.din ( din ),
.write ( write ),
.addr ( addr ),
// location
.zero ( zero ),
.group ( group ),
.op ( op ),
.slot ( slot ),
.rhy_en ( rhy_en ),
// Phase Generator
.fnum_I ( fnum_I ),
.block_I ( block_I ),
.mul_II ( mul_II ),
// Operator
.wavsel_I ( wavsel_I ),
// Envelope Generator
.keyon_I ( keyon_I ),
.en_sus_I ( en_sus_I ),
.arate_I ( arate_I ),
.drate_I ( drate_I ),
.rrate_I ( rrate_I ),
.sl_I ( sl_I ),
.ks_II ( ksr_II ),
.tl_IV ( tl_IV ),
.ksl_IV ( ksl_IV ),
.amen_IV ( amen_IV ),
.viben_I ( viben_I ),
// Global Values
.am_dep ( am_dep ),
.vib_dep ( vib_dep ),
// Timbre
.fb_I ( fb_I ),
.con_I ( con_I )
);
jtopl_lfo u_lfo(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.slot ( slot ),
.vib_cnt ( vib_cnt ),
.trem ( trem )
);
jtopl_pg u_pg(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.slot ( slot ),
.rhy_en ( rhy_en ),
// Channel frequency
.fnum_I ( { fnum_I, 1'b0 } ),
.block_I ( block_I ),
// Operator multiplying
.mul_II ( mul_II ),
// phase modulation from LFO (vibrato at 6.4Hz)
.vib_cnt ( vib_cnt ),
.vib_dep ( vib_dep ),
.viben_I ( viben_I ),
// phase operation
.pg_rst_II ( pg_rst_II ),
.keycode_II ( keycode_II ),
.phase_IV ( phase_IV )
);
jtopl_eg u_eg(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.zero ( zero ),
.eg_stop ( eg_stop ),
// envelope configuration
.en_sus_I ( en_sus_I ), // enable sustain
.keycode_II ( keycode_II ),
.arate_I ( arate_I ), // attack rate
.drate_I ( drate_I ), // decay rate
.rrate_I ( rrate_I ), // release rate
.sl_I ( sl_I ), // sustain level
.ksr_II ( ksr_II ), // key scale
// envelope operation
.keyon_I ( keyon_I ),
// envelope number
.fnum_I ( { fnum_I, 1'b0 } ),
.block_I ( block_I ),
.lfo_mod ( trem ),
.amsen_IV ( amen_IV ),
.ams_IV ( am_dep ),
.tl_IV ( tl_IV ),
.ksl_IV ( ksl_IV ),
.eg_V ( eg_V ),
.pg_rst_II ( pg_rst_II )
);
jtopl_op #(.OPL_TYPE(OPL_TYPE)) u_op(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
// location of current operator
.group ( group ),
.op ( op ),
.zero ( zero ),
.pg_phase_I ( phase_IV ),
.eg_atten_II( eg_V ), // output from envelope generator
.fb_I ( fb_I ), // voice feedback
.wavsel_I ( wavsel_I ), // sine mask (OPL2)
.con_I ( con_I ),
.op_result ( op_result ),
.op_out ( op_out ),
.con_out ( con_out )
);
jtopl_acc u_acc(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.zero ( zero ),
.op_result ( op_result ),
.op ( op_out ),
.con ( con_out ),
.snd ( snd )
);
endmodule

253
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl.v
View File

@@ -1,253 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 10-6-2020
*/
module jtopl(
input rst, // rst should be at least 6 clk&cen cycles long
input clk, // CPU clock
input cen, // optional clock enable, it not needed leave as 1'b1
input [ 7:0] din,
input addr,
input cs_n,
input wr_n,
output [ 7:0] dout,
output irq_n,
// combined output
output signed [15:0] snd,
output sample
);
parameter OPL_TYPE=1;
wire cenop;
wire write;
wire [ 1:0] group;
wire [17:0] slot;
wire [ 3:0] trem;
// Timers
wire flag_A, flag_B, flagen_A, flagen_B;
wire [ 7:0] value_A;
wire [ 7:0] value_B;
wire load_A, load_B;
wire clr_flag_A, clr_flag_B;
wire overflow_A;
wire zero; // Single-clock pulse at the begginig of s1_enters
// Phase
wire [ 9:0] fnum_I;
wire [ 2:0] block_I;
wire [ 3:0] mul_II;
wire [ 9:0] phase_IV;
wire pg_rst_II;
wire viben_I;
wire [ 2:0] vib_cnt;
// envelope configuration
wire en_sus_I; // enable sustain
wire [ 3:0] keycode_II;
wire [ 3:0] arate_I; // attack rate
wire [ 3:0] drate_I; // decay rate
wire [ 3:0] rrate_I; // release rate
wire [ 3:0] sl_I; // sustain level
wire ksr_II; // key scale rate - affects rates
wire [ 1:0] ksl_IV; // key scale level - affects amplitude
// envelope operation
wire keyon_I;
wire eg_stop;
// envelope number
wire amen_IV;
wire [ 5:0] tl_IV;
wire [ 9:0] eg_V;
// Global values
wire am_dep, vib_dep, rhy_en;
// Operator
wire [ 2:0] fb_I;
wire [ 1:0] wavsel_I;
wire op, con_I, op_out, con_out;
wire signed [12:0] op_result;
assign write = !cs_n && !wr_n;
assign dout = { ~irq_n, flag_A, flag_B, 5'd6 };
assign eg_stop = 0;
assign sample = zero;
jtopl_mmr #(.OPL_TYPE(OPL_TYPE)) u_mmr(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ), // external clock enable
.cenop ( cenop ), // internal clock enable
.din ( din ),
.write ( write ),
.addr ( addr ),
.zero ( zero ),
.group ( group ),
.op ( op ),
.slot ( slot ),
.rhy_en ( rhy_en ),
// Timers
.value_A ( value_A ),
.value_B ( value_B ),
.load_A ( load_A ),
.load_B ( load_B ),
.flagen_A ( flagen_A ),
.flagen_B ( flagen_B ),
.clr_flag_A ( clr_flag_A ),
.clr_flag_B ( clr_flag_B ),
.flag_A ( flag_A ),
.overflow_A ( overflow_A ),
// Phase Generator
.fnum_I ( fnum_I ),
.block_I ( block_I ),
.mul_II ( mul_II ),
// Operator
.wavsel_I ( wavsel_I ),
// Envelope Generator
.keyon_I ( keyon_I ),
.en_sus_I ( en_sus_I ),
.arate_I ( arate_I ),
.drate_I ( drate_I ),
.rrate_I ( rrate_I ),
.sl_I ( sl_I ),
.ks_II ( ksr_II ),
.tl_IV ( tl_IV ),
.ksl_IV ( ksl_IV ),
.amen_IV ( amen_IV ),
.viben_I ( viben_I ),
// Global Values
.am_dep ( am_dep ),
.vib_dep ( vib_dep ),
// Timbre
.fb_I ( fb_I ),
.con_I ( con_I )
);
jtopl_timers u_timers(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.zero ( zero ),
.value_A ( value_A ),
.value_B ( value_B ),
.load_A ( load_A ),
.load_B ( load_B ),
.flagen_A ( flagen_A ),
.flagen_B ( flagen_B ),
.clr_flag_A ( clr_flag_A ),
.clr_flag_B ( clr_flag_B ),
.flag_A ( flag_A ),
.flag_B ( flag_B ),
.overflow_A ( overflow_A ),
.irq_n ( irq_n )
);
jtopl_lfo u_lfo(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.slot ( slot ),
.vib_cnt ( vib_cnt ),
.trem ( trem )
);
jtopl_pg u_pg(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.slot ( slot ),
.rhy_en ( rhy_en ),
// Channel frequency
.fnum_I ( fnum_I ),
.block_I ( block_I ),
// Operator multiplying
.mul_II ( mul_II ),
// phase modulation from LFO (vibrato at 6.4Hz)
.vib_cnt ( vib_cnt ),
.vib_dep ( vib_dep ),
.viben_I ( viben_I ),
// phase operation
.pg_rst_II ( pg_rst_II ),
.keycode_II ( keycode_II ),
.phase_IV ( phase_IV )
);
jtopl_eg u_eg(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.zero ( zero ),
.eg_stop ( eg_stop ),
// envelope configuration
.en_sus_I ( en_sus_I ), // enable sustain
.keycode_II ( keycode_II ),
.arate_I ( arate_I ), // attack rate
.drate_I ( drate_I ), // decay rate
.rrate_I ( rrate_I ), // release rate
.sl_I ( sl_I ), // sustain level
.ksr_II ( ksr_II ), // key scale
// envelope operation
.keyon_I ( keyon_I ),
// envelope number
.fnum_I ( fnum_I ),
.block_I ( block_I ),
.lfo_mod ( trem ),
.amsen_IV ( amen_IV ),
.ams_IV ( am_dep ),
.tl_IV ( tl_IV ),
.ksl_IV ( ksl_IV ),
.eg_V ( eg_V ),
.pg_rst_II ( pg_rst_II )
);
jtopl_op #(.OPL_TYPE(OPL_TYPE)) u_op(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
// location of current operator
.group ( group ),
.op ( op ),
.zero ( zero ),
.pg_phase_I ( phase_IV ),
.eg_atten_II( eg_V ), // output from envelope generator
.fb_I ( fb_I ), // voice feedback
.wavsel_I ( wavsel_I ), // sine mask (OPL2)
.con_I ( con_I ),
.op_result ( op_result ),
.op_out ( op_out ),
.con_out ( con_out )
);
jtopl_acc u_acc(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.zero ( zero ),
.op_result ( op_result ),
.op ( op_out ),
.con ( con_out ),
.snd ( snd )
);
endmodule

52
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl2.v
View File

@@ -1,52 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 10-10-2021
*/
module jtopl2(
input rst, // rst should be at least 6 clk&cen cycles long
input clk, // CPU clock
input cen, // optional clock enable, it not needed leave as 1'b1
input [ 7:0] din,
input addr,
input cs_n,
input wr_n,
output [ 7:0] dout,
output irq_n,
// combined output
output signed [15:0] snd,
output sample
);
`define JTOPL2
jtopl #(.OPL_TYPE(2)) u_base(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( din ),
.addr ( addr ),
.cs_n ( cs_n ),
.wr_n ( wr_n ),
.dout ( dout ),
.irq_n ( irq_n ),
.snd ( snd ),
.sample ( sample )
);
endmodule

48
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_acc.v
View File

@@ -1,48 +0,0 @@
/* This file is part of JTOPL.
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 20-6-2020
*/
module jtopl_acc(
input rst,
input clk,
input cenop,
input signed [12:0] op_result,
input zero,
input op, // 0 for modulator operators
input con, // 0 for modulated connection
output signed [15:0] snd
);
wire sum_en;
assign sum_en = op | con;
// Continuous output
jtopl_single_acc u_acc(
.clk ( clk ),
.cenop ( cenop ),
.op_result ( op_result ),
.sum_en ( sum_en ),
.zero ( zero ),
.snd ( snd )
);
endmodule

75
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_csr.v
View File

@@ -1,75 +0,0 @@
/* This file is part of JTOPL.
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_csr #(
parameter LEN=18, W=34
) ( // Circular Shift Register + input mux
input rst,
input clk,
input cen,
input [ 7:0] din,
output [W-1:0] shift_out,
input up_mult,
input up_ksl_tl,
input up_ar_dr,
input up_sl_rr,
input up_wav,
input update_op_I,
input update_op_II,
input update_op_IV
);
wire [W-1:0] regop_in;
jtopl_sh_rst #(.width(W),.stages(LEN)) u_regch(
.clk ( clk ),
.cen ( cen ),
.rst ( rst ),
.din ( regop_in ),
.drop ( shift_out )
);
wire up_mult_I = up_mult & update_op_I;
wire up_mult_II = up_mult & update_op_II;
wire up_mult_IV = up_mult & update_op_IV;
wire up_ksl_tl_IV = up_ksl_tl & update_op_IV;
wire up_ar_dr_op = up_ar_dr & update_op_I;
wire up_sl_rr_op = up_sl_rr & update_op_I;
wire up_wav_I = up_wav & update_op_I;
assign regop_in[31:0] = { // 4 bytes:
up_mult_IV ? din[7] : shift_out[31], // AM enable
up_mult_I ? din[6:5] : shift_out[30:29], // Vib enable, EG type, KSR
up_mult_II ? din[4:0] : shift_out[28:24], // KSR + Mult
up_ksl_tl_IV? din : shift_out[23:16], // KSL + TL
up_ar_dr_op ? din : shift_out[15: 8],
up_sl_rr_op ? din : shift_out[ 7: 0]
};
assign regop_in[33:32] = up_wav_I ? din[1:0] : shift_out[33:32];
endmodule // jtopl_reg

47
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_div.v
View File

@@ -1,47 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 10-6-2020
*/
module jtopl_div(
input rst,
input clk,
input cen,
output reg cenop // clock enable at operator rate
);
parameter OPL_TYPE=1;
localparam W = 2; // OPL_TYPE==2 ? 1 : 2;
reg [W-1:0] cnt;
`ifdef SIMULATION
initial cnt={W{1'b0}};
`endif
always @(posedge clk) if(cen) begin
cnt <= cnt+1'd1;
end
always @(posedge clk) begin
cenop <= cen && (&cnt);
end
endmodule

203
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_eg.v
View File

@@ -1,203 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg (
input rst,
input clk,
input cenop,
input zero,
input eg_stop,
// envelope configuration
input en_sus_I, // enable sustain
input [3:0] keycode_II,
input [3:0] arate_I, // attack rate
input [3:0] drate_I, // decay rate
input [3:0] rrate_I, // release rate
input [3:0] sl_I, // sustain level
input ksr_II, // key scale
// envelope operation
input keyon_I,
// envelope number
input [9:0] fnum_I,
input [2:0] block_I,
input [3:0] lfo_mod,
input amsen_IV,
input ams_IV,
input [5:0] tl_IV,
input [1:0] ksl_IV,
output reg [9:0] eg_V,
output reg pg_rst_II
);
parameter SLOTS=18;
wire [14:0] eg_cnt;
jtopl_eg_cnt u_egcnt(
.rst ( rst ),
.clk ( clk ),
.cen ( cenop & ~eg_stop ),
.zero ( zero ),
.eg_cnt ( eg_cnt)
);
wire keyon_last_I;
wire keyon_now_I = !keyon_last_I && keyon_I;
wire keyoff_now_I = keyon_last_I && !keyon_I;
wire cnt_in_II, cnt_lsb_II, step_II, pg_rst_I;
wire [2:0] state_in_I, state_next_I;
reg attack_II, attack_III;
wire [4:0] base_rate_I;
reg [4:0] base_rate_II;
wire [5:0] rate_out_II;
reg [5:1] rate_in_III;
reg step_III;
wire sum_out_II;
reg sum_in_III;
wire [9:0] eg_in_I, pure_eg_out_III, eg_next_III, eg_out_IV;
reg [9:0] eg_in_II, eg_in_III, eg_in_IV;
reg [3:0] keycode_III, keycode_IV;
wire [3:0] fnum_IV;
wire [2:0] block_IV;
jtopl_eg_comb u_comb(
///////////////////////////////////
// I
.keyon_now ( keyon_now_I ),
.keyoff_now ( keyoff_now_I ),
.state_in ( state_in_I ),
.eg_in ( eg_in_I ),
// envelope configuration
.en_sus ( en_sus_I ),
.arate ( arate_I ), // attack rate
.drate ( drate_I ), // decay rate
.rrate ( rrate_I ),
.sl ( sl_I ), // sustain level
.base_rate ( base_rate_I ),
.state_next ( state_next_I ),
.pg_rst ( pg_rst_I ),
///////////////////////////////////
// II
.step_attack ( attack_II ),
.step_rate_in ( base_rate_II ),
.keycode ( keycode_II ),
.eg_cnt ( eg_cnt ),
.cnt_in ( cnt_in_II ),
.ksr ( ksr_II ),
.cnt_lsb ( cnt_lsb_II ),
.step ( step_II ),
.step_rate_out ( rate_out_II ),
.sum_up_out ( sum_out_II ),
///////////////////////////////////
// III
.pure_attack ( attack_III ),
.pure_step ( step_III ),
.pure_rate ( rate_in_III[5:1] ),
.pure_eg_in ( eg_in_III ),
.pure_eg_out ( pure_eg_out_III ),
.sum_up_in ( sum_in_III ),
///////////////////////////////////
// IV
.fnum ( fnum_IV ),
.block ( block_IV ),
.lfo_mod ( lfo_mod ),
.amsen ( amsen_IV ),
.ams ( ams_IV ),
.ksl ( ksl_IV ),
.tl ( tl_IV ),
.final_keycode ( keycode_IV ),
.final_eg_in ( eg_in_IV ),
.final_eg_out ( eg_out_IV )
);
always @(posedge clk) if(cenop) begin
eg_in_II <= eg_in_I;
attack_II <= state_next_I[0];
base_rate_II<= base_rate_I;
pg_rst_II <= pg_rst_I;
eg_in_III <= eg_in_II;
attack_III <= attack_II;
rate_in_III <= rate_out_II[5:1];
step_III <= step_II;
sum_in_III <= sum_out_II;
eg_in_IV <= pure_eg_out_III;
eg_V <= eg_out_IV;
keycode_III <= keycode_II;
keycode_IV <= keycode_III;
end
jtopl_sh #( .width(1), .stages(SLOTS) ) u_cntsh(
.clk ( clk ),
.cen ( cenop ),
.din ( cnt_lsb_II),
.drop ( cnt_in_II )
);
jtopl_sh #( .width(4), .stages(3) ) u_fnumsh(
.clk ( clk ),
.cen ( cenop ),
.din ( fnum_I[9:6] ),
.drop ( fnum_IV )
);
jtopl_sh #( .width(3), .stages(3) ) u_blocksh(
.clk ( clk ),
.cen ( cenop ),
.din ( block_I ),
.drop ( block_IV )
);
jtopl_sh_rst #( .width(10), .stages(SLOTS-3), .rstval(1'b1) ) u_egsh(
.clk ( clk ),
.cen ( cenop ),
.rst ( rst ),
.din ( eg_in_IV ),
.drop ( eg_in_I )
);
jtopl_sh_rst #( .width(3), .stages(SLOTS), .rstval(1'b1) ) u_egstate(
.clk ( clk ),
.cen ( cenop ),
.rst ( rst ),
.din ( state_next_I ),
.drop ( state_in_I )
);
jtopl_sh_rst #( .width(1), .stages(SLOTS), .rstval(1'b0) ) u_konsh(
.clk ( clk ),
.cen ( cenop ),
.rst ( rst ),
.din ( keyon_I ),
.drop ( keyon_last_I )
);
endmodule // jtopl_eg

44
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_eg_cnt.v
View File

@@ -1,44 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg_cnt(
input rst,
input clk,
input cen,
input zero,
output reg [14:0] eg_cnt
);
always @(posedge clk, posedge rst) begin : envelope_counter
if( rst ) begin
eg_cnt <=15'd0;
end
else begin
if( zero && cen ) begin
// envelope counter increases at each zero input
// This is different from OPN/M where it increased
// once every three zero inputs
eg_cnt <= eg_cnt + 1'b1;
end
end
end
endmodule

130
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_eg_comb.v
View File

@@ -1,130 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg_comb(
input keyon_now,
input keyoff_now,
input [ 2:0] state_in,
input [ 9:0] eg_in,
// envelope configuration
input en_sus, // enable sustain
input [ 3:0] arate, // attack rate
input [ 3:0] drate, // decay rate
input [ 3:0] rrate,
input [ 3:0] sl, // sustain level
output [ 4:0] base_rate,
output [ 2:0] state_next,
output pg_rst,
///////////////////////////////////
// II
input step_attack,
input [ 4:0] step_rate_in,
input [ 3:0] keycode,
input [14:0] eg_cnt,
input cnt_in,
input ksr,
output cnt_lsb,
output step,
output [ 5:0] step_rate_out,
output sum_up_out,
///////////////////////////////////
// III
input pure_attack,
input pure_step,
input [ 5:1] pure_rate,
input [ 9:0] pure_eg_in,
output [ 9:0] pure_eg_out,
input sum_up_in,
///////////////////////////////////
// IV
input [ 3:0] lfo_mod,
input [ 3:0] fnum,
input [ 2:0] block,
input amsen,
input ams,
input [ 5:0] tl,
input [ 1:0] ksl,
input [ 3:0] final_keycode,
input [ 9:0] final_eg_in,
output [ 9:0] final_eg_out
);
// I
jtopl_eg_ctrl u_ctrl(
.keyon_now ( keyon_now ),
.keyoff_now ( keyoff_now ),
.state_in ( state_in ),
.eg ( eg_in ),
// envelope configuration
.en_sus ( en_sus ),
.arate ( arate ), // attack rate
.drate ( drate ), // decay rate
.rrate ( rrate ),
.sl ( sl ), // sustain level
.base_rate ( base_rate ),
.state_next ( state_next ),
.pg_rst ( pg_rst )
);
// II
jtopl_eg_step u_step(
.attack ( step_attack ),
.base_rate ( step_rate_in ),
.keycode ( keycode ),
.eg_cnt ( eg_cnt ),
.cnt_in ( cnt_in ),
.ksr ( ksr ),
.cnt_lsb ( cnt_lsb ),
.step ( step ),
.rate ( step_rate_out ),
.sum_up ( sum_up_out )
);
// III
wire [9:0] egin, egout;
jtopl_eg_pure u_pure(
.attack ( pure_attack ),
.step ( pure_step ),
.rate ( pure_rate ),
.eg_in ( pure_eg_in ),
.eg_pure( pure_eg_out ),
.sum_up ( sum_up_in )
);
// IV
jtopl_eg_final u_final(
.fnum ( fnum ),
.block ( block ),
.lfo_mod ( lfo_mod ),
.amsen ( amsen ),
.ams ( ams ),
.tl ( tl ),
.ksl ( ksl ),
.eg_pure_in ( final_eg_in ),
.eg_limited ( final_eg_out )
);
endmodule // jtopl_eg_comb

87
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_eg_ctrl.v
View File

@@ -1,87 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg_ctrl(
input keyon_now,
input keyoff_now,
input [2:0] state_in,
input [9:0] eg,
// envelope configuration
input en_sus, // enable sustain
input [3:0] arate, // attack rate
input [3:0] drate, // decay rate
input [3:0] rrate,
input [3:0] sl, // sustain level
output reg [4:0] base_rate,
output reg [2:0] state_next,
output reg pg_rst
);
localparam ATTACK = 3'b001,
DECAY = 3'b010,
HOLD = 3'b100,
RELEASE= 3'b000; // default state is release
// wire is_decaying = state_in[1] | state_in[2];
wire [4:0] sustain = { &sl, sl}; //93dB if sl==4'hF
always @(*) begin
pg_rst = keyon_now;
end
always @(*)
casez ( { keyoff_now, keyon_now, state_in} )
5'b01_???: begin // key on
base_rate = {arate,1'b0};
state_next = ATTACK;
end
{2'b00, ATTACK}:
if( eg==10'd0 ) begin
base_rate = {drate,1'b0};
state_next = DECAY;
end
else begin
base_rate = {arate,1'b0};
state_next = ATTACK;
end
{2'b00, DECAY}: begin
if( eg[9:5] >= sustain ) begin
base_rate = en_sus ? 5'd0 : {rrate,1'b0};
state_next = en_sus ? HOLD : RELEASE;
end else begin
base_rate = {drate,1'b0};
state_next = DECAY;
end
end
{2'b00, HOLD}: begin
base_rate = 5'd0;
state_next = HOLD;
end
default: begin // RELEASE, note that keyoff_now==1 will enter this state too
base_rate = {rrate,1'b1};
state_next = RELEASE; // release
end
endcase
endmodule // jtopl_eg_ctrl

69
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_eg_final.v
View File

@@ -1,69 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg_final(
input [3:0] lfo_mod,
input [3:0] fnum,
input [2:0] block,
input amsen,
input ams,
input [5:0] tl,
input [1:0] ksl, // level damped by pitch
input [9:0] eg_pure_in,
output reg [9:0] eg_limited
);
reg [ 5:0] am_final;
reg [11:0] sum_eg_tl;
reg [11:0] sum_eg_tl_am;
reg [ 8:0] ksl_dB;
reg [ 6:0] ksl_lut[0:15];
reg [ 7:0] ksl_base;
always @(*) begin
ksl_base = {1'b0, ksl_lut[fnum]}- { 1'b0, 4'd8-{1'b0,block}, 3'b0 };
if( ksl_base[7] || ksl==2'b0 ) begin
ksl_dB = 9'd0;
end else begin
ksl_dB = {ksl_base[6:0],2'b0} >> ~ksl;
end
end
always @(*) begin
am_final = amsen ? ( ams ? {lfo_mod, 2'b0} : {2'b0, lfo_mod} ) : 6'd0;
sum_eg_tl = { 2'b0, tl, 3'd0 } +
{ 1'b0, ksl_dB, 1'd0 } +
{ 1'b0, eg_pure_in}; // leading zeros needed to compute correctly
sum_eg_tl_am = sum_eg_tl + { 5'd0, am_final };
end
always @(*) begin
eg_limited = sum_eg_tl_am[11:10]==2'd0 ? sum_eg_tl_am[9:0] : 10'h3ff;
end
initial begin
ksl_lut[ 0] = 7'd00; ksl_lut[ 1] = 7'd32; ksl_lut[ 2] = 7'd40; ksl_lut[ 3] = 7'd45;
ksl_lut[ 4] = 7'd48; ksl_lut[ 5] = 7'd51; ksl_lut[ 6] = 7'd53; ksl_lut[ 7] = 7'd55;
ksl_lut[ 8] = 7'd56; ksl_lut[ 9] = 7'd58; ksl_lut[10] = 7'd59; ksl_lut[11] = 7'd60;
ksl_lut[12] = 7'd61; ksl_lut[13] = 7'd62; ksl_lut[14] = 7'd63; ksl_lut[15] = 7'd64;
end
endmodule

87
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_eg_pure.v
View File

@@ -1,87 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg_pure(
input attack,
input step,
input [ 5:1] rate,
input [ 9:0] eg_in,
input sum_up,
output reg [9:0] eg_pure
);
reg [ 3:0] dr_sum;
reg [ 9:0] dr_adj;
reg [10:0] dr_result;
always @(*) begin : dr_calculation
case( rate[5:2] )
4'b1100: dr_sum = 4'h2; // 12
4'b1101: dr_sum = 4'h4; // 13
4'b1110: dr_sum = 4'h8; // 14
4'b1111: dr_sum = 4'hf;// 15
default: dr_sum = { 2'b0, step, 1'b0 };
endcase
// Decay rate attenuation is multiplied by 4 for SSG operation
dr_adj = {6'd0, dr_sum};
dr_result = dr_adj + eg_in;
end
reg [ 7:0] ar_sum0;
reg [ 8:0] ar_sum1;
reg [10:0] ar_result;
reg [ 9:0] ar_sum;
always @(*) begin : ar_calculation
casez( rate[5:2] )
default: ar_sum0 = {2'd0, eg_in[9:4]};
4'b1011, 4'b1100: ar_sum0 = {1'd0, eg_in[9:3]}; // 'hb
// 4'b1101: ar_sum0 = {1'd0, eg_in[9:3]}; // 'hd
// 4'b111?: ar_sum0 = eg_in[9:2]; // 'he/f
4'b1101, 4'b111?: ar_sum0 = eg_in[9:2]; // 'he/f
endcase
ar_sum1 = ar_sum0+9'd1;
if( rate[5:2] == 4'he )
ar_sum = { ar_sum1, 1'b0 };
else if( rate[5:2] > 4'hb )
ar_sum = step ? { ar_sum1, 1'b0 } : { 1'b0, ar_sum1 }; // adds ar_sum1*3/2 max
// else if( rate[5:2] == 4'hb )
// ar_sum = step ? { ar_sum1, 1'b0 } : 10'd0; // adds ar_sum1 max
else
ar_sum = step ? { 1'b0, ar_sum1 } : 10'd0; // adds ar_sum1/2 max
ar_result = eg_in-ar_sum;
end
///////////////////////////////////////////////////////////
// rate not used below this point
reg [9:0] eg_pre_fastar; // pre fast attack rate
always @(*) begin
if(sum_up) begin
if( attack )
eg_pre_fastar = ar_result[10] ? 10'd0: ar_result[9:0];
else
eg_pre_fastar = dr_result[10] ? 10'h3FF : dr_result[9:0];
end
else eg_pre_fastar = eg_in;
eg_pure = (attack&rate[5:1]==5'h1F) ? 10'd0 : eg_pre_fastar;
end
endmodule

106
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_eg_step.v
View File

@@ -1,106 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg_step(
input attack,
input [ 4:0] base_rate,
input [ 3:0] keycode,
input [14:0] eg_cnt,
input cnt_in,
input ksr,
output cnt_lsb,
output reg step,
output reg [ 5:0] rate,
output reg sum_up
);
reg [6:0] pre_rate;
always @(*) begin : pre_rate_calc
if( base_rate == 5'd0 )
pre_rate = 7'd0;
else
pre_rate = { 1'b0, base_rate, 1'b0 } + // base_rate LSB is always zero except for RR
({ 3'b0, keycode } >> (ksr ? 1 : 3));
end
always @(*)
rate = pre_rate>=7'b1111_00 ? 6'b1111_11 : pre_rate[5:0];
reg [2:0] cnt;
reg [4:0] mux_sel;
always @(*) begin
mux_sel = attack ? (rate[5:2]+4'd1): {1'b0,rate[5:2]};
end
always @(*)
case( mux_sel )
5'h0: cnt = eg_cnt[13:11];
5'h1: cnt = eg_cnt[12:10];
5'h2: cnt = eg_cnt[11: 9];
5'h3: cnt = eg_cnt[10: 8];
5'h4: cnt = eg_cnt[ 9: 7];
5'h5: cnt = eg_cnt[ 8: 6];
5'h6: cnt = eg_cnt[ 7: 5];
5'h7: cnt = eg_cnt[ 6: 4];
5'h8: cnt = eg_cnt[ 5: 3];
5'h9: cnt = eg_cnt[ 4: 2];
5'ha: cnt = eg_cnt[ 3: 1];
default: cnt = eg_cnt[ 2: 0];
endcase
////////////////////////////////
reg [7:0] step_idx;
always @(*) begin : rate_step
if( rate[5:4]==2'b11 ) begin // 0 means 1x, 1 means 2x
if( rate[5:2]==4'hf && attack)
step_idx = 8'b11111111; // Maximum attack speed, rates 60&61
else
case( rate[1:0] )
2'd0: step_idx = 8'b00000000;
2'd1: step_idx = 8'b10001000; // 2
2'd2: step_idx = 8'b10101010; // 4
2'd3: step_idx = 8'b11101110; // 6
endcase
end
else begin
if( rate[5:2]==4'd0 && !attack)
step_idx = 8'b11111110; // limit slowest decay rate
else
case( rate[1:0] )
2'd0: step_idx = 8'b10101010; // 4
2'd1: step_idx = 8'b11101010; // 5
2'd2: step_idx = 8'b11101110; // 6
2'd3: step_idx = 8'b11111110; // 7
endcase
end
// a rate of zero keeps the level still
step = rate[5:1]==5'd0 ? 1'b0 : step_idx[ cnt ];
end
assign cnt_lsb = cnt[0];
always @(*) begin
sum_up = cnt[0] != cnt_in;
end
endmodule // eg_step

305
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_exprom.v
View File

@@ -1,305 +0,0 @@
/* This file is part of JTOPL.
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 20-6-2020
*/
// Yamaha used the same table for OPN, OPM and OPL
// Originally written in more compact way that required some logic to decompress
// Not really worth compressing when the target is an FPGA as one BRAM will be
// used in either case. So it's better to leave it uncompress and save the
// decoding logic
// altera message_off 10030
module jtopl_exprom
(
input [7:0] addr,
input clk,
input cen,
output reg [9:0] exp
);
reg [9:0] explut_jt51[255:0];
initial
begin
explut_jt51[8'd000] = 10'd1018;
explut_jt51[8'd001] = 10'd1013;
explut_jt51[8'd002] = 10'd1007;
explut_jt51[8'd003] = 10'd1002;
explut_jt51[8'd004] = 10'd0996;
explut_jt51[8'd005] = 10'd0991;
explut_jt51[8'd006] = 10'd0986;
explut_jt51[8'd007] = 10'd0980;
explut_jt51[8'd008] = 10'd0975;
explut_jt51[8'd009] = 10'd0969;
explut_jt51[8'd010] = 10'd0964;
explut_jt51[8'd011] = 10'd0959;
explut_jt51[8'd012] = 10'd0953;
explut_jt51[8'd013] = 10'd0948;
explut_jt51[8'd014] = 10'd0942;
explut_jt51[8'd015] = 10'd0937;
explut_jt51[8'd016] = 10'd0932;
explut_jt51[8'd017] = 10'd0927;
explut_jt51[8'd018] = 10'd0921;
explut_jt51[8'd019] = 10'd0916;
explut_jt51[8'd020] = 10'd0911;
explut_jt51[8'd021] = 10'd0906;
explut_jt51[8'd022] = 10'd0900;
explut_jt51[8'd023] = 10'd0895;
explut_jt51[8'd024] = 10'd0890;
explut_jt51[8'd025] = 10'd0885;
explut_jt51[8'd026] = 10'd0880;
explut_jt51[8'd027] = 10'd0874;
explut_jt51[8'd028] = 10'd0869;
explut_jt51[8'd029] = 10'd0864;
explut_jt51[8'd030] = 10'd0859;
explut_jt51[8'd031] = 10'd0854;
explut_jt51[8'd032] = 10'd0849;
explut_jt51[8'd033] = 10'd0844;
explut_jt51[8'd034] = 10'd0839;
explut_jt51[8'd035] = 10'd0834;
explut_jt51[8'd036] = 10'd0829;
explut_jt51[8'd037] = 10'd0824;
explut_jt51[8'd038] = 10'd0819;
explut_jt51[8'd039] = 10'd0814;
explut_jt51[8'd040] = 10'd0809;
explut_jt51[8'd041] = 10'd0804;
explut_jt51[8'd042] = 10'd0799;
explut_jt51[8'd043] = 10'd0794;
explut_jt51[8'd044] = 10'd0789;
explut_jt51[8'd045] = 10'd0784;
explut_jt51[8'd046] = 10'd0779;
explut_jt51[8'd047] = 10'd0774;
explut_jt51[8'd048] = 10'd0770;
explut_jt51[8'd049] = 10'd0765;
explut_jt51[8'd050] = 10'd0760;
explut_jt51[8'd051] = 10'd0755;
explut_jt51[8'd052] = 10'd0750;
explut_jt51[8'd053] = 10'd0745;
explut_jt51[8'd054] = 10'd0741;
explut_jt51[8'd055] = 10'd0736;
explut_jt51[8'd056] = 10'd0731;
explut_jt51[8'd057] = 10'd0726;
explut_jt51[8'd058] = 10'd0722;
explut_jt51[8'd059] = 10'd0717;
explut_jt51[8'd060] = 10'd0712;
explut_jt51[8'd061] = 10'd0708;
explut_jt51[8'd062] = 10'd0703;
explut_jt51[8'd063] = 10'd0698;
explut_jt51[8'd064] = 10'd0693;
explut_jt51[8'd065] = 10'd0689;
explut_jt51[8'd066] = 10'd0684;
explut_jt51[8'd067] = 10'd0680;
explut_jt51[8'd068] = 10'd0675;
explut_jt51[8'd069] = 10'd0670;
explut_jt51[8'd070] = 10'd0666;
explut_jt51[8'd071] = 10'd0661;
explut_jt51[8'd072] = 10'd0657;
explut_jt51[8'd073] = 10'd0652;
explut_jt51[8'd074] = 10'd0648;
explut_jt51[8'd075] = 10'd0643;
explut_jt51[8'd076] = 10'd0639;
explut_jt51[8'd077] = 10'd0634;
explut_jt51[8'd078] = 10'd0630;
explut_jt51[8'd079] = 10'd0625;
explut_jt51[8'd080] = 10'd0621;
explut_jt51[8'd081] = 10'd0616;
explut_jt51[8'd082] = 10'd0612;
explut_jt51[8'd083] = 10'd0607;
explut_jt51[8'd084] = 10'd0603;
explut_jt51[8'd085] = 10'd0599;
explut_jt51[8'd086] = 10'd0594;
explut_jt51[8'd087] = 10'd0590;
explut_jt51[8'd088] = 10'd0585;
explut_jt51[8'd089] = 10'd0581;
explut_jt51[8'd090] = 10'd0577;
explut_jt51[8'd091] = 10'd0572;
explut_jt51[8'd092] = 10'd0568;
explut_jt51[8'd093] = 10'd0564;
explut_jt51[8'd094] = 10'd0560;
explut_jt51[8'd095] = 10'd0555;
explut_jt51[8'd096] = 10'd0551;
explut_jt51[8'd097] = 10'd0547;
explut_jt51[8'd098] = 10'd0542;
explut_jt51[8'd099] = 10'd0538;
explut_jt51[8'd100] = 10'd0534;
explut_jt51[8'd101] = 10'd0530;
explut_jt51[8'd102] = 10'd0526;
explut_jt51[8'd103] = 10'd0521;
explut_jt51[8'd104] = 10'd0517;
explut_jt51[8'd105] = 10'd0513;
explut_jt51[8'd106] = 10'd0509;
explut_jt51[8'd107] = 10'd0505;
explut_jt51[8'd108] = 10'd0501;
explut_jt51[8'd109] = 10'd0496;
explut_jt51[8'd110] = 10'd0492;
explut_jt51[8'd111] = 10'd0488;
explut_jt51[8'd112] = 10'd0484;
explut_jt51[8'd113] = 10'd0480;
explut_jt51[8'd114] = 10'd0476;
explut_jt51[8'd115] = 10'd0472;
explut_jt51[8'd116] = 10'd0468;
explut_jt51[8'd117] = 10'd0464;
explut_jt51[8'd118] = 10'd0460;
explut_jt51[8'd119] = 10'd0456;
explut_jt51[8'd120] = 10'd0452;
explut_jt51[8'd121] = 10'd0448;
explut_jt51[8'd122] = 10'd0444;
explut_jt51[8'd123] = 10'd0440;
explut_jt51[8'd124] = 10'd0436;
explut_jt51[8'd125] = 10'd0432;
explut_jt51[8'd126] = 10'd0428;
explut_jt51[8'd127] = 10'd0424;
explut_jt51[8'd128] = 10'd0420;
explut_jt51[8'd129] = 10'd0416;
explut_jt51[8'd130] = 10'd0412;
explut_jt51[8'd131] = 10'd0409;
explut_jt51[8'd132] = 10'd0405;
explut_jt51[8'd133] = 10'd0401;
explut_jt51[8'd134] = 10'd0397;
explut_jt51[8'd135] = 10'd0393;
explut_jt51[8'd136] = 10'd0389;
explut_jt51[8'd137] = 10'd0385;
explut_jt51[8'd138] = 10'd0382;
explut_jt51[8'd139] = 10'd0378;
explut_jt51[8'd140] = 10'd0374;
explut_jt51[8'd141] = 10'd0370;
explut_jt51[8'd142] = 10'd0367;
explut_jt51[8'd143] = 10'd0363;
explut_jt51[8'd144] = 10'd0359;
explut_jt51[8'd145] = 10'd0355;
explut_jt51[8'd146] = 10'd0352;
explut_jt51[8'd147] = 10'd0348;
explut_jt51[8'd148] = 10'd0344;
explut_jt51[8'd149] = 10'd0340;
explut_jt51[8'd150] = 10'd0337;
explut_jt51[8'd151] = 10'd0333;
explut_jt51[8'd152] = 10'd0329;
explut_jt51[8'd153] = 10'd0326;
explut_jt51[8'd154] = 10'd0322;
explut_jt51[8'd155] = 10'd0318;
explut_jt51[8'd156] = 10'd0315;
explut_jt51[8'd157] = 10'd0311;
explut_jt51[8'd158] = 10'd0308;
explut_jt51[8'd159] = 10'd0304;
explut_jt51[8'd160] = 10'd0300;
explut_jt51[8'd161] = 10'd0297;
explut_jt51[8'd162] = 10'd0293;
explut_jt51[8'd163] = 10'd0290;
explut_jt51[8'd164] = 10'd0286;
explut_jt51[8'd165] = 10'd0283;
explut_jt51[8'd166] = 10'd0279;
explut_jt51[8'd167] = 10'd0276;
explut_jt51[8'd168] = 10'd0272;
explut_jt51[8'd169] = 10'd0268;
explut_jt51[8'd170] = 10'd0265;
explut_jt51[8'd171] = 10'd0262;
explut_jt51[8'd172] = 10'd0258;
explut_jt51[8'd173] = 10'd0255;
explut_jt51[8'd174] = 10'd0251;
explut_jt51[8'd175] = 10'd0248;
explut_jt51[8'd176] = 10'd0244;
explut_jt51[8'd177] = 10'd0241;
explut_jt51[8'd178] = 10'd0237;
explut_jt51[8'd179] = 10'd0234;
explut_jt51[8'd180] = 10'd0231;
explut_jt51[8'd181] = 10'd0227;
explut_jt51[8'd182] = 10'd0224;
explut_jt51[8'd183] = 10'd0220;
explut_jt51[8'd184] = 10'd0217;
explut_jt51[8'd185] = 10'd0214;
explut_jt51[8'd186] = 10'd0210;
explut_jt51[8'd187] = 10'd0207;
explut_jt51[8'd188] = 10'd0204;
explut_jt51[8'd189] = 10'd0200;
explut_jt51[8'd190] = 10'd0197;
explut_jt51[8'd191] = 10'd0194;
explut_jt51[8'd192] = 10'd0190;
explut_jt51[8'd193] = 10'd0187;
explut_jt51[8'd194] = 10'd0184;
explut_jt51[8'd195] = 10'd0181;
explut_jt51[8'd196] = 10'd0177;
explut_jt51[8'd197] = 10'd0174;
explut_jt51[8'd198] = 10'd0171;
explut_jt51[8'd199] = 10'd0168;
explut_jt51[8'd200] = 10'd0164;
explut_jt51[8'd201] = 10'd0161;
explut_jt51[8'd202] = 10'd0158;
explut_jt51[8'd203] = 10'd0155;
explut_jt51[8'd204] = 10'd0152;
explut_jt51[8'd205] = 10'd0148;
explut_jt51[8'd206] = 10'd0145;
explut_jt51[8'd207] = 10'd0142;
explut_jt51[8'd208] = 10'd0139;
explut_jt51[8'd209] = 10'd0136;
explut_jt51[8'd210] = 10'd0133;
explut_jt51[8'd211] = 10'd0130;
explut_jt51[8'd212] = 10'd0126;
explut_jt51[8'd213] = 10'd0123;
explut_jt51[8'd214] = 10'd0120;
explut_jt51[8'd215] = 10'd0117;
explut_jt51[8'd216] = 10'd0114;
explut_jt51[8'd217] = 10'd0111;
explut_jt51[8'd218] = 10'd0108;
explut_jt51[8'd219] = 10'd0105;
explut_jt51[8'd220] = 10'd0102;
explut_jt51[8'd221] = 10'd0099;
explut_jt51[8'd222] = 10'd0096;
explut_jt51[8'd223] = 10'd0093;
explut_jt51[8'd224] = 10'd0090;
explut_jt51[8'd225] = 10'd0087;
explut_jt51[8'd226] = 10'd0084;
explut_jt51[8'd227] = 10'd0081;
explut_jt51[8'd228] = 10'd0078;
explut_jt51[8'd229] = 10'd0075;
explut_jt51[8'd230] = 10'd0072;
explut_jt51[8'd231] = 10'd0069;
explut_jt51[8'd232] = 10'd0066;
explut_jt51[8'd233] = 10'd0063;
explut_jt51[8'd234] = 10'd0060;
explut_jt51[8'd235] = 10'd0057;
explut_jt51[8'd236] = 10'd0054;
explut_jt51[8'd237] = 10'd0051;
explut_jt51[8'd238] = 10'd0048;
explut_jt51[8'd239] = 10'd0045;
explut_jt51[8'd240] = 10'd0042;
explut_jt51[8'd241] = 10'd0040;
explut_jt51[8'd242] = 10'd0037;
explut_jt51[8'd243] = 10'd0034;
explut_jt51[8'd244] = 10'd0031;
explut_jt51[8'd245] = 10'd0028;
explut_jt51[8'd246] = 10'd0025;
explut_jt51[8'd247] = 10'd0022;
explut_jt51[8'd248] = 10'd0020;
explut_jt51[8'd249] = 10'd0017;
explut_jt51[8'd250] = 10'd0014;
explut_jt51[8'd251] = 10'd0011;
explut_jt51[8'd252] = 10'd0008;
explut_jt51[8'd253] = 10'd0006;
explut_jt51[8'd254] = 10'd0003;
explut_jt51[8'd255] = 10'd0000;
end
always @ (posedge clk) if(cen)
exp <= explut_jt51[addr];
endmodule

80
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_lfo.v
View File

@@ -1,80 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-6-2020
*/
// Follows OPLL Reverse Engineering from Nuked
// https://github.com/nukeykt/Nuked-OPLL
// The AM logic renders a triangular waveform. The logic for it is rather
// obscure, but apparently that's how the original was done
module jtopl_lfo(
input rst,
input clk,
input cenop,
input [17:0] slot,
output [ 2:0] vib_cnt,
output reg [ 3:0] trem
);
parameter [6:0] LIM=7'd60;
reg [12:0] cnt;
reg am_inc, am_incen, am_dir, am_step;
reg [ 1:0] am_bit;
reg am_carry;
reg [ 8:0] am_cnt;
wire [12:0] next = cnt+1'b1;
assign vib_cnt = cnt[12:10];
always @(*) begin
am_inc = (slot[0] | am_dir ) & am_step & am_incen;
am_bit = {1'b0, am_cnt[0]} + {1'b0, am_inc} + {1'b0, am_carry & am_incen};
end
always @(posedge clk) begin
if( rst ) begin
cnt <= 13'd0;
am_incen <= 1;
am_dir <= 0;
am_carry <= 0;
am_cnt <= 9'd0;
am_step <= 0;
end else if( cenop ) begin
if( slot[17] ) begin
cnt <= next;
am_step <= &next[5:0];
am_incen <= 1;
end
else if(slot[8]) am_incen <= 0;
am_cnt <= { am_bit[0], am_cnt[8:1] };
am_carry <= am_bit[1];
if( slot[0] ) begin
if( am_dir && am_cnt[6:0]==7'd0 ) am_dir <= 0;
else
if( !am_dir && ( (am_cnt[6:0]&7'h69) == 7'h69) ) am_dir <= 1;
end
// output
if( slot[0] ) trem <= am_cnt[6:3];
end
end
endmodule

297
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_logsin.v
View File

@@ -1,297 +0,0 @@
/* This file is part of JTOPL.
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
//altera message_off 10030
module jtopl_logsin(
input clk,
input cen,
input [ 7:0] addr,
output reg [11:0] logsin
);
reg [11:0] sinelut[255:0];
initial begin
sinelut[8'd000] = 12'h000;
sinelut[8'd001] = 12'h000;
sinelut[8'd002] = 12'h000;
sinelut[8'd003] = 12'h000;
sinelut[8'd004] = 12'h000;
sinelut[8'd005] = 12'h000;
sinelut[8'd006] = 12'h000;
sinelut[8'd007] = 12'h000;
sinelut[8'd008] = 12'h001;
sinelut[8'd009] = 12'h001;
sinelut[8'd010] = 12'h001;
sinelut[8'd011] = 12'h001;
sinelut[8'd012] = 12'h001;
sinelut[8'd013] = 12'h001;
sinelut[8'd014] = 12'h001;
sinelut[8'd015] = 12'h002;
sinelut[8'd016] = 12'h002;
sinelut[8'd017] = 12'h002;
sinelut[8'd018] = 12'h002;
sinelut[8'd019] = 12'h003;
sinelut[8'd020] = 12'h003;
sinelut[8'd021] = 12'h003;
sinelut[8'd022] = 12'h004;
sinelut[8'd023] = 12'h004;
sinelut[8'd024] = 12'h004;
sinelut[8'd025] = 12'h005;
sinelut[8'd026] = 12'h005;
sinelut[8'd027] = 12'h005;
sinelut[8'd028] = 12'h006;
sinelut[8'd029] = 12'h006;
sinelut[8'd030] = 12'h007;
sinelut[8'd031] = 12'h007;
sinelut[8'd032] = 12'h007;
sinelut[8'd033] = 12'h008;
sinelut[8'd034] = 12'h008;
sinelut[8'd035] = 12'h009;
sinelut[8'd036] = 12'h009;
sinelut[8'd037] = 12'h00a;
sinelut[8'd038] = 12'h00a;
sinelut[8'd039] = 12'h00b;
sinelut[8'd040] = 12'h00c;
sinelut[8'd041] = 12'h00c;
sinelut[8'd042] = 12'h00d;
sinelut[8'd043] = 12'h00d;
sinelut[8'd044] = 12'h00e;
sinelut[8'd045] = 12'h00f;
sinelut[8'd046] = 12'h00f;
sinelut[8'd047] = 12'h010;
sinelut[8'd048] = 12'h011;
sinelut[8'd049] = 12'h011;
sinelut[8'd050] = 12'h012;
sinelut[8'd051] = 12'h013;
sinelut[8'd052] = 12'h014;
sinelut[8'd053] = 12'h014;
sinelut[8'd054] = 12'h015;
sinelut[8'd055] = 12'h016;
sinelut[8'd056] = 12'h017;
sinelut[8'd057] = 12'h017;
sinelut[8'd058] = 12'h018;
sinelut[8'd059] = 12'h019;
sinelut[8'd060] = 12'h01a;
sinelut[8'd061] = 12'h01b;
sinelut[8'd062] = 12'h01c;
sinelut[8'd063] = 12'h01d;
sinelut[8'd064] = 12'h01e;
sinelut[8'd065] = 12'h01f;
sinelut[8'd066] = 12'h020;
sinelut[8'd067] = 12'h021;
sinelut[8'd068] = 12'h022;
sinelut[8'd069] = 12'h023;
sinelut[8'd070] = 12'h024;
sinelut[8'd071] = 12'h025;
sinelut[8'd072] = 12'h026;
sinelut[8'd073] = 12'h027;
sinelut[8'd074] = 12'h028;
sinelut[8'd075] = 12'h029;
sinelut[8'd076] = 12'h02a;
sinelut[8'd077] = 12'h02b;
sinelut[8'd078] = 12'h02d;
sinelut[8'd079] = 12'h02e;
sinelut[8'd080] = 12'h02f;
sinelut[8'd081] = 12'h030;
sinelut[8'd082] = 12'h031;
sinelut[8'd083] = 12'h033;
sinelut[8'd084] = 12'h034;
sinelut[8'd085] = 12'h035;
sinelut[8'd086] = 12'h037;
sinelut[8'd087] = 12'h038;
sinelut[8'd088] = 12'h039;
sinelut[8'd089] = 12'h03b;
sinelut[8'd090] = 12'h03c;
sinelut[8'd091] = 12'h03e;
sinelut[8'd092] = 12'h03f;
sinelut[8'd093] = 12'h040;
sinelut[8'd094] = 12'h042;
sinelut[8'd095] = 12'h043;
sinelut[8'd096] = 12'h045;
sinelut[8'd097] = 12'h046;
sinelut[8'd098] = 12'h048;
sinelut[8'd099] = 12'h04a;
sinelut[8'd100] = 12'h04b;
sinelut[8'd101] = 12'h04d;
sinelut[8'd102] = 12'h04e;
sinelut[8'd103] = 12'h050;
sinelut[8'd104] = 12'h052;
sinelut[8'd105] = 12'h053;
sinelut[8'd106] = 12'h055;
sinelut[8'd107] = 12'h057;
sinelut[8'd108] = 12'h059;
sinelut[8'd109] = 12'h05b;
sinelut[8'd110] = 12'h05c;
sinelut[8'd111] = 12'h05e;
sinelut[8'd112] = 12'h060;
sinelut[8'd113] = 12'h062;
sinelut[8'd114] = 12'h064;
sinelut[8'd115] = 12'h066;
sinelut[8'd116] = 12'h068;
sinelut[8'd117] = 12'h06a;
sinelut[8'd118] = 12'h06c;
sinelut[8'd119] = 12'h06e;
sinelut[8'd120] = 12'h070;
sinelut[8'd121] = 12'h072;
sinelut[8'd122] = 12'h074;
sinelut[8'd123] = 12'h076;
sinelut[8'd124] = 12'h078;
sinelut[8'd125] = 12'h07a;
sinelut[8'd126] = 12'h07d;
sinelut[8'd127] = 12'h07f;
sinelut[8'd128] = 12'h081;
sinelut[8'd129] = 12'h083;
sinelut[8'd130] = 12'h086;
sinelut[8'd131] = 12'h088;
sinelut[8'd132] = 12'h08a;
sinelut[8'd133] = 12'h08d;
sinelut[8'd134] = 12'h08f;
sinelut[8'd135] = 12'h092;
sinelut[8'd136] = 12'h094;
sinelut[8'd137] = 12'h097;
sinelut[8'd138] = 12'h099;
sinelut[8'd139] = 12'h09c;
sinelut[8'd140] = 12'h09f;
sinelut[8'd141] = 12'h0a1;
sinelut[8'd142] = 12'h0a4;
sinelut[8'd143] = 12'h0a7;
sinelut[8'd144] = 12'h0a9;
sinelut[8'd145] = 12'h0ac;
sinelut[8'd146] = 12'h0af;
sinelut[8'd147] = 12'h0b2;
sinelut[8'd148] = 12'h0b5;
sinelut[8'd149] = 12'h0b8;
sinelut[8'd150] = 12'h0bb;
sinelut[8'd151] = 12'h0be;
sinelut[8'd152] = 12'h0c1;
sinelut[8'd153] = 12'h0c4;
sinelut[8'd154] = 12'h0c7;
sinelut[8'd155] = 12'h0ca;
sinelut[8'd156] = 12'h0cd;
sinelut[8'd157] = 12'h0d1;
sinelut[8'd158] = 12'h0d4;
sinelut[8'd159] = 12'h0d7;
sinelut[8'd160] = 12'h0db;
sinelut[8'd161] = 12'h0de;
sinelut[8'd162] = 12'h0e2;
sinelut[8'd163] = 12'h0e5;
sinelut[8'd164] = 12'h0e9;
sinelut[8'd165] = 12'h0ec;
sinelut[8'd166] = 12'h0f0;
sinelut[8'd167] = 12'h0f4;
sinelut[8'd168] = 12'h0f8;
sinelut[8'd169] = 12'h0fb;
sinelut[8'd170] = 12'h0ff;
sinelut[8'd171] = 12'h103;
sinelut[8'd172] = 12'h107;
sinelut[8'd173] = 12'h10b;
sinelut[8'd174] = 12'h10f;
sinelut[8'd175] = 12'h114;
sinelut[8'd176] = 12'h118;
sinelut[8'd177] = 12'h11c;
sinelut[8'd178] = 12'h121;
sinelut[8'd179] = 12'h125;
sinelut[8'd180] = 12'h129;
sinelut[8'd181] = 12'h12e;
sinelut[8'd182] = 12'h133;
sinelut[8'd183] = 12'h137;
sinelut[8'd184] = 12'h13c;
sinelut[8'd185] = 12'h141;
sinelut[8'd186] = 12'h146;
sinelut[8'd187] = 12'h14b;
sinelut[8'd188] = 12'h150;
sinelut[8'd189] = 12'h155;
sinelut[8'd190] = 12'h15b;
sinelut[8'd191] = 12'h160;
sinelut[8'd192] = 12'h166;
sinelut[8'd193] = 12'h16b;
sinelut[8'd194] = 12'h171;
sinelut[8'd195] = 12'h177;
sinelut[8'd196] = 12'h17c;
sinelut[8'd197] = 12'h182;
sinelut[8'd198] = 12'h188;
sinelut[8'd199] = 12'h18f;
sinelut[8'd200] = 12'h195;
sinelut[8'd201] = 12'h19b;
sinelut[8'd202] = 12'h1a2;
sinelut[8'd203] = 12'h1a9;
sinelut[8'd204] = 12'h1b0;
sinelut[8'd205] = 12'h1b7;
sinelut[8'd206] = 12'h1be;
sinelut[8'd207] = 12'h1c5;
sinelut[8'd208] = 12'h1cd;
sinelut[8'd209] = 12'h1d4;
sinelut[8'd210] = 12'h1dc;
sinelut[8'd211] = 12'h1e4;
sinelut[8'd212] = 12'h1ec;
sinelut[8'd213] = 12'h1f5;
sinelut[8'd214] = 12'h1fd;
sinelut[8'd215] = 12'h206;
sinelut[8'd216] = 12'h20f;
sinelut[8'd217] = 12'h218;
sinelut[8'd218] = 12'h222;
sinelut[8'd219] = 12'h22c;
sinelut[8'd220] = 12'h236;
sinelut[8'd221] = 12'h240;
sinelut[8'd222] = 12'h24b;
sinelut[8'd223] = 12'h256;
sinelut[8'd224] = 12'h261;
sinelut[8'd225] = 12'h26d;
sinelut[8'd226] = 12'h279;
sinelut[8'd227] = 12'h286;
sinelut[8'd228] = 12'h293;
sinelut[8'd229] = 12'h2a0;
sinelut[8'd230] = 12'h2af;
sinelut[8'd231] = 12'h2bd;
sinelut[8'd232] = 12'h2cd;
sinelut[8'd233] = 12'h2dc;
sinelut[8'd234] = 12'h2ed;
sinelut[8'd235] = 12'h2ff;
sinelut[8'd236] = 12'h311;
sinelut[8'd237] = 12'h324;
sinelut[8'd238] = 12'h339;
sinelut[8'd239] = 12'h34e;
sinelut[8'd240] = 12'h365;
sinelut[8'd241] = 12'h37e;
sinelut[8'd242] = 12'h398;
sinelut[8'd243] = 12'h3b5;
sinelut[8'd244] = 12'h3d3;
sinelut[8'd245] = 12'h3f5;
sinelut[8'd246] = 12'h41a;
sinelut[8'd247] = 12'h443;
sinelut[8'd248] = 12'h471;
sinelut[8'd249] = 12'h4a6;
sinelut[8'd250] = 12'h4e4;
sinelut[8'd251] = 12'h52e;
sinelut[8'd252] = 12'h58b;
sinelut[8'd253] = 12'h607;
sinelut[8'd254] = 12'h6c3;
sinelut[8'd255] = 12'h859;
end
always @ (posedge clk) if(cen) begin
logsin <= sinelut[addr];
end
endmodule

276
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_mmr.v
View File

@@ -1,276 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 10-6-2020
*/
module jtopl_mmr(
input rst,
input clk,
input cen,
output cenop,
input [ 7:0] din,
input write,
input addr,
// location
output zero,
output [ 1:0] group,
output op,
output [17:0] slot,
output reg rhy_en,
// Timers
output reg [ 7:0] value_A,
output reg [ 7:0] value_B,
output reg load_A,
output reg load_B,
output reg flagen_A,
output reg flagen_B,
output reg clr_flag_A,
output reg clr_flag_B,
input flag_A,
input overflow_A,
// Phase Generator
output [ 9:0] fnum_I,
output [ 2:0] block_I,
output [ 3:0] mul_II,
output viben_I,
// Operator
output [ 1:0] wavsel_I,
// Envelope Generator
output keyon_I,
output en_sus_I, // enable sustain
output [ 3:0] arate_I, // attack rate
output [ 3:0] drate_I, // decay rate
output [ 3:0] rrate_I, // release rate
output [ 3:0] sl_I, // sustain level
output ks_II, // key scale
output [ 5:0] tl_IV,
output amen_IV,
// global values
output reg am_dep,
output reg vib_dep,
output [ 1:0] ksl_IV,
// Operator configuration
output [ 2:0] fb_I,
output con_I
);
parameter OPL_TYPE=1;
jtopl_div #(OPL_TYPE) u_div (
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.cenop ( cenop )
);
localparam [7:0] REG_TESTYM = 8'h01,
REG_CLKA = 8'h02,
REG_CLKB = 8'h03,
REG_TIMER = 8'h04,
REG_CSM = 8'h08,
REG_RYTHM = 8'hBD;
reg [ 7:0] selreg; // selected register
reg [ 7:0] din_copy;
reg csm, effect;
reg [ 1:0] sel_group; // group to update
reg [ 2:0] sel_sub; // subslot to update
reg up_fnumlo, up_fnumhi, up_fbcon,
up_mult, up_ksl_tl, up_ar_dr, up_sl_rr,
up_wav;
reg wave_mode, // 1 if waveform selection is enabled (OPL2)
csm_en,
note_sel; // keyboard split, not implemented
reg [ 4:0] rhy_kon;
// this runs at clk speed, no clock gating here
// if I try to make this an async rst it fails to map it
// as flip flops but uses latches instead. So I keep it as sync. reset
always @(posedge clk) begin
if( rst ) begin
selreg <= 8'h0;
sel_group <= 2'd0;
sel_sub <= 3'd0;
// Updaters
up_fbcon <= 0;
up_fnumlo <= 0;
up_fnumhi <= 0;
up_mult <= 0;
up_ksl_tl <= 0;
up_ar_dr <= 0;
up_sl_rr <= 0;
up_wav <= 0;
// Rhythms
rhy_en <= 0;
rhy_kon <= 5'd0;
// sensitivity to LFO
am_dep <= 0;
vib_dep <= 0;
csm_en <= 0;
note_sel <= 0;
// OPL2 waveforms
wave_mode <= 0;
// timers
{ value_A, value_B } <= 16'd0;
{ clr_flag_B, clr_flag_A, load_B, load_A } <= 4'd0;
flagen_A <= 1;
flagen_B <= 1;
din_copy <= 8'd0;
end else begin
// WRITE IN REGISTERS
if( write ) begin
if( !addr ) begin
selreg <= din;
end else begin
// Global registers
din_copy <= din;
up_fnumhi <= 0;
up_fnumlo <= 0;
up_fbcon <= 0;
up_mult <= 0;
up_ksl_tl <= 0;
up_ar_dr <= 0;
up_sl_rr <= 0;
up_wav <= 0;
// General control (<0x20 registers)
casez( selreg )
REG_TESTYM: if(OPL_TYPE>1) wave_mode <= din[5];
REG_CLKA: value_A <= din;
REG_CLKB: value_B <= din;
REG_TIMER: begin
clr_flag_A <= din[7] | din[6];
clr_flag_B <= din[7] | din[5];
if (~din[7]) begin
flagen_A <= ~din[6];
flagen_B <= ~din[5];
{ load_B, load_A } <= din[1:0];
end
end
REG_CSM: {csm_en, note_sel} <= din[7:6];
default:;
endcase
// Operator registers
// Mapping done according to Table 2-3, page 7 of YM3812 App. Manual
if( selreg >= 8'h20 &&
(selreg < 8'hA0 || (selreg>=8'hE0 && OPL_TYPE>1) ) &&
selreg[2:0]<=3'd5 && selreg[4:3]!=2'b11) begin
sel_group <= selreg[4:3];
sel_sub <= selreg[2:0];
case( selreg[7:5] )
3'b001: up_mult <= 1;
3'b010: up_ksl_tl <= 1;
3'b011: up_ar_dr <= 1;
3'b100: up_sl_rr <= 1;
3'b111: up_wav <= OPL_TYPE!=1;
default:;
endcase
end
// Channel registers
if( selreg[3:0]<=4'd8) begin
case( selreg[7:4] )
4'hA: up_fnumlo <= 1;
4'hB: up_fnumhi <= 1;
4'hC: up_fbcon <= 1;
default:;
endcase
end
if( selreg[7:4]>=4'hA && selreg[7:4]<4'hd
&& selreg[3:0]<=8 ) begin
// Each group has three channels
// Channels 0-2 -> group 0
// Channels 3-5 -> group 1
// Channels 6-8 -> group 2
// other -> group 3 - ignored
sel_group <= selreg[3:0] < 4'd3 ? 2'd0 :
selreg[3:0] < 4'd6 ? 2'd1 :
selreg[3:0] < 4'd9 ? 2'd2 : 2'd3;
sel_sub <= selreg[3:0] < 4'd6 ? selreg[2:0] :
{ 1'b0, ~&selreg[2:1], selreg[0] };
end
// Global register
if( selreg==REG_RYTHM ) begin
am_dep <= din[7];
vib_dep <= din[6];
rhy_en <= din[5];
rhy_kon <= din[4:0];
end
end
end
else if(cenop) begin /* clear once-only bits */
{ clr_flag_B, clr_flag_A } <= 2'd0;
end
end
end
jtopl_reg #(.OPL_TYPE(OPL_TYPE)) u_reg(
.rst ( rst ),
.clk ( clk ),
.cen ( cenop ),
.din ( din_copy ),
.write ( write ),
// Pipeline order
.zero ( zero ),
.group ( group ),
.op ( op ),
.slot ( slot ),
.sel_group ( sel_group ), // group to update
.sel_sub ( sel_sub ), // subslot to update
.rhy_en ( rhy_en ),
.rhy_kon ( rhy_kon ),
//input csm,
//input flag_A,
//input overflow_A,
.up_fbcon ( up_fbcon ),
.up_fnumlo ( up_fnumlo ),
.up_fnumhi ( up_fnumhi ),
.up_mult ( up_mult ),
.up_ksl_tl ( up_ksl_tl ),
.up_ar_dr ( up_ar_dr ),
.up_sl_rr ( up_sl_rr ),
.up_wav ( up_wav ),
// PG
.fnum_I ( fnum_I ),
.block_I ( block_I ),
.mul_II ( mul_II ),
.viben_I ( viben_I ),
// OP
.wavsel_I ( wavsel_I ),
.wave_mode ( wave_mode ),
// EG
.keyon_I ( keyon_I ),
.en_sus_I ( en_sus_I ),
.arate_I ( arate_I ),
.drate_I ( drate_I ),
.rrate_I ( rrate_I ),
.sl_I ( sl_I ),
.ks_II ( ks_II ),
.ksl_IV ( ksl_IV ),
.amen_IV ( amen_IV ),
.tl_IV ( tl_IV ),
// Timbre - Neiro
.fb_I ( fb_I ),
.con_I ( con_I )
);
endmodule

47
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_noise.v
View File

@@ -1,47 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 24-6-2020
*/
// Following research by Andete in
// https://github.com/andete/ym2413
// This has been research for the YM2413 (OPLL)
// I assume other OPL chips use the same one
module jtopl_noise(
input rst, // rst should be at least 6 clk&cen cycles long
input clk, // CPU clock
input cen, // optional clock enable, it not needed leave as 1'b1
output noise
);
reg [22:0] poly;
reg nbit;
assign noise = poly[22] ^ poly[9] ^ poly[8] ^ poly[0];
always @(posedge clk, posedge rst) begin
if( rst )
poly <= 1;
else if(cen) begin
poly <= poly==0 ? 23'd1 : { poly[21:0], noise };
end
end
endmodule

262
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_op.v
View File

@@ -1,262 +0,0 @@
/* This file is part of JTOPL.
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 19-6-2020
*/
module jtopl_op(
input rst,
input clk,
input cenop,
// these signals need be delayed
input [1:0] group,
input op, // 0 for modulator operators
input con_I,
input [2:0] fb_I, // voice feedback
input zero,
input [9:0] pg_phase_I,
input [1:0] wavsel_I,
input [9:0] eg_atten_II, // output from envelope generator
output reg signed [12:0] op_result,
output op_out,
output con_out
);
parameter OPL_TYPE=1;
localparam OPW=13, // Operator Width
PW=OPW*2; // Previous data Width
reg [11:0] level_II;
reg signbit_II, signbit_III;
reg nullify_II;
wire [ 8:0] ctrl_in, ctrl_dly;
wire [ 1:0] group_d;
wire op_d, con_I_d;
wire [ 1:0] wavsel_d;
wire [ 2:0] fb_I_d;
reg [PW-1:0] prev, prev0_din, prev1_din, prev2_din;
wire [PW-1:0] prev0, prev1, prev2;
assign ctrl_in = { wavsel_I, group, op, con_I, fb_I };
assign { wavsel_d, group_d, op_d, con_I_d, fb_I_d } = ctrl_dly;
jtopl_sh #( .width(9), .stages(3)) u_delay(
.clk ( clk ),
.cen ( cenop ),
.din ( ctrl_in ),
.drop ( ctrl_dly )
);
jtopl_sh #( .width(2), .stages(3)) u_condly(
.clk ( clk ),
.cen ( cenop ),
.din ( {op_d, con_I_d} ),
.drop ( {op_out, con_out} )
);
always @(*) begin
prev0_din = op_d && group_d==2'd0 ? { prev0[OPW-1:0], op_result } : prev0;
prev1_din = op_d && group_d==2'd1 ? { prev1[OPW-1:0], op_result } : prev1;
prev2_din = op_d && group_d==2'd2 ? { prev2[OPW-1:0], op_result } : prev2;
case( group_d )
default: prev = prev0;
2'd1: prev = prev1;
2'd2: prev = prev2;
endcase
end
jtopl_sh #( .width(PW), .stages(3)) u_csr0(
.clk ( clk ),
.cen ( cenop ),
.din ( prev0_din ),
.drop ( prev0 )
);
jtopl_sh #( .width(PW), .stages(3)) u_csr1(
.clk ( clk ),
.cen ( cenop ),
.din ( prev1_din ),
.drop ( prev1 )
);
jtopl_sh #( .width(PW), .stages(3)) u_csr2(
.clk ( clk ),
.cen ( cenop ),
.din ( prev2_din ),
.drop ( prev2 )
);
reg [ 10:0] subtresult;
reg [OPW-1:0] shifter;
wire signed [OPW-1:0] fb1 = prev[PW-1:OPW];
wire signed [OPW-1:0] fb0 = prev[OPW-1:0];
// REGISTER/CYCLE 1
// Creation of phase modulation (FM) feedback signal, before shifting
reg signed [OPW-1:0] modmux_I;
reg signed [OPW-1:0] fbmod_I;
always @(*) begin
modmux_I = op_d ? op_result : fb1+fb0;
// OPL-L shifts by 8-FB
// OPL3 shifts by 9-FB
// OPLL seems to use lower resolution for OPW so it makes
// sense that it shifts by one fewer
fbmod_I = modmux_I>>>(4'd9-{1'b0,fb_I_d});
end
reg signed [9:0] phasemod_I;
always @(*) begin
// Shift FM feedback signal
if (op_d)
phasemod_I = con_I_d ? 10'd0 : modmux_I[9:0];
else
phasemod_I = fb_I_d==3'd0 ? 10'd0 : fbmod_I[9:0];
end
reg [ 9:0] phase;
reg [ 7:0] aux_I;
always @(*) begin
phase = phasemod_I + pg_phase_I;
aux_I = phase[7:0] ^ {8{~phase[8]}};
end
// REGISTER/CYCLE 1
always @(posedge clk) if( cenop ) begin
if( OPL_TYPE==1 ) begin
signbit_II <= phase[9];
nullify_II <= 0;
end else begin
signbit_II <= wavsel_d==0 && phase[9];
nullify_II <= (wavsel_d==2'b01 && phase[9]) || (wavsel_d==2'b11 && phase[8]);
end
end
wire [11:0] logsin_II;
jtopl_logsin u_logsin (
.clk ( clk ),
.cen ( cenop ),
.addr ( aux_I[7:0] ),
.logsin ( logsin_II )
);
// REGISTER/CYCLE 2
// Sine table
// Main sine table body
always @(*) begin
subtresult = eg_atten_II + logsin_II[11:2];
level_II = { subtresult[9:0], logsin_II[1:0] } | {12{subtresult[10]}};
if( nullify_II ) begin
level_II = ~12'h0;
end
end
wire [9:0] mantissa_III;
reg [3:0] exponent_III;
jtopl_exprom u_exprom(
.clk ( clk ),
.cen ( cenop ),
.addr ( level_II[7:0] ),
.exp ( mantissa_III )
);
always @(posedge clk) if( cenop ) begin
exponent_III <= level_II[11:8];
signbit_III <= signbit_II;
end
// REGISTER/CYCLE 3
// 2's complement & Carry-out discarded
always @(*) begin
// Floating-point to integer, and incorporating sign bit
shifter = { 2'b01, mantissa_III,1'b0 } >> exponent_III;
end
// It looks like OPLL and OPL3 don't do full 2's complement but just bit inversion
always @(posedge clk) if( cenop ) begin
op_result <= ( shifter ^ {OPW{signbit_III}});// + {13'd0,signbit_III};
end
`ifdef SIMULATION
reg signed [OPW-1:0] op_sep0_0;
reg signed [OPW-1:0] op_sep1_0;
reg signed [OPW-1:0] op_sep2_0;
reg signed [OPW-1:0] op_sep0_1;
reg signed [OPW-1:0] op_sep1_1;
reg signed [OPW-1:0] op_sep2_1;
reg signed [OPW-1:0] op_sep4_0;
reg signed [OPW-1:0] op_sep5_0;
reg signed [OPW-1:0] op_sep6_0;
reg signed [OPW-1:0] op_sep4_1;
reg signed [OPW-1:0] op_sep5_1;
reg signed [OPW-1:0] op_sep6_1;
reg signed [OPW-1:0] op_sep7_0;
reg signed [OPW-1:0] op_sep8_0;
reg signed [OPW-1:0] op_sep9_0;
reg signed [OPW-1:0] op_sep7_1;
reg signed [OPW-1:0] op_sep8_1;
reg signed [OPW-1:0] op_sep9_1;
reg [ 4:0] sepcnt;
always @(posedge clk) if(cenop) begin
sepcnt <= zero ? 5'd0 : sepcnt+5'd1;
case( (sepcnt+3)%18 )
0: op_sep0_0 <= op_result;
1: op_sep1_0 <= op_result;
2: op_sep2_0 <= op_result;
3: op_sep0_1 <= op_result;
4: op_sep1_1 <= op_result;
5: op_sep2_1 <= op_result;
6: op_sep4_0 <= op_result;
7: op_sep5_0 <= op_result;
8: op_sep6_0 <= op_result;
9: op_sep4_1 <= op_result;
10: op_sep5_1 <= op_result;
11: op_sep6_1 <= op_result;
12: op_sep7_0 <= op_result;
13: op_sep8_0 <= op_result;
14: op_sep9_0 <= op_result;
15: op_sep7_1 <= op_result;
16: op_sep8_1 <= op_result;
17: op_sep9_1 <= op_result;
endcase
end
`endif
endmodule

129
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_pg.v
View File

@@ -1,129 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
module jtopl_pg(
input rst,
input clk,
input cenop,
input [17:0] slot,
input rhy_en,
// Channel frequency
input [ 9:0] fnum_I,
input [ 2:0] block_I,
// Operator multiplying
input [ 3:0] mul_II,
// phase modulation from LFO (vibrato at 6.4Hz)
input [ 2:0] vib_cnt,
input vib_dep,
input viben_I,
// phase operation
input pg_rst_II,
output reg [ 3:0] keycode_II,
output [ 9:0] phase_IV
);
parameter CH=9;
wire [ 3:0] keycode_I;
wire [16:0] phinc_I;
reg [16:0] phinc_II;
wire [18:0] phase_drop, phase_in;
wire [ 9:0] phase_II;
wire noise;
reg [ 9:0] hh, tc;
reg rm_xor;
wire hh_en, sd_en, tc_en;
always @(posedge clk) if(cenop) begin
keycode_II <= keycode_I;
phinc_II <= phinc_I;
end
// Rhythm phase
always @(posedge clk, posedge rst) begin
if( rst ) begin
hh <= 10'd0;
tc <= 10'd0;
end else begin
if( slot[13] ) hh <= phase_drop[18:9];
if( slot[17] ) tc <= phase_drop[18:9];
rm_xor <= (hh[2]^hh[7]) | (hh[3]^tc[5]) | (tc[3]^tc[5]);
end
end
assign hh_en = rhy_en & slot[14]; // 13+1
assign sd_en = rhy_en & slot[17]; // 16+1
assign tc_en = rhy_en & slot[ 0]; // (17+1)%18
jtopl_noise u_noise(
.clk ( clk ),
.cen ( cenop ),
.rst ( rst ),
.noise ( noise )
);
jtopl_pg_comb u_comb(
.block ( block_I ),
.fnum ( fnum_I ),
// Phase Modulation
.vib_cnt ( vib_cnt ),
.vib_dep ( vib_dep ),
.viben ( viben_I ),
.keycode ( keycode_I ),
// Phase increment
.phinc_out ( phinc_I ),
// Phase add
.mul ( mul_II ),
.phase_in ( phase_drop ),
.pg_rst ( pg_rst_II ),
.phinc_in ( phinc_II ),
// Rhythm
.hh_en ( hh_en ),
.sd_en ( sd_en ),
.tc_en ( tc_en ),
.rm_xor ( rm_xor ),
.noise ( noise ),
.hh ( hh ),
.phase_out ( phase_in ),
.phase_op ( phase_II )
);
jtopl_sh_rst #( .width(19), .stages(2*CH) ) u_phsh(
.clk ( clk ),
.cen ( cenop ),
.rst ( rst ),
.din ( phase_in ),
.drop ( phase_drop)
);
jtopl_sh_rst #( .width(10), .stages(2) ) u_pad(
.clk ( clk ),
.cen ( cenop ),
.rst ( rst ),
.din ( phase_II ),
.drop ( phase_IV )
);
endmodule

95
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_pg_comb.v
View File

@@ -1,95 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
module jtopl_pg_comb (
input [ 2:0] block,
input [ 9:0] fnum,
// Phase Modulation
input [ 2:0] vib_cnt,
input vib_dep,
input viben,
output [ 3:0] keycode,
// Phase increment
output [16:0] phinc_out,
// Phase add
input [ 3:0] mul,
input [18:0] phase_in,
input pg_rst,
// input signed [7:0] pm_in,
input [16:0] phinc_in,
// Rhythm
input noise,
input [ 9:0] hh,
input hh_en,
input tc_en,
input sd_en,
input rm_xor,
output [18:0] phase_out,
output [ 9:0] phase_op
);
wire signed [3:0] pm_offset;
wire [9:0] phase_pre;
assign keycode = { block, fnum[9] };
/* pm and pg_inc operate in parallel */
jtopl_pm u_pm(
.vib_cnt ( vib_cnt ),
.fnum ( fnum ),
.vib_dep ( vib_dep ),
.viben ( viben ),
.pm_offset ( pm_offset )
);
jtopl_pg_inc u_inc(
.block ( block ),
.fnum ( fnum ),
.pm_offset ( pm_offset ),
.phinc_pure ( phinc_out )
);
// pg_sum uses the output from the previous blocks
jtopl_pg_sum u_sum(
.mul ( mul ),
.phase_in ( phase_in ),
.pg_rst ( pg_rst ),
.phinc_pure ( phinc_in ),
.phase_out ( phase_out ),
.phase_op ( phase_pre )
);
jtopl_pg_rhy u_rhy(
.phase_pre ( phase_pre ),
// Rhythm
.noise ( noise ),
.hh ( hh ),
.hh_en ( hh_en ),
.tc_en ( tc_en ),
.sd_en ( sd_en ),
.rm_xor ( rm_xor ),
.phase_op ( phase_op )
);
endmodule // jtopl_pg_comb

38
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_pg_inc.v
View File

@@ -1,38 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
module jtopl_pg_inc (
input [ 2:0] block,
input [ 9:0] fnum,
input signed [ 3:0] pm_offset,
output reg [16:0] phinc_pure
);
reg [16:0] freq;
always @(*) begin
freq = { 7'd0, fnum } + { {13{pm_offset[3]}}, pm_offset };
// Add PM here
freq = freq << block;
phinc_pure = freq >> 1;
end
endmodule // jtopl_pg_inc

49
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_pg_rhy.v
View File

@@ -1,49 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 25-6-2020
*/
module jtopl_pg_rhy (
input [ 9:0] phase_pre,
// Rhythm
input noise,
input [ 9:0] hh,
input hh_en,
input tc_en,
input sd_en,
input rm_xor,
output reg [ 9:0] phase_op
);
always @(*) begin
if( hh_en ) begin
phase_op = {rm_xor, 9'd0 };
if( rm_xor ^ noise )
phase_op = phase_op | 10'hd0;
else
phase_op = phase_op | 10'h34;
end else if( sd_en ) begin
phase_op = { hh[8], hh[8]^noise, 8'd0 };
end else if( tc_en ) begin
phase_op = { rm_xor, 9'h80 };
end else
phase_op = phase_pre;
end
endmodule // jtopl_pg_sum

52
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_pg_sum.v
View File

@@ -1,52 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
// Original hardware uses an adder to do the multiplication
// but I think it will take less resources of the FPGA to
// use a real multiplier instead
module jtopl_pg_sum (
input [ 3:0] mul,
input [18:0] phase_in,
input pg_rst,
input [16:0] phinc_pure,
output reg [18:0] phase_out,
output reg [ 9:0] phase_op
);
reg [21:0] phinc_mul;
reg [ 4:0] factor[0:15];
always @(*) begin
phinc_mul = { 5'b0, phinc_pure} * factor[mul];
phase_out = pg_rst ? 'd0 : (phase_in + phinc_mul[19:1]);
phase_op = phase_out[18:9];
end
initial begin
factor[ 0] = 5'd01; factor[ 1] = 5'd02; factor[ 2] = 5'd04; factor[ 3] = 5'd06;
factor[ 4] = 5'd08; factor[ 5] = 5'd10; factor[ 6] = 5'd12; factor[ 7] = 5'd14;
factor[ 8] = 5'd16; factor[ 9] = 5'd18; factor[10] = 5'd20; factor[11] = 5'd20;
factor[12] = 5'd24; factor[13] = 5'd24; factor[14] = 5'd30; factor[15] = 5'd30;
end
endmodule // jtopl_pg_sum

47
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_pm.v
View File

@@ -1,47 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-6-2020
*/
// Based on Nuked's work on OPLL and OPL3
module jtopl_pm (
input [ 2:0] vib_cnt,
input [ 9:0] fnum,
input vib_dep,
input viben,
output reg [ 3:0] pm_offset
);
reg [2:0] range;
always @(*) begin
if( vib_cnt[1:0]==2'b00 )
range = 3'd0;
else begin
range = fnum[9:7]>>vib_cnt[0];
if(!vib_dep) range = range>>1;
end
if( vib_cnt[2] )
pm_offset = ~{1'b0, range } + 4'd1;
else
pm_offset = {1'b0, range };
if(!viben) pm_offset = 4'd0;
end
endmodule

199
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_reg.v
View File

@@ -1,199 +0,0 @@
/* This file is part of JTOPL
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
module jtopl_reg(
input rst,
input clk,
input cen,
input [7:0] din,
input write,
// Pipeline order
output zero,
output [1:0] group,
output op, // 0 for modulator operators
output [17:0] slot, // hot one encoding of active slot
input [1:0] sel_group, // group to update
input [2:0] sel_sub, // subslot to update
input rhy_en, // rhythm enable
input [4:0] rhy_kon, // key-on for each rhythm instrument
//input csm,
//input flag_A,
//input overflow_A,
input up_fbcon,
input up_fnumlo,
input up_fnumhi,
input up_mult,
input up_ksl_tl,
input up_ar_dr,
input up_sl_rr,
input up_wav,
// PG
output [9:0] fnum_I,
output [2:0] block_I,
// channel configuration
output [2:0] fb_I,
output [3:0] mul_II, // frequency multiplier
output [1:0] ksl_IV, // key shift level
output amen_IV,
output viben_I,
// OP
output [1:0] wavsel_I,
input wave_mode,
// EG
output keyon_I,
output [5:0] tl_IV,
output en_sus_I, // enable sustain
output [3:0] arate_I, // attack rate
output [3:0] drate_I, // decay rate
output [3:0] rrate_I, // release rate
output [3:0] sl_I, // sustain level
output ks_II, // key scale
output con_I
);
parameter OPL_TYPE=1;
localparam CH=9;
wire [2:0] subslot;
wire match;
// channel data
wire [2:0] fb_in = din[3:1];
wire con_in = din[0];
wire up_fnumlo_ch = up_fnumlo & match,
up_fnumhi_ch = up_fnumhi & match,
up_fbcon_ch = up_fbcon & match,
update_op_I = !write && sel_group == group && sel_sub == subslot;
reg update_op_II, update_op_III, update_op_IV;
assign match = { group, subslot } == { sel_group, sel_sub};
jtopl_slot_cnt u_slot_cnt(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
// Pipeline order
.zero ( zero ),
.group ( group ),
.op ( op ), // 0 for modulator operators
.subslot(subslot),
.slot ( slot ) // hot one encoding of active slot
);
always @(posedge clk) begin
if(write) begin
update_op_II <= 0;
update_op_III <= 0;
update_op_IV <= 0;
end else if( cen ) begin
update_op_II <= update_op_I;
update_op_III <= update_op_II;
update_op_IV <= update_op_III;
end
end
localparam OPCFGW = 4*8 + (OPL_TYPE!=1 ? 2 : 0);
wire [OPCFGW-1:0] shift_out;
wire en_sus, rhy_oen;
// Sustained is disabled in rhythm mode for channels in group 2 (i.e. 6,7,8)
assign en_sus_I = rhy_oen ? 1'b0 : en_sus;
jtopl_csr #(.LEN(CH*2),.W(OPCFGW)) u_csr(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( din ),
.shift_out ( shift_out ),
.up_mult ( up_mult ),
.up_ksl_tl ( up_ksl_tl ),
.up_ar_dr ( up_ar_dr ),
.up_sl_rr ( up_sl_rr ),
.up_wav ( up_wav ),
.update_op_I ( update_op_I ),
.update_op_II ( update_op_II ),
.update_op_IV ( update_op_IV )
);
assign { amen_IV, viben_I, en_sus, ks_II, mul_II,
ksl_IV, tl_IV,
arate_I, drate_I,
sl_I, rrate_I } = shift_out[4*8-1:0];
generate
if( OPL_TYPE==1 )
assign wavsel_I = 0;
else
assign wavsel_I = shift_out[OPCFGW-1:OPCFGW-2] & {2{wave_mode}};
endgenerate
// Memory for CH registers
localparam KONW = 1,
FNUMW = 10,
BLOCKW = 3,
FBW = 3,
CONW = 1;
localparam CHCSRW = KONW+FNUMW+BLOCKW+FBW+CONW;
wire [CHCSRW-1:0] chcfg, chcfg_inmux;
wire keyon_csr, con_csr, rhyon_csr;
wire disable_con;
assign chcfg_inmux = {
up_fnumhi_ch ? din[5:0] : { keyon_csr, block_I, fnum_I[9:8] },
up_fnumlo_ch ? din : fnum_I[7:0],
up_fbcon_ch ? { fb_in, con_in } : { fb_I, con_csr }
};
assign disable_con = rhy_oen && !slot[12] && !slot[13];
assign con_I = !rhy_en || !disable_con ? con_csr : 1'b1;
assign { keyon_csr, block_I, fnum_I, fb_I, con_csr } = chcfg;
assign keyon_I = rhy_oen ? rhyon_csr : keyon_csr;
jtopl_reg_ch#(CHCSRW) u_reg_ch(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.zero ( zero ),
.rhy_en ( rhy_en ),
.rhy_kon ( rhy_kon ),
.slot ( slot ),
.group ( group ),
.chcfg_inmux ( chcfg_inmux ),
.chcfg ( chcfg ),
.rhy_oen ( rhy_oen ),
.rhyon_csr ( rhyon_csr )
);
endmodule

111
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_reg_ch.v
View File

@@ -1,111 +0,0 @@
/* This file is part of JTOPL
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 28-5-2022
*/
module jtopl_reg_ch#( parameter
CHCSRW = 10
) (
input rst,
input clk,
input cen,
input zero,
input rhy_en,
input [4:0] rhy_kon,
input [17:0] slot,
input [1:0] group,
input [CHCSRW-1:0] chcfg_inmux,
output reg [CHCSRW-1:0] chcfg,
output reg rhy_oen, // high for rhythm operators if rhy_en is set
output rhyon_csr
);
// Rhythm key-on CSR
localparam BD=4, SD=3, TOM=2, TC=1, HH=0;
reg [CHCSRW-1:0] chcfg0_in, chcfg1_in, chcfg2_in;
wire [CHCSRW-1:0] chcfg0_out, chcfg1_out, chcfg2_out;
reg [5:0] rhy_csr;
assign rhyon_csr = rhy_csr[5];
always @(*) begin
case( group )
default: chcfg = chcfg0_out;
2'd1: chcfg = chcfg1_out;
2'd2: chcfg = chcfg2_out;
endcase
chcfg0_in = group==2'b00 ? chcfg_inmux : chcfg0_out;
chcfg1_in = group==2'b01 ? chcfg_inmux : chcfg1_out;
chcfg2_in = group==2'b10 ? chcfg_inmux : chcfg2_out;
end
`ifdef SIMULATION
reg [CHCSRW-1:0] chsnap0, chsnap1,chsnap2;
always @(posedge clk) if(zero) begin
chsnap0 <= chcfg0_out;
chsnap1 <= chcfg1_out;
chsnap2 <= chcfg2_out;
end
`endif
always @(posedge clk, posedge rst) begin
if( rst ) begin
rhy_csr <= 6'd0;
rhy_oen <= 0;
end else if(cen) begin
if(slot[11]) rhy_oen <= rhy_en;
if(slot[17]) begin
rhy_csr <= { rhy_kon[BD], rhy_kon[HH], rhy_kon[TOM],
rhy_kon[BD], rhy_kon[SD], rhy_kon[TC] };
rhy_oen <= 0;
end else
rhy_csr <= { rhy_csr[4:0], rhy_csr[5] };
end
end
jtopl_sh_rst #(.width(CHCSRW),.stages(3)) u_group0(
.clk ( clk ),
.cen ( cen ),
.rst ( rst ),
.din ( chcfg0_in ),
.drop ( chcfg0_out )
);
jtopl_sh_rst #(.width(CHCSRW),.stages(3)) u_group1(
.clk ( clk ),
.cen ( cen ),
.rst ( rst ),
.din ( chcfg1_in ),
.drop ( chcfg1_out )
);
jtopl_sh_rst #(.width(CHCSRW),.stages(3)) u_group2(
.clk ( clk ),
.cen ( cen ),
.rst ( rst ),
.din ( chcfg2_in ),
.drop ( chcfg2_out )
);
endmodule

42
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_sh.v
View File

@@ -1,42 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 19-6-2020
*/
// stages must be greater than 2
module jtopl_sh #(parameter width=5, stages=24 )
(
input clk,
input cen,
input [width-1:0] din,
output [width-1:0] drop
);
reg [stages-1:0] bits[width-1:0];
genvar i;
generate
for (i=0; i < width; i=i+1) begin: bit_shifter
always @(posedge clk) if(cen) begin
bits[i] <= {bits[i][stages-2:0], din[i]};
end
assign drop[i] = bits[i][stages-1];
end
endgenerate
endmodule

54
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_sh_rst.v
View File

@@ -1,54 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
// stages must be greater than 2
module jtopl_sh_rst #(parameter width=5, stages=18, rstval=1'b0 )
(
input rst,
input clk,
input cen,
input [width-1:0] din,
output [width-1:0] drop
);
reg [stages-1:0] bits[width-1:0];
genvar i;
integer k;
generate
initial
for (k=0; k < width; k=k+1) begin
bits[k] = { stages{rstval}};
end
endgenerate
generate
for (i=0; i < width; i=i+1) begin: bit_shifter
always @(posedge clk, posedge rst)
if( rst ) begin
bits[i] <= {stages{rstval}};
end else if(cen) begin
bits[i] <= {bits[i][stages-2:0], din[i]};
end
assign drop[i] = bits[i][stages-1];
end
endgenerate
endmodule

61
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_single_acc.v
View File

@@ -1,61 +0,0 @@
/* This file is part of JTOPL.
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 20-6-2020
*/
// Accumulates an arbitrary number of inputs with saturation
// restart the sum when input "zero" is high
module jtopl_single_acc #(parameter
INW=13, // input data width
OUTW=16 // output data width
)(
input clk,
input cenop,
input [INW-1:0] op_result,
input sum_en,
input zero,
output reg [OUTW-1:0] snd
);
// for full resolution use INW=14, OUTW=16
// for cut down resolution use INW=9, OUTW=12
// OUTW-INW should be > 0
reg signed [OUTW-1:0] next, acc, current;
reg overflow;
wire [OUTW-1:0] plus_inf = { 1'b0, {(OUTW-1){1'b1}} }; // maximum positive value
wire [OUTW-1:0] minus_inf = { 1'b1, {(OUTW-1){1'b0}} }; // minimum negative value
always @(*) begin
current = sum_en ? { {(OUTW-INW){op_result[INW-1]}}, op_result } : {OUTW{1'b0}};
next = zero ? current : current + acc;
overflow = !zero &&
(current[OUTW-1] == acc[OUTW-1]) &&
(acc[OUTW-1]!=next[OUTW-1]);
end
always @(posedge clk) if( cenop ) begin
acc <= overflow ? (acc[OUTW-1] ? minus_inf : plus_inf) : next;
if(zero) snd <= acc;
end
endmodule

65
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_slot_cnt.v
View File

@@ -1,65 +0,0 @@
/* This file is part of JTOPL
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
module jtopl_slot_cnt(
input rst,
input clk,
input cen,
// Pipeline order
output zero,
output reg [ 1:0] group,
output reg op, // 0 for modulator operators
output reg [ 2:0] subslot,
output reg [17:0] slot // hot one encoding of active slot
);
// Each group contains three channels
// and each subslot contains six operators
wire [2:0] next_sub = subslot==3'd5 ? 3'd0 : (subslot+3'd1);
wire [1:0] next_group = subslot==3'd5 ? (group==2'b10 ? 2'b00 : group+2'b1) : group;
`ifdef SIMULATION
// These signals need to operate during rst
// initial state is not relevant (or critical) in real life
// but we need a clear value during simulation
initial begin
group = 2'd0;
subslot = 3'd0;
slot = 18'd1;
end
`endif
assign zero = slot[0];
always @(posedge clk) begin : up_counter
if( cen ) begin
{ group, subslot } <= { next_group, next_sub };
if( { next_group, next_sub }==5'd0 ) begin
slot <= 18'd1;
end else begin
slot <= { slot[16:0], 1'b0 };
end
op <= next_sub >= 3'd3;
end
end
endmodule

125
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopl_timers.v
View File

@@ -1,125 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 10-6-2020
*/
module jtopl_timers(
input clk,
input rst,
input cenop,
input zero,
input [7:0] value_A,
input [7:0] value_B,
input load_A,
input load_B,
input clr_flag_A,
input clr_flag_B,
output flag_A,
output flag_B,
input flagen_A,
input flagen_B,
output overflow_A,
output irq_n
);
wire pre_A, pre_B;
assign flag_A = pre_A & flagen_A;
assign flag_B = pre_B & flagen_B;
assign irq_n = ~( flag_A | flag_B );
// 1 count per 288 master clock ticks
jtopl_timer #(.MW(2)) timer_A (
.clk ( clk ),
.rst ( rst ),
.cenop ( cenop ),
.zero ( zero ),
.start_value( value_A ),
.load ( load_A ),
.clr_flag ( clr_flag_A),
.flag ( pre_A ),
.overflow ( overflow_A)
);
// 1 count per 288*4 master clock ticks
jtopl_timer #(.MW(4)) timer_B(
.clk ( clk ),
.rst ( rst ),
.cenop ( cenop ),
.zero ( zero ),
.start_value( value_B ),
.load ( load_B ),
.clr_flag ( clr_flag_B),
.flag ( pre_B ),
.overflow ( )
);
endmodule
module jtopl_timer #(parameter MW=2) (
input clk,
input rst,
input cenop,
input zero,
input [7:0] start_value,
input load,
input clr_flag,
output reg flag,
output reg overflow
);
reg [7:0] cnt, next, init;
reg [MW-1:0] free_cnt, free_next;
reg load_l, free_ov;
always@(posedge clk)
if( clr_flag || rst)
flag <= 1'b0;
else if(cenop && zero && load && overflow) flag<=1'b1;
always @(*) begin
{free_ov, free_next} = { 1'b0, free_cnt} + 1'b1;
/* verilator lint_off WIDTH */
{overflow, next } = {1'b0, cnt}+free_ov;
/* verilator lint_on WIDTH */
init = start_value;
end
always @(posedge clk) begin
load_l <= load;
if( (!load_l && load) || rst) begin
cnt <= start_value;
end else if( cenop && zero && load ) begin
cnt <= overflow ? init : next;
end
end
// Free running counter, resetting
// the value of this part with the load
// event can slow down music, vg Bad Dudes
always @(posedge clk) begin
if( rst ) begin
free_cnt <= 0;
end else if( cenop && zero ) begin
free_cnt <= free_next;
end
end
endmodule

207
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopll_mmr.v
View File

@@ -1,207 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 10-6-2020
*/
module jtopll_mmr(
input rst,
input clk,
input cen,
output cenop,
input [ 7:0] din,
input write,
input addr,
// location
output zero,
output [ 1:0] group,
output op,
output [17:0] slot,
output reg rhy_en,
// Phase Generator
output [ 8:0] fnum_I,
output [ 2:0] block_I,
output [ 3:0] mul_II,
output viben_I,
// Operator
output [ 1:0] wavsel_I,
// Envelope Generator
output keyon_I,
output en_sus_I, // enable sustain
output [ 3:0] arate_I, // attack rate
output [ 3:0] drate_I, // decay rate
output [ 3:0] rrate_I, // release rate
output [ 3:0] sl_I, // sustain level
output ks_II, // key scale
output [ 5:0] tl_IV,
output amen_IV,
// global values
output reg am_dep,
output reg vib_dep,
output [ 1:0] ksl_IV,
// Operator configuration
output [ 2:0] fb_I,
output con_I
);
parameter OPL_TYPE=1;
jtopl_div #(OPL_TYPE) u_div (
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.cenop ( cenop )
);
localparam [7:0] REG_TESTYM = 8'h0F,
REG_RYTHM = 8'h0E;
reg [ 7:0] selreg; // selected register
reg [ 7:0] din_copy;
reg csm, effect;
reg [ 1:0] sel_group; // group to update
reg [ 2:0] sel_sub; // subslot to update
reg up_fnumlo, up_fnumhi, up_inst,
up_original;
reg wave_mode, // 1 if waveform selection is enabled (OPL2)
csm_en,
note_sel; // keyboard split, not implemented
reg [ 4:0] rhy_kon;
// this runs at clk speed, no clock gating here
// if I try to make this an async rst it fails to map it
// as flip flops but uses latches instead. So I keep it as sync. reset
always @(posedge clk) begin
if( rst ) begin
selreg <= 0;
sel_group <= 0;
sel_sub <= 0;
// Updaters
up_inst <= 0;
up_fnumlo <= 0;
up_fnumhi <= 0;
up_original <= 0;
// Rhythms
rhy_en <= 0;
rhy_kon <= 0;
// sensitivity to LFO
am_dep <= 0;
vib_dep <= 0;
csm_en <= 0;
note_sel <= 0;
// OPL2 waveforms
wave_mode <= 0;
din_copy <= 0;
end else begin
// WRITE IN REGISTERS
if( write ) begin
if( !addr ) begin
selreg <= din;
end else begin
// Global registers
din_copy <= din;
up_fnumhi <= 0;
up_fnumlo <= 0;
up_inst <= 0;
up_original <= 0;
// Operator registers
// Mapping done according to Table 2-3, page 7 of YM3812 App. Manual
if( selreg < 8 ) begin
up_original <= 1;
sel_sub <= selreg[2:0];
end
// Channel registers
if( selreg[3:0]<=4'd8) begin
case( selreg[7:4] )
4'h1: up_fnumlo <= 1;
4'h2: up_fnumhi <= 1;
4'h3: up_inst <= 1;
default:;
endcase
end
if( selreg[7:4]>=4'h1 && selreg[7:4]<4'h4
&& selreg[3:0]<=8 ) begin
// Each group has three channels
// Channels 0-2 -> group 0
// Channels 3-5 -> group 1
// Channels 6-8 -> group 2
// other -> group 3 - ignored
sel_group <= selreg[3:0] < 4'd3 ? 2'd0 :
selreg[3:0] < 4'd6 ? 2'd1 :
selreg[3:0] < 4'd9 ? 2'd2 : 2'd3;
sel_sub <= selreg[3:0] < 4'd6 ? selreg[2:0] :
{ 1'b0, ~&selreg[2:1], selreg[0] };
end
// Global register
if( selreg==REG_RYTHM ) begin
am_dep <= din[7];
vib_dep <= din[6];
rhy_en <= din[5];
rhy_kon <= din[4:0];
end
end
end
end
end
jtopll_reg u_reg(
.rst ( rst ),
.clk ( clk ),
.cen ( cenop ),
.din ( din_copy ),
// Pipeline order
.zero ( zero ),
.group ( group ),
.op ( op ),
.slot ( slot ),
.sel_group ( sel_group ), // group to update
.sel_sub ( sel_sub ), // subslot to update
.rhy_en ( rhy_en ),
.rhy_kon ( rhy_kon ),
.up_original( up_original ),
.up_inst ( up_inst ),
.up_fnumlo ( up_fnumlo ),
.up_fnumhi ( up_fnumhi ),
// PG
.fnum_I ( fnum_I ),
.block_I ( block_I ),
.mul_II ( mul_II ),
.viben_I ( viben_I ),
// OP
.wavsel_I ( wavsel_I ),
.wave_mode ( wave_mode ),
// EG
.keyon_I ( keyon_I ),
.en_sus_I ( en_sus_I ),
.arate_I ( arate_I ),
.drate_I ( drate_I ),
.rrate_I ( rrate_I ),
.sl_I ( sl_I ),
.ks_II ( ks_II ),
.ksl_IV ( ksl_IV ),
.amen_IV ( amen_IV ),
.tl_IV ( tl_IV ),
// Timbre - Neiro
.fb_I ( fb_I ),
.con_I ( con_I )
);
endmodule

208
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/hdl/jtopll_reg.v
View File

@@ -1,208 +0,0 @@
/* This file is part of JTOPL
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-5-2022
*/
module jtopll_reg(
input rst,
input clk,
input cen,
input [7:0] din,
input rhy_en, // rhythm enable
input [4:0] rhy_kon, // key-on for each rhythm instrument
// Pipeline order
output zero,
output [1:0] group,
output op, // 0 for modulator operators
output [17:0] slot, // hot one encoding of active slot
// Register update
input [1:0] sel_group, // group to update
input [2:0] sel_sub, // subslot to update
input up_fnumlo,
input up_fnumhi,
input up_inst,
input up_original,
// PG
output [8:0] fnum_I,
output [2:0] block_I,
// channel configuration
output [2:0] fb_I,
output reg [3:0] mul_II, // frequency multiplier
output [1:0] ksl_IV, // key shift level
output amen_IV,
output viben_I,
// OP
output [1:0] wavsel_I,
input wave_mode,
// EG
output keyon_I,
output [5:0] tl_IV,
output en_sus_I, // enable sustain
output [3:0] arate_I, // attack rate
output [3:0] drate_I, // decay rate
output [3:0] rrate_I, // release rate
output [3:0] sl_I, // sustain level
output reg ks_II, // key scale
output con_I // 1 for adding the modulator operator at the accumulator
// carrier op. are always added
);
localparam CH=9;
reg [ 5:0] rhy_csr;
wire rhy_oen, rhyon_csr;
wire [ 2:0] subslot;
wire match;
wire [ 3:0] vol_I; // channel volume
wire [ 5:0] tl_I;
wire [ 1:0] ksl_I;
wire [ 3:0] mul_I;
wire amen_I, ks_I;
// The original instrument (programmable patch) is at location 0
reg [63:0] patch[0:(16+6-1)]; // instrument memory, 15 instruments + original + 6 drums
wire [ 3:0] inst_I;
wire [ 4:0] inst_sel;
assign wavsel_I[1] = 0;
assign match = { group, subslot } == { sel_group, sel_sub};
jtopl_slot_cnt u_slot_cnt(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
// Pipeline order
.zero ( zero ),
.group ( group ),
.op ( op ), // 0 for modulator operators
.subslot(subslot ),
.slot ( slot ) // hot one encoding of active slot
);
always @(posedge clk, posedge rst) begin
if( rst ) begin
patch[00]<=64'h0000000000000000;
patch[01]<=64'h170078D0171E6171;
patch[02]<=64'h1323F7D80D1A4113;
patch[03]<=64'h2311C4F200990113;
patch[04]<=64'h277064A8070E6131;
patch[05]<=64'h280076E0061E2132;
patch[06]<=64'h180071E005162231;
patch[07]<=64'h07108182071D6121;
patch[08]<=64'h070072A2142D2123;
patch[09]<=64'h17106564061B6161;
patch[10]<=64'h0771F785180B6141;
patch[11]<=64'h0410E4FA11830113;
patch[12]<=64'h1222F8F80724C117;
patch[13]<=64'h4220F5C2050C5061;
patch[14]<=64'h020395C903550101;
patch[15]<=64'h1340E4F103894161;
patch[16]<=64'h006A00DF0F180001;
patch[17]<=64'h00A700C800000001;
patch[18]<=64'h005900F800000005;
patch[19]<=64'h6D00F80000000100;
patch[20]<=64'h4800D80000000100;
patch[21]<=64'h5500AA0000000100;
end else begin
if( up_original ) begin
patch[0][ {sel_sub,3'd0} +: 8 ] <= din;
end
end
end
// Selects the current patch
assign inst_sel = rhy_oen ? { 2'b10, subslot } : { 1'b0, inst_I };
assign { amen_I, viben_I, en_sus_I, ks_I, mul_I } = patch[ inst_sel ][ (op ? 8:0) +: 8 ];
assign ksl_I = patch[ inst_sel ][ (op ? 31:23) -: 2 ];
assign tl_I =
rhy_oen & (slot[13] | slot[14]) ? { inst_I, 2'd0 } : // HH and TT have the volume set this way
op ? { vol_I, 2'd0 } : patch[ inst_sel ][ 16 +: 6 ];
assign wavsel_I[0] = patch[ inst_sel ][ op ? 28 : 27];
assign fb_I = op ? 3'd0 : patch[ inst_sel ][ 24 +: 3 ];
assign { arate_I, drate_I } = patch[ inst_sel ][ (op ? 40 : 32) +: 8 ];
assign { sl_I, rrate_I } = patch[ inst_sel ][ op ? 56 : 48 +: 8 ];
always @(posedge clk, posedge rst) begin
if( rst ) begin
{ ks_II, mul_II } <= 0;
end else if(cen) begin
{ ks_II, mul_II } <= { ks_I, mul_I };
end
end
jtopl_sh_rst #(.width(2+1+6),.stages(3)) u_iv(
.clk ( clk ),
.cen ( cen ),
.rst ( rst ),
.din ( { ksl_I, amen_I, tl_I } ),
.drop ( { ksl_IV, amen_IV, tl_IV } )
);
// Memory for CH registers
localparam KONW = 1,
SUSENW = 1,
FNUMW = 9,
BLOCKW = 3,
INSTW = 4,
VOLW = 4;
localparam CHCSRW = SUSENW+KONW+FNUMW+BLOCKW+INSTW+VOLW;
wire [CHCSRW-1:0] chcfg, chcfg_inmux;
wire sus_en, keyon_csr, con_csr;
wire up_fnumlo_ch = up_fnumlo & match,
up_fnumhi_ch = up_fnumhi & match,
up_inst_ch = up_inst & match;
assign chcfg_inmux = {
up_fnumhi_ch ? din[5:0] : { sus_en, keyon_csr, block_I, fnum_I[8] },
up_fnumlo_ch ? din : fnum_I[7:0],
up_inst_ch ? din : { inst_I, vol_I }
};
assign con_I = rhy_oen && !slot[12]; // slot 12 = BD, which uses modulation
// slots 13/14 as rhythm, need to be added in the accumulator, so con_I is set to 1
assign { sus_en, keyon_csr, block_I, fnum_I[8:0], inst_I, vol_I } = chcfg;
assign keyon_I = rhy_oen ? rhyon_csr : keyon_csr;
jtopl_reg_ch#(CHCSRW) u_reg_ch(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.zero ( zero ),
.rhy_en ( rhy_en ),
.rhy_kon ( rhy_kon ),
.slot ( slot ),
.group ( group ),
.chcfg_inmux ( chcfg_inmux ),
.chcfg ( chcfg ),
.rhy_oen ( rhy_oen ),
.rhyon_csr ( rhyon_csr )
);
endmodule

36
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/jt2413.qip
View File

@@ -1,36 +0,0 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jt2413.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopll_mmr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopll_reg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_acc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_csr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_div.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_lfo.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_pm.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg_cnt.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg_comb.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg_ctrl.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg_final.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg_pure.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg_step.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_exprom.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_logsin.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_mmr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_op.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_pg_comb.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_pg_inc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_pg_sum.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_pg_rhy.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_pg.v]
# set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_reg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_reg_ch.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_slot_cnt.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_sh_rst.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_sh.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_single_acc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_timers.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_noise.v]
# set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl.v]

30
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/jt26.qip
View File

@@ -1,30 +0,0 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_acc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_csr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_div.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_lfo.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_pm.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg_cnt.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg_comb.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg_ctrl.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg_final.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg_pure.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg_step.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_eg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_exprom.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_logsin.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_mmr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_op.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_pg_comb.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_pg_inc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_pg_sum.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_pg_rhy.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_pg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_reg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_reg_ch.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_slot_cnt.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_sh_rst.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_sh.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_single_acc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_timers.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl_noise.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hdl/jtopl.v]

2
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/jtopl/jtopl2.qip
View File

@@ -1,2 +0,0 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl2.v ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) jt26.qip ]

123
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/mem/cache.v
View File

@@ -1,123 +0,0 @@
///----------------------------------------------------------------------------
//
// Copyright 2022 Darren Olafson
//
// MiSTer Copyright (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//----------------------------------------------------------------------------
// simple read-only cache
// specificly for 68k program rom. todo - parameterize
module cache
(
input reset,
input clk,
input cache_req,
input [22:0] cache_addr,
output reg cache_valid,
output [15:0] cache_data,
input [15:0] rom_data,
input rom_valid,
output reg rom_req,
output reg [22:0] rom_addr
);
reg [22:10] tag [1023:0];
reg [1023:0] valid ;
reg [1:0] state = 0;
reg [9:0] idx_r;
wire [9:0] idx = cache_addr[9:0];
wire hit;
// if tag value matches the upper bits of the address
// and valid then no need to pass request to sdram
assign hit = ( tag[idx] == cache_addr[22:10] && valid[idx] == 1 && state == 1 );
assign cache_data = ( hit == 1 ) ? cache_dout : rom_data;
always @ (posedge clk) begin
cache_valid <= ( cache_req != 0 ) && ( hit == 1 || rom_valid == 1 );
if ( reset == 1 ) begin
state <= 0;
// reset bits that indicate tag is valid
valid <= 0;
end else begin
// if no read request then do nothing
if ( cache_req == 0 ) begin
rom_req <= 0;
state <= 1;
end else begin
// if there is a hit then read from cache and say we are done
if ( hit == 1 ) begin
rom_req <= 0;
end else if ( state == 1 ) begin
// read from memory
idx_r <= idx;
// we need to read from sdram
rom_req <= 1;
rom_addr <= cache_addr;
// next state is wait for rom ready
state <= 2;
end else if ( state == 2 && rom_valid == 1 ) begin
// write updated tag
tag[idx_r] <= rom_addr[22:10];
// mark tag valid
valid[idx_r] <= 1'b1;
cache_din <= rom_data;
state <= 3;
end else if ( state == 3 ) begin
state <= 0;
end
end
end
end
reg [15:0] cache_din;
wire [15:0] cache_dout;
dual_port_ram #(.LEN(1024), .DATA_WIDTH(16)) cache_ram (
.clock_a ( clk ),
.address_a ( idx_r ),
.wren_a ( state == 3 ),
.data_a ( cache_din ),
.q_a ( ),
.clock_b ( clk ),
.address_b ( idx ),
.wren_b ( 0 ),
.q_b ( cache_dout )
);
endmodule

98
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/mem/download_buffer.vhd
View File

@@ -1,98 +0,0 @@
-- __ __ __ __ __ __
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
-- ______ ______ __ ______ ______ ______
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
--
-- https://joshbassett.info
-- https://twitter.com/nullobject
-- https://github.com/nullobject
--
-- Copyright (c) 2020 Josh Bassett
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- use work.types.all;
-- The download buffer writes a stream of bytes to an internal buffer. When the
-- buffer is full, it is flushed as a single word.
--
-- For example, with a buffer size of four, every four bytes written will be
-- flushed as a single 32-bit word.
entity download_buffer is
generic (
-- the size of the buffer (in bytes)
SIZE : natural
);
port (
-- reset
reset : in std_logic := '0';
-- clock
clk : in std_logic;
-- data in
din : in std_logic_vector(7 downto 0);
-- data out
dout : out std_logic_vector(SIZE*8-1 downto 0);
-- write enable
we : in std_logic;
-- when the valid signal is asserted there is a word on the output data bus
valid : out std_logic
);
end download_buffer;
architecture arch of download_buffer is
signal counter : natural range 0 to SIZE-1;
begin
process (clk, reset)
begin
if reset = '1' then
counter <= 0;
valid <= '0';
elsif rising_edge(clk) then
if we = '1' then
-- write the word to the output data bus
dout((SIZE-counter)*8-1 downto (SIZE-counter-1)*8) <= din;
-- increment the counter
counter <= counter + 1;
-- flush the buffer if it is full
if counter = SIZE-1 then
valid <= '1';
else
valid <= '0';
end if;
end if;
end if;
end process;
end architecture;

117
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/mem/dual_port_ram.vhd
View File

@@ -1,117 +0,0 @@
-- __ __ __ __ __ __
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
-- ______ ______ __ ______ ______ ______
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
--
-- https://joshbassett.info
-- https://twitter.com/nullobject
-- https://github.com/nullobject
--
-- Copyright (c) 2020 Josh Bassett
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- 2022-05-24 Changed to use word count instead of address width
-- and renamed ports to match quartus IP naming
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--use work.common.all;
use work.math.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity dual_port_ram is
generic (
LEN : natural := 8192;
DATA_WIDTH : natural := 8
);
port (
-- port A
clock_a : in std_logic;
address_a : in unsigned(ilog2(LEN)-1 downto 0);
data_a : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
q_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
wren_a : in std_logic := '0';
-- port B
clock_b : in std_logic;
address_b : in unsigned(ilog2(LEN)-1 downto 0);
data_b : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
q_b : out std_logic_vector(DATA_WIDTH-1 downto 0);
wren_b : in std_logic := '0'
);
end dual_port_ram;
architecture arch of dual_port_ram is
begin
altsyncram_component : altsyncram
generic map (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => LEN,
numwords_b => LEN,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
width_a => DATA_WIDTH,
width_b => DATA_WIDTH,
width_byteena_a => 1,
width_byteena_b => 1,
widthad_a => ilog2(LEN),
widthad_b => ilog2(LEN),
wrcontrol_wraddress_reg_b => "CLOCK1"
)
port map (
address_a => std_logic_vector(address_a),
address_b => std_logic_vector(address_b),
clock0 => clock_a,
clock1 => clock_b,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => q_a,
q_b => q_b
);
end architecture arch;

72
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/mem/math.vhd
View File

@@ -1,72 +0,0 @@
-- __ __ __ __ __ __
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
-- ______ ______ __ ______ ______ ______
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
--
-- https://joshbassett.info
-- https://twitter.com/nullobject
-- https://github.com/nullobject
--
-- Copyright (c) 2020 Josh Bassett
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package math is
-- calculates the log2 of the given number
function ilog2(n : natural) return natural;
-- Masks the given range of bits for a vector.
--
-- Only the bits between the MSB and LSB (inclusive) will be kept, all other
-- bits will be masked out.
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector;
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector;
end package math;
package body math is
function ilog2(n : natural) return natural is
begin
return natural(ceil(log2(real(n))));
end ilog2;
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector is
variable n : natural;
variable mask : std_logic_vector(data'length-1 downto 0);
begin
n := (2**(msb-lsb+1))-1;
mask := std_logic_vector(shift_left(to_unsigned(n, mask'length), lsb));
return std_logic_vector(shift_right(unsigned(data AND mask), lsb));
end mask_bits;
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector is
begin
return std_logic_vector(resize(unsigned(mask_bits(data, msb, lsb)), size));
end mask_bits;
end package body math;

325
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/mem/rom_controller.v
View File

@@ -1,325 +0,0 @@
`default_nettype none
module rom_controller
(
// reset
input reset,
// clock
input clk,
// program ROM interface
input prog_rom_cs,
input prog_rom_oe,
input [23:1] prog_rom_addr,
output [15:0] prog_rom_data,
output prog_rom_data_valid,
// character ROM interface
input tile_rom_cs,
input tile_rom_oe,
input [18:0] tile_rom_addr,
output [31:0] tile_rom_data,
output tile_rom_data_valid,
// sprite ROM interface
input sprite_rom_cs,
input sprite_rom_oe,
input [17:0] sprite_rom_addr,
output [31:0] sprite_rom_data,
output sprite_rom_data_valid,
// sound ROM #1 interface
input sound_rom_1_cs,
input sound_rom_1_oe,
input [15:0] sound_rom_1_addr,
output [7:0] sound_rom_1_data,
output sound_rom_1_data_valid,
// IOCTL interface
input [24:0] ioctl_addr,
input [7:0] ioctl_data,
input [15:0] ioctl_index,
input ioctl_wr,
input ioctl_download,
// SDRAM interface
output reg [22:0] sdram_addr,
output reg [31:0] sdram_data,
output reg sdram_we,
output reg sdram_req,
input sdram_ack,
input sdram_valid,
input [31:0] sdram_q
);
localparam NONE = 0;
localparam PROG_ROM = 1;
localparam TILE_ROM = 2;
localparam SPRITE_ROM = 3;
localparam SOUND_ROM_1 = 4;
// ROM wires
reg [2:0] rom;
reg [2:0] next_rom;
reg [2:0] pending_rom;
// ROM request wires
reg prog_rom_ctrl_req;
reg tile_rom_ctrl_req;
reg sprite_rom_ctrl_req;
reg sound_rom_1_ctrl_req;
// ROM acknowledge wires
reg prog_rom_ctrl_ack;
reg tile_rom_ctrl_ack;
reg sprite_rom_ctrl_ack;
reg sound_rom_1_ctrl_ack;
reg prog_rom_ctrl_hit;
reg tile_rom_ctrl_hit;
reg sprite_rom_ctrl_hit;
reg sound_rom_1_ctrl_hit;
// ROM valid wires
reg prog_rom_ctrl_valid;
reg tile_rom_ctrl_valid;
reg sprite_rom_ctrl_valid;
reg sound_rom_1_ctrl_valid;
// address mux wires
reg [22:0] prog_rom_ctrl_addr;
reg [22:0] tile_rom_ctrl_addr;
reg [22:0] sprite_rom_ctrl_addr;
reg [22:0] sound_rom_1_ctrl_addr;
// download wires
reg [22:0] download_addr;
reg [32:0] download_data;
reg download_req;
// control wires
reg ctrl_req;
// The SDRAM controller has a 32-bit interface, so we need to buffer the
// bytes received from the IOCTL interface in order to write 32-bit words to
// the SDRAM.
download_buffer #(.SIZE(4) ) download_buffer
(
.clk(clk),
.reset(~ioctl_download | ~sdram_we),
.din(ioctl_data),
.dout(download_data),
.we(ioctl_download & ioctl_wr),
.valid(download_req)
);
segment
#(
.ROM_ADDR_WIDTH(19),
.ROM_DATA_WIDTH(16),
.ROM_OFFSET(24'h000000)
) prog_rom_segment
(
.reset(reset),
.clk(clk),
.cs(prog_rom_cs & !ioctl_download),
.oe(prog_rom_oe),
.ctrl_addr(prog_rom_ctrl_addr),
.ctrl_req(prog_rom_ctrl_req),
.ctrl_ack(prog_rom_ctrl_ack),
.ctrl_valid(prog_rom_ctrl_valid),
.ctrl_hit(prog_rom_ctrl_hit),
.ctrl_data(sdram_q),
.rom_addr(prog_rom_addr),
.rom_data(prog_rom_data)
);
segment
#(
.ROM_ADDR_WIDTH(18),
.ROM_DATA_WIDTH(32),
.ROM_OFFSET(24'h080000)
) tile_rom_segment
(
.reset(reset),
.clk(clk),
.cs(tile_rom_cs & !ioctl_download),
.oe(tile_rom_oe),
.ctrl_addr(tile_rom_ctrl_addr),
.ctrl_req(tile_rom_ctrl_req),
.ctrl_ack(tile_rom_ctrl_ack),
.ctrl_valid(tile_rom_ctrl_valid),
.ctrl_hit(tile_rom_ctrl_hit),
.ctrl_data(sdram_q),
.rom_addr(tile_rom_addr),
.rom_data(tile_rom_data)
);
segment
#(
.ROM_ADDR_WIDTH(18),
.ROM_DATA_WIDTH(32),
.ROM_OFFSET(24'h180000)
) sprite_rom_segment
(
.reset(reset),
.clk(clk),
.cs(sprite_rom_cs & !ioctl_download),
.oe(sprite_rom_oe),
.ctrl_addr(sprite_rom_ctrl_addr),
.ctrl_req(sprite_rom_ctrl_req),
.ctrl_ack(sprite_rom_ctrl_ack),
.ctrl_valid(sprite_rom_ctrl_valid),
.ctrl_hit(sprite_rom_ctrl_hit),
.ctrl_data(sdram_q),
.rom_addr(sprite_rom_addr),
.rom_data(sprite_rom_data)
);
//segment
//#(
// .ROM_ADDR_WIDTH(16),
// .ROM_DATA_WIDTH(8),
// .ROM_OFFSET(24'h200000)
//) sound_rom_1_segment
//(
// .reset(reset),
// .clk(clk),
// .cs(sound_rom_1_cs & !ioctl_download),
// .oe(sound_rom_1_oe),
// .ctrl_addr(sound_rom_1_ctrl_addr),
// .ctrl_req(sound_rom_1_ctrl_req),
// .ctrl_ack(sound_rom_1_ctrl_ack),
// .ctrl_valid(sound_rom_1_ctrl_valid),
// .ctrl_hit(sound_rom_1_ctrl_hit),
// .ctrl_data(sdram_q),
// .rom_addr(sound_rom_1_addr),
// .rom_data(sound_rom_1_data)
//);
// latch the next ROM
always @ (posedge clk, posedge reset) begin
if ( reset == 1 ) begin
rom <= NONE;
pending_rom <= NONE;
end else begin
// default to not having any ROM selected
rom <= NONE;
// set the current ROM register when ROM data is not being downloaded
if ( ioctl_download == 0 ) begin
rom <= next_rom;
end;
// set the pending ROM register when a request is acknowledged (i.e.
// a new request has been started)
if ( sdram_ack == 1 ) begin
pending_rom <= rom;
end
sdram_valid_reg <= sdram_valid;
end
end
reg sdram_valid_reg;
// select cpu data input based on what is active
assign prog_rom_data_valid = prog_rom_cs & ( prog_rom_ctrl_hit | (pending_rom == PROG_ROM ? sdram_valid : 0) ) & ~reset;
assign tile_rom_data_valid = tile_rom_cs & ( tile_rom_ctrl_hit | (pending_rom == TILE_ROM ? sdram_valid : 0) ) & ~reset;
assign sprite_rom_data_valid = sprite_rom_cs & ( sprite_rom_ctrl_hit | (pending_rom == SPRITE_ROM ? sdram_valid : 0) ) & ~reset;
//assign sound_rom_1_data_valid = sound_rom_1_cs & ( sound_rom_1_ctrl_hit | (pending_rom == SOUND_ROM_1 ? sdram_valid : 0) ) & ~reset;
always @ (*) begin
// mux the next ROM in priority order
next_rom <= NONE; // default
case (1)
prog_rom_ctrl_req: next_rom <= PROG_ROM;
// sound_rom_1_ctrl_req: next_rom <= SOUND_ROM_1;
tile_rom_ctrl_req: next_rom <= TILE_ROM;
sprite_rom_ctrl_req: next_rom <= SPRITE_ROM;
endcase
// route SDRAM acknowledge wire to the current ROM
prog_rom_ctrl_ack <= 0;
// sound_rom_1_ctrl_ack <= 0;
tile_rom_ctrl_ack <= 0;
sprite_rom_ctrl_ack <= 0;
case (rom)
PROG_ROM: prog_rom_ctrl_ack <= sdram_ack;
// SOUND_ROM_1: sound_rom_1_ctrl_ack <= sdram_ack;
TILE_ROM: tile_rom_ctrl_ack <= sdram_ack;
SPRITE_ROM: sprite_rom_ctrl_ack <= sdram_ack;
endcase
// route SDRAM valid wire to the pending ROM
prog_rom_ctrl_valid <= 0;
tile_rom_ctrl_valid <= 0;
sprite_rom_ctrl_valid <= 0;
// sound_rom_1_ctrl_valid <= 0;
case (pending_rom)
PROG_ROM: prog_rom_ctrl_valid <= sdram_valid;
// SOUND_ROM_1: sound_rom_1_ctrl_valid <= sdram_valid;
TILE_ROM: tile_rom_ctrl_valid <= sdram_valid;
SPRITE_ROM: sprite_rom_ctrl_valid <= sdram_valid;
endcase
// mux ROM request
ctrl_req <= prog_rom_ctrl_req |
tile_rom_ctrl_req |
sprite_rom_ctrl_req ;
// | sound_rom_1_ctrl_req;
// mux SDRAM address in priority order
sdram_addr <= 0;
case (1)
ioctl_download: sdram_addr <= download_addr;
prog_rom_ctrl_req: sdram_addr <= prog_rom_ctrl_addr;
//sound_rom_1_ctrl_req: sdram_addr <= sound_rom_1_ctrl_addr;
tile_rom_ctrl_req: sdram_addr <= tile_rom_ctrl_addr;
sprite_rom_ctrl_req: sdram_addr <= sprite_rom_ctrl_addr;
endcase
// set SDRAM data input
sdram_data <= download_data;
// sdram_data <= download_addr; poor man's testbench
// set SDRAM request
sdram_req <= (ioctl_download & download_req) | (!ioctl_download & ctrl_req);
// enable writing to the SDRAM when downloading ROM data
sdram_we <= ioctl_download & ( ioctl_index == 0 );
// we need to divide the address by four, because we're converting from
// a 8-bit IOCTL address to a 32-bit SDRAM address
download_addr <= ioctl_addr[24:2];
end
wire [14:0] sound_rom_ofs = ioctl_addr[14:0];
wire sound_rom_w = ( ioctl_index === 0 ) && ioctl_wr && ( ioctl_addr >= 24'h200000 ) && ( ioctl_addr < 24'h208000 );
assign sound_rom_1_data_valid = sound_rom_1_oe;
dual_port_ram #(.LEN(32768), .DATA_WIDTH(8)) sound_rom (
.clock_a ( clk ),
.address_a ( sound_rom_ofs ),
.wren_a ( sound_rom_w ),
.data_a ( ioctl_data ),
.q_a ( ),
.clock_b ( clk ),
.address_b ( sound_rom_1_addr[14:0] ),
.wren_b ( 0 ),
.data_b ( ),
.q_b ( sound_rom_1_data )
);
endmodule

443
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/mem/sdram.vhd
View File

@@ -1,443 +0,0 @@
-- __ __ __ __ __ __
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
-- ______ ______ __ ______ ______ ______
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
--
-- https://joshbassett.info
-- https://twitter.com/nullobject
-- https://github.com/nullobject
--
-- Copyright (c) 2020 Josh Bassett
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--use work.common.all;
use work.math.all;
-- This SDRAM controller provides a symmetric 32-bit synchronous read/write
-- interface for a 16Mx16-bit SDRAM chip (e.g. AS4C16M16SA-6TCN, IS42S16400F,
-- etc.).
entity sdram is
generic (
-- clock frequency (in MHz)
--
-- This value must be provided, as it is used to calculate the number of
-- clock cycles required for the other timing values.
CLK_FREQ : real;
-- 32-bit controller interface
ADDR_WIDTH : natural := 23;
DATA_WIDTH : natural := 32;
-- SDRAM interface
SDRAM_ADDR_WIDTH : natural := 13;
SDRAM_DATA_WIDTH : natural := 16;
SDRAM_COL_WIDTH : natural := 9;
SDRAM_ROW_WIDTH : natural := 13;
SDRAM_BANK_WIDTH : natural := 2;
-- The delay in clock cycles, between the start of a read command and the
-- availability of the output data.
CAS_LATENCY : natural := 2; -- 2=below 133MHz, 3=above 133MHz
-- The number of 16-bit words to be bursted during a read/write.
BURST_LENGTH : natural := 2;
-- timing values (in nanoseconds)
--
-- These values can be adjusted to match the exact timing of your SDRAM
-- chip (refer to the datasheet).
T_DESL : real := 200000.0; -- startup delay
T_MRD : real := 12.0; -- mode register cycle time
T_RC : real := 60.0; -- row cycle time
T_RCD : real := 18.0; -- RAS to CAS delay
T_RP : real := 18.0; -- precharge to activate delay
T_WR : real := 12.0; -- write recovery time
T_REFI : real := 7800.0 -- average refresh interval
);
port (
-- reset
reset : in std_logic := '0';
-- clock
clk : in std_logic;
-- address bus
addr : in unsigned(ADDR_WIDTH-1 downto 0);
-- input data bus
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- When the write enable signal is asserted, a write operation will be performed.
we : in std_logic;
-- When the request signal is asserted, an operation will be performed.
req : in std_logic;
-- The acknowledge signal is asserted by the SDRAM controller when
-- a request has been accepted.
ack : out std_logic;
-- The valid signal is asserted when there is a valid word on the output
-- data bus.
valid : out std_logic;
-- output data bus
q : out std_logic_vector(DATA_WIDTH-1 downto 0);
-- SDRAM interface (e.g. AS4C16M16SA-6TCN, IS42S16400F, etc.)
sdram_a : out unsigned(SDRAM_ADDR_WIDTH-1 downto 0);
sdram_ba : out unsigned(SDRAM_BANK_WIDTH-1 downto 0);
sdram_dq : inout std_logic_vector(SDRAM_DATA_WIDTH-1 downto 0);
sdram_cke : out std_logic;
sdram_cs_n : out std_logic;
sdram_ras_n : out std_logic;
sdram_cas_n : out std_logic;
sdram_we_n : out std_logic;
sdram_dqml : out std_logic;
sdram_dqmh : out std_logic
);
end sdram;
architecture arch of sdram is
subtype command_t is std_logic_vector(3 downto 0);
-- commands
constant CMD_DESELECT : command_t := "1---";
constant CMD_LOAD_MODE : command_t := "0000";
constant CMD_AUTO_REFRESH : command_t := "0001";
constant CMD_PRECHARGE : command_t := "0010";
constant CMD_ACTIVE : command_t := "0011";
constant CMD_WRITE : command_t := "0100";
constant CMD_READ : command_t := "0101";
constant CMD_STOP : command_t := "0110";
constant CMD_NOP : command_t := "0111";
-- the ordering of the accesses within a burst
constant BURST_TYPE : std_logic := '0'; -- 0=sequential, 1=interleaved
-- the write burst mode enables bursting for write operations
constant WRITE_BURST_MODE : std_logic := '0'; -- 0=burst, 1=single
-- the value written to the mode register to configure the memory
constant MODE_REG : unsigned(SDRAM_ADDR_WIDTH-1 downto 0) := (
"000" &
WRITE_BURST_MODE &
"00" &
to_unsigned(CAS_LATENCY, 3) &
BURST_TYPE &
to_unsigned(ilog2(BURST_LENGTH), 3)
);
-- calculate the clock period (in nanoseconds)
constant CLK_PERIOD : real := 1.0/CLK_FREQ*1000.0;
-- the number of clock cycles to wait before initialising the device
constant INIT_WAIT : natural := natural(ceil(T_DESL/CLK_PERIOD));
-- the number of clock cycles to wait while a LOAD MODE command is being
-- executed
constant LOAD_MODE_WAIT : natural := natural(ceil(T_MRD/CLK_PERIOD));
-- the number of clock cycles to wait while an ACTIVE command is being
-- executed
constant ACTIVE_WAIT : natural := natural(ceil(T_RCD/CLK_PERIOD));
-- the number of clock cycles to wait while a REFRESH command is being
-- executed
constant REFRESH_WAIT : natural := natural(ceil(T_RC/CLK_PERIOD));
-- the number of clock cycles to wait while a PRECHARGE command is being
-- executed
constant PRECHARGE_WAIT : natural := natural(ceil(T_RP/CLK_PERIOD));
-- the number of clock cycles to wait while a READ command is being executed
constant READ_WAIT : natural := CAS_LATENCY+BURST_LENGTH;
-- the number of clock cycles to wait while a WRITE command is being executed
constant WRITE_WAIT : natural := BURST_LENGTH+natural(ceil((T_WR+T_RP)/CLK_PERIOD));
-- the number of clock cycles before the memory controller needs to refresh
-- the SDRAM
constant REFRESH_INTERVAL : natural := natural(floor(T_REFI/CLK_PERIOD))-10;
type state_t is (INIT, MODE, IDLE, ACTIVE, READ, WRITE, REFRESH);
-- state signals
signal state, next_state : state_t;
-- command signals
signal cmd, next_cmd : command_t := CMD_NOP;
-- control signals
signal start : std_logic;
signal load_mode_done : std_logic;
signal active_done : std_logic;
signal refresh_done : std_logic;
signal first_word : std_logic;
signal read_done : std_logic;
signal write_done : std_logic;
signal should_refresh : std_logic;
-- counters
signal wait_counter : natural range 0 to 16383;
signal refresh_counter : natural range 0 to 1023;
-- registers
signal addr_reg : unsigned(SDRAM_COL_WIDTH+SDRAM_ROW_WIDTH+SDRAM_BANK_WIDTH-1 downto 0);
signal data_reg : std_logic_vector(DATA_WIDTH-1 downto 0);
signal we_reg : std_logic;
signal q_reg : std_logic_vector(DATA_WIDTH-1 downto 0);
-- aliases to decode the address register
alias col : unsigned(SDRAM_COL_WIDTH-1 downto 0) is addr_reg(SDRAM_COL_WIDTH-1 downto 0);
alias row : unsigned(SDRAM_ROW_WIDTH-1 downto 0) is addr_reg(SDRAM_COL_WIDTH+SDRAM_ROW_WIDTH-1 downto SDRAM_COL_WIDTH);
alias bank : unsigned(SDRAM_BANK_WIDTH-1 downto 0) is addr_reg(SDRAM_COL_WIDTH+SDRAM_ROW_WIDTH+SDRAM_BANK_WIDTH-1 downto SDRAM_COL_WIDTH+SDRAM_ROW_WIDTH);
begin
-- state machine
fsm : process (state, wait_counter, req, we_reg, load_mode_done, active_done, refresh_done, read_done, write_done, should_refresh)
begin
next_state <= state;
-- default to a NOP command
next_cmd <= CMD_NOP;
case state is
-- execute the initialisation sequence
when INIT =>
if wait_counter = 0 then
next_cmd <= CMD_DESELECT;
elsif wait_counter = INIT_WAIT-1 then
next_cmd <= CMD_PRECHARGE;
elsif wait_counter = INIT_WAIT+PRECHARGE_WAIT-1 then
next_cmd <= CMD_AUTO_REFRESH;
elsif wait_counter = INIT_WAIT+PRECHARGE_WAIT+REFRESH_WAIT-1 then
next_cmd <= CMD_AUTO_REFRESH;
elsif wait_counter = INIT_WAIT+PRECHARGE_WAIT+REFRESH_WAIT+REFRESH_WAIT-1 then
next_state <= MODE;
next_cmd <= CMD_LOAD_MODE;
end if;
-- load the mode register
when MODE =>
if load_mode_done = '1' then
next_state <= IDLE;
end if;
-- wait for a read/write request
when IDLE =>
if should_refresh = '1' then
next_state <= REFRESH;
next_cmd <= CMD_AUTO_REFRESH;
elsif req = '1' then
next_state <= ACTIVE;
next_cmd <= CMD_ACTIVE;
end if;
-- activate the row
when ACTIVE =>
if active_done = '1' then
if we_reg = '1' then
next_state <= WRITE;
next_cmd <= CMD_WRITE;
else
next_state <= READ;
next_cmd <= CMD_READ;
end if;
end if;
-- execute a read command
when READ =>
if read_done = '1' then
if should_refresh = '1' then
next_state <= REFRESH;
next_cmd <= CMD_AUTO_REFRESH;
elsif req = '1' then
next_state <= ACTIVE;
next_cmd <= CMD_ACTIVE;
else
next_state <= IDLE;
end if;
end if;
-- execute a write command
when WRITE =>
if write_done = '1' then
if should_refresh = '1' then
next_state <= REFRESH;
next_cmd <= CMD_AUTO_REFRESH;
elsif req = '1' then
next_state <= ACTIVE;
next_cmd <= CMD_ACTIVE;
else
next_state <= IDLE;
end if;
end if;
-- execute an auto refresh
when REFRESH =>
if refresh_done = '1' then
if req = '1' then
next_state <= ACTIVE;
next_cmd <= CMD_ACTIVE;
else
next_state <= IDLE;
end if;
end if;
end case;
end process;
-- latch the next state
latch_next_state : process (clk, reset)
begin
if reset = '1' then
state <= INIT;
cmd <= CMD_NOP;
elsif rising_edge(clk) then
state <= next_state;
cmd <= next_cmd;
end if;
end process;
-- the wait counter is used to hold the current state for a number of clock
-- cycles
update_wait_counter : process (clk, reset)
begin
if reset = '1' then
wait_counter <= 0;
elsif rising_edge(clk) then
if state /= next_state then -- state changing
wait_counter <= 0;
else
wait_counter <= wait_counter + 1;
end if;
end if;
end process;
-- the refresh counter is used to periodically trigger a refresh operation
update_refresh_counter : process (clk, reset)
begin
if reset = '1' then
refresh_counter <= 0;
elsif rising_edge(clk) then
if state = REFRESH and wait_counter = 0 then
refresh_counter <= 0;
else
refresh_counter <= refresh_counter + 1;
end if;
end if;
end process;
-- latch the rquest
latch_request : process (clk)
begin
if rising_edge(clk) then
if start = '1' then
-- we need to multiply the address by two, because we are converting
-- from a 32-bit controller address to a 16-bit SDRAM address
addr_reg <= shift_left(resize(addr, addr_reg'length), 1);
data_reg <= data;
we_reg <= we;
end if;
end if;
end process;
-- latch the output data as it's bursted from the SDRAM
latch_sdram_data : process (clk)
begin
if rising_edge(clk) then
valid <= '0';
if state = READ then
if first_word = '1' then
q_reg(31 downto 16) <= sdram_dq;
elsif read_done = '1' then
q_reg(15 downto 0) <= sdram_dq;
valid <= '1';
end if;
end if;
end if;
end process;
-- set wait signals
load_mode_done <= '1' when wait_counter = LOAD_MODE_WAIT-1 else '0';
active_done <= '1' when wait_counter = ACTIVE_WAIT-1 else '0';
refresh_done <= '1' when wait_counter = REFRESH_WAIT-1 else '0';
first_word <= '1' when wait_counter = CAS_LATENCY else '0';
read_done <= '1' when wait_counter = READ_WAIT-1 else '0';
write_done <= '1' when wait_counter = WRITE_WAIT-1 else '0';
-- the SDRAM should be refreshed when the refresh interval has elapsed
should_refresh <= '1' when refresh_counter >= REFRESH_INTERVAL-1 else '0';
-- a new request is only allowed at the end of the IDLE, READ, WRITE, and
-- REFRESH states
start <= '1' when (state = IDLE) or
(state = READ and read_done = '1') or
(state = WRITE and write_done = '1') or
(state = REFRESH and refresh_done = '1') else '0';
-- assert the acknowledge signal at the beginning of the ACTIVE state
ack <= '1' when state = ACTIVE and wait_counter = 0 else '0';
-- set output data
q <= q_reg;
-- deassert the clock enable at the beginning of the INIT state
sdram_cke <= '0' when state = INIT and wait_counter = 0 else '1';
-- set SDRAM control signals
(sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n) <= cmd;
-- set SDRAM bank
with state select
sdram_ba <=
bank when ACTIVE,
bank when READ,
bank when WRITE,
(others => '0') when others;
-- set SDRAM address
with state select
sdram_a <=
"0010000000000" when INIT,
MODE_REG when MODE,
row when ACTIVE,
"0010" & col when READ, -- auto precharge
"0010" & col when WRITE, -- auto precharge
(others => '0') when others;
-- decode the next 16-bit word from the write buffer
sdram_dq <= data_reg((BURST_LENGTH-wait_counter)*SDRAM_DATA_WIDTH-1 downto (BURST_LENGTH-wait_counter-1)*SDRAM_DATA_WIDTH) when state = WRITE else (others => 'Z');
-- set SDRAM data mask
sdram_dqmh <= '0';
sdram_dqml <= '0';
end architecture arch;

153
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/mem/segment.vhd
View File

@@ -1,153 +0,0 @@
-- __ __ __ __ __ __
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
-- ______ ______ __ ______ ______ ______
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
--
-- https://joshbassett.info
-- https://twitter.com/nullobject
-- https://github.com/nullobject
--
-- Copyright (c) 2020 Josh Bassett
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.common.all;
use work.math.all;
-- A segment provides a read-only interface to a contiguous block of ROM data,
-- located somewhere in memory.
entity segment is
generic (
-- the width of the ROM address bus
ROM_ADDR_WIDTH : natural;
-- the width of the ROM data bus
ROM_DATA_WIDTH : natural;
-- the byte offset of the ROM data in memory
ROM_OFFSET : natural := 0
);
port (
-- reset
reset : in std_logic;
-- clock
clk : in std_logic;
-- When the chip select signal is asserted, the segment will request data
-- from the ROM controller when there is a cache miss.
cs : in std_logic := '1';
-- When the output enable signal is asserted, the output buffer is enabled
-- and the word at the requested address will be placed on the ROM data
-- bus.
oe : in std_logic := '1';
-- controller interface
ctrl_addr : buffer unsigned(22 downto 0);
ctrl_req : out std_logic;
ctrl_hit : buffer std_logic;
ctrl_ack : in std_logic;
ctrl_valid : in std_logic;
ctrl_data : in std_logic_vector(31 downto 0);
-- ROM interface
rom_addr : in unsigned(ROM_ADDR_WIDTH-1 downto 0);
rom_data : out std_logic_vector(ROM_DATA_WIDTH-1 downto 0)
);
end segment;
architecture arch of segment is
-- the number of ROM words in a 32-bit word (e.g. there are four 8-bit ROM
-- words in a 32-bit word)
constant ROM_WORDS : natural := 32/ROM_DATA_WIDTH;
-- the number of bits in the offset component of the ROM address
constant OFFSET_WIDTH : natural := ilog2(ROM_WORDS);
-- the offset of the word from the requested ROM address in the cache
signal offset : natural range 0 to ROM_WORDS-1;
-- control signals
-- signal hit : std_logic;
-- registers
signal full : std_logic;
signal pending : std_logic;
signal pending_addr : unsigned(22 downto 0);
signal cache_addr : unsigned(22 downto 0);
signal cache_data : std_logic_vector(31 downto 0);
begin
-- latch data received from the memory controller
latch_data : process (clk, reset)
begin
if reset = '1' then
full <= '0';
pending <= '0';
elsif rising_edge(clk) then
if ctrl_ack = '1' then
-- set the pending register
pending <= '1';
-- set the pending addr
pending_addr <= ctrl_addr;
elsif ctrl_valid = '1' then
-- set the full register
full <= '1';
-- clear the pending register
pending <= '0';
-- set the cached address/data
cache_addr <= pending_addr;
cache_data <= ctrl_data;
end if;
end if;
end process;
-- assert the hit signal when the cache has been filled, and the requested
-- address is in the cache
ctrl_hit <= '1' when full = '1' and ctrl_addr = cache_addr else '0';
-- calculate the offset of the ROM address within a 32-bit word
offset <= to_integer(rom_addr(OFFSET_WIDTH-1 downto 0)) when OFFSET_WIDTH > 0 else 0;
-- extract the word at the requested offset in the cache
-- rom_data <= cache_data((ROM_WORDS-offset)*ROM_DATA_WIDTH-1 downto (ROM_WORDS-offset-1)*ROM_DATA_WIDTH) when cs = '1' and oe = '1' else (others => '0');
rom_data <= cache_data((ROM_WORDS-offset)*ROM_DATA_WIDTH-1 downto (ROM_WORDS-offset-1)*ROM_DATA_WIDTH) when cs = '1' and oe = '1' and ctrl_valid = '0'
else ctrl_data((ROM_WORDS-offset)*ROM_DATA_WIDTH-1 downto (ROM_WORDS-offset-1)*ROM_DATA_WIDTH) when cs = '1' and oe = '1' and ctrl_valid = '1'
else (others => '0');
-- we need to divide the ROM offset by four, because we are converting from
-- an 8-bit ROM offset to a 32-bit address
ctrl_addr <= resize(shift_right(rom_addr, OFFSET_WIDTH), 23) + ROM_OFFSET/4;
-- assert the request signal unless there is a pending request or a cache hit
ctrl_req <= cs and not (pending or ctrl_hit);
end architecture arch;

98
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/mem/single_port_ram.vhd
View File

@@ -1,98 +0,0 @@
-- __ __ __ __ __ __
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
-- ______ ______ __ ______ ______ ______
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
--
-- https://joshbassett.info
-- https://twitter.com/nullobject
-- https://github.com/nullobject
--
-- Copyright (c) 2020 Josh Bassett
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity single_port_ram is
generic (
ADDR_WIDTH : natural := 8;
DATA_WIDTH : natural := 8
);
port (
-- clock
clk : in std_logic;
-- chip select
cs : in std_logic := '1';
-- address
addr : in unsigned(ADDR_WIDTH-1 downto 0);
-- data in
din : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
-- data out
dout : out std_logic_vector(DATA_WIDTH-1 downto 0);
-- write enable
we : in std_logic := '0'
);
end single_port_ram;
architecture arch of single_port_ram is
signal q : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
altsyncram_component : altsyncram
generic map (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**ADDR_WIDTH,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
width_a => DATA_WIDTH,
width_byteena_a => 1,
widthad_a => ADDR_WIDTH
)
port map (
address_a => std_logic_vector(addr),
clock0 => clk,
data_a => din,
wren_a => cs and we,
q_a => q
);
dout <= q when cs = '1' else (others => '0');
end architecture arch;

91
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/mem/single_port_rom.vhd
View File

@@ -1,91 +0,0 @@
-- __ __ __ __ __ __
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
-- ______ ______ __ ______ ______ ______
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
--
-- https://joshbassett.info
-- https://twitter.com/nullobject
-- https://github.com/nullobject
--
-- Copyright (c) 2020 Josh Bassett
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity single_port_rom is
generic (
ADDR_WIDTH : natural := 8;
DATA_WIDTH : natural := 8;
INIT_FILE : string := ""
);
port (
-- clock
clk : in std_logic;
-- chip select
cs : in std_logic := '1';
-- address
addr : in unsigned(ADDR_WIDTH-1 downto 0);
-- data out
dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end single_port_rom;
architecture arch of single_port_rom is
signal q : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
altsyncram_component : altsyncram
generic map (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => INIT_FILE,
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**ADDR_WIDTH,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
width_a => DATA_WIDTH,
width_byteena_a => 1,
widthad_a => ADDR_WIDTH
)
port map (
address_a => std_logic_vector(addr),
clock0 => clk,
q_a => q
);
dout <= q when cs = '1' else (others => '0');
end architecture arch;

127
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/mem/tile_cache.v
View File

@@ -1,127 +0,0 @@
///----------------------------------------------------------------------------
//
// Copyright 2022 Darren Olafson
//
// MiSTer Copyright (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//----------------------------------------------------------------------------
// input tile_rom_cs,
// input tile_rom_oe,
// input [19:0] tile_rom_addr,
// output [31:0] tile_rom_data,
// output tile_rom_data_valid,
module tile_cache
(
input reset,
input clk,
input cache_req,
input [17:0] cache_addr,
output reg cache_valid,
output [31:0] cache_data,
input [31:0] rom_data,
input rom_valid,
output reg rom_req,
output reg [17:0] rom_addr
);
reg [17:10] tag [1023:0];
reg [1023:0] valid ;
reg [1:0] state = 0;
reg [9:0] idx_r;
wire [9:0] idx = cache_addr[9:0];
wire hit;
// if tag value matches the upper bits of the address
// and valid then no need to pass request to sdram
assign hit = ( tag[idx] == cache_addr[17:10] && valid[idx] == 1 && state == 1 );
//assign cache_valid = ( cache_req != 0 ) && ( hit == 1 || rom_valid == 1 );
assign cache_data = ( hit == 1 ) ? cache_dout : rom_data;
always @ (posedge clk) begin
cache_valid <= ( cache_req != 0 ) && ( hit == 1 || rom_valid == 1 );
if ( reset == 1 ) begin
state <= 0;
// reset bits that indicate tag is valid
valid <= 0;
end else begin
// if no read request then do nothing
if ( cache_req == 0 ) begin
rom_req <= 0;
state <= 1;
end else begin
// if there is a hit then read from cache and say we are done
if ( hit == 1 ) begin
rom_req <= 0;
end else if ( state == 1 ) begin
// read from memory
idx_r <= idx;
// we need to read from sdram
rom_req <= 1;
rom_addr <= cache_addr;
// next state is wait for rom ready
state <= 2;
end else if ( state == 2 && rom_valid == 1 ) begin
// write updated tag
tag[idx_r] <= rom_addr[17:10];
// mark tag valid
valid[idx_r] <= 1'b1;
cache_din <= rom_data;
state <= 3;
end else if ( state == 3 ) begin
state <= 0;
end
end
end
end
reg [31:0] cache_din;
wire [31:0] cache_dout;
dual_port_ram #(.LEN(1024), .DATA_WIDTH(32)) cache_ram (
.clock_a ( clk ),
.address_a ( idx_r ),
.wren_a ( state == 3 ),
.data_a ( cache_din ),
.q_a ( ),
.clock_b ( clk ),
.address_b ( idx ),
.wren_b ( 0 ),
.q_b ( cache_dout )
);
endmodule

117
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/mem/true_dual_port_ram.vhd
View File

@@ -1,117 +0,0 @@
-- __ __ __ __ __ __
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
-- ______ ______ __ ______ ______ ______
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
--
-- https://joshbassett.info
-- https://twitter.com/nullobject
-- https://github.com/nullobject
--
-- Copyright (c) 2020 Josh Bassett
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity true_dual_port_ram is
generic (
ADDR_WIDTH_A : natural := 8;
ADDR_WIDTH_B : natural := 8;
DATA_WIDTH_A : natural := 8;
DATA_WIDTH_B : natural := 8
);
port (
-- port A
clk_a : in std_logic;
cs_a : in std_logic := '1';
addr_a : in unsigned(ADDR_WIDTH_A-1 downto 0);
din_a : in std_logic_vector(DATA_WIDTH_A-1 downto 0) := (others => '0');
dout_a : out std_logic_vector(DATA_WIDTH_A-1 downto 0);
we_a : in std_logic := '0';
-- port B
clk_b : in std_logic;
cs_b : in std_logic := '1';
addr_b : in unsigned(ADDR_WIDTH_B-1 downto 0);
din_b : in std_logic_vector(DATA_WIDTH_B-1 downto 0) := (others => '0');
dout_b : out std_logic_vector(DATA_WIDTH_B-1 downto 0);
we_b : in std_logic := '0'
);
end true_dual_port_ram;
architecture arch of true_dual_port_ram is
signal q_a : std_logic_vector(DATA_WIDTH_A-1 downto 0);
signal q_b : std_logic_vector(DATA_WIDTH_B-1 downto 0);
begin
altsyncram_component : altsyncram
generic map (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 2**ADDR_WIDTH_A,
numwords_b => 2**ADDR_WIDTH_B,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
width_a => DATA_WIDTH_A,
width_b => DATA_WIDTH_B,
width_byteena_a => 1,
width_byteena_b => 1,
widthad_a => ADDR_WIDTH_A,
widthad_b => ADDR_WIDTH_B,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
port map (
address_a => std_logic_vector(addr_a),
address_b => std_logic_vector(addr_b),
clock0 => clk_a,
clock1 => clk_b,
data_a => din_a,
data_b => din_b,
wren_a => cs_a and we_a,
wren_b => cs_b and we_b,
q_a => q_a,
q_b => q_b
);
-- output
dout_a <= q_a when cs_a = '1' else (others => '0');
dout_b <= q_b when cs_b = '1' else (others => '0');
end architecture arch;

4
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/pll/pll_0002.qip
View File

@@ -1,4 +0,0 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"

90
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/pll/pll_0002.v
View File

@@ -1,90 +0,0 @@
`timescale 1ns/10ps
module pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("70.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("70.000000 MHz"),
.phase_shift1("-3571 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule

4
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/rtl/pll/pll_0002_q13.qip
View File

@@ -1,4 +0,0 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"

157
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/sys/alsa.sv
View File

@@ -1,157 +0,0 @@
//============================================================================
//
// ALSA sound support for MiSTer
// (c)2019,2020 Alexey Melnikov
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module alsa
#(
parameter CLK_RATE = 24576000
)
(
input reset,
input clk,
output reg [31:3] ram_address,
input [63:0] ram_data,
output reg ram_req = 0,
input ram_ready,
input spi_ss,
input spi_sck,
input spi_mosi,
output spi_miso,
output reg [15:0] pcm_l,
output reg [15:0] pcm_r
);
reg [60:0] buf_info;
reg [6:0] spicnt = 0;
always @(posedge spi_sck, posedge spi_ss) begin
reg [95:0] spi_data;
if(spi_ss) spicnt <= 0;
else begin
spi_data[{spicnt[6:3],~spicnt[2:0]}] <= spi_mosi;
if(&spicnt) buf_info <= {spi_data[82:67],spi_data[50:35],spi_data[31:3]};
spicnt <= spicnt + 1'd1;
end
end
assign spi_miso = spi_out[{spicnt[4:3],~spicnt[2:0]}];
reg [31:0] spi_out = 0;
always @(posedge clk) if(spi_ss) spi_out <= {buf_rptr, hurryup, 8'h00};
reg [31:3] buf_addr;
reg [18:3] buf_len;
reg [18:3] buf_wptr = 0;
always @(posedge clk) begin
reg [60:0] data1,data2;
data1 <= buf_info;
data2 <= data1;
if(data2 == data1) {buf_wptr,buf_len,buf_addr} <= data2;
end
reg [2:0] hurryup = 0;
reg [18:3] buf_rptr = 0;
always @(posedge clk) begin
reg [18:3] len = 0;
reg [1:0] ready = 0;
reg [63:0] readdata;
reg got_first = 0;
reg [7:0] ce_cnt = 0;
reg [1:0] state = 0;
if(reset) begin
ready <= 0;
ce_cnt <= 0;
state <= 0;
got_first <= 0;
len <= 0;
end
else begin
//ramp up
if(len[18:14] && (hurryup < 1)) hurryup <= 1;
if(len[18:16] && (hurryup < 2)) hurryup <= 2;
if(len[18:17] && (hurryup < 4)) hurryup <= 4;
//ramp down
if(!len[18:15] && (hurryup > 2)) hurryup <= 2;
if(!len[18:13] && (hurryup > 1)) hurryup <= 1;
if(!len[18:10]) hurryup <= 0;
if(ce_sample && ~&ce_cnt) ce_cnt <= ce_cnt + 1'd1;
case(state)
0: if(!ce_sample) begin
if(ready) begin
if(ce_cnt) begin
{readdata[31:0],pcm_r,pcm_l} <= readdata;
ready <= ready - 1'd1;
ce_cnt <= ce_cnt - 1'd1;
end
end
else if(buf_rptr != buf_wptr) begin
if(~got_first) begin
buf_rptr <= buf_wptr;
got_first <= 1;
end
else begin
ram_address <= buf_addr + buf_rptr;
ram_req <= ~ram_req;
buf_rptr <= buf_rptr + 1'd1;
len <= (buf_wptr < buf_rptr) ? (buf_len + buf_wptr - buf_rptr) : (buf_wptr - buf_rptr);
state <= 1;
end
end
else begin
len <= 0;
ce_cnt <= 0;
hurryup <= 0;
end
end
1: if(ram_ready) begin
ready <= 2;
readdata <= ram_data;
if(buf_rptr >= buf_len) buf_rptr <= buf_rptr - buf_len;
state <= 0;
end
endcase
end
end
reg ce_sample;
always @(posedge clk) begin
reg [31:0] acc = 0;
ce_sample <= 0;
acc <= acc + 48000 + {hurryup,6'd0};
if(acc >= CLK_RATE) begin
acc <= acc - CLK_RATE;
ce_sample <= 1;
end
end
endmodule

324
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/sys/arcade_video.v
View File

@@ -1,324 +0,0 @@
//============================================================================
//
// Copyright (C) 2017-2020 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
//////////////////////////////////////////////////////////
// DW:
// 6 : 2R 2G 2B
// 8 : 3R 3G 2B
// 9 : 3R 3G 3B
// 12 : 4R 4G 4B
// 24 : 8R 8G 8B
module arcade_video #(parameter WIDTH=320, DW=8, GAMMA=1)
(
input clk_video,
input ce_pix,
input[DW-1:0] RGB_in,
input HBlank,
input VBlank,
input HSync,
input VSync,
output CLK_VIDEO,
output CE_PIXEL,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE,
output [2:0] VGA_SL,
input [2:0] fx,
input forced_scandoubler,
inout [21:0] gamma_bus
);
assign CLK_VIDEO = clk_video;
wire hs_fix,vs_fix;
sync_fix sync_v(CLK_VIDEO, HSync, hs_fix);
sync_fix sync_h(CLK_VIDEO, VSync, vs_fix);
reg [DW-1:0] RGB_fix;
reg CE,HS,VS,HBL,VBL;
always @(posedge CLK_VIDEO) begin
reg old_ce;
old_ce <= ce_pix;
CE <= 0;
if(~old_ce & ce_pix) begin
CE <= 1;
HS <= hs_fix;
if(~HS & hs_fix) VS <= vs_fix;
RGB_fix <= RGB_in;
HBL <= HBlank;
if(HBL & ~HBlank) VBL <= VBlank;
end
end
wire [7:0] R,G,B;
generate
if(DW == 6) begin
assign R = {RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4]};
assign G = {RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2]};
assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
end
else if(DW == 8) begin
assign R = {RGB_fix[7:5],RGB_fix[7:5],RGB_fix[7:6]};
assign G = {RGB_fix[4:2],RGB_fix[4:2],RGB_fix[4:3]};
assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
end
else if(DW == 9) begin
assign R = {RGB_fix[8:6],RGB_fix[8:6],RGB_fix[8:7]};
assign G = {RGB_fix[5:3],RGB_fix[5:3],RGB_fix[5:4]};
assign B = {RGB_fix[2:0],RGB_fix[2:0],RGB_fix[2:1]};
end
else if(DW == 12) begin
assign R = {RGB_fix[11:8],RGB_fix[11:8]};
assign G = {RGB_fix[7:4],RGB_fix[7:4]};
assign B = {RGB_fix[3:0],RGB_fix[3:0]};
end
else begin // 24
assign R = RGB_fix[23:16];
assign G = RGB_fix[15:8];
assign B = RGB_fix[7:0];
end
endgenerate
assign VGA_SL = sl[2:0];
wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
wire scandoubler = fx || forced_scandoubler;
video_mixer #(.LINE_LENGTH(WIDTH+4), .HALF_DEPTH(DW!=24), .GAMMA(GAMMA)) video_mixer
(
.CLK_VIDEO(CLK_VIDEO),
.ce_pix(CE),
.CE_PIXEL(CE_PIXEL),
.scandoubler(scandoubler),
.hq2x(fx==1),
.gamma_bus(gamma_bus),
.R((DW!=24) ? R[7:4] : R),
.G((DW!=24) ? G[7:4] : G),
.B((DW!=24) ? B[7:4] : B),
.HSync (HS),
.VSync (VS),
.HBlank(HBL),
.VBlank(VBL),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.VGA_DE(VGA_DE)
);
endmodule
//============================================================================
//
// Screen +90/-90 deg. rotation
// Copyright (C) 2020 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module screen_rotate
(
input CLK_VIDEO,
input CE_PIXEL,
input [7:0] VGA_R,
input [7:0] VGA_G,
input [7:0] VGA_B,
input VGA_HS,
input VGA_VS,
input VGA_DE,
input rotate_ccw,
input no_rotate,
input flip,
output video_rotated,
output FB_EN,
output [4:0] FB_FORMAT,
output reg [11:0] FB_WIDTH,
output reg [11:0] FB_HEIGHT,
output [31:0] FB_BASE,
output [13:0] FB_STRIDE,
input FB_VBL,
input FB_LL,
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
output DDRAM_RD
);
parameter MEM_BASE = 7'b0010010; // buffer at 0x24000000, 3x8MB
reg do_flip;
assign DDRAM_CLK = CLK_VIDEO;
assign DDRAM_BURSTCNT = 1;
assign DDRAM_ADDR = {MEM_BASE, i_fb, ram_addr[22:3]};
assign DDRAM_BE = ram_addr[2] ? 8'hF0 : 8'h0F;
assign DDRAM_DIN = {ram_data,ram_data};
assign DDRAM_WE = ram_wr;
assign DDRAM_RD = 0;
assign FB_EN = fb_en[2];
assign FB_FORMAT = 5'b00110;
assign FB_BASE = {MEM_BASE,o_fb,23'd0};
assign FB_STRIDE = stride;
function [1:0] buf_next;
input [1:0] a,b;
begin
buf_next = 1;
if ((a==0 && b==1) || (a==1 && b==0)) buf_next = 2;
if ((a==1 && b==2) || (a==2 && b==1)) buf_next = 0;
end
endfunction
assign video_rotated = ~no_rotate;
always @(posedge CLK_VIDEO) begin
do_flip <= no_rotate && flip;
if( do_flip ) begin
FB_WIDTH <= hsz;
FB_HEIGHT <= vsz;
end else begin
FB_WIDTH <= vsz;
FB_HEIGHT <= hsz;
end
end
reg [1:0] i_fb,o_fb;
always @(posedge CLK_VIDEO) begin
reg old_vbl,old_vs;
old_vbl <= FB_VBL;
old_vs <= VGA_VS;
if(FB_LL) begin
if(~old_vbl & FB_VBL) o_fb<={1'b0,~i_fb[0]};
if(~old_vs & VGA_VS) i_fb<={1'b0,~i_fb[0]};
end
else begin
if(~old_vbl & FB_VBL) o_fb<=buf_next(o_fb,i_fb);
if(~old_vs & VGA_VS) i_fb<=buf_next(i_fb,o_fb);
end
end
initial begin
fb_en = 0;
end
reg [2:0] fb_en = 0;
reg [11:0] hsz = 320, vsz = 240;
reg [11:0] bwidth;
reg [22:0] bufsize;
always @(posedge CLK_VIDEO) begin
reg [11:0] hcnt = 0, vcnt = 0;
reg old_vs, old_de;
if(CE_PIXEL) begin
old_vs <= VGA_VS;
old_de <= VGA_DE;
hcnt <= hcnt + 1'd1;
if(~old_de & VGA_DE) begin
hcnt <= 1;
vcnt <= vcnt + 1'd1;
end
if(old_de & ~VGA_DE) begin
hsz <= hcnt;
if( do_flip ) bwidth <= hcnt + 2'd3;
end
if(~old_vs & VGA_VS) begin
vsz <= vcnt;
if( !do_flip ) bwidth <= vcnt + 2'd3;
vcnt <= 0;
fb_en <= {fb_en[1:0], ~no_rotate | flip};
end
if(old_vs & ~VGA_VS) bufsize <= (do_flip ? vsz : hsz ) * stride;
end
end
wire [13:0] stride = {bwidth[11:2], 4'd0};
reg [22:0] ram_addr, next_addr;
reg [31:0] ram_data;
reg ram_wr;
always @(posedge CLK_VIDEO) begin
reg [13:0] hcnt = 0;
reg old_vs, old_de;
ram_wr <= 0;
if(CE_PIXEL && FB_EN) begin
old_vs <= VGA_VS;
old_de <= VGA_DE;
if(~old_vs & VGA_VS) begin
next_addr <=
do_flip ? bufsize-3'd4 :
rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00};
hcnt <= rotate_ccw ? 3'd4 : {vsz-2'd2, 2'b00};
end
if(VGA_DE) begin
ram_wr <= 1;
ram_data <= {8'd0,VGA_B,VGA_G,VGA_R};
ram_addr <= next_addr;
next_addr <=
do_flip ? next_addr-3'd4 :
rotate_ccw ? (next_addr - stride) : (next_addr + stride);
end
if(old_de & ~VGA_DE & ~do_flip) begin
next_addr <= rotate_ccw ? (bufsize - stride + hcnt) : hcnt;
hcnt <= rotate_ccw ? (hcnt + 3'd4) : (hcnt - 3'd4);
end
end
end
endmodule

2877
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/sys/ascal.vhd
View File

File diff suppressed because it is too large Load Diff

296
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/sys/audio_out.v
View File

@@ -1,296 +0,0 @@
module audio_out
#(
parameter CLK_RATE = 24576000
)
(
input reset,
input clk,
//0 - 48KHz, 1 - 96KHz
input sample_rate,
input [31:0] flt_rate,
input [39:0] cx,
input [7:0] cx0,
input [7:0] cx1,
input [7:0] cx2,
input [23:0] cy0,
input [23:0] cy1,
input [23:0] cy2,
input [4:0] att,
input [1:0] mix,
input is_signed,
input [15:0] core_l,
input [15:0] core_r,
input [15:0] alsa_l,
input [15:0] alsa_r,
// I2S
output i2s_bclk,
output i2s_lrclk,
output i2s_data,
// SPDIF
output spdif,
// Sigma-Delta DAC
output dac_l,
output dac_r
);
localparam AUDIO_RATE = 48000;
localparam AUDIO_DW = 16;
localparam CE_RATE = AUDIO_RATE*AUDIO_DW*8;
localparam FILTER_DIV = (CE_RATE/(AUDIO_RATE*32))-1;
wire [31:0] real_ce = sample_rate ? {CE_RATE[30:0],1'b0} : CE_RATE[31:0];
reg mclk_ce;
always @(posedge clk) begin
reg [31:0] cnt;
mclk_ce = 0;
cnt = cnt + real_ce;
if(cnt >= CLK_RATE) begin
cnt = cnt - CLK_RATE;
mclk_ce = 1;
end
end
reg i2s_ce;
always @(posedge clk) begin
reg div;
i2s_ce <= 0;
if(mclk_ce) begin
div <= ~div;
i2s_ce <= div;
end
end
i2s i2s
(
.reset(reset),
.clk(clk),
.ce(i2s_ce),
.sclk(i2s_bclk),
.lrclk(i2s_lrclk),
.sdata(i2s_data),
.left_chan(al),
.right_chan(ar)
);
spdif toslink
(
.rst_i(reset),
.clk_i(clk),
.bit_out_en_i(mclk_ce),
.sample_i({ar,al}),
.spdif_o(spdif)
);
sigma_delta_dac #(15) sd_l
(
.CLK(clk),
.RESET(reset),
.DACin({~al[15], al[14:0]}),
.DACout(dac_l)
);
sigma_delta_dac #(15) sd_r
(
.CLK(clk),
.RESET(reset),
.DACin({~ar[15], ar[14:0]}),
.DACout(dac_r)
);
reg sample_ce;
always @(posedge clk) begin
reg [8:0] div = 0;
reg [1:0] add = 0;
div <= div + add;
if(!div) begin
div <= 2'd1 << sample_rate;
add <= 2'd1 << sample_rate;
end
sample_ce <= !div;
end
reg flt_ce;
always @(posedge clk) begin
reg [31:0] cnt = 0;
flt_ce = 0;
cnt = cnt + {flt_rate[30:0],1'b0};
if(cnt >= CLK_RATE) begin
cnt = cnt - CLK_RATE;
flt_ce = 1;
end
end
reg [15:0] cl,cr;
always @(posedge clk) begin
reg [15:0] cl1,cl2;
reg [15:0] cr1,cr2;
cl1 <= core_l; cl2 <= cl1;
if(cl2 == cl1) cl <= cl2;
cr1 <= core_r; cr2 <= cr1;
if(cr2 == cr1) cr <= cr2;
end
reg a_en1 = 0, a_en2 = 0;
always @(posedge clk, posedge reset) begin
reg [1:0] dly1 = 0;
reg [14:0] dly2 = 0;
if(reset) begin
dly1 <= 0;
dly2 <= 0;
a_en1 <= 0;
a_en2 <= 0;
end
else begin
if(flt_ce) begin
if(~&dly1) dly1 <= dly1 + 1'd1;
else a_en1 <= 1;
end
if(sample_ce) begin
if(!dly2[13+sample_rate]) dly2 <= dly2 + 1'd1;
else a_en2 <= 1;
end
end
end
wire [15:0] acl, acr;
IIR_filter #(.use_params(0)) IIR_filter
(
.clk(clk),
.reset(reset),
.ce(flt_ce & a_en1),
.sample_ce(sample_ce),
.cx(cx),
.cx0(cx0),
.cx1(cx1),
.cx2(cx2),
.cy0(cy0),
.cy1(cy1),
.cy2(cy2),
.input_l({~is_signed ^ cl[15], cl[14:0]}),
.input_r({~is_signed ^ cr[15], cr[14:0]}),
.output_l(acl),
.output_r(acr)
);
wire [15:0] adl;
DC_blocker dcb_l
(
.clk(clk),
.ce(sample_ce),
.sample_rate(sample_rate),
.mute(~a_en2),
.din(acl),
.dout(adl)
);
wire [15:0] adr;
DC_blocker dcb_r
(
.clk(clk),
.ce(sample_ce),
.sample_rate(sample_rate),
.mute(~a_en2),
.din(acr),
.dout(adr)
);
wire [15:0] al, audio_l_pre;
aud_mix_top audmix_l
(
.clk(clk),
.ce(sample_ce),
.att(att),
.mix(mix),
.core_audio(adl),
.pre_in(audio_r_pre),
.linux_audio(alsa_l),
.pre_out(audio_l_pre),
.out(al)
);
wire [15:0] ar, audio_r_pre;
aud_mix_top audmix_r
(
.clk(clk),
.ce(sample_ce),
.att(att),
.mix(mix),
.core_audio(adr),
.pre_in(audio_l_pre),
.linux_audio(alsa_r),
.pre_out(audio_r_pre),
.out(ar)
);
endmodule
module aud_mix_top
(
input clk,
input ce,
input [4:0] att,
input [1:0] mix,
input [15:0] core_audio,
input [15:0] linux_audio,
input [15:0] pre_in,
output reg [15:0] pre_out = 0,
output reg [15:0] out = 0
);
reg signed [16:0] a1, a2, a3, a4;
always @(posedge clk) if (ce) begin
a1 <= {core_audio[15],core_audio};
a2 <= a1 + {linux_audio[15],linux_audio};
pre_out <= a2[16:1];
case(mix)
0: a3 <= a2;
1: a3 <= $signed(a2) - $signed(a2[16:3]) + $signed(pre_in[15:2]);
2: a3 <= $signed(a2) - $signed(a2[16:2]) + $signed(pre_in[15:1]);
3: a3 <= {a2[16],a2[16:1]} + {pre_in[15],pre_in};
endcase
if(att[4]) a4 <= 0;
else a4 <= a3 >>> att[3:0];
//clamping
out <= ^a4[16:15] ? {a4[16],{15{a4[15]}}} : a4[15:0];
end
endmodule

73
Arcade_MiST/Toaplan v1 Hardware/mister/demonswld-main/sys/build_id.tcl
View File

@@ -1,73 +0,0 @@
# Build TimeStamp Verilog Module
# Jeff Wiencrot - 8/1/2011
# Sorgelig - 02/11/2019
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate "`define BUILD_DATE \"[clock format [ clock seconds ] -format %y%m%d]\""
# Create a Verilog file for output
set outputFileName "build_id.v"
set fileData ""
if { [file exists $outputFileName]} {
set outputFile [open $outputFileName "r"]
set fileData [read $outputFile]
close $outputFile
}
if {$buildDate ne $fileData} {
set outputFile [open $outputFileName "w"]
puts -nonewline $outputFile $buildDate
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated: [pwd]/$outputFileName: $buildDate"
}
}
# Build CDF file
# Sorgelig - 17/2/2018
proc generateCDF {revision device outpath} {
set outputFileName "jtag.cdf"
set outputFile [open $outputFileName "w"]
puts $outputFile "JedecChain;"
puts $outputFile " FileRevision(JESD32A);"
puts $outputFile " DefaultMfr(6E);"
puts $outputFile ""
puts $outputFile " P ActionCode(Ign)"
puts $outputFile " Device PartName(SOCVHPS) MfrSpec(OpMask(0));"
puts $outputFile " P ActionCode(Cfg)"
puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));"
puts $outputFile "ChainEnd;"
puts $outputFile ""
puts $outputFile "AlteraBegin;"
puts $outputFile " ChainType(JTAG);"
puts $outputFile "AlteraEnd;"
}
set project_name [lindex $quartus(args) 1]
set revision [lindex $quartus(args) 2]
if {[project_exists $project_name]} {
if {[string equal "" $revision]} {
project_open $project_name -revision [get_current_revision $project_name]
} else {
project_open $project_name -revision $revision
}
} else {
post_message -type error "Project $project_name does not exist"
exit
}
set device [get_global_assignment -name DEVICE]
set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY]
if [is_project_open] {
project_close
}
generateBuildID_Verilog
generateCDF $revision $device $outpath

Some files were not shown because too many files have changed in this diff Show More