mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-20 01:34:38 +00:00
Marcel
GitHub
commit
77e6820d8f
373
Arcade_MiST/Midway MCR 3 Monoboard/README.txt
Normal file
373
Arcade_MiST/Midway MCR 3 Monoboard/README.txt
Normal file
@ -0,0 +1,373 @@
|
||||
Midway MCR Monoboard MiST port
|
||||
|
||||
Common controls:
|
||||
ESC - coin for all players
|
||||
5,6,7 - coin for player 1,2,3 (MAME compatible)
|
||||
F1,F2,F3 (or 1,2,3) - player 1,2,3 start
|
||||
Controller 1 and 2 can be substitued with MAME-keys
|
||||
|
||||
Supported games:
|
||||
|
||||
Sarge
|
||||
=====
|
||||
Controls:
|
||||
Player 1: joystick 1 and joystick 2
|
||||
Player 2: joystick 3 and joystick 4
|
||||
|
||||
Creating SARGE.ROM on Linux:
|
||||
cat cpu_3b.bin cpu_5b.bin spr_8e.bin spr_6e.bin spr_5e.bin spr_4e.bin til_15a.bin til_15a.bin til_14b.bin til_14b.bin tcs_u5.bin tcs_u4.bin tcs_u5.bin tcs_u4.bin > SARGE.ROM
|
||||
|
||||
Max RPM
|
||||
=======
|
||||
Controls:
|
||||
Gear : button1/button2
|
||||
Steering/gas: TODO
|
||||
|
||||
Creating MAXRPM.ROM on Linux:
|
||||
cat pro.0 pro.1 fg-0 fg-1 fg-2 fg-3 bg-0 bg-1 turbskwk.u5 turbskwk.u4 > MAXRPM.ROM
|
||||
|
||||
Rampage
|
||||
=======
|
||||
Normal controls for maximum of 3 players.
|
||||
|
||||
Creating RAMPAGE.ROM on Linux:
|
||||
cat pro-0_3b_rev_3_8-27-86.3b pro-1_5b_rev_3_8-27-86.5b \
|
||||
fg-0_8e_6-30-86.8e fg-1_6e_6-30-86.6e fg-2_5e_6-30-86.5e fg-3_4e_6-30-86.4e \
|
||||
bg-0_u15_7-23-86.15a bg-1_u14_7-23-86.14b \
|
||||
u-17_rev.2_8-14-86.u17 u-18_rev.2_8-14-86.u18 u-7_rev.2_8-14-86.u7 u-8_rev.2_8-14-86.u8 > RAMPAGE.ROM
|
||||
|
||||
Power Drive
|
||||
===========
|
||||
3 players support
|
||||
Buttons 1,2 - Gas
|
||||
Button 3 - Wheelie
|
||||
Button 4 - Shift
|
||||
|
||||
Creating POWERDRV.ROM on Linux:
|
||||
cat pdrv3b.bin pdrv5b.bin pdrv8e.bin pdrv6e.bin pdrv5e.bin pdrv4e.bin \
|
||||
pdrv15a.bin pdrv14b.bin \
|
||||
power_drive_snd_u17.u17 power_drive_snd_u18.u18 power_drive_snd_u7.u7 power_drive_snd_u8.u8 > POWERDRV.ROM
|
||||
|
||||
Based on Darfpga's work:
|
||||
---------------------------------------------------------------------------------
|
||||
-- DE10_lite Top level for Timber (Midway MCR) by Dar (darfpga@aol.fr) (22/11/2019)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
--
|
||||
-- release rev 00 : initial release
|
||||
-- (22/11/2019)
|
||||
--
|
||||
-- /!\ /!\ cannot fit de10_lite : Full size sprite rom required more room or
|
||||
-- sdram usage (TO DO)
|
||||
--
|
||||
---------------------------------------------------------------------------------
|
||||
-- Educational use only
|
||||
-- Do not redistribute synthetized file with roms
|
||||
-- Do not redistribute roms whatever the form
|
||||
-- Use at your own risk
|
||||
---------------------------------------------------------------------------------
|
||||
-- Use timber_de10_lite.sdc to compile (Timequest constraints)
|
||||
-- /!\
|
||||
-- Don't forget to set device configuration mode with memory initialization
|
||||
-- (Assignments/Device/Pin options/Configuration mode)
|
||||
---------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main features :
|
||||
-- PS2 keyboard input @gpio pins 35/34 (beware voltage translation/protection)
|
||||
-- Audio pwm output @gpio pins 1/3 (beware voltage translation/protection)
|
||||
--
|
||||
-- Video : VGA 31kHz/60Hz progressive and TV 15kHz interlaced
|
||||
-- Cocktail mode : NO
|
||||
-- Sound : OK
|
||||
--
|
||||
-- For hardware schematic see my other project : NES
|
||||
--
|
||||
-- Uses 1 pll 40MHz from 50MHz to make 20MHz and 8Mhz
|
||||
--
|
||||
-- Board key :
|
||||
-- 0 : reset game
|
||||
--
|
||||
-- Keyboard players inputs :
|
||||
--
|
||||
-- F1 : Add coin
|
||||
-- F2 : Start 1 player
|
||||
-- F3 : Start 2 players
|
||||
-- F4 : Demo sound
|
||||
-- F5 : Separate audio
|
||||
-- F7 : Service mode
|
||||
-- F8 : 15kHz interlaced / 31 kHz progressive
|
||||
|
||||
-- SPACE : bouton 1
|
||||
-- v key : bouton 2
|
||||
-- RIGHT arrow : move right
|
||||
-- LEFT arrow : move left
|
||||
-- UP arrow : move up
|
||||
-- DOWN arrow : move down
|
||||
--
|
||||
-- Other details : see timber.vhd
|
||||
-- For USB inputs and SGT5000 audio output see my other project: xevious_de10_lite
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
-- Timber by Dar (darfpga@aol.fr) (22/11/2019)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
--
|
||||
-- release rev 00 : initial release
|
||||
-- (22/11/2019)
|
||||
--
|
||||
---------------------------------------------------------------------------------
|
||||
-- gen_ram.vhd & io_ps2_keyboard
|
||||
--------------------------------
|
||||
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
|
||||
-- http://www.syntiac.com/fpga64.html
|
||||
---------------------------------------------------------------------------------
|
||||
-- T80/T80se - Version : 304
|
||||
-----------------------------
|
||||
-- Z80 compatible microprocessor core
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
---------------------------------------------------------------------------------
|
||||
-- YM2149 (AY-3-8910)
|
||||
-- Copyright (c) MikeJ - Jan 2005
|
||||
---------------------------------------------------------------------------------
|
||||
-- Educational use only
|
||||
-- Do not redistribute synthetized file with roms
|
||||
-- Do not redistribute roms whatever the form
|
||||
-- Use at your own risk
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
-- Features :
|
||||
-- Video : VGA 31Khz/60Hz progressive and TV 15kHz interlaced
|
||||
-- Coctail mode : NO
|
||||
-- Sound : OK
|
||||
|
||||
-- Use with MAME roms from timber.zip
|
||||
--
|
||||
-- Use make_timber_proms.bat to build vhd file from binaries
|
||||
-- (CRC list included)
|
||||
|
||||
-- Timber (midway mcr) Hardware caracteristics :
|
||||
--
|
||||
-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram,
|
||||
-- sprite data ram, I/O, sound board register and trigger.
|
||||
-- 56Kx8bits program rom
|
||||
--
|
||||
-- One char/background tile map 30x32
|
||||
-- 2x8Kx8bits graphics rom 4bits/pixel + 2 bit color set
|
||||
-- rbg programmable ram palette 64 colors 9bits : 3red 3green 3blue
|
||||
--
|
||||
-- 128 sprites, up to ~30/line, 32x32 with flip H/V
|
||||
-- 4x32Kx8bits graphics rom 4bits/pixel + 2 bit color set
|
||||
-- rbg programmable ram palette 64 colors 9bits : 3red 3green 3blue
|
||||
--
|
||||
-- Working ram : 2Kx8bits
|
||||
-- video (char/background) ram : 2Kx8bits
|
||||
-- Sprites ram : 512x8bits + 512x8bits cache buffer
|
||||
|
||||
-- Sprites line buffer rams (graphics and colors) : 1 scan line delay flip/flop 2x256x16bits
|
||||
--
|
||||
-- SOUND : see tron_sound_board.vhd
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- Schematics remarks :
|
||||
--
|
||||
-- Display is 512x480 pixels (video 635x525 lines @ 20MHz )
|
||||
|
||||
-- 635/20e6 = 31.75us per line (31.750KHz)
|
||||
-- 31.75*525 = 16.67ms per frame (59.99Hz)
|
||||
--
|
||||
-- Original video is interlaced 240 display lines per 1/2 frame
|
||||
--
|
||||
-- H0 and V0 are not use for background => each bg tile is 16x16 pixel but
|
||||
-- background graphics is 2x2 pixels defintion.
|
||||
--
|
||||
-- Sprite are 32x32 pixels with 1x1 pixel definition, 16 lines for odd 1/2
|
||||
-- frame and 16 lines for even 2/2 frame thanks to V8 on sprite rom ROMAD2
|
||||
-- (look at 74ls86 G1 pin 9 on video genration board schematics)
|
||||
--
|
||||
-- *H and V stand for Horizontal en Vertical counter (Hcnt, Vcnt in VHDL code)
|
||||
--
|
||||
-- /!\ For VHDL port interlaced video mode is replaced with progressive video
|
||||
-- mode.
|
||||
--
|
||||
-- Real hardware uses background ram access after each 1/2 frame (~line 240
|
||||
-- and 480). In these areas cpu can access ram since scanlines are out of
|
||||
-- visible display. In progessive mode there are video access around lines 240.
|
||||
-- These accesses will create video artfacts aound mid display. In VHDL code
|
||||
-- ram access is muliplexed between cpu and scanlines by using hcnt(0) in
|
||||
-- order to avoid these artefacts.
|
||||
--
|
||||
-- Sprite data are stored first by cpu into a 'cache' buffer (staging ram at
|
||||
-- K6/L6) this buffer is read and write for cpu. After visible display, cache
|
||||
-- buffer (512x8) is moved to actual sprite ram buffer (512x8). Actual sprite
|
||||
-- buffer is access by transfer address counter during 2 scanlines after
|
||||
-- visible area and only by sprite machine during visible area.
|
||||
--
|
||||
-- Thus cpu can read and update sprites position during entire frame except
|
||||
-- during 2 lines.
|
||||
--
|
||||
-- Sprite data are organised (as seen by cpu F000-F1FF) into 128 * 4bytes.
|
||||
-- bytes #1 : Vertical position
|
||||
-- bytes #2 : code and attribute
|
||||
-- bytes #3 : Horizontal position
|
||||
-- bytes #4 : not used
|
||||
--
|
||||
-- Athough 1x1 pixel defintion sprite position horizontal/vertical is made on
|
||||
-- on a 2x2 grid (due to only 8bits for position data)
|
||||
--
|
||||
-- Z80-CTC : interruption ar managed by CTC chip. ONly channel 3 is trigered
|
||||
-- by hardware signal line 493. channel 0 to 2 are in timer mode. Schematic
|
||||
-- show zc/to of channel 0 connected to clk/trg of channel 1. This seems to be
|
||||
-- unsued for that (Kick) game.
|
||||
--
|
||||
-- Z80-CTC VHDL port keep separated interrupt controler and each counter so
|
||||
-- one can use them on its own. Priority daisy-chain is not done (not used in
|
||||
-- that game). clock polarity selection is not done since it has no meaning
|
||||
-- with digital clock/enable (e.g cpu_ena signal) method.
|
||||
--
|
||||
-- Ressource : input clock 40MHz is chosen to allow easy making of 20MHz for
|
||||
-- pixel clock and 8MHz signal for amplitude modulation circuit of ssio board
|
||||
--
|
||||
-- TODO :
|
||||
-- Working ram could be initialized to set initial difficulty level and
|
||||
-- initial bases (live) number. Otherwise one can set it up by using service
|
||||
-- menu at each power up.
|
||||
--
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
/!\ /!\ HALF SIZE SPRITE ROM /!\ /!\
|
||||
|
||||
Full size sprite rom would required more room or external ram
|
||||
|
||||
+----------------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+------------------------------------+---------------------------------------------+
|
||||
; Fitter Status ; Successful - Fri Nov 22 17:33:36 2019 ;
|
||||
; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
|
||||
; Revision Name ; timber_de10_lite ;
|
||||
; Top-level Entity Name ; timber_de10_lite ;
|
||||
; Family ; MAX 10 ;
|
||||
; Device ; 10M50DAF484C6GES ;
|
||||
; Timing Models ; Preliminary ;
|
||||
; Total logic elements ; 6,779 / 49,760 ( 14 % ) ;
|
||||
; Total combinational functions ; 6,540 / 49,760 ( 13 % ) ;
|
||||
; Dedicated logic registers ; 1,724 / 49,760 ( 3 % ) ;
|
||||
; Total registers ; 1724 ;
|
||||
; Total pins ; 105 / 360 ( 29 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 1,399,360 / 1,677,312 ( 83 % ) <-- WITH HALF SIZE SPRITE ROM ONLY
|
||||
; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ;
|
||||
; Total PLLs ; 1 / 4 ( 25 % ) ;
|
||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||
; ADC blocks ; 0 / 2 ( 0 % ) ;
|
||||
+------------------------------------+---------------------------------------------+
|
||||
|
||||
---------------
|
||||
VHDL File list
|
||||
---------------
|
||||
|
||||
de10_lite/max10_pll_40M.vhd Pll 40MHz from 50MHz altera mf
|
||||
|
||||
rtl_dar/timber_de10_lite.vhd Top level for de10_lite board
|
||||
rtl_dar/timber.vhd Main CPU and video boards logic
|
||||
rtl_dar/timber_sound_board.vhd Main sound board logic
|
||||
rtl_dar/ctc_controler.vhd Z80-CTC controler
|
||||
rtl_dar/ctc_counter.vhd Z80-CTC counter
|
||||
|
||||
rtl_mikej/YM2149_linmix.vhd Copyright (c) MikeJ - Jan 2005
|
||||
|
||||
rtl_T80_304/T80se.vhdT80 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
rtl_T80_304/T80_Reg.vhd
|
||||
rtl_T80_304/T80_Pack.vhd
|
||||
rtl_T80_304/T80_MCode.vhd
|
||||
rtl_T80_304/T80_ALU.vhd
|
||||
rtl_T80_304/T80.vhd
|
||||
|
||||
rtl_dar/kbd_joystick.vhd Keyboard key to player/coin input
|
||||
rtl_dar/io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
|
||||
rtl_dar/gen_ram.vhd Generic RAM (Peter Wendrich + DAR Modification)
|
||||
rtl_dar/decodeur_7_seg.vhd 7 segments display decoder
|
||||
|
||||
rtl_dar/proms/timber_cpu.vhd CPU board PROMS
|
||||
rtl_dar/proms/timber_bg_bits_2.vhd
|
||||
rtl_dar/proms/timber_bg_bits_1.vhd
|
||||
|
||||
rtl_dar/proms/timber_sp_bits.vhd Video board PROMS
|
||||
|
||||
rtl_dar/proms/timber_sound_cpu.vhd Sound board PROMS
|
||||
rtl_dar/proms/midssio_82s123.vhd
|
||||
|
||||
----------------------
|
||||
Quartus project files
|
||||
----------------------
|
||||
de10_lite/timber_de10_lite.sdc Timequest constraints file
|
||||
de10_lite/timber_de10_lite.qsf de10_lite settings (files,pins...)
|
||||
de10_lite/timber_de10_lite.qpf de10_lite project
|
||||
|
||||
-----------------------------
|
||||
Required ROMs (Not included)
|
||||
-----------------------------
|
||||
You need the following 18 ROMs binary files from timber.zip and midssio.zip(MAME)
|
||||
|
||||
timpg0.bin CRC 377032ab
|
||||
timpg1.bin CRC fd772836
|
||||
timpg2.bin CRC 632989f9
|
||||
timpg3.bin CRC dae8a0dc
|
||||
|
||||
tima7.bin CRC c615dc3e
|
||||
tima8.bin CRC 83841c87
|
||||
tima9.bin CRC 22bcdcd3
|
||||
|
||||
timbg1.bin CRC b1cb2651
|
||||
timbg0.bin CRC 2ae352c4
|
||||
|
||||
timfg1.bin CRC 81de4a73
|
||||
timfg0.bin CRC 7f3a4f59
|
||||
timfg3.bin CRC 37c03272
|
||||
timfg2.bin CRC e2c2885c
|
||||
timfg5.bin CRC eb636216
|
||||
timfg4.bin CRC b7105eb7
|
||||
timfg7.bin CRC d9c27475
|
||||
timfg6.bin CRC 244778e8
|
||||
|
||||
midssio_82s123.12d CRC e1281ee9
|
||||
|
||||
------
|
||||
Tools
|
||||
------
|
||||
You need to build vhdl files from the binary file :
|
||||
- Unzip the roms file in the tools/timber_unzip directory
|
||||
- Double click (execute) the script tools/make_timber_proms.bat to get the following 6 files
|
||||
|
||||
timber_cpu.vhd
|
||||
timber_sound_cpu.vhd
|
||||
timber_bg_bits_1.vhd
|
||||
timber_bg_bits_2.vhd
|
||||
timber_sp_bits.vhd
|
||||
midssio_82s123.vhd
|
||||
|
||||
|
||||
*DO NOT REDISTRIBUTE THESE FILES*
|
||||
|
||||
VHDL files are needed to compile and include roms into the project
|
||||
|
||||
The script make_timber_proms.bat uses make_vhdl_prom executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux.
|
||||
|
||||
Source code of make_vhdl_prom.c is also delivered.
|
||||
|
||||
---------------------------------
|
||||
Compiling for de10_lite
|
||||
---------------------------------
|
||||
You can build the project with ROM image embeded in the sof file.
|
||||
*DO NOT REDISTRIBUTE THESE FILES*
|
||||
|
||||
3 steps
|
||||
|
||||
- put the VHDL ROM files (.vhd) into the rtl_dar/proms directory
|
||||
- build timber_de10_lite
|
||||
- program timber_de10_lite.sof
|
||||
|
||||
------------------------
|
||||
------------------------
|
||||
End of file
|
||||
------------------------
|
||||
15
Arcade_MiST/Midway MCR 3 Monoboard/clean.bat
Normal file
15
Arcade_MiST/Midway MCR 3 Monoboard/clean.bat
Normal file
@ -0,0 +1,15 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del *.qws
|
||||
del *.ppf
|
||||
del *.qip
|
||||
del *.ddb
|
||||
pause
|
||||
30
Arcade_MiST/Midway MCR 3 Monoboard/mcr3mono.qpf
Normal file
30
Arcade_MiST/Midway MCR 3 Monoboard/mcr3mono.qpf
Normal file
@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
# Date created = 13:02:51 November 09, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.1"
|
||||
DATE = "13:02:51 November 09, 2019"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "mcr3mono"
|
||||
235
Arcade_MiST/Midway MCR 3 Monoboard/mcr3mono.qsf
Normal file
235
Arcade_MiST/Midway MCR 3 Monoboard/mcr3mono.qsf
Normal file
@ -0,0 +1,235 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
# Date created = 19:17:51 November 03, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# mcr3mono_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
|
||||
set_location_assignment PIN_54 -to CLOCK_27
|
||||
set_location_assignment PIN_144 -to VGA_R[5]
|
||||
set_location_assignment PIN_143 -to VGA_R[4]
|
||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
||||
set_location_assignment PIN_137 -to VGA_R[1]
|
||||
set_location_assignment PIN_135 -to VGA_R[0]
|
||||
set_location_assignment PIN_133 -to VGA_B[5]
|
||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_4 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_6 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_8 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_10 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_11 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_28 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_50 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_30 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_32 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
|
||||
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
|
||||
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY MCR3Mono_MiST
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name ENABLE_NCE_PIN OFF
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE output_files/cnt.stp
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE ON
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/MCR3Mono_MiST.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/spinner.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/mcr3mono.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ctc_counter.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ctc_controler.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cmos_ram.vhd
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sounds_good.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/turbo_cheap_squeak.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/z80ctc_top.vhd
|
||||
set_global_assignment -name QIP_FILE ../../common/CPU/68000/FX68k/fx68k.qip
|
||||
set_global_assignment -name VHDL_FILE ../../common/IO/pia6821.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../common/CPU/MC6809/cpu09l_128a.vhd
|
||||
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
|
||||
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/snd.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/mcr3.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/sg.stp
|
||||
set_global_assignment -name CDF_FILE output_files/mcr3mono.cdf
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/cnt.stp
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
134
Arcade_MiST/Midway MCR 3 Monoboard/mcr3mono.sdc
Normal file
134
Arcade_MiST/Midway MCR 3 Monoboard/mcr3mono.sdc
Normal file
@ -0,0 +1,134 @@
|
||||
## Generated SDC file "vectrex_MiST.out.sdc"
|
||||
|
||||
## Copyright (C) 1991-2013 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
|
||||
|
||||
## DATE "Sun Jun 24 12:53:00 2018"
|
||||
|
||||
##
|
||||
## DEVICE "EP3C25E144C8"
|
||||
##
|
||||
|
||||
# Clock constraints
|
||||
|
||||
# Automatically constrain PLL and other generated clocks
|
||||
derive_pll_clocks -create_base_clocks
|
||||
|
||||
# Automatically calculate clock uncertainty to jitter and other effects.
|
||||
derive_clock_uncertainty
|
||||
|
||||
# tsu/th constraints
|
||||
|
||||
# tco constraints
|
||||
|
||||
# tpd constraints
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
|
||||
|
||||
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
|
||||
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
|
||||
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
|
||||
|
||||
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
|
||||
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
|
||||
|
||||
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
set_multicycle_path -to {VGA_*[*]} -setup 2
|
||||
set_multicycle_path -to {VGA_*[*]} -hold 1
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
556
Arcade_MiST/Midway MCR 3 Monoboard/rtl/MCR3Mono_MiST.sv
Normal file
556
Arcade_MiST/Midway MCR 3 Monoboard/rtl/MCR3Mono_MiST.sv
Normal file
@ -0,0 +1,556 @@
|
||||
//============================================================================
|
||||
// MCR3 monoboard arcades top-level for MiST
|
||||
// Sarge/Max RPM/Rampage/Power Drive
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//============================================================================
|
||||
|
||||
module MCR3Mono_MiST(
|
||||
output LED,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input CONF_DATA0,
|
||||
input CLOCK_27,
|
||||
output [12:0] SDRAM_A,
|
||||
inout [15:0] SDRAM_DQ,
|
||||
output SDRAM_DQML,
|
||||
output SDRAM_DQMH,
|
||||
output SDRAM_nWE,
|
||||
output SDRAM_nCAS,
|
||||
output SDRAM_nRAS,
|
||||
output SDRAM_nCS,
|
||||
output [1:0] SDRAM_BA,
|
||||
output SDRAM_CLK,
|
||||
output SDRAM_CKE
|
||||
);
|
||||
|
||||
`include "rtl/build_id.v"
|
||||
|
||||
// Uncomment one to build with game-specific core name/inputs/sound board
|
||||
`define CORE_NAME "SARGE"
|
||||
//`define CORE_NAME "MAXRPM"
|
||||
//`define CORE_NAME "RAMPAGE"
|
||||
//`define CORE_NAME "POWERDRV"
|
||||
|
||||
reg sg; // Sounds Good board
|
||||
reg [7:0] input0;
|
||||
reg [7:0] input1;
|
||||
reg [7:0] input2;
|
||||
reg [7:0] input3;
|
||||
reg [7:0] input4;
|
||||
reg [7:0] output5;
|
||||
reg [7:0] output6;
|
||||
|
||||
// Game specific sound board/DIP/input settings
|
||||
always @(*) begin
|
||||
if (`CORE_NAME == "SARGE" ||
|
||||
`CORE_NAME == "MAXRPM")
|
||||
sg = 0;
|
||||
else
|
||||
sg = 1;
|
||||
|
||||
input0 = 8'hff;
|
||||
input1 = 8'hff;
|
||||
input2 = 8'hff;
|
||||
input3 = 8'hff;
|
||||
input4 = 8'hff;
|
||||
|
||||
if (`CORE_NAME == "SARGE") begin
|
||||
// Two stick/player like the original
|
||||
input0 = ~{2'b00, service, 1'b0, m_start2, m_start1, m_coin2, m_coin1};
|
||||
input1 = ~{m_fire1 | m_fire1b, m_fire1 | m_fire1b, m_fire2 | m_fire2b, m_fire2 | m_fire2b, m_down1, m_up1, m_down2, m_up2};
|
||||
input2 = ~{m_fire3 | m_fire3b, m_fire3 | m_fire3b, m_fire4 | m_fire4b, m_fire4 | m_fire4b, m_down3, m_up3, m_down4, m_up4};
|
||||
end else if (`CORE_NAME == "MAXRPM") begin
|
||||
input0 = ~{1'b0, service, 2'b00, m_start1, m_start2, m_coin1, m_coin2};
|
||||
input1 = {pedal1[5:2], pedal2[5:2]};
|
||||
input2 = ~{maxrpm_gear1, maxrpm_gear2};
|
||||
end else if (`CORE_NAME == "RAMPAGE") begin
|
||||
// normal controls for 3 players
|
||||
input0 = ~{2'b00, service, 1'b0, 2'b00, m_coin2, m_coin1};
|
||||
input1 = ~{2'b00, m_fire1b, m_fire1, m_left1, m_down1, m_right1, m_up1};
|
||||
input2 = ~{2'b00, m_fire2b, m_fire2, m_left2, m_down2, m_right2, m_up2};
|
||||
input4 = ~{2'b00, m_fire3b, m_fire3, m_left3, m_down3, m_right3, m_up3};
|
||||
end else if (`CORE_NAME == "POWERDRV") begin
|
||||
// Controls for 3 players using 4 buttons/joystick
|
||||
input0 = ~{2'b00, service, 1'b0, 1'b0, m_coin3, m_coin2, m_coin1};
|
||||
input1 = ~{m_fire2b, m_fire2, powerdrv_gear[1], m_fire2c, m_fire1b, m_fire1, powerdrv_gear[0], m_fire1c};
|
||||
input2 = ~{sndstat[0], 3'b000, m_fire3b, m_fire3, powerdrv_gear[2], m_fire3c};
|
||||
end
|
||||
end
|
||||
|
||||
localparam CONF_STR = {
|
||||
`CORE_NAME,";ROM;",
|
||||
"O2,Rotate Controls,Off,On;",
|
||||
"O5,Blend,Off,On;",
|
||||
"O6,Swap Joystick,Off,On;",
|
||||
"O7,Service,Off,On;",
|
||||
"T0,Reset;",
|
||||
"V,v1.1.",`BUILD_DATE
|
||||
};
|
||||
|
||||
wire blend = status[5];
|
||||
wire joyswap = status[6];
|
||||
wire service = status[7];
|
||||
|
||||
assign LED = ~ioctl_downl;
|
||||
assign SDRAM_CLK = clk_mem;
|
||||
assign SDRAM_CKE = 1;
|
||||
|
||||
wire clk_sys, clk_mem;
|
||||
wire pll_locked;
|
||||
pll_mist pll(
|
||||
.inclk0(CLOCK_27),
|
||||
.areset(0),
|
||||
.c0(clk_sys),
|
||||
.c1(clk_mem),
|
||||
.locked(pll_locked)
|
||||
);
|
||||
|
||||
wire [31:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [7:0] joy_0;
|
||||
wire [7:0] joy_1;
|
||||
wire [7:0] joy_2;
|
||||
wire [7:0] joy_3;
|
||||
wire scandoublerD;
|
||||
wire ypbpr;
|
||||
wire [9:0] audio;
|
||||
wire hs, vs, cs;
|
||||
wire blankn;
|
||||
wire [2:0] g, r, b;
|
||||
|
||||
wire ioctl_downl;
|
||||
wire [7:0] ioctl_index;
|
||||
wire ioctl_wr;
|
||||
wire [24:0] ioctl_addr;
|
||||
wire [7:0] ioctl_dout;
|
||||
|
||||
/*
|
||||
ROM structure:
|
||||
|
||||
Sarge, MaxRPM (Turbo Cheap Squeak board):
|
||||
00000-0FFFF MAIN CPU 64k
|
||||
10000-2FFFF GFX2 (Sprites) 128k
|
||||
30000-37FFF GFX1 32k
|
||||
38000- TCS 32k
|
||||
|
||||
Rampage, Power Drive (Sounds Good board):
|
||||
00000-0FFFF MAIN CPU 64k
|
||||
10000-4FFFF GFX2 (Sprites) 256k
|
||||
50000-57FFF GFX1 32k
|
||||
58000- SG 128k
|
||||
*/
|
||||
|
||||
data_io data_io(
|
||||
.clk_sys ( clk_sys ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS2 ( SPI_SS2 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.ioctl_download( ioctl_downl ),
|
||||
.ioctl_index ( ioctl_index ),
|
||||
.ioctl_wr ( ioctl_wr ),
|
||||
.ioctl_addr ( ioctl_addr ),
|
||||
.ioctl_dout ( ioctl_dout )
|
||||
);
|
||||
|
||||
wire [15:0] rom_addr;
|
||||
wire [15:0] rom_do;
|
||||
wire [17:0] snd_addr;
|
||||
wire [15:0] snd_do;
|
||||
wire [15:0] sp_addr;
|
||||
wire [31:0] sp_do;
|
||||
wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h10000;
|
||||
wire [24:0] snd_ioctl_addr = ioctl_addr - snd_offset;
|
||||
reg port1_req, port2_req;
|
||||
reg [23:0] port1_a;
|
||||
reg [23:0] port2_a;
|
||||
reg [19:0] snd_offset;
|
||||
reg [19:0] gfx1_offset;
|
||||
|
||||
always @(*) begin
|
||||
if (sg) begin
|
||||
snd_offset = 20'h58000;
|
||||
gfx1_offset = 20'h50000;
|
||||
port1_a = ioctl_addr[23:0];
|
||||
port1_a = (ioctl_addr < snd_offset) ? ioctl_addr[23:0] : // 8 bit main ROM
|
||||
snd_offset + {snd_ioctl_addr[17], snd_ioctl_addr[15:0], snd_ioctl_addr[16]}; // 16 bit Sounds Good ROM
|
||||
|
||||
// merge sprite roms (4x64k) into 32-bit wide words
|
||||
port2_a = {sp_ioctl_addr[23:18], sp_ioctl_addr[15:0], sp_ioctl_addr[17:16]};
|
||||
end else begin
|
||||
snd_offset = 20'h38000;
|
||||
gfx1_offset = 20'h30000;
|
||||
port1_a = ioctl_addr[23:0];
|
||||
// merge sprite roms (4x32k) into 32-bit wide words
|
||||
port2_a = {sp_ioctl_addr[23:17], sp_ioctl_addr[14:0], sp_ioctl_addr[16:15]};
|
||||
end
|
||||
end
|
||||
|
||||
sdram sdram(
|
||||
.*,
|
||||
.init_n ( pll_locked ),
|
||||
.clk ( clk_mem ),
|
||||
|
||||
// port1 used for main + sound CPU
|
||||
.port1_req ( port1_req ),
|
||||
.port1_ack ( ),
|
||||
.port1_a ( port1_a[23:1] ),
|
||||
.port1_ds ( {port1_a[0], ~port1_a[0]} ),
|
||||
.port1_we ( ioctl_downl ),
|
||||
.port1_d ( {ioctl_dout, ioctl_dout} ),
|
||||
.port1_q ( ),
|
||||
|
||||
.cpu1_addr ( cpu1_addr ), //Turbo Cheap Squeak/Sounds Good with higher priority
|
||||
.cpu1_q ( snd_do ),
|
||||
.cpu2_addr ( ioctl_downl ? 18'h3ffff : {3'b000, rom_addr[15:1]} ),
|
||||
.cpu2_q ( rom_do ),
|
||||
|
||||
// port2 for sprite graphics
|
||||
.port2_req ( port2_req ),
|
||||
.port2_ack ( ),
|
||||
.port2_a ( port2_a[23:1] ),
|
||||
.port2_ds ( {port2_a[0], ~port2_a[0]} ),
|
||||
.port2_we ( ioctl_downl ),
|
||||
.port2_d ( {ioctl_dout, ioctl_dout} ),
|
||||
.port2_q ( ),
|
||||
|
||||
.sp_addr ( ioctl_downl ? 16'hffff : sp_addr ),
|
||||
.sp_q ( sp_do )
|
||||
);
|
||||
|
||||
reg [19:1] cpu1_addr;
|
||||
|
||||
// ROM download controller
|
||||
always @(posedge clk_sys) begin
|
||||
reg ioctl_wr_last = 0;
|
||||
|
||||
ioctl_wr_last <= ioctl_wr;
|
||||
if (ioctl_downl) begin
|
||||
if (~ioctl_wr_last && ioctl_wr) begin
|
||||
port1_req <= ~port1_req;
|
||||
port2_req <= ~port2_req;
|
||||
end
|
||||
end
|
||||
// register for better timings
|
||||
cpu1_addr <= ioctl_downl ? 19'h7ffff : (snd_offset[19:1] + snd_addr[17:1]);
|
||||
end
|
||||
|
||||
// reset signal generation
|
||||
reg reset = 1;
|
||||
reg rom_loaded = 0;
|
||||
always @(posedge clk_sys) begin
|
||||
reg ioctl_downlD;
|
||||
reg [15:0] reset_count;
|
||||
ioctl_downlD <= ioctl_downl;
|
||||
|
||||
// generate a second reset signal - needed for some reason
|
||||
if (status[0] | buttons[1] | ~rom_loaded) reset_count <= 16'hffff;
|
||||
else if (reset_count != 0) reset_count <= reset_count - 1'd1;
|
||||
|
||||
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
|
||||
reset <= status[0] | buttons[1] | ioctl_downl | ~rom_loaded | (reset_count == 16'h0001);
|
||||
end
|
||||
|
||||
wire [1:0] sndstat;
|
||||
|
||||
mcr3mono mcr3mono (
|
||||
.clock_40(clk_sys),
|
||||
.reset(reset),
|
||||
.video_r(r),
|
||||
.video_g(g),
|
||||
.video_b(b),
|
||||
.video_blankn(blankn),
|
||||
.video_hs(hs),
|
||||
.video_vs(vs),
|
||||
.video_csync(cs),
|
||||
.tv15Khz_mode(scandoublerD),
|
||||
|
||||
.soundsgood(sg),
|
||||
.snd_stat(sndstat),
|
||||
.audio_out(audio),
|
||||
|
||||
.input_0(input0),
|
||||
.input_1(input1),
|
||||
.input_2(input2),
|
||||
.input_3(input3),
|
||||
.input_4(input4),
|
||||
.output_5(output5),
|
||||
.output_6(output6),
|
||||
|
||||
.cpu_rom_addr ( rom_addr ),
|
||||
.cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
|
||||
.snd_rom_addr ( snd_addr ),
|
||||
.snd_rom_do ( snd_do ),
|
||||
.sp_addr ( sp_addr ),
|
||||
.sp_graphx32_do ( sp_do ),
|
||||
|
||||
.dl_addr(ioctl_addr-gfx1_offset),
|
||||
.dl_data(ioctl_dout),
|
||||
.dl_wr(ioctl_wr)
|
||||
);
|
||||
|
||||
wire vs_out;
|
||||
wire hs_out;
|
||||
assign VGA_VS = scandoublerD | vs_out;
|
||||
assign VGA_HS = scandoublerD ? cs : hs_out;
|
||||
|
||||
mist_video #(.COLOR_DEPTH(3)) mist_video(
|
||||
.clk_sys ( clk_sys ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS3 ( SPI_SS3 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.R ( blankn ? r : 0 ),
|
||||
.G ( blankn ? g : 0 ),
|
||||
.B ( blankn ? b : 0 ),
|
||||
.HSync ( hs ),
|
||||
.VSync ( vs ),
|
||||
.VGA_R ( VGA_R ),
|
||||
.VGA_G ( VGA_G ),
|
||||
.VGA_B ( VGA_B ),
|
||||
.VGA_VS ( vs_out ),
|
||||
.VGA_HS ( hs_out ),
|
||||
.rotate ( {1'b1,status[2]} ),
|
||||
.ce_divider ( 1 ),
|
||||
.blend ( blend ),
|
||||
.scandoubler_disable(1),//scandoublerD ),
|
||||
.no_csync ( 1'b1 ),
|
||||
.ypbpr ( ypbpr )
|
||||
);
|
||||
|
||||
user_io #(
|
||||
.STRLEN(($size(CONF_STR)>>3)))
|
||||
user_io(
|
||||
.clk_sys (clk_sys ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
.SPI_MISO (SPI_DO ),
|
||||
.SPI_MOSI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.joystick_0 (joy_0 ),
|
||||
.joystick_1 (joy_1 ),
|
||||
.joystick_2 (joy_2 ),
|
||||
.joystick_3 (joy_3 ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
dac #(10) dac(
|
||||
.clk_i(clk_sys),
|
||||
.res_n_i(1),
|
||||
.dac_i(audio),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
|
||||
wire [7:0] joystick_0 = joyswap ? joy_1 : joy_0;
|
||||
wire [7:0] joystick_1 = joyswap ? joy_0 : joy_1;
|
||||
|
||||
// Power Drive gear
|
||||
reg [2:0] powerdrv_gear;
|
||||
always @(posedge clk_sys) begin
|
||||
reg [2:0] gear_old;
|
||||
if (reset) powerdrv_gear <= 0;
|
||||
else begin
|
||||
gear_old <= {m_fire3d, m_fire2d, m_fire1d};
|
||||
if (~gear_old[0] & m_fire1d) powerdrv_gear[0] <= ~powerdrv_gear[0];
|
||||
if (~gear_old[1] & m_fire2d) powerdrv_gear[1] <= ~powerdrv_gear[1];
|
||||
if (~gear_old[2] & m_fire3d) powerdrv_gear[2] <= ~powerdrv_gear[2];
|
||||
end
|
||||
end
|
||||
|
||||
//Pedals for Max RPM
|
||||
wire [5:0] pedal1;
|
||||
spinner spinner1 (
|
||||
.clock_40(clk_sys),
|
||||
.reset(reset),
|
||||
.btn_acc(),
|
||||
.btn_left(m_up1),
|
||||
.btn_right(m_down1),
|
||||
.ctc_zc_to_2(vs),
|
||||
.spin_angle(pedal1)
|
||||
);
|
||||
|
||||
wire [5:0] pedal2;
|
||||
spinner spinner2 (
|
||||
.clock_40(clk_sys),
|
||||
.reset(reset),
|
||||
.btn_acc(),
|
||||
.btn_left(m_up2),
|
||||
.btn_right(m_down2),
|
||||
.ctc_zc_to_2(vs),
|
||||
.spin_angle(pedal2)
|
||||
);
|
||||
|
||||
// MaxRPM gearbox
|
||||
wire [3:0] maxrpm_gear_bits[5] = '{ 4'h0, 4'h5, 4'h6, 4'h1, 4'h2 };
|
||||
wire [3:0] maxrpm_gear1 = maxrpm_gear_bits[gear1];
|
||||
wire [3:0] maxrpm_gear2 = maxrpm_gear_bits[gear2];
|
||||
reg [2:0] gear1;
|
||||
reg [2:0] gear2;
|
||||
always @(posedge clk_sys) begin
|
||||
reg m_fire1_last, m_fire1b_last;
|
||||
reg m_fire2_last, m_fire2b_last;
|
||||
|
||||
if (reset) begin
|
||||
gear1 <= 0;
|
||||
gear2 <= 0;
|
||||
end else begin
|
||||
m_fire1_last <= m_fire1;
|
||||
m_fire1b_last <= m_fire1b;
|
||||
m_fire2_last <= m_fire2;
|
||||
m_fire2b_last <= m_fire2b;
|
||||
|
||||
if (m_start1) gear1 <= 0;
|
||||
else if (~m_fire1_last && m_fire1 && gear1 != 3'd4) gear1 <= gear1 + 1'd1;
|
||||
else if (~m_fire1b_last && m_fire1b && gear1 != 3'd0) gear1 <= gear1 - 1'd1;
|
||||
|
||||
if (m_start2) gear2 <= 0;
|
||||
else if (~m_fire2_last && m_fire2 && gear2 != 3'd4) gear2 <= gear2 + 1'd1;
|
||||
else if (~m_fire2b_last && m_fire2b && gear2 != 3'd0) gear2 <= gear2 - 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
// Generic controls - make a module from this?
|
||||
wire m_coin1 = btn_coin1_mame | btn_coin;
|
||||
wire m_start1 = btn_start1_mame | btn_one_player;
|
||||
wire m_up1 = btn_up | joystick_0[3];
|
||||
wire m_down1 = btn_down | joystick_0[2];
|
||||
wire m_left1 = btn_left | joystick_0[1];
|
||||
wire m_right1 = btn_right | joystick_0[0];
|
||||
wire m_fire1 = btn_fireA | joystick_0[4];
|
||||
wire m_fire1b = btn_fireB | joystick_0[5];
|
||||
wire m_fire1c = btn_fireC | joystick_0[6];
|
||||
wire m_fire1d = btn_fireD | joystick_0[7];
|
||||
|
||||
wire m_coin2 = btn_coin2_mame | btn_coin;
|
||||
wire m_start2 = btn_start2_mame | btn_two_players;
|
||||
wire m_left2 = btn_left2 | joystick_1[1];
|
||||
wire m_right2 = btn_right2 | joystick_1[0];
|
||||
wire m_up2 = btn_up2 | joystick_1[3];
|
||||
wire m_down2 = btn_down2 | joystick_1[2];
|
||||
wire m_fire2 = btn_fire2A | joystick_1[4];
|
||||
wire m_fire2b = btn_fire2B | joystick_1[5];
|
||||
wire m_fire2c = btn_fire2C | joystick_1[6];
|
||||
wire m_fire2d = btn_fire2D | joystick_1[7];
|
||||
|
||||
wire m_coin3 = btn_coin3_mame | btn_coin;
|
||||
wire m_start3 = btn_start3_mame | btn_three_players;
|
||||
wire m_left3 = joy_2[1];
|
||||
wire m_right3 = joy_2[0];
|
||||
wire m_up3 = joy_2[3];
|
||||
wire m_down3 = joy_2[2];
|
||||
wire m_fire3 = joy_2[4];
|
||||
wire m_fire3b = joy_2[5];
|
||||
wire m_fire3c = joy_2[6];
|
||||
wire m_fire3d = joy_2[7];
|
||||
|
||||
wire m_coin4 = btn_coin4_mame | btn_coin;
|
||||
wire m_start4 = btn_start4_mame | btn_four_players;
|
||||
wire m_left4 = joy_3[1];
|
||||
wire m_right4 = joy_3[0];
|
||||
wire m_up4 = joy_3[3];
|
||||
wire m_down4 = joy_3[2];
|
||||
wire m_fire4 = joy_3[4];
|
||||
wire m_fire4b = joy_3[5];
|
||||
|
||||
reg btn_one_player = 0;
|
||||
reg btn_two_players = 0;
|
||||
reg btn_three_players = 0;
|
||||
reg btn_four_players = 0;
|
||||
reg btn_left = 0;
|
||||
reg btn_right = 0;
|
||||
reg btn_down = 0;
|
||||
reg btn_up = 0;
|
||||
reg btn_fireA = 0;
|
||||
reg btn_fireB = 0;
|
||||
reg btn_fireC = 0;
|
||||
reg btn_fireD = 0;
|
||||
reg btn_coin = 0;
|
||||
reg btn_start1_mame = 0;
|
||||
reg btn_start2_mame = 0;
|
||||
reg btn_start3_mame = 0;
|
||||
reg btn_start4_mame = 0;
|
||||
reg btn_coin1_mame = 0;
|
||||
reg btn_coin2_mame = 0;
|
||||
reg btn_coin3_mame = 0;
|
||||
reg btn_coin4_mame = 0;
|
||||
reg btn_up2 = 0;
|
||||
reg btn_down2 = 0;
|
||||
reg btn_left2 = 0;
|
||||
reg btn_right2 = 0;
|
||||
reg btn_fire2A = 0;
|
||||
reg btn_fire2B = 0;
|
||||
reg btn_fire2C = 0;
|
||||
reg btn_fire2D = 0;
|
||||
|
||||
wire key_pressed;
|
||||
wire [7:0] key_code;
|
||||
wire key_strobe;
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
if(key_strobe) begin
|
||||
case(key_code)
|
||||
'h75: btn_up <= key_pressed; // up
|
||||
'h72: btn_down <= key_pressed; // down
|
||||
'h6B: btn_left <= key_pressed; // left
|
||||
'h74: btn_right <= key_pressed; // right
|
||||
'h76: btn_coin <= key_pressed; // ESC
|
||||
'h05: btn_one_player <= key_pressed; // F1
|
||||
'h06: btn_two_players <= key_pressed; // F2
|
||||
'h04: btn_three_players <= key_pressed; // F3
|
||||
'h0C: btn_four_players <= key_pressed; // F4
|
||||
'h12: btn_fireD <= key_pressed; // l-shift
|
||||
'h14: btn_fireC <= key_pressed; // ctrl
|
||||
'h11: btn_fireB <= key_pressed; // alt
|
||||
'h29: btn_fireA <= key_pressed; // Space
|
||||
// JPAC/IPAC/MAME Style Codes
|
||||
'h16: btn_start1_mame <= key_pressed; // 1
|
||||
'h1E: btn_start2_mame <= key_pressed; // 2
|
||||
'h26: btn_start3_mame <= key_pressed; // 3
|
||||
'h25: btn_start4_mame <= key_pressed; // 4
|
||||
'h2E: btn_coin1_mame <= key_pressed; // 5
|
||||
'h36: btn_coin2_mame <= key_pressed; // 6
|
||||
'h3D: btn_coin3_mame <= key_pressed; // 7
|
||||
'h3E: btn_coin4_mame <= key_pressed; // 8
|
||||
'h2D: btn_up2 <= key_pressed; // R
|
||||
'h2B: btn_down2 <= key_pressed; // F
|
||||
'h23: btn_left2 <= key_pressed; // D
|
||||
'h34: btn_right2 <= key_pressed; // G
|
||||
'h1C: btn_fire2A <= key_pressed; // A
|
||||
'h1B: btn_fire2B <= key_pressed; // S
|
||||
'h21: btn_fire2C <= key_pressed; // Q
|
||||
'h1D: btn_fire2D <= key_pressed; // W
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
35
Arcade_MiST/Midway MCR 3 Monoboard/rtl/build_id.tcl
Normal file
35
Arcade_MiST/Midway MCR 3 Monoboard/rtl/build_id.tcl
Normal file
@ -0,0 +1,35 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
356
Arcade_MiST/Midway MCR 3 Monoboard/rtl/cmos_ram.vhd
Normal file
356
Arcade_MiST/Midway MCR 3 Monoboard/rtl/cmos_ram.vhd
Normal file
@ -0,0 +1,356 @@
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- Syntiac's generic VHDL support files.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
|
||||
-- http://www.syntiac.com/fpga64.html
|
||||
--
|
||||
-- Modified April 2016 by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
-- Remove address register when writing
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- gen_rwram.vhd
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- generic ram.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
entity cmos_ram is
|
||||
generic (
|
||||
dWidth : integer := 8;
|
||||
aWidth : integer := 10
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
we : in std_logic;
|
||||
addr : in std_logic_vector((aWidth-1) downto 0);
|
||||
d : in std_logic_vector((dWidth-1) downto 0);
|
||||
q : out std_logic_vector((dWidth-1) downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
architecture rtl of cmos_ram is
|
||||
subtype addressRange is integer range 0 to ((2**aWidth)-1);
|
||||
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
|
||||
signal ram: ramDef:= (
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --000-00F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --010-01F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --020-02F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --030-03F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --040-04F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --050-05F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --060-06F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --070-07F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --080-08F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --090-09F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --0A0-0AF
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --0B0-0BF
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --0C0-0CF
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --0D0-0DF
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --0E0-0EF
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --0F0-0FF
|
||||
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --100-10F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --1F0-1FF
|
||||
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --200-20F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --2F0-2FF
|
||||
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --300-30F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --3F0-3FF
|
||||
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --400-40F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --4F0-4FF
|
||||
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --500-50F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --5F0-5FF
|
||||
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --600-60F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --6F0-6FF
|
||||
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --700-70F
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF" --7F0-7FF
|
||||
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --800-80F
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --8F0-8FF
|
||||
--
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --900-90F
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --9F0-9FF
|
||||
--
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --A00-A0F
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --AF0-AFF
|
||||
--
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --B00-B0F
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --BF0-BFF
|
||||
--
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --C00-C0F
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --CF0-CFF
|
||||
--
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --D00-D0F
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --DF0-DFF
|
||||
--
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --E00-E0F
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --EF0-EFF
|
||||
--
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --F00-F0F
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF" --FF0-FFF
|
||||
);
|
||||
|
||||
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
|
||||
signal qReg : std_logic_vector((dWidth-1) downto 0);
|
||||
begin
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Signals to entity interface
|
||||
-- -----------------------------------------------------------------------
|
||||
-- q <= qReg;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory write
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if we = '1' then
|
||||
ram(to_integer(unsigned(addr))) <= d;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory read
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
|
||||
-- rAddrReg <= addr;
|
||||
---- qReg <= ram(to_integer(unsigned(addr)));
|
||||
q <= ram(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
--q <= ram(to_integer(unsigned(addr)));
|
||||
end architecture;
|
||||
|
||||
120
Arcade_MiST/Midway MCR 3 Monoboard/rtl/ctc_controler.vhd
Normal file
120
Arcade_MiST/Midway MCR 3 Monoboard/rtl/ctc_controler.vhd
Normal file
@ -0,0 +1,120 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Z80-CTC controler by Dar (darfpga@aol.fr) (19/10/2019)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity ctc_controler is
|
||||
port(
|
||||
clock : in std_logic;
|
||||
clock_ena : in std_logic;
|
||||
reset : in std_logic;
|
||||
|
||||
d_in : in std_logic_vector( 7 downto 0);
|
||||
load_data : in std_logic;
|
||||
int_ack : in std_logic;
|
||||
int_end : in std_logic; -- RETI detected
|
||||
|
||||
int_pulse_0 : in std_logic;
|
||||
int_pulse_1 : in std_logic;
|
||||
int_pulse_2 : in std_logic;
|
||||
int_pulse_3 : in std_logic;
|
||||
|
||||
d_out : out std_logic_vector( 7 downto 0);
|
||||
int_n : out std_logic
|
||||
);
|
||||
end ctc_controler;
|
||||
|
||||
architecture struct of ctc_controler is
|
||||
|
||||
signal int_vector : std_logic_vector(4 downto 0);
|
||||
|
||||
signal wait_for_time_constant : std_logic;
|
||||
signal load_data_r : std_logic; -- make sure load_data toggles to get one new data
|
||||
|
||||
signal int_reg_0 : std_logic;
|
||||
signal int_reg_1 : std_logic;
|
||||
signal int_reg_2 : std_logic;
|
||||
signal int_reg_3 : std_logic;
|
||||
|
||||
signal int_in_service : std_logic_vector(3 downto 0);
|
||||
|
||||
signal int_ack_r : std_logic;
|
||||
signal int_end_r : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
int_n <= '0' when (int_reg_0 or int_reg_1 or int_reg_2 or int_reg_3) = '1' else '1';
|
||||
|
||||
d_out <= int_vector & "000" when int_reg_0 = '1' else
|
||||
int_vector & "010" when int_reg_1 = '1' else
|
||||
int_vector & "100" when int_reg_2 = '1' else
|
||||
int_vector & "110" when int_reg_3 = '1' else (others => '0');
|
||||
|
||||
process (reset, clock)
|
||||
begin
|
||||
|
||||
if reset = '1' then -- hardware and software reset
|
||||
wait_for_time_constant <= '0';
|
||||
int_reg_0 <= '0';
|
||||
int_reg_1 <= '0';
|
||||
int_reg_2 <= '0';
|
||||
int_reg_3 <= '0';
|
||||
int_in_service <= (others => '0');
|
||||
load_data_r <= '0';
|
||||
int_vector <= (others => '0');
|
||||
else
|
||||
if rising_edge(clock) then
|
||||
if clock_ena = '1' then
|
||||
|
||||
load_data_r <= load_data;
|
||||
int_ack_r <= int_ack;
|
||||
int_end_r <= int_end;
|
||||
|
||||
if load_data = '1' and load_data_r = '0' then
|
||||
|
||||
if wait_for_time_constant = '1' then
|
||||
wait_for_time_constant <= '0';
|
||||
else
|
||||
if d_in(0) = '1' then -- check if its a control world
|
||||
wait_for_time_constant <= d_in(2);
|
||||
-- if d_in(1) = '1' then -- software reset
|
||||
-- wait_for_time_constant <= '0';
|
||||
-- end if;
|
||||
else -- its an interrupt vector
|
||||
int_vector <= d_in(7 downto 3);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
if int_pulse_0 = '1' and int_in_service(0) = '0' then int_reg_0 <= '1'; end if;
|
||||
if int_pulse_1 = '1' and int_in_service(1 downto 0) = "00" then int_reg_1 <= '1'; end if;
|
||||
if int_pulse_2 = '1' and int_in_service(2 downto 0) = "000" then int_reg_2 <= '1'; end if;
|
||||
if int_pulse_3 = '1' and int_in_service(3 downto 0) = "0000" then int_reg_3 <= '1'; end if;
|
||||
|
||||
if int_ack_r = '0' and int_ack = '1' then
|
||||
if int_reg_0 = '1' then int_reg_0 <= '0'; int_in_service(0) <= '1';
|
||||
elsif int_reg_1 = '1' then int_reg_1 <= '0'; int_in_service(1) <= '1';
|
||||
elsif int_reg_2 = '1' then int_reg_2 <= '0'; int_in_service(2) <= '1';
|
||||
elsif int_reg_3 = '1' then int_reg_3 <= '0'; int_in_service(3) <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if int_end_r = '0' and int_end = '1' then
|
||||
if int_in_service(0) = '1' then int_in_service(0) <= '0';
|
||||
elsif int_in_service(1) = '1' then int_in_service(1) <= '0';
|
||||
elsif int_in_service(2) = '1' then int_in_service(2) <= '0';
|
||||
elsif int_in_service(3) = '1' then int_in_service(3) <= '0';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end struct;
|
||||
151
Arcade_MiST/Midway MCR 3 Monoboard/rtl/ctc_counter.vhd
Normal file
151
Arcade_MiST/Midway MCR 3 Monoboard/rtl/ctc_counter.vhd
Normal file
@ -0,0 +1,151 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Z80-CTC counter by Dar (darfpga@aol.fr) (19/10/2019)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity ctc_counter is
|
||||
port(
|
||||
clock : in std_logic;
|
||||
clock_ena : in std_logic;
|
||||
reset : in std_logic;
|
||||
|
||||
d_in : in std_logic_vector( 7 downto 0);
|
||||
load_data : in std_logic;
|
||||
|
||||
clk_trg : in std_logic;
|
||||
|
||||
d_out : out std_logic_vector(7 downto 0);
|
||||
zc_to : out std_logic;
|
||||
int_pulse : out std_logic
|
||||
|
||||
);
|
||||
end ctc_counter;
|
||||
|
||||
architecture struct of ctc_counter is
|
||||
|
||||
signal control_word : std_logic_vector(7 downto 0);
|
||||
signal wait_for_time_constant : std_logic;
|
||||
signal time_constant_loaded : std_logic;
|
||||
signal restart_on_next_clock : std_logic;
|
||||
signal restart_on_next_trigger : std_logic;
|
||||
|
||||
signal prescale_max : std_logic_vector(7 downto 0);
|
||||
signal prescale_in : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal count_max : std_logic_vector(7 downto 0);
|
||||
signal count_in : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal zc_to_in : std_logic;
|
||||
signal clk_trg_in : std_logic;
|
||||
signal clk_trg_r : std_logic;
|
||||
signal trigger : std_logic;
|
||||
signal count_ena : std_logic;
|
||||
signal load_data_r : std_logic; -- make sure load_data toggles to get one new data
|
||||
|
||||
begin
|
||||
|
||||
prescale_max <=
|
||||
(others => '0') when control_word(6) = '1' else -- counter mode (prescale max = 0)
|
||||
X"0F" when control_word(6 downto 5) = "00" else -- timer mode prescale 16
|
||||
X"FF"; -- timer mode prescale 256
|
||||
|
||||
clk_trg_in <= clk_trg xor control_word(4);
|
||||
trigger <= '1' when clk_trg_in = '0' and clk_trg_r = '1' else '0';
|
||||
|
||||
d_out <= count_in(7 downto 0);
|
||||
|
||||
zc_to <= zc_to_in;
|
||||
int_pulse <= zc_to_in when control_word(7) = '1' else '0';
|
||||
|
||||
process (reset, clock)
|
||||
begin
|
||||
|
||||
if reset = '1' then -- hardware reset
|
||||
count_ena <= '0';
|
||||
wait_for_time_constant <= '0';
|
||||
time_constant_loaded <= '0';
|
||||
restart_on_next_clock <= '0';
|
||||
restart_on_next_trigger <= '0';
|
||||
count_in <= (others=> '0');
|
||||
zc_to_in <= '0';
|
||||
clk_trg_r <= '0';
|
||||
else
|
||||
if rising_edge(clock) then
|
||||
if clock_ena = '1' then
|
||||
|
||||
clk_trg_r <= clk_trg_in;
|
||||
load_data_r <= load_data;
|
||||
|
||||
if (restart_on_next_trigger = '1' and trigger = '1') or (restart_on_next_clock = '1') then
|
||||
restart_on_next_clock <= '0';
|
||||
restart_on_next_trigger <= '0';
|
||||
count_ena <= '1';
|
||||
count_in <= count_max;
|
||||
prescale_in <= prescale_max;
|
||||
end if;
|
||||
|
||||
if load_data = '1' and load_data_r = '0' then
|
||||
|
||||
if wait_for_time_constant = '1' then
|
||||
wait_for_time_constant <= '0';
|
||||
time_constant_loaded <= '1';
|
||||
count_max <= d_in;
|
||||
|
||||
if control_word(6) = '0' and count_ena = '0' then -- in timer mode, if count was stooped
|
||||
if control_word(3) = '0' then -- auto start when time_constant loaded
|
||||
restart_on_next_clock <= '1';
|
||||
else -- wait for trigger to start
|
||||
restart_on_next_trigger <= '1';
|
||||
end if;
|
||||
end if;
|
||||
if control_word(6) = '1' then -- in trigger mode reload the counter immediately,
|
||||
-- otherwise the first period will undefined
|
||||
prescale_in <= (others => '0');
|
||||
count_in <= d_in;
|
||||
end if;
|
||||
else -- not waiting for time constant
|
||||
|
||||
if d_in(0) = '1' then -- check if its a control world
|
||||
control_word <= d_in;
|
||||
wait_for_time_constant <= d_in(2);
|
||||
restart_on_next_clock <= '0';
|
||||
restart_on_next_trigger <= '0';
|
||||
|
||||
if d_in(1) = '1' then -- software reset
|
||||
count_ena <= '0';
|
||||
time_constant_loaded <= '0';
|
||||
zc_to_in <= '0';
|
||||
-- zc_to_in_r <= '0';
|
||||
clk_trg_r <= clk_trg;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end if; -- end load data
|
||||
|
||||
-- counter
|
||||
zc_to_in <= '0';
|
||||
if ((control_word(6) = '1' and trigger = '1' ) or
|
||||
(control_word(6) = '0' and count_ena = '1') ) and time_constant_loaded = '1' then
|
||||
if prescale_in = 0 then
|
||||
prescale_in <= prescale_max;
|
||||
if count_in = 1 then
|
||||
zc_to_in <= '1';
|
||||
count_in <= count_max;
|
||||
else
|
||||
count_in <= count_in - '1';
|
||||
end if;
|
||||
else
|
||||
prescale_in <= prescale_in - '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end struct;
|
||||
81
Arcade_MiST/Midway MCR 3 Monoboard/rtl/dpram.vhd
Normal file
81
Arcade_MiST/Midway MCR 3 Monoboard/rtl/dpram.vhd
Normal file
@ -0,0 +1,81 @@
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- Syntiac's generic VHDL support files.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
|
||||
-- http://www.syntiac.com/fpga64.html
|
||||
--
|
||||
-- Modified April 2016 by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
-- Remove address register when writing
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- dpram.vhd
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- generic ram.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
entity dpram is
|
||||
generic (
|
||||
dWidth : integer := 8;
|
||||
aWidth : integer := 10
|
||||
);
|
||||
port (
|
||||
clk_a : in std_logic;
|
||||
we_a : in std_logic := '0';
|
||||
addr_a : in std_logic_vector((aWidth-1) downto 0);
|
||||
d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
|
||||
q_a : out std_logic_vector((dWidth-1) downto 0);
|
||||
|
||||
clk_b : in std_logic;
|
||||
we_b : in std_logic := '0';
|
||||
addr_b : in std_logic_vector((aWidth-1) downto 0);
|
||||
d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
|
||||
q_b : out std_logic_vector((dWidth-1) downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
architecture rtl of dpram is
|
||||
subtype addressRange is integer range 0 to ((2**aWidth)-1);
|
||||
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
|
||||
signal ram: ramDef;
|
||||
signal addr_a_reg: std_logic_vector((aWidth-1) downto 0);
|
||||
signal addr_b_reg: std_logic_vector((aWidth-1) downto 0);
|
||||
begin
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk_a)
|
||||
begin
|
||||
if rising_edge(clk_a) then
|
||||
if we_a = '1' then
|
||||
ram(to_integer(unsigned(addr_a))) <= d_a;
|
||||
end if;
|
||||
q_a <= ram(to_integer(unsigned(addr_a)));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_b)
|
||||
begin
|
||||
if rising_edge(clk_b) then
|
||||
if we_b = '1' then
|
||||
ram(to_integer(unsigned(addr_b))) <= d_b;
|
||||
end if;
|
||||
q_b <= ram(to_integer(unsigned(addr_b)));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
|
||||
84
Arcade_MiST/Midway MCR 3 Monoboard/rtl/gen_ram.vhd
Normal file
84
Arcade_MiST/Midway MCR 3 Monoboard/rtl/gen_ram.vhd
Normal file
@ -0,0 +1,84 @@
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- Syntiac's generic VHDL support files.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
|
||||
-- http://www.syntiac.com/fpga64.html
|
||||
--
|
||||
-- Modified April 2016 by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
-- Remove address register when writing
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- gen_rwram.vhd
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- generic ram.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
entity gen_ram is
|
||||
generic (
|
||||
dWidth : integer := 8;
|
||||
aWidth : integer := 10
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
we : in std_logic;
|
||||
addr : in std_logic_vector((aWidth-1) downto 0);
|
||||
d : in std_logic_vector((dWidth-1) downto 0);
|
||||
q : out std_logic_vector((dWidth-1) downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
architecture rtl of gen_ram is
|
||||
subtype addressRange is integer range 0 to ((2**aWidth)-1);
|
||||
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
|
||||
signal ram: ramDef;
|
||||
|
||||
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
|
||||
signal qReg : std_logic_vector((dWidth-1) downto 0);
|
||||
begin
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Signals to entity interface
|
||||
-- -----------------------------------------------------------------------
|
||||
-- q <= qReg;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory write
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if we = '1' then
|
||||
ram(to_integer(unsigned(addr))) <= d;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory read
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
|
||||
-- rAddrReg <= addr;
|
||||
---- qReg <= ram(to_integer(unsigned(addr)));
|
||||
q <= ram(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
--q <= ram(to_integer(unsigned(addr)));
|
||||
end architecture;
|
||||
|
||||
919
Arcade_MiST/Midway MCR 3 Monoboard/rtl/mcr3mono.vhd
Normal file
919
Arcade_MiST/Midway MCR 3 Monoboard/rtl/mcr3mono.vhd
Normal file
@ -0,0 +1,919 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- DDerby by Dar (darfpga@aol.fr) (22/11/2019)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
--
|
||||
-- release rev 00 : initial release
|
||||
-- (22/11/2019)
|
||||
--
|
||||
---------------------------------------------------------------------------------
|
||||
-- gen_ram.vhd & io_ps2_keyboard
|
||||
--------------------------------
|
||||
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
|
||||
-- http://www.syntiac.com/fpga64.html
|
||||
---------------------------------------------------------------------------------
|
||||
-- T80/T80se - Version : 304
|
||||
-----------------------------
|
||||
-- Z80 compatible microprocessor core
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
---------------------------------------------------------------------------------
|
||||
-- YM2149 (AY-3-8910)
|
||||
-- Copyright (c) MikeJ - Jan 2005
|
||||
---------------------------------------------------------------------------------
|
||||
-- Educational use only
|
||||
-- Do not redistribute synthetized file with roms
|
||||
-- Do not redistribute roms whatever the form
|
||||
-- Use at your own risk
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
-- Features :
|
||||
-- Video : VGA 31Khz/60Hz progressive and TV 15kHz interlaced
|
||||
-- Coctail mode : NO
|
||||
-- Sound : OK
|
||||
|
||||
-- Use with MAME roms from timber.zip
|
||||
--
|
||||
-- Use make_timber_proms.bat to build vhd file from binaries
|
||||
-- (CRC list included)
|
||||
|
||||
-- Timber (midway mcr) Hardware caracteristics :
|
||||
--
|
||||
-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram,
|
||||
-- sprite data ram, I/O, sound board register and trigger.
|
||||
-- 56Kx8bits program rom
|
||||
--
|
||||
-- One char/background tile map 30x32
|
||||
-- 2x8Kx8bits graphics rom 4bits/pixel + 2 bit color set
|
||||
-- rbg programmable ram palette 64 colors 9bits : 3red 3green 3blue
|
||||
--
|
||||
-- 128 sprites, up to ~30/line, 32x32 with flip H/V
|
||||
-- 4x32Kx8bits graphics rom 4bits/pixel + 2 bit color set
|
||||
-- rbg programmable ram palette 64 colors 9bits : 3red 3green 3blue
|
||||
--
|
||||
-- Working ram : 2Kx8bits
|
||||
-- video (char/background) ram : 2Kx8bits
|
||||
-- Sprites ram : 512x8bits + 512x8bits cache buffer
|
||||
|
||||
-- Sprites line buffer rams (graphics and colors) : 1 scan line delay flip/flop 2x256x16bits
|
||||
--
|
||||
-- SOUND : see tron_sound_board.vhd
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- Schematics remarks :
|
||||
--
|
||||
-- Display is 512x480 pixels (video 635x525 lines @ 20MHz )
|
||||
|
||||
-- 635/20e6 = 31.75us per line (31.750KHz)
|
||||
-- 31.75*525 = 16.67ms per frame (59.99Hz)
|
||||
--
|
||||
-- Original video is interlaced 240 display lines per 1/2 frame
|
||||
--
|
||||
-- H0 and V0 are not use for background => each bg tile is 16x16 pixel but
|
||||
-- background graphics is 2x2 pixels defintion.
|
||||
--
|
||||
-- Sprite are 32x32 pixels with 1x1 pixel definition, 16 lines for odd 1/2
|
||||
-- frame and 16 lines for even 2/2 frame thanks to V8 on sprite rom ROMAD2
|
||||
-- (look at 74ls86 G1 pin 9 on video genration board schematics)
|
||||
--
|
||||
-- *H and V stand for Horizontal en Vertical counter (Hcnt, Vcnt in VHDL code)
|
||||
--
|
||||
-- /!\ For VHDL port interlaced video mode is replaced with progressive video
|
||||
-- mode.
|
||||
--
|
||||
-- Real hardware uses background ram access after each 1/2 frame (~line 240
|
||||
-- and 480). In these areas cpu can access ram since scanlines are out of
|
||||
-- visible display. In progessive mode there are video access around lines 240.
|
||||
-- These accesses will create video artfacts aound mid display. In VHDL code
|
||||
-- ram access is muliplexed between cpu and scanlines by using hcnt(0) in
|
||||
-- order to avoid these artefacts.
|
||||
--
|
||||
-- Sprite data are stored first by cpu into a 'cache' buffer (staging ram at
|
||||
-- K6/L6) this buffer is read and write for cpu. After visible display, cache
|
||||
-- buffer (512x8) is moved to actual sprite ram buffer (512x8). Actual sprite
|
||||
-- buffer is access by transfer address counter during 2 scanlines after
|
||||
-- visible area and only by sprite machine during visible area.
|
||||
--
|
||||
-- Thus cpu can read and update sprites position during entire frame except
|
||||
-- during 2 lines.
|
||||
--
|
||||
-- Sprite data are organised (as seen by cpu F000-F1FF) into 128 * 4bytes.
|
||||
-- bytes #1 : Vertical position
|
||||
-- bytes #2 : code and attribute
|
||||
-- bytes #3 : Horizontal position
|
||||
-- bytes #4 : not used
|
||||
--
|
||||
-- Athough 1x1 pixel defintion sprite position horizontal/vertical is made on
|
||||
-- on a 2x2 grid (due to only 8bits for position data)
|
||||
--
|
||||
-- Z80-CTC : interruption ar managed by CTC chip. ONly channel 3 is trigered
|
||||
-- by hardware signal line 493. channel 0 to 2 are in timer mode. Schematic
|
||||
-- show zc/to of channel 0 connected to clk/trg of channel 1. This seems to be
|
||||
-- unsued for that (Kick) game.
|
||||
--
|
||||
-- Z80-CTC VHDL port keep separated interrupt controler and each counter so
|
||||
-- one can use them on its own. Priority daisy-chain is not done (not used in
|
||||
-- that game). clock polarity selection is not done since it has no meaning
|
||||
-- with digital clock/enable (e.g cpu_ena signal) method.
|
||||
--
|
||||
-- Ressource : input clock 40MHz is chosen to allow easy making of 20MHz for
|
||||
-- pixel clock and 8MHz signal for amplitude modulation circuit of ssio board
|
||||
--
|
||||
-- TODO :
|
||||
-- Working ram could be initialized to set initial difficulty level and
|
||||
-- initial bases (live) number. Otherwise one can set it up by using service
|
||||
-- menu at each power up.
|
||||
--
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity mcr3mono is
|
||||
port(
|
||||
clock_40 : in std_logic;
|
||||
reset : in std_logic;
|
||||
tv15Khz_mode : in std_logic;
|
||||
video_r : out std_logic_vector(2 downto 0);
|
||||
video_g : out std_logic_vector(2 downto 0);
|
||||
video_b : out std_logic_vector(2 downto 0);
|
||||
video_clk : out std_logic;
|
||||
video_csync : out std_logic;
|
||||
video_blankn : out std_logic;
|
||||
video_hs : out std_logic;
|
||||
video_vs : out std_logic;
|
||||
|
||||
soundsgood : in std_logic; -- Turbo Cheap Squeak/Sounds Good switch
|
||||
snd_stat : out std_logic_vector(1 downto 0); -- sound board stat output
|
||||
audio_out : out std_logic_vector(9 downto 0);
|
||||
|
||||
-- ssio input/outputs
|
||||
input_0 : in std_logic_vector(7 downto 0);
|
||||
input_1 : in std_logic_vector(7 downto 0);
|
||||
input_2 : in std_logic_vector(7 downto 0);
|
||||
input_3 : in std_logic_vector(7 downto 0);
|
||||
input_4 : in std_logic_vector(7 downto 0);
|
||||
output_5 : out std_logic_vector(7 downto 0);
|
||||
output_6 : out std_logic_vector(7 downto 0);
|
||||
|
||||
-- external ROM signals
|
||||
cpu_rom_addr : out std_logic_vector(15 downto 0);
|
||||
cpu_rom_do : in std_logic_vector(7 downto 0);
|
||||
snd_rom_addr : out std_logic_vector(17 downto 0);
|
||||
snd_rom_do : in std_logic_vector(15 downto 0);
|
||||
|
||||
sp_addr : out std_logic_vector(15 downto 0);
|
||||
sp_graphx32_do : in std_logic_vector(31 downto 0);
|
||||
|
||||
-- internal ROM download
|
||||
dl_addr : in std_logic_vector(18 downto 0);
|
||||
dl_data : in std_logic_vector(7 downto 0);
|
||||
dl_wr : in std_logic
|
||||
);
|
||||
end mcr3mono;
|
||||
|
||||
architecture struct of mcr3mono is
|
||||
|
||||
signal reset_n : std_logic;
|
||||
signal clock_vid : std_logic;
|
||||
signal clock_vidn: std_logic;
|
||||
signal clock_cnt : std_logic_vector(3 downto 0) := "0000";
|
||||
|
||||
signal hcnt : std_logic_vector(9 downto 0) := (others=>'0'); -- horizontal counter
|
||||
signal hflip : std_logic_vector(9 downto 0) := (others=>'0'); -- horizontal counter flip
|
||||
signal vcnt : std_logic_vector(9 downto 0) := (others=>'0'); -- vertical counter
|
||||
signal vflip : std_logic_vector(9 downto 0) := (others=>'0'); -- vertical counter flip
|
||||
|
||||
signal hs_cnt, vs_cnt :std_logic_vector(9 downto 0) ;
|
||||
signal hsync0, hsync1, hsync2, hsync3, hsync4 : std_logic;
|
||||
signal top_frame : std_logic := '0';
|
||||
|
||||
signal pix_ena : std_logic;
|
||||
signal cpu_ena : std_logic;
|
||||
|
||||
signal cpu_addr : std_logic_vector(15 downto 0);
|
||||
signal cpu_di : std_logic_vector( 7 downto 0);
|
||||
signal cpu_do : std_logic_vector( 7 downto 0);
|
||||
signal cpu_wr_n : std_logic;
|
||||
signal cpu_rd_n : std_logic;
|
||||
signal cpu_mreq_n : std_logic;
|
||||
signal cpu_ioreq_n : std_logic;
|
||||
signal cpu_irq_n : std_logic;
|
||||
signal cpu_m1_n : std_logic;
|
||||
signal cpu_rfsh_n : std_logic;
|
||||
signal cpu_int_ack_n : std_logic;
|
||||
|
||||
signal ctc_ce : std_logic;
|
||||
signal ctc_do : std_logic_vector(7 downto 0);
|
||||
|
||||
signal ctc_counter_1_trg : std_logic;
|
||||
signal ctc_counter_2_trg : std_logic;
|
||||
signal ctc_counter_3_trg : std_logic;
|
||||
|
||||
-- signal cpu_rom_do : std_logic_vector( 7 downto 0);
|
||||
|
||||
signal wram_we : std_logic;
|
||||
signal wram_do : std_logic_vector( 7 downto 0);
|
||||
|
||||
signal bg_ram_addr: std_logic_vector(10 downto 0);
|
||||
signal bg_ram_we : std_logic;
|
||||
signal bg_ram_do : std_logic_vector(7 downto 0);
|
||||
signal bg_ram_do_r: std_logic_vector(7 downto 0); -- registred ram data for cpu
|
||||
|
||||
signal bg_code : std_logic_vector(7 downto 0);
|
||||
signal bg_code_r : std_logic_vector(7 downto 0);
|
||||
signal bg_attr : std_logic_vector(7 downto 0);
|
||||
|
||||
signal bg_code_line : std_logic_vector(13 downto 0);
|
||||
signal bg_graphx1_do : std_logic_vector( 7 downto 0);
|
||||
signal bg_graphx2_do : std_logic_vector( 7 downto 0);
|
||||
signal bg_palette_addr : std_logic_vector( 5 downto 0);
|
||||
|
||||
signal sp_ram_cache_addr : std_logic_vector(8 downto 0);
|
||||
signal sp_ram_cache_we : std_logic;
|
||||
signal sp_ram_cache_do : std_logic_vector(7 downto 0);
|
||||
signal sp_ram_cache_do_r : std_logic_vector(7 downto 0);-- registred ram data for cpu
|
||||
|
||||
signal move_buf : std_logic;
|
||||
signal sp_ram_addr : std_logic_vector(8 downto 0);
|
||||
signal sp_ram_we : std_logic;
|
||||
signal sp_ram_do : std_logic_vector(7 downto 0);
|
||||
|
||||
signal sp_cnt : std_logic_vector( 6 downto 0);
|
||||
signal sp_code : std_logic_vector( 7 downto 0);
|
||||
signal sp_attr : std_logic_vector( 7 downto 0);
|
||||
signal sp_input_phase : std_logic_vector( 5 downto 0);
|
||||
|
||||
signal sp_done : std_logic;
|
||||
signal sp_vcnt : std_logic_vector( 9 downto 0);
|
||||
signal sp_line : std_logic_vector( 4 downto 0);
|
||||
signal sp_hcnt : std_logic_vector( 8 downto 0); -- lsb used to mux rd/wr line buffer
|
||||
signal sp_on_line : std_logic;
|
||||
signal sp_on_line_r : std_logic;
|
||||
signal sp_byte_cnt : std_logic_vector( 1 downto 0);
|
||||
signal sp_code_line_mux: std_logic_vector(16 downto 0);
|
||||
signal sp_hflip : std_logic_vector( 1 downto 0);
|
||||
signal sp_vflip : std_logic_vector( 4 downto 0);
|
||||
|
||||
signal sp_graphx_do : std_logic_vector( 7 downto 0);
|
||||
signal sp_graphx32_do_r: std_logic_vector(31 downto 0);
|
||||
signal sp_graphx_mux : std_logic_vector( 7 downto 0);
|
||||
signal sp_mux_roms : std_logic_vector( 1 downto 0);
|
||||
|
||||
signal sp_graphx_a : std_logic_vector( 3 downto 0);
|
||||
signal sp_graphx_b : std_logic_vector( 3 downto 0);
|
||||
signal sp_graphx_a_ok : std_logic;
|
||||
signal sp_graphx_b_ok : std_logic;
|
||||
|
||||
signal sp_buffer_ram1_addr : std_logic_vector(7 downto 0);
|
||||
signal sp_buffer_ram1a_we : std_logic;
|
||||
signal sp_buffer_ram1b_we : std_logic;
|
||||
signal sp_buffer_ram1a_di : std_logic_vector( 7 downto 0);
|
||||
signal sp_buffer_ram1b_di : std_logic_vector( 7 downto 0);
|
||||
signal sp_buffer_ram1a_do : std_logic_vector( 7 downto 0);
|
||||
signal sp_buffer_ram1b_do : std_logic_vector( 7 downto 0);
|
||||
signal sp_buffer_ram1_do_r : std_logic_vector(15 downto 0);
|
||||
|
||||
signal sp_buffer_ram2_addr : std_logic_vector(7 downto 0);
|
||||
signal sp_buffer_ram2a_we : std_logic;
|
||||
signal sp_buffer_ram2b_we : std_logic;
|
||||
signal sp_buffer_ram2a_di : std_logic_vector( 7 downto 0);
|
||||
signal sp_buffer_ram2b_di : std_logic_vector( 7 downto 0);
|
||||
signal sp_buffer_ram2a_do : std_logic_vector( 7 downto 0);
|
||||
signal sp_buffer_ram2b_do : std_logic_vector( 7 downto 0);
|
||||
signal sp_buffer_ram2_do_r : std_logic_vector(15 downto 0);
|
||||
|
||||
signal sp_buffer_sel : std_logic;
|
||||
|
||||
signal sp_vid : std_logic_vector(3 downto 0);
|
||||
signal sp_col : std_logic_vector(3 downto 0);
|
||||
signal sp_palette_addr : std_logic_vector(5 downto 0);
|
||||
|
||||
signal palette_addr : std_logic_vector(5 downto 0);
|
||||
signal palette_we : std_logic;
|
||||
signal palette_do : std_logic_vector(8 downto 0);
|
||||
|
||||
-- SSIO signals
|
||||
signal ssio_iowe : std_logic;
|
||||
signal ssio_do : std_logic_vector(7 downto 0);
|
||||
|
||||
signal op_5 : std_logic_vector(7 downto 0);
|
||||
signal op_6 : std_logic_vector(7 downto 0);
|
||||
-- signal max_sprite: std_logic_vector(7 downto 0); -- dbg
|
||||
-- signal max_sprite_r: std_logic_vector(7 downto 0); -- dbg
|
||||
-- signal max_sprite_rr: std_logic_vector(7 downto 0); -- dbg
|
||||
signal bg_graphics_1_we : std_logic;
|
||||
signal bg_graphics_2_we : std_logic;
|
||||
|
||||
signal tcs_rom_addr : std_logic_vector(14 downto 0);
|
||||
signal tcs_rom_do : std_logic_vector( 7 downto 0);
|
||||
signal tcs_audio : std_logic_vector( 9 downto 0);
|
||||
signal sg_rom_addr : std_logic_vector(17 downto 1);
|
||||
signal sg_audio : std_logic_vector( 9 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
clock_vid <= clock_40;
|
||||
clock_vidn <= not clock_40;
|
||||
reset_n <= not reset;
|
||||
|
||||
-- make enables clock from clock_vid
|
||||
process (clock_vid, reset)
|
||||
begin
|
||||
if reset='1' then
|
||||
clock_cnt <= (others=>'0');
|
||||
else
|
||||
if rising_edge(clock_vid) then
|
||||
if clock_cnt = "1111" then -- divide by 16
|
||||
clock_cnt <= (others=>'0');
|
||||
else
|
||||
clock_cnt <= clock_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
--
|
||||
cpu_ena <= '1' when clock_cnt(2 downto 0) = "111" else '0'; -- (5MHz for 91490 super cpu board)
|
||||
pix_ena <= '1' when (clock_cnt(1 downto 0) = "11" and tv15Khz_mode = '1') or -- (10MHz)
|
||||
(clock_cnt(0) = '1' and tv15Khz_mode = '0') else '0'; -- (20MHz)
|
||||
|
||||
-----------------------------------
|
||||
-- Video scanner 634x525 @20Mhz --
|
||||
-- display 512x480 --
|
||||
-----------------------------------
|
||||
process (reset, clock_vid)
|
||||
begin
|
||||
if reset='1' then
|
||||
hcnt <= (others=>'0');
|
||||
vcnt <= (others=>'0');
|
||||
top_frame <= '0';
|
||||
elsif rising_edge(clock_vid) then
|
||||
if pix_ena = '1' then
|
||||
|
||||
hcnt <= hcnt + 1;
|
||||
if hcnt = 633 then
|
||||
hcnt <= (others=>'0');
|
||||
vcnt <= vcnt + 1;
|
||||
if (vcnt = 524 and tv15Khz_mode = '0') or (vcnt = 263 and tv15Khz_mode = '1') then
|
||||
vcnt <= (others=>'0');
|
||||
top_frame <= not top_frame;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if tv15Khz_mode = '0' then
|
||||
-- progessive mode
|
||||
|
||||
if vcnt = 490-1 then video_vs <= '0'; end if; -- front porch 10
|
||||
if vcnt = 492-1 then video_vs <= '1'; end if; -- sync pulse 2
|
||||
-- back porch 33
|
||||
|
||||
if hcnt = 512+13+9+6 then video_hs <= '0'; end if; -- front porch 16/25*20 = 13
|
||||
if hcnt = 512+90+9+6 then video_hs <= '1'; end if; -- sync pulse 96/25*20 = 77
|
||||
-- back porch 48/25*20 = 38
|
||||
video_blankn <= '0';
|
||||
if hcnt >= 2+16-1 and hcnt < 514+16-1 and
|
||||
vcnt >= 2 and vcnt < 481 then video_blankn <= '1';end if;
|
||||
|
||||
else -- interlaced mode
|
||||
|
||||
if hcnt = 530+22 then
|
||||
hs_cnt <= (others => '0');
|
||||
if (vcnt = 240) then
|
||||
vs_cnt <= (others => '0');
|
||||
else
|
||||
vs_cnt <= vs_cnt +1;
|
||||
end if;
|
||||
|
||||
if vcnt = 240 then video_vs <= '0'; end if;
|
||||
if vcnt = 242 then video_vs <= '1'; end if;
|
||||
|
||||
else
|
||||
hs_cnt <= hs_cnt + 1;
|
||||
end if;
|
||||
|
||||
video_blankn <= '0';
|
||||
if hcnt >= 2+16 and hcnt < 514+16 and
|
||||
vcnt >= 1 and vcnt < 241 then video_blankn <= '1';end if;
|
||||
|
||||
|
||||
if hs_cnt = 0 then hsync0 <= '0';
|
||||
elsif hs_cnt = 47 then hsync0 <= '1';
|
||||
end if;
|
||||
|
||||
if hs_cnt = 0 then hsync1 <= '0';
|
||||
elsif hs_cnt = 23 then hsync1 <= '1';
|
||||
elsif hs_cnt = 317+ 0 then hsync1 <= '0';
|
||||
elsif hs_cnt = 317+23 then hsync1 <= '1';
|
||||
end if;
|
||||
|
||||
if hs_cnt = 0 then hsync2 <= '0';
|
||||
elsif hs_cnt = 317-47 then hsync2 <= '1';
|
||||
elsif hs_cnt = 317 then hsync2 <= '0';
|
||||
elsif hs_cnt = 634-47 then hsync2 <= '1';
|
||||
end if;
|
||||
|
||||
|
||||
if hs_cnt = 0 then hsync3 <= '0';
|
||||
elsif hs_cnt = 23 then hsync3 <= '1';
|
||||
elsif hs_cnt = 317 then hsync3 <= '0';
|
||||
elsif hs_cnt = 634-47 then hsync3 <= '1';
|
||||
end if;
|
||||
|
||||
if hs_cnt = 0 then hsync4 <= '0';
|
||||
elsif hs_cnt = 317-47 then hsync4 <= '1';
|
||||
elsif hs_cnt = 317 then hsync4 <= '0';
|
||||
elsif hs_cnt = 317+23 then hsync4 <= '1';
|
||||
end if;
|
||||
|
||||
|
||||
if vs_cnt = 1 then video_csync <= hsync1;
|
||||
elsif vs_cnt = 2 then video_csync <= hsync1;
|
||||
elsif vs_cnt = 3 then video_csync <= hsync1;
|
||||
elsif vs_cnt = 4 and top_frame = '1' then video_csync <= hsync3;
|
||||
elsif vs_cnt = 4 and top_frame = '0' then video_csync <= hsync1;
|
||||
elsif vs_cnt = 5 then video_csync <= hsync2;
|
||||
elsif vs_cnt = 6 then video_csync <= hsync2;
|
||||
elsif vs_cnt = 7 and top_frame = '1' then video_csync <= hsync4;
|
||||
elsif vs_cnt = 7 and top_frame = '0' then video_csync <= hsync2;
|
||||
elsif vs_cnt = 8 then video_csync <= hsync1;
|
||||
elsif vs_cnt = 9 then video_csync <= hsync1;
|
||||
elsif vs_cnt = 10 then video_csync <= hsync1;
|
||||
elsif vs_cnt = 11 then video_csync <= hsync0;
|
||||
else video_csync <= hsync0;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------
|
||||
-- cpu data input with address decoding --
|
||||
------------------------------------------
|
||||
cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"E" else -- 0000-DFFF
|
||||
wram_do when cpu_mreq_n = '0' and (cpu_addr and X"F800") = x"E000" else -- E000-E7FF
|
||||
sp_ram_cache_do_r when cpu_mreq_n = '0' and (cpu_addr and x"FC00") = x"E800" else -- sprite ram E800-E9FF + mirroring 0200
|
||||
bg_ram_do_r when cpu_mreq_n = '0' and (cpu_addr and x"F800") = x"F000" else -- video ram F000-F7FF
|
||||
ctc_do when cpu_int_ack_n = '0' or ctc_ce = '1' else -- ctc (interrupt vector or counter data)
|
||||
ssio_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 5) = "000" else -- 0x00-0x1F
|
||||
X"FF";
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Misc registers : ctc write enable / interrupt acknowledge
|
||||
------------------------------------------------------------------------
|
||||
cpu_int_ack_n <= cpu_ioreq_n or cpu_m1_n;
|
||||
ctc_ce <= '1' when cpu_ioreq_n = '0' and cpu_addr(7 downto 4) = x"F" else '0';
|
||||
ctc_counter_2_trg <= '1' when (vcnt = 240 and tv15Khz_mode = '1') or (vcnt >= 480 and tv15Khz_mode = '0') else '0'; --gvblank
|
||||
ctc_counter_3_trg <= '1' when top_frame = '1' and ((vcnt = 246 and tv15Khz_mode = '1') or (vcnt = 493 and tv15Khz_mode = '0')) else '0';
|
||||
|
||||
------------------------------------------
|
||||
-- write enable / ram access from CPU --
|
||||
------------------------------------------
|
||||
wram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"F800") = x"E000" else '0';
|
||||
sp_ram_cache_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"FC00") = x"E800" and hcnt(0) = '0' else '0';
|
||||
bg_ram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"F800") = x"F000" and hcnt(0) = '0' else '0';
|
||||
|
||||
---------------------------------------------
|
||||
-- SSIO (extracted from Super Sound Board) --
|
||||
---------------------------------------------
|
||||
|
||||
output_5 <= op_5;
|
||||
output_6 <= op_6;
|
||||
|
||||
ssio_iowe <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' else '0';
|
||||
|
||||
ssio_do <= input_0 when cpu_addr(2 downto 0) = "000" else -- Input 0 -- players, coins, ...
|
||||
input_1 when cpu_addr(2 downto 0) = "001" else -- Input 1
|
||||
input_2 when cpu_addr(2 downto 0) = "010" else -- Input 2
|
||||
input_3 when cpu_addr(2 downto 0) = "011" else -- Input 3 -- sw1 dip
|
||||
input_4 when cpu_addr(2 downto 0) = "100" else -- Input 4
|
||||
--ssio_status when cpu_addr(2 downto 0) = "111" else -- ssio status
|
||||
x"FF";
|
||||
|
||||
process (clock_vid, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
op_5 <= (others => '0');
|
||||
op_6 <= (others => '0');
|
||||
elsif rising_edge(clock_vid) then
|
||||
if ssio_iowe = '1' then
|
||||
if cpu_addr(7 downto 0) = x"05" then
|
||||
op_5 <= cpu_do;
|
||||
end if;
|
||||
if cpu_addr(7 downto 0) = x"06" then
|
||||
op_6 <= cpu_do;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
----------------------------------
|
||||
--------- sprite machine ---------
|
||||
---- 91464 Super Video Board ----
|
||||
----------------------------------
|
||||
--hflip <= not(hcnt); -- apply mirror horizontal flip
|
||||
hflip <= hcnt; -- do not apply mirror horizontal flip
|
||||
|
||||
vflip <= vcnt(8 downto 0) & not top_frame when tv15Khz_mode = '1' else vcnt; -- do not apply mirror flip
|
||||
|
||||
sp_buffer_sel <= vflip(1) when tv15Khz_mode = '1' else vflip(0);
|
||||
|
||||
process (clock_vid)
|
||||
begin
|
||||
if rising_edge(clock_vid) then
|
||||
|
||||
-- debug -- max sprite counter
|
||||
-- if vcnt = 0 and hcnt = 0 and pix_ena = '1' then
|
||||
-- max_sprite_r <= (others => '0');
|
||||
-- if max_sprite_r > max_sprite_rr then
|
||||
-- max_sprite_rr <= max_sprite_r;
|
||||
-- end if;
|
||||
-- end if;
|
||||
|
||||
if hcnt = 0 then
|
||||
sp_cnt <= (others => '0');
|
||||
sp_input_phase <= (others => '0');
|
||||
sp_on_line <= '0';
|
||||
sp_done <= '0';
|
||||
-- max_sprite <= (others => '0');
|
||||
-- if max_sprite > max_sprite_r then
|
||||
-- max_sprite_r <= max_sprite;
|
||||
-- end if;
|
||||
end if;
|
||||
|
||||
if sp_done = '0' then
|
||||
sp_input_phase <= sp_input_phase + 1 ;
|
||||
if sp_input_phase >= 10 then sp_hcnt <= sp_hcnt + 1; end if;
|
||||
|
||||
case sp_input_phase is
|
||||
when "000000" =>
|
||||
if sp_vcnt(8 downto 5) = x"F" then -- and sp_ram_do > x"10" then
|
||||
sp_line <= sp_vcnt(4 downto 0);
|
||||
else
|
||||
sp_input_phase <= (others => '0');
|
||||
sp_cnt <= sp_cnt + 1;
|
||||
if sp_cnt = "1111111" then sp_done <= '1'; end if;
|
||||
end if;
|
||||
sp_byte_cnt <= (others => '0');
|
||||
when "000001" =>
|
||||
sp_attr <= sp_ram_do;
|
||||
when "000010" =>
|
||||
sp_code <= sp_ram_do;
|
||||
sp_addr <= sp_attr(3) & sp_ram_do(7 downto 0) & (sp_line xor sp_vflip) & (sp_byte_cnt xor sp_hflip); -- graphics rom addr
|
||||
when "000011" =>
|
||||
sp_hcnt <= sp_ram_do & '0';
|
||||
when "001010" => -- 10
|
||||
sp_graphx32_do_r <= sp_graphx32_do; -- latch incoming sprite data
|
||||
sp_addr <= sp_attr(3) & sp_code(7 downto 0) & (sp_line xor sp_vflip) & (sp_byte_cnt+1 xor sp_hflip); -- advance graphics rom addr
|
||||
sp_on_line <= '1';
|
||||
when "010010"|"011010"|"100010" => -- 18,26,34
|
||||
sp_graphx32_do_r <= sp_graphx32_do; -- latch incoming sprite data
|
||||
sp_addr <= sp_attr(3) & sp_code(7 downto 0) & (sp_line xor sp_vflip) & (sp_byte_cnt+2 xor sp_hflip); -- advance graphics rom addr
|
||||
sp_byte_cnt <= sp_byte_cnt + 1;
|
||||
when "101010" => -- 42
|
||||
sp_on_line <= '0';
|
||||
sp_input_phase <= (others => '0');
|
||||
sp_cnt <= sp_cnt + 1;
|
||||
if sp_cnt = "1111111" then sp_done <= '1'; end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
sp_mux_roms <= sp_input_phase(2 downto 1);
|
||||
end if;
|
||||
|
||||
if pix_ena = '1' then
|
||||
if hcnt(0) = '0' then
|
||||
sp_buffer_ram1_do_r <= sp_buffer_ram1b_do & sp_buffer_ram1a_do;
|
||||
sp_buffer_ram2_do_r <= sp_buffer_ram2b_do & sp_buffer_ram2a_do;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- sp_ram_cache can be read/write by cpu when hcnt(0) = 0;
|
||||
-- sp_ram_cache can be read by sprite machine when hcnt(0) = 1;
|
||||
|
||||
sp_ram_cache_addr <= cpu_addr(8 downto 0) when hcnt(0) = '0' else sp_ram_addr;
|
||||
|
||||
move_buf <= '1' when (vcnt(8 downto 1) = 250 and tv15Khz_mode = '0') or (vcnt(7 downto 1) = 125 and tv15Khz_mode = '1') else '0'; -- line 500-501
|
||||
sp_ram_addr <= vcnt(0) & hcnt(8 downto 1) when move_buf = '1' else sp_cnt & sp_input_phase(1 downto 0);
|
||||
sp_ram_we <= hcnt(0) when move_buf = '1' else '0';
|
||||
|
||||
sp_vcnt <= vflip + (sp_ram_do & '0') -1 ; -- valid when sp_input_phase = 0
|
||||
|
||||
sp_hflip <= (others => sp_attr(4));
|
||||
sp_vflip <= (others => sp_attr(5));
|
||||
|
||||
sp_graphx_do <= sp_graphx32_do_r( 7 downto 0) when (sp_hflip(0) = '0' and sp_mux_roms = "01") or (sp_hflip(0) = '1' and sp_mux_roms = "00") else
|
||||
sp_graphx32_do_r(15 downto 8) when (sp_hflip(0) = '0' and sp_mux_roms = "10") or (sp_hflip(0) = '1' and sp_mux_roms = "11") else
|
||||
sp_graphx32_do_r(23 downto 16) when (sp_hflip(0) = '0' and sp_mux_roms = "11") or (sp_hflip(0) = '1' and sp_mux_roms = "10") else
|
||||
sp_graphx32_do_r(31 downto 24);-- when (sp_hflip(0) = '0' and sp_mux_roms = "00") or (sp_hflip(0) = '1' and sp_mux_roms = "01") ;
|
||||
|
||||
sp_graphx_a <= sp_graphx_do(7 downto 4) when sp_hflip(0) = '1' else sp_graphx_do(3 downto 0);
|
||||
sp_graphx_b <= sp_graphx_do(3 downto 0) when sp_hflip(0) = '1' else sp_graphx_do(7 downto 4);
|
||||
|
||||
sp_graphx_a_ok <= '1' when sp_graphx_a /= x"0" else '0';
|
||||
sp_graphx_b_ok <= '1' when sp_graphx_b /= x"0" else '0';
|
||||
|
||||
sp_buffer_ram1a_di <= '0' & sp_attr(2 downto 0) & sp_graphx_a when sp_buffer_sel = '1' else x"00";
|
||||
sp_buffer_ram1b_di <= '0' & sp_attr(2 downto 0) & sp_graphx_b when sp_buffer_sel = '1' else x"00";
|
||||
sp_buffer_ram1_addr <= sp_hcnt(8 downto 1) when sp_buffer_sel = '1' else hflip(8 downto 1) - x"04";
|
||||
sp_buffer_ram1a_we <= not sp_hcnt(0) and sp_on_line and sp_graphx_a_ok when sp_buffer_sel = '1' else hcnt(0);
|
||||
sp_buffer_ram1b_we <= not sp_hcnt(0) and sp_on_line and sp_graphx_b_ok when sp_buffer_sel = '1' else hcnt(0);
|
||||
|
||||
sp_buffer_ram2a_di <= '0' & sp_attr(2 downto 0) & sp_graphx_a when sp_buffer_sel = '0' else x"00";
|
||||
sp_buffer_ram2b_di <= '0' & sp_attr(2 downto 0) & sp_graphx_b when sp_buffer_sel = '0' else x"00";
|
||||
sp_buffer_ram2_addr <= sp_hcnt(8 downto 1) when sp_buffer_sel = '0' else hflip(8 downto 1) - x"04";
|
||||
sp_buffer_ram2a_we <= not sp_hcnt(0) and sp_on_line and sp_graphx_a_ok when sp_buffer_sel = '0' else hcnt(0);
|
||||
sp_buffer_ram2b_we <= not sp_hcnt(0) and sp_on_line and sp_graphx_b_ok when sp_buffer_sel = '0' else hcnt(0);
|
||||
|
||||
sp_vid <= sp_buffer_ram1_do_r(11 downto 8) when (sp_buffer_sel = '0') and (hflip(0) = '1') else
|
||||
sp_buffer_ram1_do_r( 3 downto 0) when (sp_buffer_sel = '0') and (hflip(0) = '0') else
|
||||
sp_buffer_ram2_do_r(11 downto 8) when (sp_buffer_sel = '1') and (hflip(0) = '1') else
|
||||
sp_buffer_ram2_do_r( 3 downto 0);-- when (sp_buffer_sel = '1') and (hflip(0) = '0');
|
||||
|
||||
sp_col <= sp_buffer_ram1_do_r(15 downto 12) when (sp_buffer_sel = '0') and (hflip(0) = '1') else
|
||||
sp_buffer_ram1_do_r( 7 downto 4) when (sp_buffer_sel = '0') and (hflip(0) = '0') else
|
||||
sp_buffer_ram2_do_r(15 downto 12) when (sp_buffer_sel = '1') and (hflip(0) = '1') else
|
||||
sp_buffer_ram2_do_r( 7 downto 4);-- when (sp_buffer_sel = '1') and (hflip(0) = '0');
|
||||
|
||||
--------------------
|
||||
--- char machine ---
|
||||
--- 91490 Board ----
|
||||
--------------------
|
||||
bg_ram_addr <= cpu_addr(10 downto 0) when hcnt(0) = '0' else vflip(8 downto 4) & hflip(8 downto 4) & hcnt(1);
|
||||
|
||||
bg_code_line <= bg_attr(1 downto 0) & bg_code_r & (vflip(3 downto 1) xor (bg_attr(3) & bg_attr(3) & bg_attr(3) ) ) & (hflip(3) xor bg_attr(2));
|
||||
|
||||
process (clock_vid)
|
||||
begin
|
||||
if rising_edge(clock_vid) then
|
||||
|
||||
-- catch ram data for cpu
|
||||
if hcnt(0) = '0' then
|
||||
bg_ram_do_r <= bg_ram_do;
|
||||
sp_ram_cache_do_r <= sp_ram_cache_do;
|
||||
end if;
|
||||
|
||||
if pix_ena = '1' then
|
||||
|
||||
if hcnt(0) = '1' then
|
||||
case hcnt(3 downto 1) is
|
||||
when "110" => bg_code <= bg_ram_do;
|
||||
when "111" => bg_attr <= bg_ram_do;
|
||||
bg_code_r <= bg_code;
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
case hflip(2 downto 1) xor (bg_attr(2) & bg_attr(2)) is
|
||||
when "00" => bg_palette_addr <= not (bg_attr(5 downto 4) & bg_graphx2_do(7 downto 6) & bg_graphx1_do(7 downto 6));
|
||||
when "01" => bg_palette_addr <= not (bg_attr(5 downto 4) & bg_graphx2_do(5 downto 4) & bg_graphx1_do(5 downto 4));
|
||||
when "10" => bg_palette_addr <= not (bg_attr(5 downto 4) & bg_graphx2_do(3 downto 2) & bg_graphx1_do(3 downto 2));
|
||||
when others => bg_palette_addr <= not (bg_attr(5 downto 4) & bg_graphx2_do(1 downto 0) & bg_graphx1_do(1 downto 0));
|
||||
end case;
|
||||
end if;
|
||||
|
||||
sp_palette_addr <= not sp_col(1 downto 0) & sp_vid;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------
|
||||
-- mux char/sprite video --
|
||||
---------------------------
|
||||
palette_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 10) = x"E"&"11" else '0'; -- 0xEC00-EFFF
|
||||
|
||||
palette_addr <= cpu_addr(6 downto 1) when palette_we = '1' else
|
||||
bg_palette_addr when sp_palette_addr(2 downto 0) = "000" else
|
||||
sp_palette_addr;
|
||||
|
||||
process (clock_vid)
|
||||
begin
|
||||
if rising_edge(clock_vid) then
|
||||
video_g <= palette_do(2 downto 0);
|
||||
video_b <= palette_do(5 downto 3);
|
||||
video_r <= palette_do(8 downto 6);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------
|
||||
-- components & sound board --
|
||||
------------------------------
|
||||
|
||||
-- microprocessor Z80
|
||||
cpu : entity work.T80se
|
||||
generic map(Mode => 0, T2Write => 1, IOWait => 1)
|
||||
port map(
|
||||
RESET_n => reset_n,
|
||||
CLK_n => clock_vid,
|
||||
CLKEN => cpu_ena,
|
||||
WAIT_n => '1',
|
||||
INT_n => cpu_irq_n,
|
||||
NMI_n => '1', --cpu_nmi_n,
|
||||
BUSRQ_n => '1',
|
||||
M1_n => cpu_m1_n,
|
||||
MREQ_n => cpu_mreq_n,
|
||||
IORQ_n => cpu_ioreq_n,
|
||||
RD_n => cpu_rd_n,
|
||||
WR_n => cpu_wr_n,
|
||||
RFSH_n => cpu_rfsh_n,
|
||||
HALT_n => open,
|
||||
BUSAK_n => open,
|
||||
A => cpu_addr,
|
||||
DI => cpu_di,
|
||||
DO => cpu_do
|
||||
);
|
||||
|
||||
-- Z80-CTC (MK3882)
|
||||
z80ctc : entity work.z80ctc_top
|
||||
port map (
|
||||
clock => clock_vid,
|
||||
clock_ena => cpu_ena,
|
||||
reset => reset,
|
||||
din => cpu_do,
|
||||
cpu_din => cpu_di,
|
||||
dout => ctc_do,
|
||||
ce_n => not ctc_ce,
|
||||
cs => cpu_addr(1 downto 0),
|
||||
m1_n => cpu_m1_n,
|
||||
iorq_n => cpu_ioreq_n,
|
||||
rd_n => cpu_rd_n,
|
||||
int_n => cpu_irq_n,
|
||||
trg0 => '0',
|
||||
to0 => ctc_counter_1_trg,
|
||||
trg1 => ctc_counter_1_trg,
|
||||
to1 => open,
|
||||
trg2 => ctc_counter_2_trg,
|
||||
to2 => open,
|
||||
trg3 => ctc_counter_3_trg
|
||||
);
|
||||
|
||||
process (clock_vid, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
cpu_rom_addr <= x"FFFF";
|
||||
elsif rising_edge(clock_vid) then
|
||||
if cpu_rfsh_n = '1' and cpu_addr(15 downto 12) < X"E" then
|
||||
cpu_rom_addr <= cpu_addr(15 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- working RAM 0xE000-0xE7FF
|
||||
wram : entity work.cmos_ram
|
||||
generic map( dWidth => 8, aWidth => 11)
|
||||
port map(
|
||||
clk => clock_vidn,
|
||||
we => wram_we,
|
||||
addr => cpu_addr(10 downto 0),
|
||||
d => cpu_do,
|
||||
q => wram_do
|
||||
);
|
||||
|
||||
-- video RAM 0xF000-0xF7FF
|
||||
video_ram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 11)
|
||||
port map(
|
||||
clk => clock_vidn,
|
||||
we => bg_ram_we,
|
||||
addr => bg_ram_addr,
|
||||
d => cpu_do,
|
||||
q => bg_ram_do
|
||||
);
|
||||
|
||||
-- sprite RAM (no cpu access)
|
||||
sprite_ram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 9)
|
||||
port map(
|
||||
clk => clock_vidn,
|
||||
we => sp_ram_we,
|
||||
addr => sp_ram_addr,
|
||||
d => sp_ram_cache_do,
|
||||
q => sp_ram_do
|
||||
);
|
||||
|
||||
-- sprite RAM 0xE800-0xE9FF + mirroring adresses
|
||||
sprites_ram_cache : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 9)
|
||||
port map(
|
||||
clk => clock_vidn,
|
||||
we => sp_ram_cache_we,
|
||||
addr => sp_ram_cache_addr,
|
||||
d => cpu_do,
|
||||
q => sp_ram_cache_do
|
||||
);
|
||||
|
||||
-- sprite line buffer 1a
|
||||
sprlinebuf1a : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 8)
|
||||
port map(
|
||||
clk => clock_vidn,
|
||||
we => sp_buffer_ram1a_we,
|
||||
addr => sp_buffer_ram1_addr,
|
||||
d => sp_buffer_ram1a_di,
|
||||
q => sp_buffer_ram1a_do
|
||||
);
|
||||
|
||||
-- sprite line buffer 1b
|
||||
sprlinebuf1b : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 8)
|
||||
port map(
|
||||
clk => clock_vidn,
|
||||
we => sp_buffer_ram1b_we,
|
||||
addr => sp_buffer_ram1_addr,
|
||||
d => sp_buffer_ram1b_di,
|
||||
q => sp_buffer_ram1b_do
|
||||
);
|
||||
|
||||
-- sprite line buffer 2a
|
||||
sprlinebuf2a : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 8)
|
||||
port map(
|
||||
clk => clock_vidn,
|
||||
we => sp_buffer_ram2a_we,
|
||||
addr => sp_buffer_ram2_addr,
|
||||
d => sp_buffer_ram2a_di,
|
||||
q => sp_buffer_ram2a_do
|
||||
);
|
||||
|
||||
-- sprite line buffer 2b
|
||||
sprlinebuf2b : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 8)
|
||||
port map(
|
||||
clk => clock_vidn,
|
||||
we => sp_buffer_ram2b_we,
|
||||
addr => sp_buffer_ram2_addr,
|
||||
d => sp_buffer_ram2b_di,
|
||||
q => sp_buffer_ram2b_do
|
||||
);
|
||||
|
||||
bg_graphics_1 : entity work.dpram
|
||||
generic map( dWidth => 8, aWidth => 14)
|
||||
port map(
|
||||
clk_a => clock_vidn,
|
||||
addr_a => bg_code_line(13 downto 0),
|
||||
q_a => bg_graphx1_do,
|
||||
clk_b => clock_vid,
|
||||
we_b => bg_graphics_1_we,
|
||||
addr_b => dl_addr(13 downto 0),
|
||||
d_b => dl_data
|
||||
);
|
||||
bg_graphics_1_we <= '1' when dl_addr(18 downto 14) = "00000" and dl_wr = '1' else '0'; -- 0000-3FFF
|
||||
|
||||
bg_graphics_2 : entity work.dpram
|
||||
generic map( dWidth => 8, aWidth => 14)
|
||||
port map(
|
||||
clk_a => clock_vidn,
|
||||
addr_a => bg_code_line(13 downto 0),
|
||||
q_a => bg_graphx2_do,
|
||||
clk_b => clock_vid,
|
||||
we_b => bg_graphics_2_we,
|
||||
addr_b => dl_addr(13 downto 0),
|
||||
d_b => dl_data
|
||||
);
|
||||
bg_graphics_2_we <= '1' when dl_addr(18 downto 14) = "00001" and dl_wr = '1' else '0'; -- 4000-7FFF
|
||||
|
||||
-- background & sprite palette
|
||||
palette : entity work.gen_ram
|
||||
generic map( dWidth => 9, aWidth => 6)
|
||||
port map(
|
||||
clk => clock_vidn,
|
||||
we => palette_we,
|
||||
addr => palette_addr,
|
||||
d => cpu_addr(0) & cpu_do,
|
||||
q => palette_do
|
||||
);
|
||||
|
||||
-- Turbo Cheap Squeak
|
||||
tcs: entity work.turbo_cheap_squeak
|
||||
port map (
|
||||
clock_40 => clock_40,
|
||||
reset => reset,
|
||||
input => op_6,
|
||||
rom_addr => tcs_rom_addr,
|
||||
rom_do => tcs_rom_do,
|
||||
audio_out => tcs_audio
|
||||
);
|
||||
|
||||
-- Sounds Good
|
||||
sg: entity work.sounds_good
|
||||
port map (
|
||||
clock_40 => clock_40,
|
||||
reset => reset,
|
||||
sint => op_6(0),
|
||||
sndsel => op_6(4 downto 1),
|
||||
stat => snd_stat,
|
||||
extreset_n => '1', -- should come from watchdog
|
||||
rom_addr => sg_rom_addr,
|
||||
rom_do => snd_rom_do,
|
||||
audio_out => sg_audio
|
||||
);
|
||||
|
||||
tcs_rom_do <= snd_rom_do(15 downto 8) when tcs_rom_addr(0) = '1' else snd_rom_do(7 downto 0);
|
||||
snd_rom_addr <= "000" & tcs_rom_addr when soundsgood = '0' else sg_rom_addr&'0';
|
||||
audio_out <= tcs_audio when soundsgood = '0' else sg_audio;
|
||||
|
||||
end struct;
|
||||
397
Arcade_MiST/Midway MCR 3 Monoboard/rtl/pll_mist.vhd
Normal file
397
Arcade_MiST/Midway MCR 3 Monoboard/rtl/pll_mist.vhd
Normal file
@ -0,0 +1,397 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: pll_mist.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2014 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY pll_mist IS
|
||||
PORT
|
||||
(
|
||||
areset : IN STD_LOGIC := '0';
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
END pll_mist;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF pll_mist IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
bandwidth_type : STRING;
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
pll_type : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
self_reset_on_loss_lock : STRING;
|
||||
width_clock : NATURAL
|
||||
);
|
||||
PORT (
|
||||
areset : IN STD_LOGIC ;
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire6_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
|
||||
sub_wire3 <= sub_wire0(0);
|
||||
sub_wire1 <= sub_wire0(1);
|
||||
c1 <= sub_wire1;
|
||||
locked <= sub_wire2;
|
||||
c0 <= sub_wire3;
|
||||
sub_wire4 <= inclk0;
|
||||
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
bandwidth_type => "AUTO",
|
||||
clk0_divide_by => 27,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 40,
|
||||
clk0_phase_shift => "0",
|
||||
clk1_divide_by => 27,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 80,
|
||||
clk1_phase_shift => "0",
|
||||
compensate_clock => "CLK0",
|
||||
inclk0_input_frequency => 37037,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_hint => "CBX_MODULE_PREFIX=pll_mist",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "NORMAL",
|
||||
pll_type => "AUTO",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_USED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_USED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_UNUSED",
|
||||
port_clk3 => "PORT_UNUSED",
|
||||
port_clk4 => "PORT_UNUSED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
self_reset_on_loss_lock => "OFF",
|
||||
width_clock => 5
|
||||
)
|
||||
PORT MAP (
|
||||
areset => areset,
|
||||
inclk => sub_wire5,
|
||||
clk => sub_wire0,
|
||||
locked => sub_wire2
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "80.000000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "40"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "80"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "80.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "40"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "80"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
351
Arcade_MiST/Midway MCR 3 Monoboard/rtl/sdram.sv
Normal file
351
Arcade_MiST/Midway MCR 3 Monoboard/rtl/sdram.sv
Normal file
@ -0,0 +1,351 @@
|
||||
//
|
||||
// sdram.v
|
||||
//
|
||||
// sdram controller implementation for the MiST board
|
||||
// https://github.com/mist-devel/mist-board
|
||||
//
|
||||
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2019 Gyorgy Szombathelyi
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
|
||||
module sdram (
|
||||
|
||||
// interface to the MT48LC16M16 chip
|
||||
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
|
||||
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
|
||||
output reg SDRAM_DQML, // two byte masks
|
||||
output reg SDRAM_DQMH, // two byte masks
|
||||
output reg [1:0] SDRAM_BA, // two banks
|
||||
output SDRAM_nCS, // a single chip select
|
||||
output SDRAM_nWE, // write enable
|
||||
output SDRAM_nRAS, // row address select
|
||||
output SDRAM_nCAS, // columns address select
|
||||
|
||||
// cpu/chipset interface
|
||||
input init_n, // init signal after FPGA config to initialize RAM
|
||||
input clk, // sdram clock
|
||||
|
||||
input port1_req,
|
||||
output reg port1_ack,
|
||||
input port1_we,
|
||||
input [23:1] port1_a,
|
||||
input [1:0] port1_ds,
|
||||
input [15:0] port1_d,
|
||||
output reg [15:0] port1_q,
|
||||
|
||||
input [19:1] cpu1_addr,
|
||||
output reg [15:0] cpu1_q,
|
||||
input [19:1] cpu2_addr,
|
||||
output reg [15:0] cpu2_q,
|
||||
|
||||
input port2_req,
|
||||
output reg port2_ack,
|
||||
input port2_we,
|
||||
input [23:1] port2_a,
|
||||
input [1:0] port2_ds,
|
||||
input [15:0] port2_d,
|
||||
output reg [31:0] port2_q,
|
||||
|
||||
input [17:2] sp_addr,
|
||||
output reg [31:0] sp_q
|
||||
);
|
||||
|
||||
parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
|
||||
|
||||
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
|
||||
localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
|
||||
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
|
||||
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
|
||||
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
|
||||
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
|
||||
|
||||
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
|
||||
|
||||
// 64ms/8192 rows = 7.8us
|
||||
localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// ------------------------ cycle state machine ------------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
/*
|
||||
SDRAM state machine for 2 bank interleaved access
|
||||
1 word burst, CL2
|
||||
cmd issued registered
|
||||
0 RAS0 cas1 - data0 read burst terminated
|
||||
1 ras0
|
||||
2 data1 returned
|
||||
3 CAS0 data1 returned
|
||||
4 RAS1 cas0
|
||||
5 ras1
|
||||
6 CAS1 data0 returned
|
||||
*/
|
||||
|
||||
localparam STATE_RAS0 = 3'd0; // first state in cycle
|
||||
localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
|
||||
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
|
||||
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
|
||||
localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
|
||||
localparam STATE_READ1 = 3'd3;
|
||||
localparam STATE_DS1b = 3'd0;
|
||||
localparam STATE_READ1b = 3'd4;
|
||||
localparam STATE_LAST = 3'd6;
|
||||
|
||||
reg [2:0] t;
|
||||
|
||||
always @(posedge clk) begin
|
||||
t <= t + 1'd1;
|
||||
if (t == STATE_LAST) t <= STATE_RAS0;
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// --------------------------- startup/reset ---------------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
|
||||
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
|
||||
reg [4:0] reset;
|
||||
reg init = 1'b1;
|
||||
always @(posedge clk, negedge init_n) begin
|
||||
if(!init_n) begin
|
||||
reset <= 5'h1f;
|
||||
init <= 1'b1;
|
||||
end else begin
|
||||
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
|
||||
init <= !(reset == 0);
|
||||
end
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// ------------------ generate ram control signals ---------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// all possible commands
|
||||
localparam CMD_INHIBIT = 4'b1111;
|
||||
localparam CMD_NOP = 4'b0111;
|
||||
localparam CMD_ACTIVE = 4'b0011;
|
||||
localparam CMD_READ = 4'b0101;
|
||||
localparam CMD_WRITE = 4'b0100;
|
||||
localparam CMD_BURST_TERMINATE = 4'b0110;
|
||||
localparam CMD_PRECHARGE = 4'b0010;
|
||||
localparam CMD_AUTO_REFRESH = 4'b0001;
|
||||
localparam CMD_LOAD_MODE = 4'b0000;
|
||||
|
||||
reg [3:0] sd_cmd; // current command sent to sd ram
|
||||
reg [15:0] sd_din; // Fast Input register latching incoming SDRAM data
|
||||
|
||||
// drive control signals according to current command
|
||||
assign SDRAM_nCS = sd_cmd[3];
|
||||
assign SDRAM_nRAS = sd_cmd[2];
|
||||
assign SDRAM_nCAS = sd_cmd[1];
|
||||
assign SDRAM_nWE = sd_cmd[0];
|
||||
|
||||
reg [24:1] addr_latch[2];
|
||||
reg [24:1] addr_latch_next[2];
|
||||
reg [19:1] addr_last[2];
|
||||
reg [17:2] addr_last2[2];
|
||||
reg [15:0] din_latch[2];
|
||||
reg [1:0] oe_latch;
|
||||
reg [1:0] we_latch;
|
||||
reg [1:0] ds[2];
|
||||
|
||||
reg port1_state;
|
||||
reg port2_state;
|
||||
|
||||
localparam PORT_NONE = 2'd0;
|
||||
localparam PORT_CPU1 = 2'd1;
|
||||
localparam PORT_CPU2 = 2'd2;
|
||||
localparam PORT_SP = 2'd1;
|
||||
localparam PORT_REQ = 2'd3;
|
||||
|
||||
reg [1:0] next_port[2];
|
||||
reg [1:0] port[2];
|
||||
|
||||
reg refresh;
|
||||
reg [11:0] refresh_cnt;
|
||||
reg need_refresh;
|
||||
|
||||
// PORT1: bank 0,1
|
||||
always @(*) begin
|
||||
if (refresh) begin
|
||||
next_port[0] = PORT_NONE;
|
||||
addr_latch_next[0] = addr_latch[1];
|
||||
end else if (port1_req ^ port1_state) begin
|
||||
next_port[0] = PORT_REQ;
|
||||
addr_latch_next[0] = { 1'b0, port1_a };
|
||||
end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
|
||||
next_port[0] = PORT_CPU1;
|
||||
addr_latch_next[0] = { 5'd0, cpu1_addr };
|
||||
end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
|
||||
next_port[0] = PORT_CPU2;
|
||||
addr_latch_next[0] = { 5'd0, cpu2_addr };
|
||||
end else begin
|
||||
next_port[0] = PORT_NONE;
|
||||
addr_latch_next[0] = addr_latch[0];
|
||||
end
|
||||
end
|
||||
|
||||
// PORT1: bank 2,3
|
||||
always @(*) begin
|
||||
if (port2_req ^ port2_state) begin
|
||||
next_port[1] = PORT_REQ;
|
||||
addr_latch_next[1] = { 1'b1, port2_a };
|
||||
end else if (sp_addr != addr_last2[PORT_SP]) begin
|
||||
next_port[1] = PORT_SP;
|
||||
addr_latch_next[1] = { 1'b1, 6'd0, sp_addr, 1'b0 };
|
||||
end else begin
|
||||
next_port[1] = PORT_NONE;
|
||||
addr_latch_next[1] = addr_latch[1];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
// permanently latch ram data to reduce delays
|
||||
sd_din <= SDRAM_DQ;
|
||||
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
|
||||
sd_cmd <= CMD_NOP; // default: idle
|
||||
refresh_cnt <= refresh_cnt + 1'd1;
|
||||
need_refresh <= (refresh_cnt >= RFRSH_CYCLES);
|
||||
|
||||
if(init) begin
|
||||
// initialization takes place at the end of the reset phase
|
||||
if(t == STATE_RAS0) begin
|
||||
|
||||
if(reset == 15) begin
|
||||
sd_cmd <= CMD_PRECHARGE;
|
||||
SDRAM_A[10] <= 1'b1; // precharge all banks
|
||||
end
|
||||
|
||||
if(reset == 10 || reset == 8) begin
|
||||
sd_cmd <= CMD_AUTO_REFRESH;
|
||||
end
|
||||
|
||||
if(reset == 2) begin
|
||||
sd_cmd <= CMD_LOAD_MODE;
|
||||
SDRAM_A <= MODE;
|
||||
SDRAM_BA <= 2'b00;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
// RAS phase
|
||||
// bank 0,1
|
||||
if(t == STATE_RAS0) begin
|
||||
addr_latch[0] <= addr_latch_next[0];
|
||||
port[0] <= next_port[0];
|
||||
{ oe_latch[0], we_latch[0] } <= 2'b00;
|
||||
|
||||
if (next_port[0] != PORT_NONE) begin
|
||||
sd_cmd <= CMD_ACTIVE;
|
||||
SDRAM_A <= addr_latch_next[0][22:10];
|
||||
SDRAM_BA <= addr_latch_next[0][24:23];
|
||||
addr_last[next_port[0]] <= addr_latch_next[0][19:1];
|
||||
if (next_port[0] == PORT_REQ) begin
|
||||
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
|
||||
ds[0] <= port1_ds;
|
||||
din_latch[0] <= port1_d;
|
||||
port1_state <= port1_req;
|
||||
end else begin
|
||||
{ oe_latch[0], we_latch[0] } <= 2'b10;
|
||||
ds[0] <= 2'b11;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// bank 2,3
|
||||
if(t == STATE_RAS1) begin
|
||||
refresh <= 0;
|
||||
addr_latch[1] <= addr_latch_next[1];
|
||||
{ oe_latch[1], we_latch[1] } <= 2'b00;
|
||||
port[1] <= next_port[1];
|
||||
|
||||
if (next_port[1] != PORT_NONE) begin
|
||||
sd_cmd <= CMD_ACTIVE;
|
||||
SDRAM_A <= addr_latch_next[1][22:10];
|
||||
SDRAM_BA <= addr_latch_next[1][24:23];
|
||||
addr_last2[next_port[1]] <= addr_latch_next[1][16:2];
|
||||
if (next_port[1] == PORT_REQ) begin
|
||||
{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
|
||||
ds[1] <= port2_ds;
|
||||
din_latch[1] <= port2_d;
|
||||
port2_state <= port2_req;
|
||||
end else begin
|
||||
{ oe_latch[1], we_latch[1] } <= 2'b10;
|
||||
ds[1] <= 2'b11;
|
||||
end
|
||||
end else if (need_refresh && !oe_latch[0] & !we_latch[0]) begin
|
||||
refresh <= 1;
|
||||
refresh_cnt <= 0;
|
||||
sd_cmd <= CMD_AUTO_REFRESH;
|
||||
end
|
||||
end
|
||||
|
||||
// CAS phase
|
||||
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
|
||||
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
|
||||
if (we_latch[0]) begin
|
||||
SDRAM_DQ <= din_latch[0];
|
||||
port1_ack <= port1_req;
|
||||
end
|
||||
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
|
||||
SDRAM_BA <= addr_latch[0][24:23];
|
||||
end
|
||||
|
||||
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
|
||||
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
|
||||
if (we_latch[1]) begin
|
||||
SDRAM_DQ <= din_latch[1];
|
||||
port2_ack <= port2_req;
|
||||
end
|
||||
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
|
||||
SDRAM_BA <= addr_latch[1][24:23];
|
||||
end
|
||||
|
||||
// Data returned
|
||||
if(t == STATE_READ0 && oe_latch[0]) begin
|
||||
case(port[0])
|
||||
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
|
||||
PORT_CPU1: begin cpu1_q <= sd_din; end
|
||||
PORT_CPU2: begin cpu2_q <= sd_din; end
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
|
||||
if(t == STATE_READ1 && oe_latch[1]) begin
|
||||
case(port[1])
|
||||
PORT_REQ: port2_q[15:0] <= sd_din;
|
||||
PORT_SP : sp_q[15:0] <= sd_din;
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
|
||||
//set DQM two cycles before the 2nd word in the burst
|
||||
if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
|
||||
|
||||
if(t == STATE_READ1b && oe_latch[1]) begin
|
||||
case(port[1])
|
||||
PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
|
||||
PORT_SP : begin sp_q[31:16] <= sd_din; end
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
225
Arcade_MiST/Midway MCR 3 Monoboard/rtl/sounds_good.vhd
Normal file
225
Arcade_MiST/Midway MCR 3 Monoboard/rtl/sounds_good.vhd
Normal file
@ -0,0 +1,225 @@
|
||||
-- Midway Sounds Good sound board by Slingshot
|
||||
--
|
||||
-- Almost the same as Cheap Squeak Deluxe.
|
||||
-- The differences:
|
||||
-- - A(18-16) used for address decoding
|
||||
-- - supports max. 256k ROM
|
||||
-- - no ROMD signal for inserting wait states for ROM access
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.fx68k.all;
|
||||
|
||||
entity sounds_good is
|
||||
port(
|
||||
clock_40 : in std_logic;
|
||||
reset : in std_logic;
|
||||
extreset_n : in std_logic;
|
||||
sint : in std_logic;
|
||||
sndsel : in std_logic_vector( 3 downto 0);
|
||||
stat : out std_logic_vector( 1 downto 0);
|
||||
rom_addr : out std_logic_vector(17 downto 1);
|
||||
rom_do : in std_logic_vector(15 downto 0);
|
||||
audio_out : out std_logic_vector( 9 downto 0)
|
||||
);
|
||||
end sounds_good;
|
||||
|
||||
architecture rtl of sounds_good is
|
||||
|
||||
signal int_reset : std_logic;
|
||||
|
||||
signal cpu_ce1 : std_logic;
|
||||
signal cpu_ce2 : std_logic;
|
||||
signal cpu_ce_count : std_logic_vector( 4 downto 0);
|
||||
signal cpu_addr : std_logic_vector(23 downto 1);
|
||||
signal cpu_rw : std_logic;
|
||||
signal cpu_irq : std_logic;
|
||||
signal cpu_data_in : std_logic_vector(15 downto 0);
|
||||
signal cpu_data_out : std_logic_vector(15 downto 0);
|
||||
signal cpu_as_n : std_logic;
|
||||
signal cpu_lds_n : std_logic;
|
||||
signal cpu_uds_n : std_logic;
|
||||
signal cpu_dtack_n : std_logic;
|
||||
signal cpu_vpa_n : std_logic;
|
||||
signal cpu_fc : std_logic_vector( 2 downto 0);
|
||||
signal cpu_ipl2_N : std_logic;
|
||||
signal cpu_sel : std_logic;
|
||||
|
||||
signal pia_data_out : std_logic_vector( 7 downto 0);
|
||||
signal pia_pa_in : std_logic_vector( 7 downto 0);
|
||||
signal pia_pa_out : std_logic_vector( 7 downto 0);
|
||||
signal pia_pa_oe : std_logic_vector( 7 downto 0);
|
||||
signal pia_pb_in : std_logic_vector( 7 downto 0);
|
||||
signal pia_pb_out : std_logic_vector( 7 downto 0);
|
||||
signal pia_pb_oe : std_logic_vector( 7 downto 0);
|
||||
signal pia_ca1_in : std_logic;
|
||||
signal pia_ca2_out : std_logic;
|
||||
signal pia_cb1_in : std_logic;
|
||||
signal pia_cb2_out : std_logic;
|
||||
signal pia_irqa : std_logic;
|
||||
signal pia_irqb : std_logic;
|
||||
|
||||
signal cs_rom : std_logic;
|
||||
signal cs_ram : std_logic;
|
||||
signal cs_pia : std_logic;
|
||||
|
||||
signal ram_we : std_logic;
|
||||
signal ram_data_out : std_logic_vector(15 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
fx68k_inst: fx68k
|
||||
port map (
|
||||
clk => clock_40,
|
||||
extReset => int_reset,
|
||||
pwrUp => int_reset,
|
||||
enPhi1 => cpu_ce1,
|
||||
enPhi2 => cpu_ce2,
|
||||
|
||||
eRWn => cpu_rw,
|
||||
ASn => cpu_as_n,
|
||||
LDSn => cpu_lds_n,
|
||||
UDSn => cpu_uds_n,
|
||||
E => open,
|
||||
VMAn => open,
|
||||
FC0 => cpu_fc(0),
|
||||
FC1 => cpu_fc(1),
|
||||
FC2 => cpu_fc(2),
|
||||
BGn => open,
|
||||
oRESETn => open,
|
||||
oHALTEDn => open,
|
||||
DTACKn => cpu_dtack_n,
|
||||
VPAn => cpu_vpa_n,
|
||||
BERRn => '1',
|
||||
BRn => '1',
|
||||
BGACKn => '1',
|
||||
IPL0n => '1',
|
||||
IPL1n => '1',
|
||||
IPL2n => cpu_ipl2_n,
|
||||
iEdb => cpu_data_in,
|
||||
oEdb => cpu_data_out,
|
||||
eab => cpu_addr
|
||||
);
|
||||
|
||||
-- U6
|
||||
u_wram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 11)
|
||||
port map(
|
||||
clk => clock_40,
|
||||
we => ram_we and not cpu_uds_n,
|
||||
addr => cpu_addr(11 downto 1),
|
||||
d => cpu_data_out(15 downto 8),
|
||||
q => ram_data_out(15 downto 8)
|
||||
);
|
||||
|
||||
-- U16
|
||||
l_wram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 11)
|
||||
port map(
|
||||
clk => clock_40,
|
||||
we => ram_we and not cpu_lds_n,
|
||||
addr => cpu_addr(11 downto 1),
|
||||
d => cpu_data_out(7 downto 0),
|
||||
q => ram_data_out(7 downto 0)
|
||||
);
|
||||
|
||||
-- U9
|
||||
pia6821 : entity work.pia6821
|
||||
port map (
|
||||
clk => clock_40,
|
||||
rst => int_reset,
|
||||
cs => cs_pia,
|
||||
rw => cpu_rw,
|
||||
addr => cpu_addr(1)&cpu_addr(2), -- wired in reverse order
|
||||
data_in => cpu_data_out(15 downto 8),
|
||||
data_out => pia_data_out,
|
||||
irqa => pia_irqa,
|
||||
irqb => pia_irqb,
|
||||
pa_i => pia_pa_in,
|
||||
pa_o => pia_pa_out,
|
||||
pa_oe => open,
|
||||
ca1 => pia_ca1_in,
|
||||
ca2_i => '0',
|
||||
ca2_o => open,
|
||||
ca2_oe => open,
|
||||
pb_i => pia_pb_in,
|
||||
pb_o => pia_pb_out,
|
||||
pb_oe => open,
|
||||
cb1 => pia_cb1_in,
|
||||
cb2_i => '0',
|
||||
cb2_o => open,
|
||||
cb2_oe => open
|
||||
);
|
||||
|
||||
-- reset gen.
|
||||
process (clock_40)
|
||||
begin
|
||||
if rising_edge(clock_40) then
|
||||
int_reset <= '0';
|
||||
if reset = '1' or extreset_n = '0' then
|
||||
int_reset <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- clock enable generation: 40/5 = 8 MHz effective clock (original: 16/2=8 MHz)
|
||||
process (clock_40, int_reset)
|
||||
begin
|
||||
if int_reset = '1' then
|
||||
cpu_ce1 <= '0';
|
||||
cpu_ce2 <= '0';
|
||||
cpu_ce_count <= (others => '0');
|
||||
elsif rising_edge(clock_40) then
|
||||
cpu_ce1 <= '0';
|
||||
cpu_ce2 <= '0';
|
||||
cpu_ce_count <= cpu_ce_count + 1;
|
||||
if cpu_ce_count = 2 then
|
||||
cpu_ce1 <= '1';
|
||||
end if;
|
||||
if cpu_ce_count = 4 then
|
||||
cpu_ce2 <= '1';
|
||||
cpu_ce_count <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clock_40, int_reset)
|
||||
begin
|
||||
if int_reset = '1' then
|
||||
rom_addr <= (others => '1');
|
||||
elsif rising_edge(clock_40) then
|
||||
if cpu_addr(18) = '0' then
|
||||
rom_addr <= "0" & cpu_addr(16 downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cpu_sel <= '1' when cpu_as_n = '0' and (cpu_uds_n = '0' or cpu_lds_n = '0') else '0';
|
||||
cpu_dtack_n <= not (cs_rom or cs_ram or cs_pia);
|
||||
|
||||
-- auto-vectored interrupt handling
|
||||
cpu_vpa_n <= '0' when cpu_fc = "111" else '1';
|
||||
cpu_ipl2_n <= not (pia_irqa or pia_irqb);
|
||||
|
||||
cs_rom <= '1' when cpu_sel = '1' and cpu_addr(18) = '0' else '0';
|
||||
cs_ram <= '1' when cpu_sel = '1' and cpu_addr(18 downto 16) = "111" else '0';
|
||||
-- PIA uses 6800 bus cycle originally with VMA, VPA and E clock
|
||||
cs_pia <= '1' when cpu_sel = '1' and cpu_addr(18 downto 16) = "110" else '0';
|
||||
|
||||
ram_we <= '1' when cs_ram = '1' and cpu_rw = '0' else '0';
|
||||
|
||||
cpu_data_in <= rom_do when cs_rom = '1' else
|
||||
ram_data_out when cs_ram = '1' else
|
||||
pia_data_out&x"FF" when cs_pia = '1' else
|
||||
(others => '1');
|
||||
|
||||
audio_out <= pia_pa_out(7 downto 0)&pia_pb_out(7 downto 6);
|
||||
pia_pb_in <= "1100"&sndsel;
|
||||
pia_ca1_in <= not sint;
|
||||
pia_pa_in <= (others => '0');
|
||||
pia_cb1_in <= '0'; -- spare
|
||||
stat <= pia_pb_out(5 downto 4);
|
||||
|
||||
end rtl;
|
||||
46
Arcade_MiST/Midway MCR 3 Monoboard/rtl/spinner.vhd
Normal file
46
Arcade_MiST/Midway MCR 3 Monoboard/rtl/spinner.vhd
Normal file
@ -0,0 +1,46 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity spinner is
|
||||
port(
|
||||
clock_40 : in std_logic;
|
||||
reset : in std_logic;
|
||||
btn_left : in std_logic;
|
||||
btn_right : in std_logic;
|
||||
btn_acc : in std_logic; -- speed up button
|
||||
ctc_zc_to_2 : in std_logic;
|
||||
spin_angle : out std_logic_vector(6 downto 0)
|
||||
);
|
||||
end spinner;
|
||||
|
||||
architecture rtl of spinner is
|
||||
|
||||
signal ctc_zc_to_2_r : std_logic;
|
||||
signal spin_count : std_logic_vector(9 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
spin_angle <= spin_count(9 downto 3);
|
||||
|
||||
process (clock_40, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
spin_count <= (others => '0');
|
||||
elsif rising_edge(clock_40) then
|
||||
ctc_zc_to_2_r <= ctc_zc_to_2;
|
||||
|
||||
if ctc_zc_to_2_r ='0' and ctc_zc_to_2 = '1' then
|
||||
if btn_acc = '0' then -- space -- speed up
|
||||
if btn_left = '1' then spin_count <= spin_count - 40; end if; -- left
|
||||
if btn_right = '1' then spin_count <= spin_count + 40; end if; -- right
|
||||
else
|
||||
if btn_left = '1' then spin_count <= spin_count - 55; end if;
|
||||
if btn_right = '1' then spin_count <= spin_count + 55; end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
143
Arcade_MiST/Midway MCR 3 Monoboard/rtl/turbo_cheap_squeak.vhd
Normal file
143
Arcade_MiST/Midway MCR 3 Monoboard/rtl/turbo_cheap_squeak.vhd
Normal file
@ -0,0 +1,143 @@
|
||||
-- Midway Turbo Cheap Squeak sound board
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity turbo_cheap_squeak is
|
||||
port(
|
||||
clock_40 : in std_logic;
|
||||
reset : in std_logic;
|
||||
input : in std_logic_vector(7 downto 0);
|
||||
rom_addr : out std_logic_vector(14 downto 0);
|
||||
rom_do : in std_logic_vector(7 downto 0);
|
||||
audio_out : out std_logic_vector(9 downto 0)
|
||||
);
|
||||
end turbo_cheap_squeak;
|
||||
|
||||
architecture rtl of turbo_cheap_squeak is
|
||||
|
||||
signal cpu_ce : std_logic;
|
||||
signal cpu_ce_count : std_logic_vector( 4 downto 0);
|
||||
signal cpu_addr : std_logic_vector(15 downto 0);
|
||||
signal cpu_rw : std_logic;
|
||||
signal cpu_irq : std_logic;
|
||||
signal cpu_data_in : std_logic_vector( 7 downto 0);
|
||||
signal cpu_data_out : std_logic_vector( 7 downto 0);
|
||||
|
||||
signal pia_data_out : std_logic_vector( 7 downto 0);
|
||||
signal pia_pa_in : std_logic_vector( 7 downto 0);
|
||||
signal pia_pa_out : std_logic_vector( 7 downto 0);
|
||||
signal pia_pa_oe : std_logic_vector( 7 downto 0);
|
||||
signal pia_pb_in : std_logic_vector( 7 downto 0);
|
||||
signal pia_pb_out : std_logic_vector( 7 downto 0);
|
||||
signal pia_pb_oe : std_logic_vector( 7 downto 0);
|
||||
signal pia_ca1_in : std_logic;
|
||||
signal pia_ca2_out : std_logic;
|
||||
signal pia_cb1_in : std_logic;
|
||||
signal pia_cb2_out : std_logic;
|
||||
signal pia_irqa : std_logic;
|
||||
signal pia_irqb : std_logic;
|
||||
|
||||
signal cs_rom : std_logic;
|
||||
signal cs_ram : std_logic;
|
||||
signal cs_pia : std_logic;
|
||||
|
||||
signal ram_we : std_logic;
|
||||
signal ram_data_out : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
cpu09 : entity work.cpu09
|
||||
port map (
|
||||
clk => clock_40, -- clock input (falling edge)
|
||||
ce => cpu_ce, -- 2 MHz clock enable
|
||||
rst => reset, -- reset input (active high)
|
||||
vma => open, -- valid memory address (active high)
|
||||
lic_out => open, -- last instruction cycle (active high)
|
||||
ifetch => open, -- instruction fetch cycle (active high)
|
||||
opfetch => open, -- opcode fetch (active high)
|
||||
ba => open, -- bus available (high on sync wait or DMA grant)
|
||||
bs => open, -- bus status (high on interrupt or reset vector fetch or DMA grant)
|
||||
addr => cpu_addr, -- address bus output
|
||||
rw => cpu_rw, -- read not write output
|
||||
data_out => cpu_data_out, -- data bus output
|
||||
data_in => cpu_data_in, -- data bus input
|
||||
irq => cpu_irq, -- interrupt request input (active high)
|
||||
firq => '0', -- fast interrupt request input (active high)
|
||||
nmi => '0', -- non maskable interrupt request input (active high)
|
||||
halt => '0' -- halt input (active high) grants DMA
|
||||
);
|
||||
|
||||
wram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 13)
|
||||
port map(
|
||||
clk => clock_40,
|
||||
we => ram_we,
|
||||
addr => cpu_addr(12 downto 0),
|
||||
d => cpu_data_out,
|
||||
q => ram_data_out
|
||||
);
|
||||
|
||||
pia6821 : entity work.pia6821
|
||||
port map (
|
||||
clk => clock_40,
|
||||
rst => reset,
|
||||
cs => cs_pia,
|
||||
rw => cpu_rw,
|
||||
addr => cpu_addr(0)&cpu_addr(1), -- wired in reverse order
|
||||
data_in => cpu_data_out,
|
||||
data_out => pia_data_out,
|
||||
irqa => pia_irqa,
|
||||
irqb => pia_irqb,
|
||||
pa_i => pia_pa_in,
|
||||
pa_o => pia_pa_out,
|
||||
pa_oe => open,
|
||||
ca1 => pia_ca1_in,
|
||||
ca2_i => '0',
|
||||
ca2_o => open,
|
||||
ca2_oe => open,
|
||||
pb_i => pia_pb_in,
|
||||
pb_o => pia_pb_out,
|
||||
pb_oe => open,
|
||||
cb1 => pia_cb1_in,
|
||||
cb2_i => '0',
|
||||
cb2_o => open,
|
||||
cb2_oe => open
|
||||
);
|
||||
|
||||
process (clock_40)
|
||||
begin
|
||||
if rising_edge(clock_40) then
|
||||
cpu_ce <= '0';
|
||||
cpu_ce_count <= cpu_ce_count + 1;
|
||||
if cpu_ce_count = 19 then
|
||||
cpu_ce <= '1';
|
||||
cpu_ce_count <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cs_rom <= '1' when cpu_addr(15) = '1' else '0';
|
||||
cs_ram <= '1' when cpu_addr(15) = '0' and cpu_addr(14) = '0' else '0';
|
||||
cs_pia <= '1' when cpu_addr(15) = '0' and cpu_addr(14) = '1' else '0';
|
||||
|
||||
ram_we <= '1' when cs_ram = '1' and cpu_rw = '0' else '0';
|
||||
|
||||
rom_addr <= cpu_addr(14 downto 0);
|
||||
|
||||
cpu_data_in <= rom_do when cs_rom = '1' else
|
||||
ram_data_out when cs_ram = '1' else
|
||||
pia_data_out when cs_pia = '1' else
|
||||
(others => '1');
|
||||
|
||||
cpu_irq <= pia_irqa or pia_irqb;
|
||||
|
||||
audio_out <= pia_pa_out(7 downto 0)&pia_pb_out(7 downto 6);
|
||||
pia_pb_in(5 downto 0) <= "00"&input(4 downto 1); -- stat1-stat0, sr3-sr0
|
||||
pia_ca1_in <= not input(0); -- sirq
|
||||
pia_pa_in <= (others => '0');
|
||||
pia_cb1_in <= '0'; -- spare
|
||||
|
||||
end rtl;
|
||||
185
Arcade_MiST/Midway MCR 3 Monoboard/rtl/z80ctc_top.vhd
Normal file
185
Arcade_MiST/Midway MCR 3 Monoboard/rtl/z80ctc_top.vhd
Normal file
@ -0,0 +1,185 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
-- Z80-CTC (MK3882) top-level
|
||||
entity z80ctc_top is
|
||||
port(
|
||||
clock : in std_logic;
|
||||
clock_ena : in std_logic;
|
||||
reset : in std_logic;
|
||||
|
||||
din : in std_logic_vector(7 downto 0);
|
||||
dout : out std_logic_vector(7 downto 0);
|
||||
cpu_din : in std_logic_vector(7 downto 0); -- mirror the input to the cpu, for RETI detection
|
||||
|
||||
ce_n : in std_logic;
|
||||
cs : in std_logic_vector(1 downto 0);
|
||||
m1_n : in std_logic;
|
||||
iorq_n : in std_logic;
|
||||
rd_n : in std_logic;
|
||||
int_n : out std_logic;
|
||||
|
||||
trg0 : in std_logic;
|
||||
to0 : out std_logic;
|
||||
|
||||
trg1 : in std_logic;
|
||||
to1 : out std_logic;
|
||||
|
||||
trg2 : in std_logic;
|
||||
to2 : out std_logic;
|
||||
|
||||
trg3 : in std_logic
|
||||
);
|
||||
end z80ctc_top;
|
||||
|
||||
architecture struct of z80ctc_top is
|
||||
|
||||
signal cpu_int_ack_n : std_logic;
|
||||
|
||||
signal ctc_controler_we : std_logic;
|
||||
signal ctc_controler_do : std_logic_vector(7 downto 0);
|
||||
signal ctc_int_ack : std_logic;
|
||||
signal ctc_int_ack_phase : std_logic_vector(1 downto 0);
|
||||
|
||||
signal ctc_counter_0_we : std_logic;
|
||||
signal ctc_counter_0_do : std_logic_vector(7 downto 0);
|
||||
signal ctc_counter_0_int : std_logic;
|
||||
|
||||
signal ctc_counter_1_we : std_logic;
|
||||
signal ctc_counter_1_do : std_logic_vector(7 downto 0);
|
||||
signal ctc_counter_1_int : std_logic;
|
||||
|
||||
signal ctc_counter_2_we : std_logic;
|
||||
signal ctc_counter_2_do : std_logic_vector(7 downto 0);
|
||||
signal ctc_counter_2_int : std_logic;
|
||||
|
||||
signal ctc_counter_3_we : std_logic;
|
||||
signal ctc_counter_3_do : std_logic_vector(7 downto 0);
|
||||
signal ctc_counter_3_int : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
process (clock, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
ctc_int_ack_phase <= "00";
|
||||
elsif rising_edge(clock) then
|
||||
-- decode ED4D (reti)
|
||||
if clock_ena = '1' and rd_n = '0' and m1_n = '0' then
|
||||
case ctc_int_ack_phase is
|
||||
when "00" => if cpu_din = x"ED" then ctc_int_ack_phase <= "01"; end if;
|
||||
when "01" => if cpu_din = x"4D" then ctc_int_ack_phase <= "11"; elsif cpu_din /= x"ED" then ctc_int_ack_phase <= "00"; end if;
|
||||
when "11" => if cpu_din = x"ED" then ctc_int_ack_phase <= "01"; elsif cpu_din /= x"4D" then ctc_int_ack_phase <= "00"; end if;
|
||||
when others => ctc_int_ack_phase <= "00";
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
ctc_int_ack <= '1' when ctc_int_ack_phase = "11" else '0';
|
||||
cpu_int_ack_n <= iorq_n or m1_n;
|
||||
|
||||
ctc_controler_we <= '1' when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '1' and cs = "00" else '0';
|
||||
ctc_counter_0_we <= '1' when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '1' and cs = "00" else '0';
|
||||
ctc_counter_1_we <= '1' when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '1' and cs = "01" else '0';
|
||||
ctc_counter_2_we <= '1' when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '1' and cs = "10" else '0';
|
||||
ctc_counter_3_we <= '1' when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '1' and cs = "11" else '0';
|
||||
|
||||
dout <= ctc_controler_do when cpu_int_ack_n = '0' else
|
||||
ctc_counter_0_do when iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "00" else
|
||||
ctc_counter_1_do when iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "01" else
|
||||
ctc_counter_2_do when iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "10" else
|
||||
ctc_counter_3_do when iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "11" else
|
||||
x"FF";
|
||||
|
||||
-- CTC interrupt controler Z80-CTC (MK3882)
|
||||
ctc_controler : entity work.ctc_controler
|
||||
port map(
|
||||
clock => clock,
|
||||
clock_ena => clock_ena,
|
||||
reset => reset,
|
||||
|
||||
d_in => din,
|
||||
load_data => ctc_controler_we,
|
||||
int_ack => cpu_int_ack_n,
|
||||
int_end => ctc_int_ack,
|
||||
|
||||
int_pulse_0 => ctc_counter_0_int,
|
||||
int_pulse_1 => ctc_counter_1_int,
|
||||
int_pulse_2 => ctc_counter_2_int,
|
||||
int_pulse_3 => ctc_counter_3_int,
|
||||
|
||||
d_out => ctc_controler_do,
|
||||
int_n => int_n
|
||||
);
|
||||
|
||||
ctc_counter_0 : entity work.ctc_counter
|
||||
port map(
|
||||
clock => clock,
|
||||
clock_ena => clock_ena,
|
||||
reset => reset,
|
||||
|
||||
d_in => din,
|
||||
load_data => ctc_counter_0_we,
|
||||
|
||||
clk_trg => trg0,
|
||||
|
||||
d_out => ctc_counter_0_do,
|
||||
zc_to => to0,
|
||||
int_pulse => ctc_counter_0_int
|
||||
|
||||
);
|
||||
|
||||
ctc_counter_1 : entity work.ctc_counter
|
||||
port map(
|
||||
clock => clock,
|
||||
clock_ena => clock_ena,
|
||||
reset => reset,
|
||||
|
||||
d_in => din,
|
||||
load_data => ctc_counter_1_we,
|
||||
|
||||
clk_trg => trg1,
|
||||
|
||||
d_out => ctc_counter_1_do,
|
||||
zc_to => to1,
|
||||
int_pulse => ctc_counter_1_int
|
||||
|
||||
);
|
||||
|
||||
ctc_counter_2 : entity work.ctc_counter
|
||||
port map(
|
||||
clock => clock,
|
||||
clock_ena => clock_ena,
|
||||
reset => reset,
|
||||
|
||||
d_in => din,
|
||||
load_data => ctc_counter_2_we,
|
||||
|
||||
clk_trg => trg2,
|
||||
|
||||
d_out => ctc_counter_2_do,
|
||||
zc_to => to2,
|
||||
int_pulse => ctc_counter_2_int
|
||||
|
||||
);
|
||||
|
||||
ctc_counter_3 : entity work.ctc_counter
|
||||
port map(
|
||||
clock => clock,
|
||||
clock_ena => clock_ena,
|
||||
reset => reset,
|
||||
|
||||
d_in => din,
|
||||
load_data => ctc_counter_3_we,
|
||||
|
||||
clk_trg => trg3,
|
||||
|
||||
d_out => ctc_counter_3_do,
|
||||
zc_to => open,
|
||||
int_pulse => ctc_counter_3_int
|
||||
|
||||
);
|
||||
end struct;
|
||||
Loading…
x
Reference in New Issue
Block a user