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Code Issues Releases Wiki Activity

Clean up Color Overlay

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This commit is contained in:
Marcel 2019-06-09 14:10:08 +02:00
parent 9cd6aae13b
commit 77f22cb606
9 changed files with 319 additions and 41 deletions
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15
Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/SpaceLaser_MiST/README.txt
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@ -9,18 +9,23 @@
-- Audio based on work by Paul Walsh.
-- Audio and scan converter by MikeJ.
---------------------------------------------------------------------------------
--
--
-- Only controls and OSD are rotated on Video output.
--
-- Keyboard inputs :
--
-- F1 : Start
-- SPACE : Fire
-- ESC : Coin
-- F1 : Start 1 player
-- F2 : Start 2 players
-- SPACE : Fire (Player1)
-- RIGHT/LEFT : Movement
--
-- Joystick support.
--
--
---------------------------------------------------------------------------------
ToDo: Color Prom
Controls + DIP
ToDo:
add Player 2
maybe correct Color Prom
DIP

BIN
Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/SpaceLaser_MiST/Release/SpaceLaser.rbf
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Binary file not shown.

12
Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/SpaceLaser_MiST/SpaceLaser.qsf
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@ -18,7 +18,7 @@
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 18:42:51 June 08, 2019
# Date created = 13:58:36 June 09, 2019
#
# -------------------------------------------------------------------------- #
#
@ -45,21 +45,21 @@ set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/spacelaser_mist.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/spacelaser_memory.sv
set_global_assignment -name VHDL_FILE rtl/spacelaser_overlay.vhd
set_global_assignment -name VHDL_FILE rtl/invaders.vhd
set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/spacelaser_memory.sv
set_global_assignment -name VHDL_FILE rtl/spacelaser_overlay.vhd
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VHDL_FILE rtl/roms/clr.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu8080.sv
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
@ -165,10 +165,10 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(SpaceLaser_mist)
# ---------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# ---------------------------

11
Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/SpaceLaser_MiST/SpaceLaser.srf Normal file
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@ -0,0 +1,11 @@
{ "" "" "" "Verilog HDL or VHDL warning at T8080se.vhd(105): object \"BUSRQ_n\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred dual-clock RAM node \"mist_video:mist_video\|osd:osd\|osd_buffer_rtl_0\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Net is missing source, defaulting to GND" { } { } 0 12011 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Design contains 1 input pin(s) that do not drive logic" { } { } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Output pins are stuck at VCC or GND" { } { } 0 13024 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at invaders_audio.vhd(59): object \"Clk240_ena\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Using initial value X (don't care) for net \"IHitTri\[0\]\" at invaders_audio.vhd(86)" { } { } 0 10873 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "4 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "6 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}

13
Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/SpaceLaser_MiST/rtl/SpaceLaser_mist.sv
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@ -59,6 +59,7 @@ wire r,g,b;
wire [15:0]RAB;
wire [15:0]AD;
wire [7:0]RDB;
wire [7:0]CAB;
wire [7:0]RWD;
wire [7:0]IB;
wire [5:0]SoundCtrl3;
@ -79,7 +80,6 @@ invaderst invaderst(
.Fire(~m_fire),
.MoveLeft(~m_left),
.MoveRight(~m_right),
// .DIP(""),
.RDB(RDB),
.IB(IB),
.RWD(RWD),
@ -90,6 +90,7 @@ invaderst invaderst(
.Rst_n_s(Rst_n_s),
.RWE_n(RWE_n),
.Video(Video),
.CAB(CAB),
.HSync(HSync),
.VSync(VSync)
);
@ -118,7 +119,7 @@ spacelaser_overlay spacelaser_overlay (
.Rst_n_s(Rst_n_s),
.HSync(HSync),
.VSync(VSync),
.AD(AD),
.CAB(CAB),
.O_VIDEO_R(r),
.O_VIDEO_G(g),
.O_VIDEO_B(b),
@ -175,12 +176,10 @@ dac dac (
.dac_o(AUDIO_L)
);
wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
@ -188,8 +187,6 @@ reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
reg btn_fire3 = 0;
reg btn_coin = 0;
always @(posedge clk_mist) begin
@ -202,8 +199,6 @@ always @(posedge clk_mist) begin
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
'h14: btn_fire3 <= key_pressed; // ctrl
'h11: btn_fire2 <= key_pressed; // alt
'h29: btn_fire1 <= key_pressed; // Space
endcase
end

42
Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/SpaceLaser_MiST/rtl/invaders.vhd
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@ -76,6 +76,7 @@ entity invaderst is
Rst_n_s : out std_logic;
RWE_n : out std_logic;
Video : out std_logic;
CAB : out std_logic_vector(7 downto 0);
HSync : out std_logic;
VSync : out std_logic
);
@ -160,6 +161,7 @@ begin
HldA => open,
Sample => Sample,
Wr => open,
CAB => CAB,
Video => Video,
HSync => HSync,
VSync => VSync);
@ -169,33 +171,33 @@ begin
GDB1 when "01",
GDB2 when "10",
S when others;
GDB0 <= "11111111";
-- GDB0(0) <= DIP(8); -- Unused ?
-- GDB0(1) <= DIP(7);
-- GDB0(2) <= DIP(6); -- Unused ?
-- GDB0(3) <= '1'; -- Unused ?
-- GDB0(4) <= not Fire;
-- GDB0(5) <= not MoveLeft;
-- GDB0(6) <= not MoveRight;
-- GDB0(7) <= DIP(5); -- Unused ?
GDB1(0) <= not Coin;-- Active High !
GDB0(0) <= '1';--unknown
GDB0(1) <= '1';--unknown
GDB0(2) <= '1';--unknown
GDB0(3) <= '1';--unknown
GDB0(4) <= '1';--unknown
GDB0(5) <= '1';--unknown
GDB0(6) <= '1';--unknown
GDB0(7) <= '1';--unknown
GDB1(0) <= not Coin;
GDB1(1) <= not Sel2Player;
GDB1(2) <= not Sel1Player;
GDB1(3) <= '1';-- Unused ?
GDB1(3) <= '1';--unknown
GDB1(4) <= not Fire;
GDB1(5) <= not MoveLeft;
GDB1(6) <= not MoveRight;
GDB1(7) <= '1';-- Unused ?
GDB1(7) <= '1';--unknown
GDB2(0) <= DIP(4); -- LSB Lives 3-6
GDB2(1) <= DIP(3); -- MSB Lives 3-6
GDB2(2) <= '0';-- Tilt ?
GDB2(3) <= '0';--DIP(2); -- Bonus life at 1000 or 1500
GDB2(4) <= not Fire;
GDB2(5) <= not MoveLeft;
GDB2(6) <= not MoveRight;
GDB2(7) <= '1';--DIP(1); -- Coin info
GDB2(0) <= '0';--unknown
GDB2(1) <= '0';--unknown
GDB2(2) <= '0';--unknown
GDB2(3) <= '0';--unknown
GDB2(4) <= not Fire;--player2
GDB2(5) <= not MoveLeft;--player2
GDB2(6) <= not MoveRight;--player2
GDB2(7) <= '1';-- Coinage
PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';

3
Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/SpaceLaser_MiST/rtl/mw8080.vhd
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@ -79,6 +79,7 @@ entity mw8080 is
Sample : out std_logic;
Wr : out std_logic;
Video : out std_logic;
CAB : out std_logic_vector(7 downto 0);
HSync : out std_logic;
VSync : out std_logic);
end mw8080;
@ -166,7 +167,7 @@ begin
RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
RAB <= A(12 downto 0) when CntD5(2) = '1' else
std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
CAB <= std_logic_vector(CntE7(3 downto 0)) & std_logic_vector(CntE5(3 downto 0));
u_8080: T8080se
generic map (
Mode => 2,

38
Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/SpaceLaser_MiST/rtl/roms/clr.vhd Normal file
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@ -0,0 +1,38 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity clr is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(3 downto 0)
);
end entity;
architecture prom of clr is
type rom is array(0 to 255) of std_logic_vector(3 downto 0);
signal rom_data: rom := (
"0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0010","0010","0001","0011","0010",
"0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0010","0010","0001","0011","0010",
"0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0110","0110","0001","0011","0010",
"0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0110","0110","0001","0011","0010",
"0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0010","0010","0001","0011","0010",
"0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0010","0010","0001","0011","0010",
"0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0110","0110","0001","0011","0010",
"0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0110","0110","0001","0011","0010",
"0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0011","0011","0001","0011","0110",
"0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0011","0011","0001","0011","0110",
"0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110",
"0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110",
"0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0011","0011","0001","0011","0110",
"0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110",
"0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110",
"0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

226
Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/SpaceLaser_MiST/rtl/spacelaser_overlay.vhd Normal file
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@ -0,0 +1,226 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity spacelaser_overlay is
port(
Video : in std_logic;
Overlay : in std_logic;
CLK : in std_logic;
Rst_n_s : in std_logic;
HSync : in std_logic;
VSync : in std_logic;
CAB : in std_logic_vector(7 downto 0);
O_VIDEO_R : out std_logic;
O_VIDEO_G : out std_logic;
O_VIDEO_B : out std_logic;
O_HSYNC : out std_logic;
O_VSYNC : out std_logic
);
end spacelaser_overlay;
architecture rtl of spacelaser_overlay is
signal HCnt : std_logic_vector(11 downto 0);
signal VCnt : std_logic_vector(11 downto 0);
signal HSync_t1 : std_logic;
signal Overlay_A1 : boolean;
signal Overlay_A2 : boolean;
signal Overlay_A3 : boolean;
signal Overlay_A3_VCnt : boolean;
signal Overlay_B1 : boolean;
signal Overlay_B2 : boolean;
signal Overlay_B2_VCnt : boolean;
signal Overlay_G1 : boolean;
signal Overlay_P1 : boolean;
signal Overlay_R1 : boolean;
signal Overlay_R2 : boolean;
signal Overlay_Y1 : boolean;
signal Overlay_Y2 : boolean;
signal Overlay_Y2_VCnt : boolean;
signal VideoRGB : std_logic_vector(2 downto 0);
signal col_data : std_logic_vector(3 downto 0);
begin
process (Rst_n_s, Clk)
variable cnt : unsigned(3 downto 0);
begin
if Rst_n_s = '0' then
cnt := "0000";
elsif Clk'event and Clk = '1' then
if cnt = 9 then
cnt := "0000";
else
cnt := cnt + 1;
end if;
end if;
end process;
p_overlay : process(Rst_n_s, Clk)
variable HStart : boolean;
begin
if Rst_n_s = '0' then
HCnt <= (others => '0');
VCnt <= (others => '0');
HSync_t1 <= '0';
Overlay_A1 <= false;
Overlay_A2 <= false;
Overlay_A3 <= false;
Overlay_A3_VCnt <= false;
Overlay_B1 <= false;
Overlay_B2 <= false;
Overlay_B2_VCnt <= false;
Overlay_G1 <= false;
Overlay_P1 <= false;
Overlay_R1 <= false;
Overlay_R2 <= false;
Overlay_Y1 <= false;
Overlay_Y2 <= false;
Overlay_Y2_VCnt <= false;
elsif Clk'event and Clk = '1' then
HSync_t1 <= HSync;
HStart := (HSync_t1 = '0') and (HSync = '1');
if HStart then
HCnt <= (others => '0');
else
HCnt <= HCnt + "1";
end if;
if (VSync = '0') then
VCnt <= (others => '0');
elsif HStart then
VCnt <= VCnt + "1";
end if;
if HStart then
if (Vcnt = 0) then
Overlay_A3_VCnt <= true;
elsif (Vcnt = 98) then
Overlay_B2_VCnt <= true;
Overlay_A3_VCnt <= false;
elsif (Vcnt = 140) then
Overlay_Y2_VCnt <= true;
Overlay_B2_VCnt <= false;
elsif (Vcnt = 232) then
Overlay_Y2_VCnt <= false;
end if;
end if;
if (HCnt = 500) and Overlay_A3_VCnt then
Overlay_A3 <= true;
elsif (HCnt = 540) then
Overlay_A3 <= false;
end if;
if (HCnt = 486) and Overlay_B2_VCnt then
Overlay_B2 <= true;
elsif (HCnt = 540) then
Overlay_B2 <= false;
end if;
if (HCnt = 486) and Overlay_Y2_VCnt then
Overlay_Y2 <= true;
elsif (HCnt = 540) then
Overlay_Y2 <= false;
end if;
if (HCnt = 64) then
Overlay_R2 <= true;
elsif (HCnt = 96) then
Overlay_A2 <= true;
Overlay_R2 <= false;
elsif (HCnt = 120) then
Overlay_A2 <= false;
Overlay_R1 <= true;
elsif (HCnt = 166) then
Overlay_R1 <= false;
Overlay_Y1 <= true;
elsif (HCnt = 228) then
Overlay_Y1 <= false;
Overlay_P1 <= true;
elsif (HCnt = 292) then
Overlay_P1 <= false;
Overlay_A1 <= true;
elsif (HCnt = 358) then
Overlay_G1 <= true;
Overlay_A1 <= false;
elsif (HCnt = 430) then
Overlay_G1 <= false;
Overlay_B1 <= true;
elsif (HCnt = 486) then
Overlay_B1 <= false;
-- if Overlay_A3_VCnt then
-- Overlay_A2 <= true;
-- if Overlay_B2_VCnt then
-- Overlay_B2 <= true;
-- if Overlay_Y2_VCnt then
-- Overlay_Y2 <= true;
-- elsif (HCnt = 500) then
-- Overlay_A3 <= false;
-- elsif (HCnt = 540) then
-- Overlay_B2 <= false;
-- Overlay_Y2 <= false;
end if;
end if;
end process;
p_video_out_comb : process(Video, Overlay_G1, Overlay_B1, Overlay_B2, Overlay_A1, Overlay_A2, Overlay_A3, Overlay_P1, Overlay_Y1, Overlay_Y2, Overlay_R1, Overlay_R2)
begin
if (Video = '0') then
VideoRGB <= "000";
else
if Overlay_A1 or Overlay_A2 or Overlay_A3 then--AQUA
VideoRGB <= "011";
elsif Overlay_B1 or Overlay_B2 then--BLUE
VideoRGB <= "001";
elsif Overlay_G1 then--GREEN
VideoRGB <= "010";
elsif Overlay_P1 then--PINK
VideoRGB <= "101";
elsif Overlay_R1 or Overlay_R2 then--RED
VideoRGB <= "100";
elsif Overlay_Y1 or Overlay_Y2 then--YELLOW
VideoRGB <= "110";
else
VideoRGB <= "111";--WHITE
end if;
end if;
end process;
colPROM: entity work.clr
port map(
clk => Clk,
addr => CAB, --should be Video Counters
data => col_data
);
-- O_VIDEO_R <= col_data(2);
-- O_VIDEO_G <= col_data(1);
-- O_VIDEO_B <= col_data(0);
O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
O_HSYNC <= not HSync;
O_VSYNC <= not VSync;
end;